badline 0.11.0 → 0.12.0

data/lib/badline/drive1571/serial_port.rb

@@ -0,0 +1,37 @@
+# frozen_string_literal: true
+
+module Badline
+  class Drive1571
+    # What VIA 1's ports read from outside the chip. Port B carries the
+    # serial bus inputs and the device number jumpers, as on the 1541
+    # (Drive::SerialLines). Port A reads the mechanism on two inputs:
+    #
+    #   PA0  track 0 sensor, low while the head sits on track 1
+    #   PA7  BYTE READY, latched low from a whole byte until the CPU next
+    #        reads or writes VIA 2
+    #
+    # The DOS steps the head out until PA0 reads low with the stepper on
+    # phase 0, and polls PA7 for each byte at 2 MHz, taking the byte from
+    # VIA 2's port A or putting the next one there after each. PA1 (fast serial
+    # direction), PA2 (side) and PA5 (1 or 2 MHz) are outputs, which
+    # Drive1571 follows (SerialVIA).
+    class SerialPort
+      include Drive::SerialLines
+
+      TRACK0 = 0x01
+      BYTE_READY = 0x80
+
+      def initialize(mechanism, device: 8, bus: IECBus.new)
+        @mechanism = mechanism
+        init_serial_lines(device, bus)
+      end
+
+      def read_a(_lines)
+        value = 0xff
+        value &= ~TRACK0 if @mechanism.half_track == Drive1541::Mechanism::MIN_HALF_TRACK
+        value &= ~BYTE_READY if @mechanism.byte_latched?
+        value
+      end
+    end
+  end
+end

data/lib/badline/drive1571/serial_via.rb

@@ -0,0 +1,25 @@
+# frozen_string_literal: true
+
+module Badline
+  class Drive1571
+    # VIA 1, the one facing the serial bus. Its port A also selects the
+    # side, the clock rate and the fast serial direction, so the drive
+    # hears port A after every write and reset (Drive1571#port_a_written).
+    class SerialVIA < VIA
+      def initialize(start:, peripheral:, drive:)
+        @drive = drive
+        super(start:, peripheral:)
+      end
+
+      def reset!
+        super
+        @drive.port_a_written(port_a_output)
+      end
+
+      def poke(addr, value)
+        super
+        @drive.port_a_written(port_a_output)
+      end
+    end
+  end
+end

data/lib/badline/drive1571/wd1770.rb

@@ -0,0 +1,120 @@
+# frozen_string_literal: true
+
+module Badline
+  class Drive1571
+    # The WD1770 floppy controller at $2000, which DOS 3.0 drives for MFM
+    # disks. The 1571 here only ever holds GCR disks, so the controller
+    # never finds an MFM sector: it runs each command for its time and ends
+    # it as the WD177x data sheet does on a disk without one.
+    #
+    #   $2000  status (read), command (write)
+    #   $2001  track
+    #   $2002  sector
+    #   $2003  data
+    #
+    # BUSY sets as a command is written. A restore, seek or step (type I)
+    # moves the track register and ends a few milliseconds later, with
+    # TRACK 0 reported at track 0. A sector read or write, a read address
+    # or a read track ends with RECORD NOT FOUND after five turns of the
+    # disk, and a write track after one, with nothing written. A force
+    # interrupt ends the command at once. Time is the drive CPU's cycles.
+    class WD1770
+      BUSY = 0x01
+      TRACK0 = 0x04
+      NOT_FOUND = 0x10
+      MOTOR_ON = 0x80
+
+      # Cycles at 2 MHz, the 1571's clock in 1571 mode: a turn of the disk
+      # at 300 rpm, and a step with the head settling.
+      TURN = 400_000
+      STEP = 12_000
+
+      # The CPU whose cycles time the commands.
+      attr_writer :cpu
+
+      def initialize
+        @registers = [0, 0, 0, 0]
+        @status = 0
+        @due = 0
+        @result = 0
+        @cpu = nil
+      end
+
+      # Register +offset+, 0 to 3: the status, settled to the command's end
+      # once its time has run out.
+      def peek(offset)
+        return @registers[offset] unless offset.zero?
+
+        finish if @status.anybits?(BUSY) && @cpu.cycles >= @due
+        @status
+      end
+
+      def poke(offset, value)
+        offset.zero? ? command(value) : @registers[offset] = value
+      end
+
+      def save_state(out)
+        out.ints([*@registers, @status, @due, @result])
+      end
+
+      # A state from before the controller ran commands holds the four
+      # registers alone.
+      def load_state(input)
+        values = input.ints
+        @registers = values[0, 4]
+        @status = values[4] || 0
+        @due = values[5] || 0
+        @result = values[6] || 0
+      end
+
+      private
+
+      def command(value)
+        return interrupt if (value & 0xf0) == 0xd0
+
+        @registers[0] = value
+        value < 0x80 ? step(value) : search(value)
+      end
+
+      # A restore ($0x), seek ($1x) or step ($2x to $7x), its track register
+      # moved at once.
+      def step(value)
+        track = @registers[1]
+        target = case value >> 4
+                 when 0 then 0
+                 when 1 then @registers[3]
+                 else track + step_direction(value)
+                 end
+        @registers[1] = target.clamp(0, 255) if value < 0x20 || value.anybits?(0x10)
+        start(STEP * [(target - track).abs, 1].max, @registers[1].zero? ? TRACK0 : 0)
+      end
+
+      # Step in ($4x) moves toward higher tracks, step out ($6x) toward
+      # track 0, and step ($2x) the way the last one went.
+      def step_direction(value)
+        @direction = 1 if (value >> 5) == 2
+        @direction = -1 if (value >> 5) == 3
+        @direction || 1
+      end
+
+      # A sector or track command that finds no MFM sector.
+      def search(value)
+        value >= 0xf0 ? start(TURN, 0) : start(TURN * 5, NOT_FOUND)
+      end
+
+      def start(cycles, result)
+        @status = BUSY | MOTOR_ON
+        @due = @cpu.cycles + cycles
+        @result = result
+      end
+
+      def finish
+        @status = @result
+      end
+
+      def interrupt
+        @status &= ~BUSY & 0xff
+      end
+    end
+  end
+end

data/lib/badline/drive1571.rb

@@ -0,0 +1,175 @@
+# frozen_string_literal: true
+
+require "badline/drive1571/cpu"
+require "badline/drive1571/wd1770"
+require "badline/drive1571/serial_port"
+require "badline/drive1571/serial_via"
+require "badline/drive1571/bus"
+
+module Badline
+  # The 1571 disk drive, the C128D's built-in one: the 1541's 6502, two
+  # VIAs and GCR mechanism, with a second head, a 6526 CIA for fast
+  # serial, a WD1770 for MFM disks and DOS 3.0 in 32 KB of ROM. Drive::Core
+  # clocks it against the host and sleeps through the DOS's idle loop.
+  #
+  # VIA 1's port A picks the clock, 1 or 2 MHz on PA5, and the head on
+  # PA2, and reads the track 0 sensor and BYTE READY (SerialPort). The
+  # DOS resets at 2 MHz and drops to 1 MHz as a 1541 would run, which is
+  # how it stays until a C128 asks for fast serial. The disk turns at the
+  # same speed either way (Drive1541::Mechanism#clock_hz=).
+  #
+  # The CIA sits at $4000, on the IRQ line with both VIAs. Only its serial
+  # port is wired, for fast serial through buffers PA1 turns round
+  # (Drive::FastSerial). The drive sleeps only while the CIA is quiet
+  # (CIA#quiet?).
+  class Drive1571
+    include Drive::Core
+    include Drive::VIAs
+    include Drive::FastSerial
+
+    CLOCK_HZ = 1_000_000
+    FAST_CLOCK_HZ = 2_000_000
+
+    # Where the DOS 3.0 idle loop starts over, as DOS 2.6's does.
+    IDLE_LOOP = 0xebff
+
+    # VIA 1's port A outputs.
+    FAST_SERIAL_OUT = 0x02
+    SIDE = 0x04
+    FAST = 0x20
+
+    def cia
+      settle!
+      @cia
+    end
+
+    def fdc
+      settle!
+      @fdc
+    end
+
+    def model_name = "1571"
+
+    # +rom+ covers $8000-$FFFF, and defaults to the DOS image in the ROM
+    # path. +device+ is the number the jumpers on VIA 1's PB5 and PB6 set,
+    # 8 to 11.
+    def initialize(rom: nil, host_clock_hz: CLOCK_HZ, device: 8, debug: false)
+      @device = device
+      @clock_hz = CLOCK_HZ
+      init_fast_serial
+      @mechanism = Drive1541::Mechanism.new(slip: 2)
+      @serial_port = SerialPort.new(@mechanism, device:)
+      @via1 = SerialVIA.new(start: 0x1800, peripheral: @serial_port, drive: self)
+      @via2 = Drive1541::DiskVIA.new(start: 0x1c00, mechanism: @mechanism)
+      @cia = CIA.new(start: 0x4000)
+      @fdc = WD1770.new
+      @bus = Bus.new(rom: rom || ROM.load("dos1571.rom", 0x8000), via1: @via1, via2: @via2, cia: @cia, fdc: @fdc)
+      @cpu = CPU.new(@bus, debug:)
+      @fdc.cpu = @cpu
+      @idle_loop = IDLE_LOOP
+      @host_clock_hz = host_clock_hz
+      @phase = 0
+      @cycles = 0
+      @serial_bus = nil
+      init_idle(debug)
+      # CA1 powers up at the level of a released ATN, without an edge.
+      @via1.ca1 = false
+      @via1.reset!
+      connect(IECBus.new)
+    end
+
+    # The serial bus's RESET line reaches the CPU, both VIAs and the CIA.
+    # RAM keeps its contents.
+    def reset!
+      settle!
+      @via1.reset!
+      @via2.reset!
+      @cia.reset!
+      @cpu.reset!
+    end
+
+    # VIA 1 drives port A to +lines+: the side, the clock rate and the fast
+    # serial direction follow it.
+    def port_a_written(lines)
+      @mechanism.side = lines.anybits?(SIDE) ? 1 : 0
+      fast_serial_out = lines.anybits?(FAST_SERIAL_OUT)
+      turn_fast_serial(fast_serial_out) if fast_serial_out != @fast_serial_out
+      clock_hz = lines.anybits?(FAST) ? FAST_CLOCK_HZ : CLOCK_HZ
+      return if clock_hz == @clock_hz
+
+      @clock_hz = clock_hz
+      @mechanism.clock_hz = clock_hz
+    end
+
+    # Whether the drive runs at 2 MHz.
+    def fast? = @clock_hz == FAST_CLOCK_HZ
+
+    # VIA 1's port B, with the fast serial pins pulling DATA and SRQ
+    # (IECBus::DRIVE_FAST_DATA and DRIVE_FAST_SRQ) above it.
+    def serial_output = @via1.port_b_output | @fast_output
+
+    # The drive's whole state, as the 1541's (Drive1541#save_state), with
+    # the CIA and the WD1770's registers. The clock rate, the side and the
+    # fast serial direction follow from VIA 1's port A.
+    def save_state(out)
+      settle!
+      out.marker("DRIVE1571")
+      out.int(@phase).int(@cycles).boolean(@mechanism.so_pending)
+      @serial_port.save_state(out)
+      @via1.save_state(out)
+      @via2.save_state(out)
+      @cia.save_state(out)
+      @fdc.save_state(out)
+      @bus.save_state(out)
+      @cpu.save_state(out)
+      @mechanism.save_state(out)
+    end
+
+    def load_state(input)
+      settle!
+      input.marker("DRIVE1571")
+      @phase = input.int
+      @cycles = input.int
+      @mechanism.so_pending = input.boolean?
+      @serial_port.load_state(input)
+      @via1.load_state(input)
+      @via2.load_state(input)
+      @cia.load_state(input)
+      @fdc.load_state(input)
+      @bus.load_state(input)
+      @cpu.load_state(input)
+      @mechanism.load_state(input)
+      @fast_serial_out = @via1.port_a_output.anybits?(FAST_SERIAL_OUT)
+      port_a_written(@via1.port_a_output)
+      push_fast_output(@fast_serial_out ? fast_pins : 0)
+      forget_orbits
+    end
+
+    private
+
+    # One drive cycle, as the 1541's (Drive1541#step), with the CIA
+    # clocked beside the VIAs and pulling IRQ with them.
+    def step
+      so = @mechanism.take_so
+      @mechanism.cycle!
+      @via1.ca1 = @serial_port.atn_low?
+      @via1.cycle!
+      @via2.cycle!
+      @cia.cycle!
+      drive_fast_serial if @fast_serial_out
+      @cpu.irq = @via1.irq? || @via2.irq? || @cia.interrupted?
+      @cpu.so! if so
+      @cpu.cycle!
+      @cycles += 1
+    end
+
+    # The VIAs' quiet cycles while the CIA is quiet, and none otherwise.
+    def quiet_cycles
+      @cia.quiet? ? [@via1.quiet_cycles, @via2.quiet_cycles].min : 0
+    end
+
+    def fast_forward_more(cycles)
+      @cia.fast_forward(cycles)
+    end
+  end
+end

data/lib/badline/drive1581/bus.rb

@@ -0,0 +1,137 @@
+# frozen_string_literal: true
+
+module Badline
+  class Drive1581
+    # The drive CPU's bus, as the 74LS139 decodes A13-A15 (1581 Service
+    # Manual, memory map and schematic sheet 1):
+    #
+    # $0000-$1FFF - 8 KB of RAM
+    # $2000-$3FFF - nothing: open bus
+    # $4000-$5FFF - the 8520, its sixteen registers mirrored
+    # $6000-$7FFF - the WD1772, its four registers mirrored
+    # $8000-$FFFF - the DOS ROM
+    #
+    # Writes to the ROM and to open bus go nowhere, and a read from open
+    # bus finds the last byte on the data bus, as on the 1541. A write to
+    # either of the 8520's ports or their direction registers moves the
+    # drive's lines (Drive1581#ports_written).
+    #
+    # While Idle records a pass of the DOS's idle loop, the bus watches it
+    # (watch!): the RAM it reads and writes, and whether it touched the
+    # 8520 or the WD1772, either of which makes the pass volatile. While
+    # Idle looks for an orbit, the bus guards the drive (guard!), and any
+    # access to either chip taints it.
+    class Bus
+      include Addressable
+
+      attr_reader :ram, :rom, :cia, :fdc, :data, :volatile, :touched, :tainted, :touched_timers
+
+      def initialize(rom:, cia:, fdc:, drive:)
+        addressable_at(0, length: 2**16)
+        @ram = Memory.new([], length: 0x2000, start: 0)
+        @rom = rom
+        @cia = cia
+        @fdc = fdc
+        @drive = drive
+        @data = 0
+        @recording = @guarding = @watching = false
+        @volatile = @tainted = false
+        @touched = {}
+        @touched_timers = 0
+      end
+
+      # The last byte on the data bus and the RAM. What a watched stretch
+      # touched is Idle's, and a restored bus isn't watching.
+      def save_state(out)
+        out.int(@data)
+        @ram.save_state(out)
+      end
+
+      def load_state(input)
+        @data = input.int
+        @ram.load_state(input)
+        @watching = false
+      end
+
+      def peek(addr)
+        return @data = @rom.peek(addr) if addr >= 0x8000
+        return @data = chip_peek(addr) if addr >= 0x2000
+
+        touch(addr) if @recording
+        @data = @ram.peek(addr)
+      end
+
+      def poke(addr, value)
+        @data = value
+        return if addr >= 0x8000
+        return chip_poke(addr, value) if addr >= 0x2000
+
+        touch(addr) if @recording
+        @ram.poke(addr, value)
+      end
+
+      # Starts watching: see volatile and touched.
+      def watch!
+        @recording = true
+        @volatile = false
+        @touched = {}
+        watching!
+      end
+
+      def unwatch!
+        @recording = false
+        watching!
+      end
+
+      # Starts guarding: see tainted.
+      def guard!
+        @guarding = true
+        @tainted = false
+        watching!
+      end
+
+      private
+
+      def chip_peek(addr)
+        watch_chip if @watching
+        if addr >= 0x6000
+          @fdc.peek(addr & 0x03)
+        elsif addr >= 0x4000
+          @cia.peek(0x4000 | (addr & 0x0f))
+        else
+          @data
+        end
+      end
+
+      def chip_poke(addr, value)
+        watch_chip if @watching
+        if addr >= 0x6000
+          @fdc.poke(addr & 0x03, value)
+        elsif addr >= 0x4000
+          @cia.poke(0x4000 | (addr & 0x0f), value)
+          @drive.ports_written if addr.nobits?(0x0c)
+        end
+      end
+
+      def touch(addr)
+        @touched[addr] = @ram.peek(addr) unless @touched.key?(addr)
+      end
+
+      def watching!
+        @watching = @recording || @guarding
+      end
+
+      def watch_chip
+        if @recording
+          @volatile = true
+          @recording = false
+        end
+        if @guarding
+          @tainted = true
+          @guarding = false
+        end
+        watching!
+      end
+    end
+  end
+end

data/lib/badline/drive1581/cpu.rb

@@ -0,0 +1,11 @@
+# frozen_string_literal: true
+
+module Badline
+  class Drive1581
+    # The drive's 6502, on the drive's Bus.
+    class CPU
+      include Badline::CPU::Core
+      include Drive::IdleCPU
+    end
+  end
+end

data/lib/badline/drive1581/disk.rb

@@ -0,0 +1,135 @@
+# frozen_string_literal: true
+
+require "badline/drive1581/disk_state"
+
+module Badline
+  class Drive1581
+    # A 3.5" double-sided disk as the WD1772 sees it: a Track on each side
+    # of 80 cylinders, or none where it was never formatted.
+    #
+    # A .d81 image holds the 1581 DOS's logical blocks in order, 40 of 256
+    # bytes on each logical track 1 to 80 (1581 Service Manual, format
+    # organization). Logical track t is cylinder t - 1, and the DOS puts
+    # its sectors 0 to 19 on side 0 and 20 to 39 on side 1, two to each
+    # 512-byte physical sector, numbered from 1. So physical sector s on
+    # side h of cylinder c holds logical sectors 20h + 2(s - 1) and the one
+    # after it, and every cylinder of the image is a standard Track
+    # (Track.standard) on both sides. A block the image's error table
+    # marks 20 or 21 loses its sector's ID field, 27 spoils the ID's CRC,
+    # 22 loses the data field and 23 spoils its CRC.
+    #
+    # The WD1772 writes into the tracks, and flush stores the standard
+    # sectors of each one written back in the image, which writes its host
+    # file. A track formatted another way stays on the disk alone. The disk
+    # is write-protected when the image won't take writes.
+    class Disk
+      include State
+
+      CYLINDERS = 80
+      SIDES = 2
+
+      # Logical blocks a side of a cylinder holds.
+      SIDE_BLOCKS = 20
+
+      # A logical block's bytes, and how many a physical sector holds.
+      BLOCK_SIZE = 256
+      BLOCKS = Track::SECTOR_SIZE / BLOCK_SIZE
+
+      # A disk from the .d81 image at +path+. `read_only` opens the image
+      # write-protected.
+      def self.open(path, read_only: false)
+        new(Storage::D81Image.new(path, read_only:)).opened(path, read_only)
+      end
+
+      attr_reader :image
+
+      def initialize(image = nil)
+        @image = image
+        @tracks = Array.new(CYLINDERS * SIDES)
+        @written = {}
+        @changed = {}
+        @path = nil
+        @read_only = false
+      end
+
+      # The Track on +side+ of +cylinder+, or nil where there is none: past
+      # the image's cylinders, or on a disk without an image that the head
+      # never formatted.
+      def track(cylinder, side)
+        index = (cylinder * SIDES) + side
+        return @tracks[index] if @tracks[index] || !@image || cylinder >= CYLINDERS
+
+        @tracks[index] = image_track(cylinder, side)
+      end
+
+      # A write track laid +track+ down on +side+ of +cylinder+, or a write
+      # sector changed it.
+      def write(cylinder, side, track)
+        return if cylinder >= CYLINDERS
+
+        index = (cylinder * SIDES) + side
+        @tracks[index] = track
+        @written[index] = true
+        @changed[index] = true
+      end
+
+      # Whether the write-protect hole is open: the disk's image won't take
+      # writes, or a disk without an image was opened read-only.
+      def write_protected? = @image.nil? ? @read_only : !@image.writable?
+
+      # Whether any track was written since the last flush.
+      def written? = !@written.empty?
+
+      # Stores the standard sectors of each track written since the last
+      # flush in the image, all in one write to its host file.
+      def flush
+        written = @written.keys.sort
+        @written.clear
+        return if @image.nil? || written.empty?
+
+        @image.store_blocks(written.flat_map { |index| track_blocks(index / SIDES, index % SIDES) })
+      end
+
+      private
+
+      def image_track(cylinder, side)
+        track = Track.standard(cylinder, side) { |sector| physical_block(cylinder, side, sector) }
+        track.sectors.each { |sector| mark_errors(cylinder, side, sector) }
+        track.sectors.reject! { |sector| sector.id.nil? }
+        track
+      end
+
+      # The logical track and first sector physical sector +sector+ holds.
+      def logical(cylinder, side, sector) = [cylinder + 1, (side * SIDE_BLOCKS) + ((sector - 1) * BLOCKS)]
+
+      def physical_block(cylinder, side, sector)
+        track, first = logical(cylinder, side, sector)
+        Array.new(BLOCKS) { |i| @image.read_block(track, first + i) || [] }.flatten
+      end
+
+      def mark_errors(cylinder, side, sector)
+        track, first = logical(cylinder, side, sector.id.bytes[2])
+        errors = Array.new(BLOCKS) { |i| @image.block_error(track, first + i) }
+        sector.id.good = false if errors.include?(27)
+        sector.data.good = false if errors.include?(23)
+        sector.data = nil if errors.include?(22)
+        sector.id = nil if errors.include?(20) || errors.include?(21)
+      end
+
+      # [track, sector, data, nil] for DiskImage#store_blocks, for each
+      # logical block a standard sector of the track holds.
+      def track_blocks(cylinder, side)
+        track = @tracks[(cylinder * SIDES) + side]
+        Track::SECTORS.times.flat_map do |index|
+          data = track.sector([cylinder, side, index + 1, Track::SIZE_CODE])&.data
+          next [] unless data
+
+          logical_track, first = logical(cylinder, side, index + 1)
+          Array.new(BLOCKS) do |i|
+            [logical_track, first + i, data.bytes[i * BLOCK_SIZE, BLOCK_SIZE], nil]
+          end
+        end
+      end
+    end
+  end
+end