badline 0.11.0 → 0.12.0

data/lib/badline/c128/modes.rb

@@ -2,10 +2,10 @@
 
 module Badline
   class C128
-    # Following the MMU between C128 and C64 mode: the KERNAL traps go to
-    # the KERNAL the machine runs, C= held from power-on starts it in C64
-    # mode through the C128 KERNAL, and #active_screen tells a front end
-    # which screen the mode's editor prints to.
+    # Following the MMU between C128 and C64 mode: the KERNAL traps and
+    # typed keys go to the KERNAL the machine runs, C= held from power-on
+    # starts it in C64 mode through the C128 KERNAL, and #active_screen
+    # tells a front end which screen the mode's editor prints to.
     module Modes
       # Holds C= down from power-on until the C128 KERNAL has taken the
       # machine to C64 mode, as a user does to start a C128 in C64 mode.
@@ -43,6 +43,19 @@ module Badline
         @holding_commodore = false
         @init_threshold = @cycles + Computer::INIT_THRESHOLD if @cycles < @init_threshold
       end
+
+      # The keyboard buffer of the KERNAL the machine runs: the C64's, or in
+      # C128 mode BASIC 7.0's.
+      def feed_keyboard
+        c64 = mode == :c64
+        count = c64 ? KeyboardBuffer::COUNT : C128_KEYBOARD_COUNT
+        return unless ram.peek(count).zero?
+
+        chunk = @pending_keys.shift(KeyboardBuffer::CAPACITY)
+        ram.write(c64 ? KeyboardBuffer::ADDRESS : C128_KEYBOARD_BUFFER, chunk)
+        ram.poke(count, chunk.length)
+        @pending_keys = nil if @pending_keys.empty?
+      end
     end
   end
 end

data/lib/badline/c128/saved_state.rb

@@ -81,6 +81,8 @@ module Badline
         save_cartridge(out)
         @bus.save_state(out)
         @cpu.save_state(out)
+        @z80.save_state(out)
+        out.int(@z80_due).int(@chips_ahead).boolean(@cpu_reset_pending)
         save_trap_drive(out)
         save_serial_bus(out)
       end
@@ -98,15 +100,36 @@ module Badline
         @pending_keys = input.ints if input.boolean?
         @init_handlers_lost = [input.int - @init_handlers.length, 0].max
         load_cartridge(input)
+        @cpu_reset_pending = false
         @bus.load_state(input)
         push_serial_lines
         @cpu.load_state(input)
+        load_z80(input)
         load_trap_drive(input)
         load_serial_bus(input)
+        push_fast_serial
       end
 
       private
 
+      # The Z80 and which CPU has the bus, which a state from before the
+      # Z80 leaves to the 8502. The bus, restored before it, hands the bus
+      # to its CPU without resetting the 8502.
+      def load_z80(input)
+        @z80_running = @bus.z80?
+        @z80_turn = @z80_running
+        @z80_due = @z80.cycles
+        @chips_ahead = 0
+        @cpu_reset_pending = false
+        return unless input.schema > 6
+
+        @z80.load_state(input)
+        @z80_due = input.int
+        @chips_ahead = input.int
+        @cpu_reset_pending = input.boolean?
+        @z80_turn = @z80_running || @chips_ahead.positive?
+      end
+
       def check_setup(setup)
         ours = [@model.name, @sid.model, @c64_built ? :c64 : :c128]
         return if setup == ours

data/lib/badline/c128/z80.rb

@@ -0,0 +1,49 @@
+# frozen_string_literal: true
+
+require "badline/z80/core"
+
+module Badline
+  class C128
+    # The C128's Z80A, on the Z80's side of the C128::Bus.
+    class Z80
+      include Badline::Z80::Core
+    end
+
+    # The Z80's accesses, through the pages C128::Bus lays out for it
+    # (Bus::Z80Pages). An IN or OUT first brings the chips up to the cycle
+    # it falls in, since the Z80 runs whole instructions ahead of them.
+    class Z80Bus
+      def initialize(bus)
+        @read_pages = bus.z80_read_pages
+        @write_pages = bus.z80_write_pages
+        @input_pages = bus.z80_input_pages
+        @output_pages = bus.z80_output_pages
+        @machine = nil
+      end
+
+      # The machine whose chips an IN or OUT catches up.
+      attr_writer :machine
+
+      def fetch(addr) = @read_pages[addr >> 8].peek(addr)
+
+      def read(addr) = @read_pages[addr >> 8].peek(addr)
+
+      def write(addr, value)
+        @write_pages[addr >> 8].poke(addr, value)
+      end
+
+      def input(port)
+        @machine.z80_catch_up
+        @input_pages[port >> 8].peek(port)
+      end
+
+      def output(port, value)
+        @machine.z80_catch_up
+        @output_pages[port >> 8].poke(port, value)
+      end
+
+      # Nothing drives the data bus in an interrupt acknowledge cycle.
+      def acknowledge = 0xff
+    end
+  end
+end

data/lib/badline/c128/z80_pages.rb

@@ -0,0 +1,118 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    class Bus
+      # What the Z80 sees, in memory and through IN and OUT, laid over the
+      # 8502's map whenever the MMU, the port or a cartridge changes it
+      # while the Z80 has the bus.
+      #
+      # In C128 mode, with CR's RAM bank 0, the MMU translates $0000-$0FFF
+      # to $D000-$DFFF of bank 0: a read gets the Z80 BIOS, which the
+      # KERNAL ROM holds there, and a write or an IN or OUT the RAM at
+      # $Dxxx. With bank 1 those pages are RAM, common RAM's or bank 1's.
+      # $D000-$DFFF is RAM. In C64 mode the PLA decodes the Z80's memory
+      # accesses as it does the 8502's.
+      #
+      # In both modes the chips at $D000-$DFFF answer IN and OUT whether
+      # I/O is mapped in or not. The MMU's registers at $D500 take an OUT
+      # either way in C128 mode, but answer an IN only with CR's I/O bit
+      # on, memory answering it otherwise. While I/O is mapped in, the
+      # colour RAM the 8502 sees also answers at $1000-$13FF. An IN or OUT
+      # anywhere else reaches what memory has there.
+      module Z80Pages
+        # A colour RAM bank seen at $1000-$13FF.
+        class ColorWindow
+          def initialize(color_ram)
+            @color_ram = color_ram
+          end
+
+          def peek(addr) = @color_ram.peek(0xd800 | (addr & 0x3ff))
+          def poke(addr, value) = @color_ram.poke(0xd800 | (addr & 0x3ff), value)
+        end
+
+        # The Z80's memory and I/O pages, each 256 entries.
+        attr_reader :z80_read_pages, :z80_write_pages, :z80_input_pages, :z80_output_pages
+
+        # Calls the block whenever MCR bit 0 hands the bus to the other CPU.
+        def on_processor_change(&block)
+          @on_processor_change = block
+        end
+
+        # Whether the Z80 has the bus, MCR bit 0 low.
+        def z80? = @z80
+
+        private
+
+        # Lays out the Z80's pages again while it has the bus, and tells the
+        # machine if MCR bit 0 handed the bus over.
+        def update_z80!
+          z80 = @mmu.z80?
+          map_z80_pages if z80
+          return if z80 == @z80
+
+          @z80 = z80
+          @on_processor_change&.call
+        end
+
+        def build_z80_pages
+          @z80_bios = ROM.new(ROM.read("c128/kernal.rom")[0x1000, 0x1000], length: 0x1000, start: 0)
+          @z80_read_pages = Array.new(256)
+          @z80_write_pages = Array.new(256)
+          @z80_input_pages = Array.new(256)
+          @z80_output_pages = Array.new(256)
+          @z80_color_ram = [ColorWindow.new(@color_lines.color_ram(0)), ColorWindow.new(@color_lines.color_ram(1))]
+          @z80_translated = RAMWindow.new(@ram, 0xd000, 0xfff)
+          @z80 = @mmu.z80?
+          @on_processor_change = nil
+        end
+
+        def map_z80_pages
+          c128_mode = !@mmu.c64_mode?
+          bios = c128_mode && @mmu.cr < 0x40
+          @z80_read_pages.replace(@read_pages)
+          @z80_write_pages.replace(@write_pages)
+          map_z80_ram_pages if c128_mode
+          map_z80_bios if bios
+          map_z80_color_ram(c128_mode) if @io_mapped
+          @z80_input_pages.replace(@z80_read_pages)
+          @z80_output_pages.replace(@z80_write_pages)
+          @z80_input_pages.fill(@z80_translated, 0, 16) if bios
+          @io_mapped ? map_z80_io_from_cpu : map_z80_io
+        end
+
+        def map_z80_ram_pages
+          (0xd0..0xdf).each do |page|
+            ram = bank_of(page, @mmu.cpu_bank).zero? ? @ram : @bank1
+            @z80_read_pages[page] = @z80_write_pages[page] = ram
+          end
+        end
+
+        def map_z80_bios
+          @z80_read_pages.fill(@z80_bios, 0, 16)
+          @z80_write_pages.fill(@z80_translated, 0, 16)
+        end
+
+        def map_z80_color_ram(c128_mode)
+          window = @z80_color_ram[c128_mode ? @io_port.value & 0x01 : 1]
+          @z80_read_pages.fill(window, 0x10, 4)
+          @z80_write_pages.fill(window, 0x10, 4)
+        end
+
+        def map_z80_io_from_cpu
+          (0xd0..0xdf).each do |page|
+            @z80_input_pages[page] = @read_pages[page]
+            @z80_output_pages[page] = @write_pages[page]
+          end
+        end
+
+        # The chips at $D000-$DFFF while I/O is mapped out, leaving an IN
+        # at $D500 to memory.
+        def map_z80_io
+          lay_out_io(@z80_input_pages, @z80_output_pages)
+          @z80_output_pages[0xd5] = @mmu unless @mmu.c64_mode?
+        end
+      end
+    end
+  end
+end

data/lib/badline/c128/z80_turns.rb

@@ -0,0 +1,106 @@
+# frozen_string_literal: true
+
+module Badline
+  class C128
+    # The Z80's turns on the bus. MCR bit 0 hands the bus between the 8502
+    # and the Z80, and while the Z80 has it each cycle clocks the chips,
+    # then gives the Z80 2 T-states unless BA holds it. The Z80 runs whole
+    # instructions while it is behind, so an IN or OUT first brings the
+    # chips up to the cycle it falls in (#z80_catch_up), and the cycles
+    # that follow clock nothing until the machine catches up with them.
+    module Z80Turns
+      # The T-states from the start of an I/O machine cycle to the one its
+      # data moves in. 1 and 2 pass c128modez80-23, whose IN reads open
+      # bus, and 0, 3 and 4 fail it.
+      IO_DELAY = 2
+
+      attr_reader :z80
+
+      # Brings the chips up to the cycle an IN or OUT of the Z80 falls in.
+      def z80_catch_up
+        while @z80.cycles + IO_DELAY >= @z80_due
+          clock_chips
+          @chips_ahead += 1
+          @z80_due += 2
+        end
+      end
+
+      private
+
+      def build_z80
+        z80_bus = Z80Bus.new(@bus)
+        @z80 = Z80.new(z80_bus)
+        z80_bus.machine = self
+        @z80_running = @bus.z80?
+        @z80_turn = @z80_running
+        @z80_due = 0
+        @chips_ahead = 0
+        @cpu_reset_pending = @z80_running
+        @bus.on_processor_change { processor_changed }
+      end
+
+      # A cycle while the Z80 has the bus, or after it handed the bus to the
+      # 8502 while the chips were ahead.
+      def z80_cycle!
+        if @chips_ahead.positive?
+          @chips_ahead -= 1
+          @z80_turn = @z80_running || @chips_ahead.positive?
+          return
+        end
+
+        clock_chips
+        @z80_due += 2 unless @vic.ba_low?
+        z80 = @z80
+        z80.step! while @z80_running && z80.cycles < @z80_due
+      end
+
+      # The chips' share of a cycle while the Z80 has the bus, with the
+      # interrupt lines going to the Z80.
+      def clock_chips
+        handle_init if @cycles == @init_threshold
+        feed_keyboard if @pending_keys
+
+        clock_bits = @clock_bits
+        @clock_bits = @vic.clock_bits
+        @vic.test_step! if clock_bits >= 0x02
+
+        @vic.cycle!
+        @cia1.cycle!
+        @cia2.cycle!
+        @sid.cycle!
+        @datasette.cycle!
+        @vdc.cycle!
+
+        @z80.int = @cia1.interrupted? || @vic.interrupted?
+        nmi = @cia2.interrupted? || @cartridge_nmi || @restore_pulse
+        @restore_pulse = false
+        @nmi_asserted = nmi
+        @z80.nmi = nmi
+        clock_serial_bus
+
+        @cycles += 1
+      end
+
+      # MCR bit 0 handed the bus to the other CPU. The 8502 runs its reset
+      # vector the first time it gets the bus after a reset.
+      def processor_changed
+        @z80_running = @bus.z80?
+        @z80_turn = @z80_running || @chips_ahead.positive?
+        @z80_due = @z80.cycles
+        return if @z80_running || !@cpu_reset_pending
+
+        @cpu_reset_pending = false
+        @cpu.reset!
+      end
+
+      # The RES line reaches the Z80, and the 8502 waits for the bus to run
+      # its reset vector, unless the machine resets into C64 mode.
+      def reset_z80
+        @chips_ahead = 0
+        @z80_turn = @z80_running
+        @z80.reset!
+        @c64_built ? @cpu.reset! : @cpu_reset_pending = true
+      end
+    end
+  end
+end

data/lib/badline/c128.rb

@@ -4,25 +4,33 @@ require "badline/c128/model"
 require "badline/c128/mmu"
 require "badline/c128/vdc"
 require "badline/c128/mmu_pages"
+require "badline/c128/io_pages"
+require "badline/c128/z80_pages"
 require "badline/c128/color_lines"
 require "badline/c128/banks"
 require "badline/c128/bus_state"
 require "badline/c128/bus"
 require "badline/c128/cpu"
+require "badline/c128/z80"
+require "badline/c128/z80_turns"
 require "badline/c128/saved_state"
 require "badline/c128/keys"
 require "badline/c128/modes"
+require "badline/c128/drives"
+require "badline/c128/fast_serial"
+require "badline/drive1571"
 
 module Badline
   # The Commodore 128: the 8502 on the VIC-IIe's clock, two CIAs, the SID,
   # the VDC and its 80 column display, and 128K of RAM, which the 8722 MMU
   # maps (C128::Bus).
   #
-  # Built for C128 mode, it runs BASIC 7.0 and the C128 KERNAL from reset.
-  # The C128's Z80 runs first and hands the bus to the 8502, but here the
-  # 8502 starts at its reset vector, with the MMU as the Z80 leaves it.
-  # The KERNAL goes to C64 mode as on the C128, with C= held at reset, a
-  # C64 cartridge or GO64.
+  # Built for C128 mode, it powers on as the C128 does: the Z80 runs the
+  # boot code in its BIOS and hands the bus to the 8502, which then runs
+  # its reset vector into BASIC 7.0 and the C128 KERNAL. The KERNAL goes
+  # to C64 mode as on the C128, with C= held at reset, a C64 cartridge or
+  # GO64. MCR bit 0 hands the bus back and forth from then on, and the
+  # Z80 runs 2 T-states in each cycle the VIC leaves it the bus.
   #
   # Built for C64 mode, the default, it powers on in C64 mode, the state
   # the C128 KERNAL reaches when C= is held at power-on, and a reset comes
@@ -40,6 +48,9 @@ module Badline
     include Computer::KernalTraps
     include Keys
     include Modes
+    include Drives
+    include FastSerial
+    include Z80Turns
 
     # The C64's 8x8 matrix and the three rows K0-K2 select, in port B
     # column order.
@@ -111,6 +122,7 @@ module Badline
       @holding_commodore = false
       @bus = Bus.new(@model, sid_model: sid_model || @model.sid_model, mode:)
       @cpu = CPU.new(@bus, debug:)
+      build_z80
       @vic = @bus.vic
       @vic.open_bus = -> { @bus.ram.peek(@cpu.program_counter) }
       @cia1 = @bus.cia1
@@ -125,12 +137,8 @@ module Badline
       @restore_pulse = false
       @init_handlers = []
       @pending_keys = nil
-      @drive = nil
-      @serial_trap = nil
-      @save_trap = nil
-      @drive1541 = nil
       @capture_output = nil
-      plug_serial_bus
+      init_drives
       enter_c64_mode if @c64_built
       @bus.on_mode_change { mode_changed }
     end
@@ -140,6 +148,8 @@ module Badline
     # mode the CPU runs in both halves of the cycle (#clock_fast), and the
     # TEST bit steps the raster counter in every cycle.
     def cycle!
+      return z80_cycle! if @z80_turn
+
       handle_init if @cycles == @init_threshold
       feed_keyboard if @pending_keys
 
@@ -158,7 +168,7 @@ module Badline
 
       drive_nmi
       clock_bits.odd? ? clock_fast : clock_cpu
-      @drive1541&.host_cycle!
+      clock_serial_bus
 
       @cycles += 1
     end
@@ -230,7 +240,7 @@ module Badline
     end
 
     # The RES line reaches the CPU and its port, the MMU, both CIAs, the
-    # SID, the cartridge port and, through the serial bus, the drive.
+    # SID, the cartridge port and, through the serial bus, the drives.
     def reset!
       @bus.reset!
       @cia1.reset!
@@ -239,8 +249,10 @@ module Badline
       @bus.cartridge&.reset
       @drive&.reset!
       @drive1541&.reset!
+      @drive1571&.reset!
+      @drive1581&.reset!
       @nmi_asserted = false
-      @cpu.reset!
+      reset_z80
     end
 
     # CHROUT is at $FFD2 in both KERNALs, and the trap follows the mode.
@@ -303,18 +315,5 @@ module Badline
     def handle_init
       @init_handlers.each(&:call)
     end
-
-    # The keyboard buffer of the KERNAL the machine runs: the C64's, or in
-    # C128 mode BASIC 7.0's.
-    def feed_keyboard
-      c64 = mode == :c64
-      count = c64 ? KeyboardBuffer::COUNT : C128_KEYBOARD_COUNT
-      return unless ram.peek(count).zero?
-
-      chunk = @pending_keys.shift(KeyboardBuffer::CAPACITY)
-      ram.write(c64 ? KeyboardBuffer::ADDRESS : C128_KEYBOARD_BUFFER, chunk)
-      ram.poke(count, chunk.length)
-      @pending_keys = nil if @pending_keys.empty?
-    end
   end
 end

data/lib/badline/cartridge/action_replay.rb

@@ -65,12 +65,12 @@ module Badline
       private
 
       def save_mapper(out)
-        save_windows(out, windows)
+        super
         out.int(window_index(@rom, windows)).boolean(@active).boolean(@io2_ram).blob(@ram_data)
       end
 
       def load_mapper(input)
-        load_windows(input, windows)
+        super
         @rom = window_at(input.int, windows)
         @active = input.boolean?
         @io2_ram = input.boolean?

data/lib/badline/cartridge/comal80.rb

@@ -33,13 +33,7 @@ module Badline
 
       private
 
-      def save_mapper(out)
-        save_windows(out, [*@roml_banks, *@romh_banks, EMPTY_BANK])
-      end
-
-      def load_mapper(input)
-        load_windows(input, [*@roml_banks, *@romh_banks, EMPTY_BANK])
-      end
+      def windows = [*@roml_banks, *@romh_banks, EMPTY_BANK]
 
       def select(number, mode)
         @roml = bank(@roml_banks, number)

data/lib/badline/cartridge/dinamic.rb

@@ -24,14 +24,6 @@ module Badline
 
       private
 
-      def save_mapper(out)
-        save_windows(out, [*@banks, EMPTY_BANK])
-      end
-
-      def load_mapper(input)
-        load_windows(input, [*@banks, EMPTY_BANK])
-      end
-
       def install_chips(chips)
         @banks = banks_from(chips).first
         self.mode = :rom8k

data/lib/badline/cartridge/final_cartridge3.rb

@@ -49,31 +49,31 @@ module Badline
         @phi1_ultimax = false
         self.nmi = false
         select(0)
-        self.mode = :rom16k
-        changed!
+        select_mode(:rom16k)
       end
 
       def freeze!
         @register_visible = true
         @phi1_ultimax = false
-        self.mode = :ultimax
-        changed!
+        select_mode(:ultimax)
       end
 
       private
 
       def save_mapper(out)
-        save_windows(out, [*@roml_banks, *@romh_banks, EMPTY_BANK])
+        super
         out.boolean(@register_visible).boolean(@phi1_ultimax)
       end
 
       def load_mapper(input)
-        load_windows(input, [*@roml_banks, *@romh_banks, EMPTY_BANK])
+        super
         @io_bank = @roml
         @register_visible = input.boolean?
         @phi1_ultimax = input.boolean?
       end
 
+      def windows = [*@roml_banks, *@romh_banks, EMPTY_BANK]
+
       def select(number)
         @io_bank = @roml = bank(@roml_banks, number)
         @romh = bank(@romh_banks, number)

data/lib/badline/cartridge/fun_play.rb

@@ -28,14 +28,6 @@ module Badline
 
       private
 
-      def save_mapper(out)
-        save_windows(out, [*@banks, EMPTY_BANK])
-      end
-
-      def load_mapper(input)
-        load_windows(input, [*@banks, EMPTY_BANK])
-      end
-
       def install_chips(chips)
         @banks = []
         chips.each { |chip| @banks[self.class.bank_number(chip.bank)] = rom_bank(chip.data) }

data/lib/badline/cartridge/game_system.rb

@@ -25,14 +25,6 @@ module Badline
 
       private
 
-      def save_mapper(out)
-        save_windows(out, [*@banks, EMPTY_BANK])
-      end
-
-      def load_mapper(input)
-        load_windows(input, [*@banks, EMPTY_BANK])
-      end
-
       def select(addr)
         @roml = bank(@banks, addr & 0x3f)
         changed!

data/lib/badline/cartridge/kcs_power.rb

@@ -26,7 +26,7 @@ module Badline
 
       def peek(addr)
         if addr < 0xdf00
-          switch(addr.anybits?(0x02) ? :off : :rom8k)
+          select_mode(addr.anybits?(0x02) ? :off : :rom8k)
           @roml.peek(IO1_ROM_PAGE | (addr & 0xff))
         elsif addr.anybits?(0x80)
           (@exrom << 7) | (@game << 6) | (open_bus(addr) & 0x3f)
@@ -37,7 +37,7 @@ module Badline
 
       def poke(addr, value)
         if addr < 0xdf00
-          switch(addr.anybits?(0x02) ? :ultimax : :rom16k)
+          select_mode(addr.anybits?(0x02) ? :ultimax : :rom16k)
         elsif addr.nobits?(0x80)
           @io_ram[addr & 0x7f] = value
         end
@@ -45,19 +45,22 @@ module Badline
 
       def reset
         self.nmi = false
-        switch(:rom16k)
+        select_mode(:rom16k)
       end
 
       def freeze!
         self.nmi = false
-        switch(:ultimax)
+        select_mode(:ultimax)
       end
 
       private
 
-      def switch(mode)
-        self.mode = mode
-        changed!
+      def save_mapper(out)
+        out.blob(@io_ram)
+      end
+
+      def load_mapper(input)
+        input.blob_into(@io_ram)
       end
 
       def install_chips(chips)

data/lib/badline/cartridge/mach5.rb

@@ -14,13 +14,11 @@ module Badline
       end
 
       def poke(addr, _value)
-        self.mode = addr < 0xdf00 ? :rom8k : :off
-        changed!
+        select_mode(addr < 0xdf00 ? :rom8k : :off)
       end
 
       def reset
-        self.mode = :rom8k
-        changed!
+        select_mode(:rom8k)
       end
 
       private

data/lib/badline/cartridge/magic_desk.rb

@@ -20,14 +20,6 @@ module Badline
 
       private
 
-      def save_mapper(out)
-        save_windows(out, [*@banks, EMPTY_BANK])
-      end
-
-      def load_mapper(input)
-        load_windows(input, [*@banks, EMPTY_BANK])
-      end
-
       def install_chips(chips)
         @banks = banks_from(chips).first
         @bank_mask = (bank_mask(@banks) | 0x03) & 0x7f