badline 0.11.0 → 0.12.0

data/lib/badline/via/fast_forward.rb

@@ -3,14 +3,14 @@
 module Badline
   class VIA
     # Running a VIA a stretch of cycles at once while nothing but its
-    # counters would change, for Drive1541::Idle.
+    # counters would change, for Drive::Idle.
     module FastForward
       # quiet_cycles for a VIA that will never set a flag of its own.
       QUIET = 1 << 40
 
       # How many cycles the VIA can run with nothing but its counters
       # changing: no flag set, no pulse on a control line and no bit
-      # shifted. See Drive1541::Idle.
+      # shifted. See Drive::Idle.
       def quiet_cycles
         return 0 if @sr_uses_t2 || @shift_register.clocking? || @ca.pulsing? || @cb.pulsing?
 
@@ -26,7 +26,7 @@ module Badline
         @t2.fast_forward(cycles)
       end
 
-      # The counters an orbit (see Drive1541::Idle) has to bring back: those
+      # The counters an orbit (see Drive::Idle) has to bring back: those
       # of the armed timers, and of the timers +touched+ names (bit 0 for
       # timer 1, bit 1 for timer 2). The others only count.
       def counter_state(touched)

data/lib/badline/vic20/attachments.rb

@@ -4,8 +4,10 @@ module Badline
   class Vic20
     # What plugs into the VIC-20 besides its chips: cartridge ROM in the
     # expansion blocks, the disk device 8 serves through the KERNAL traps,
-    # and a true 1541 on the serial bus.
+    # and a true 1541 or 1581 on the serial bus.
     module Attachments
+      include Drive1581::Slot
+
       # The cycle by which a 1541 switched on with the machine has run its
       # DOS's reset, the RAM test and the ROM checksum, and waits on the
       # bus, with a margin: about 1.1 million of the VIC-20's cycles.
@@ -48,7 +50,7 @@ module Badline
 
         cpu.remove_trap(KernalTrap::VIC20_LAYOUT.load)
         cpu.remove_trap(KernalTrap::VIC20_LAYOUT.save)
-        @serial_trap.device = nil
+        @serial_trap.uninstall
         @serial_trap = nil
         @save_trap = nil
         @drive = nil
@@ -75,6 +77,17 @@ module Badline
         @serial_trap&.device = serial_trap_device
       end
 
+      # The true drive on the serial bus: the Drive1581 ahead of the
+      # Drive1541, or nil.
+      def true_drive = @drive1581 || @drive1541
+
+      # Plugs a Drive1541 in as device 8, in place of a 1581 there, and
+      # returns it.
+      def plug_true_drive
+        detach_drive1581 if drive1581_on_device8?
+        Drive1541.new.tap { |drive| attach_drive1541(drive) }
+      end
+
       # Unplugs the Drive1541, leaving the serial bus with nothing on it.
       def detach_drive1541
         return unless @drive1541
@@ -96,7 +109,14 @@ module Badline
       # The device number the serial traps answer: device 8, unless a true
       # drive is on the bus as device 8.
       def serial_trap_device
-        @drive1541&.device == KernalTrap::Routine::DEVICE ? nil : KernalTrap::Routine::DEVICE
+        device = KernalTrap::Routine::DEVICE
+        @drive1541&.device == device || drive1581_on_device8? ? nil : device
+      end
+
+      # A 1581 plugged in, as a 1541 does, holds the machine's on_init
+      # handlers back until its DOS has booted.
+      def drive1581_attached
+        @init_threshold = [@init_threshold, Drive1581::BOOT_CYCLES].max if @cycles < @init_threshold
       end
     end
   end

data/lib/badline/vic20/saved_state.rb

@@ -78,6 +78,7 @@ module Badline
         @datasette.save_state(out)
         save_trap_drive(out)
         save_drive1541(out)
+        save_drive1581(out)
       end
 
       def load_state(input)
@@ -99,6 +100,7 @@ module Badline
         @datasette.load_state(input)
         load_trap_drive(input)
         load_drive1541(input)
+        load_drive1581(input)
       end
 
       private

data/lib/badline/vic20.rb

@@ -75,6 +75,7 @@ module Badline
       @save_trap = nil
       @capture_output = nil
       @drive1541 = nil
+      @drive1581 = nil
       @init_threshold = boot_cycles
       wire_ports
     end
@@ -94,6 +95,7 @@ module Badline
       drive_nmi
       @cpu.cycle!
       @drive1541&.host_cycle!
+      @drive1581&.host_cycle!
 
       @cycles += 1
     end
@@ -176,6 +178,7 @@ module Badline
       via_written
       @drive&.reset!
       @drive1541&.reset!
+      @drive1581&.reset!
       @nmi_asserted = false
       @cpu.reset!
     end

data/lib/badline/z80/arithmetic.rb

@@ -0,0 +1,117 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # The ALU's 8- and 16-bit arithmetic. Bits 5 and 3 of F come from the
+    # result, except for CP, which takes them from the operand, and the
+    # 16-bit operations, which take them from the high byte.
+    module Arithmetic
+      private
+
+      # The eight operations an opcode's bits 5-3 pick: ADD ADC SUB SBC AND
+      # XOR OR CP.
+      def alu(operation, value)
+        case operation
+        when 0 then add_a(value, 0)
+        when 1 then add_a(value, @f & CF)
+        when 2 then @a = subtract(value, 0)
+        when 3 then @a = subtract(value, @f & CF)
+        when 4 then logic(@a & value, HF)
+        when 5 then logic(@a ^ value, 0)
+        when 6 then logic(@a | value, 0)
+        else compare(value)
+        end
+      end
+
+      def add_a(value, carry)
+        result = @a + value + carry
+        assign_flags(SZ53[result & 0xff] | (result >> 8) | ((@a ^ value ^ result) & HF) |
+                  (((@a ^ value ^ 0x80) & (@a ^ result) & 0x80) >> 5))
+        @a = result & 0xff
+      end
+
+      def subtract(value, carry)
+        result = @a - value - carry
+        assign_flags(SZ53[result & 0xff] | NF | ((result >> 8) & CF) | ((@a ^ value ^ result) & HF) |
+                  (((@a ^ value) & (@a ^ result) & 0x80) >> 5))
+        result & 0xff
+      end
+
+      def compare(value)
+        subtract(value, 0)
+        assign_flags((@f & ~XYF) | (value & XYF))
+      end
+
+      def logic(result, half)
+        @a = result
+        assign_flags(SZ53P[result] | half)
+      end
+
+      def increment(value)
+        result = (value + 1) & 0xff
+        assign_flags((@f & CF) | SZ53[result] | (result == 0x80 ? PF : 0) | (result.nobits?(0x0f) ? HF : 0))
+        result
+      end
+
+      def decrement(value)
+        result = (value - 1) & 0xff
+        assign_flags((@f & CF) | NF | SZ53[result] | (result == 0x7f ? PF : 0) | (value.nobits?(0x0f) ? HF : 0))
+        result
+      end
+
+      def add16(left, right)
+        result = left + right
+        @wz = (left + 1) & 0xffff
+        assign_flags((@f & (SF | ZF | PF)) | ((result >> 8) & XYF) | (((left ^ right ^ result) >> 8) & HF) |
+                  (result >> 16))
+        result & 0xffff
+      end
+
+      def adc16(right)
+        left = hl
+        result = left + right + (@f & CF)
+        @wz = (left + 1) & 0xffff
+        self.hl = result & 0xffff
+        assign_flags(word_flags(result) | (((left ^ right ^ result) >> 8) & HF) |
+                  (((left ^ right ^ 0x8000) & (left ^ result) & 0x8000) >> 13))
+      end
+
+      def sbc16(right)
+        left = hl
+        result = left - right - (@f & CF)
+        @wz = (left + 1) & 0xffff
+        self.hl = result & 0xffff
+        assign_flags(word_flags(result) | NF | (((left ^ right ^ result) >> 8) & HF) |
+                  (((left ^ right) & (left ^ result) & 0x8000) >> 13))
+      end
+
+      def word_flags(result)
+        ((result >> 8) & (SF | XYF)) | (result.nobits?(0xffff) ? ZF : 0) | ((result >> 16) & CF)
+      end
+
+      def daa
+        low = @a & 0x0f
+        carry = @f.anybits?(CF) || @a > 0x99 ? CF : 0
+        correction = (carry.zero? ? 0 : 0x60) | (@f.anybits?(HF) || low > 9 ? 0x06 : 0)
+        subtracting = @f.anybits?(NF)
+        half = daa_half(low, subtracting)
+        @a = (subtracting ? @a - correction : @a + correction) & 0xff
+        assign_flags(SZ53P[@a] | (@f & NF) | carry | half)
+      end
+
+      def daa_half(low, subtracting)
+        if subtracting
+          @f.anybits?(HF) && low < 6 ? HF : 0
+        else
+          low > 9 ? HF : 0
+        end
+      end
+
+      def neg
+        value = @a
+        @a = 0
+        @a = subtract(value, 0)
+      end
+    end
+  end
+end

data/lib/badline/z80/bit_page.rb

@@ -0,0 +1,55 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # The CB page: rotates and shifts (quarter 0), BIT (1), RES (2) and SET
+    # (3) of the bit the row names, on the column's register or (HL). After
+    # DD or FD the operand is always (IX+d): the displacement comes before
+    # the opcode, and an opcode that names a register other than (HL) also
+    # copies the result into it.
+    module BitPage
+      private
+
+      def execute_bits(opcode)
+        operation = opcode >> 6
+        number = (opcode >> 3) & 7
+        index = opcode & 7
+        return bits_in_memory(operation, number, hl) if index == 6
+
+        value = register(index)
+        if operation == 1
+          bit(number, value, value)
+        else
+          set_register(index, bit_result(operation, number, value))
+        end
+      end
+
+      def execute_index_bits
+        displaced
+        opcode = fetch_byte
+        @cycles += 2
+        result = bits_in_memory(opcode >> 6, (opcode >> 3) & 7, @wz)
+        index = opcode & 7
+        set_plain_register(index, result) unless index == 6 || (opcode >> 6) == 1
+      end
+
+      def bits_in_memory(operation, number, address)
+        value = read_byte(address)
+        @cycles += 1
+        return bit(number, value, @wz >> 8) if operation == 1
+
+        result = bit_result(operation, number, value)
+        write_byte(address, result)
+        result
+      end
+
+      def bit_result(operation, number, value)
+        case operation
+        when 0 then shift(number, value)
+        when 2 then value & ~(1 << number) & 0xff
+        else value | (1 << number)
+        end
+      end
+    end
+  end
+end

data/lib/badline/z80/block_io.rb

@@ -0,0 +1,58 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # INI, IND, OUTI, OUTD and their repeating forms. B counts the bytes
+    # and sets S, Z, 5 and 3. The byte's bit 7 sets N, and adding it to C
+    # plus or minus one for INI and IND, or to L for OUTI and OUTD, sets H
+    # and C on a carry out and P/V from the parity of its low 3 bits
+    # exclusive-ored with B.
+    module BlockIO
+      private
+
+      def block_input(step, repeat)
+        @cycles += 1
+        port = bc
+        value = input(port)
+        @wz = (port + step) & 0xffff
+        @b = (@b - 1) & 0xff
+        write_byte(hl, value)
+        self.hl = (hl + step) & 0xffff
+        block_io_flags(value, value + ((@c + step) & 0xff), repeat)
+      end
+
+      def block_output(step, repeat)
+        @cycles += 1
+        value = read_byte(hl)
+        @b = (@b - 1) & 0xff
+        output(bc, value)
+        self.hl = (hl + step) & 0xffff
+        @wz = (bc + step) & 0xffff
+        block_io_flags(value, value + @l, repeat)
+      end
+
+      def block_io_flags(value, sum, repeat)
+        carry = sum > 0xff ? HF | CF : 0
+        assign_flags(SZ53[@b] | ((value >> 6) & NF) | carry | PARITY[(sum & 7) ^ @b])
+        return unless repeat && !@b.zero?
+
+        repeat_block
+        repeat_io_flags(value, carry)
+      end
+
+      def repeat_io_flags(value, carry)
+        flags = @f & ~HF
+        if carry.zero?
+          flags ^= PARITY[@b & 7] ^ PF
+        elsif value.anybits?(0x80)
+          flags ^= PARITY[(@b - 1) & 7] ^ PF
+          flags |= HF if @b.nobits?(0x0f)
+        else
+          flags ^= PARITY[(@b + 1) & 7] ^ PF
+          flags |= HF if @b.allbits?(0x0f)
+        end
+        assign_flags(flags)
+      end
+    end
+  end
+end

data/lib/badline/z80/block_transfers.rb

@@ -0,0 +1,59 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # LDI, LDD, CPI, CPD and their repeating forms. A repeating form that
+    # goes round again winds the program counter back to its ED and spends
+    # 5 T-states more, and bits 5 and 3 then come from the program
+    # counter's high byte.
+    module BlockTransfers
+      private
+
+      # ED A0-BB: the column picks LD, CP, IN or OUT, bit 3 counts down, and
+      # bit 4 repeats.
+      def block_operation(opcode)
+        step = opcode.nobits?(0x08) ? 1 : -1
+        repeat = opcode.anybits?(0x10)
+        case opcode & 3
+        when 0 then block_load(step, repeat)
+        when 1 then block_compare(step, repeat)
+        when 2 then block_input(step, repeat)
+        else block_output(step, repeat)
+        end
+      end
+
+      def block_load(step, repeat)
+        value = read_byte(hl)
+        write_byte(de, value)
+        @cycles += 2
+        self.hl = (hl + step) & 0xffff
+        self.de = (de + step) & 0xffff
+        self.bc = (bc - 1) & 0xffff
+        sum = value + @a
+        assign_flags((@f & (SF | ZF | CF)) | (sum & XF) | ((sum & 0x02) << 4) | (bc.zero? ? 0 : PF))
+        repeat_block if repeat && !bc.zero?
+      end
+
+      def block_compare(step, repeat)
+        value = read_byte(hl)
+        @cycles += 5
+        result = (@a - value) & 0xff
+        half = (@a ^ value ^ result) & HF
+        adjusted = result - (half >> 4)
+        self.hl = (hl + step) & 0xffff
+        self.bc = (bc - 1) & 0xffff
+        @wz = (@wz + step) & 0xffff
+        assign_flags((@f & CF) | NF | half | (SZ53[result] & (SF | ZF)) | (adjusted & XF) | ((adjusted & 0x02) << 4) |
+                  (bc.zero? ? 0 : PF))
+        repeat_block if repeat && !bc.zero? && !result.zero?
+      end
+
+      def repeat_block
+        @cycles += 5
+        @pc = (@pc - 2) & 0xffff
+        @wz = (@pc + 1) & 0xffff
+        assign_flags((@f & ~XYF) | ((@pc >> 8) & XYF))
+      end
+    end
+  end
+end

data/lib/badline/z80/bus_cycles.rb

@@ -0,0 +1,111 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # The machine cycles that reach the bus. An opcode fetch (M1) takes 4
+    # T-states and refreshes a row of DRAM, which counts up the low 7 bits
+    # of R. A memory read or write takes 3, and an I/O read or write 4,
+    # one of them the wait state the Z80 inserts itself. Each calls the bus
+    # on its first T-state, and T-states the CPU spends inside lengthen
+    # the machine cycle before them.
+    module BusCycles
+      private
+
+      def fetch_opcode
+        opcode = @bus.fetch(@pc)
+        @pc = (@pc + 1) & 0xffff
+        refresh
+        @cycles += 4
+        opcode
+      end
+
+      # A halted CPU fetches from the address after HALT, again and again,
+      # and leaves the program counter there.
+      def idle_fetch
+        @bus.fetch(@pc)
+        refresh
+        @cycles += 4
+      end
+
+      def refresh
+        @r = (@r & 0x80) | ((@r + 1) & 0x7f)
+      end
+
+      def read_byte(address)
+        value = @bus.read(address)
+        @cycles += 3
+        value
+      end
+
+      def write_byte(address, value)
+        @bus.write(address, value)
+        @cycles += 3
+      end
+
+      def read_word(address)
+        low = read_byte(address)
+        low | (read_byte((address + 1) & 0xffff) << 8)
+      end
+
+      def write_word(address, value)
+        write_byte(address, value & 0xff)
+        write_byte((address + 1) & 0xffff, value >> 8)
+      end
+
+      def input(port)
+        value = @bus.input(port)
+        @cycles += 4
+        value
+      end
+
+      def output(port, value)
+        @bus.output(port, value)
+        @cycles += 4
+      end
+
+      # The byte after the opcode.
+      def fetch_byte
+        value = read_byte(@pc)
+        @pc = (@pc + 1) & 0xffff
+        value
+      end
+
+      def fetch_word
+        low = fetch_byte
+        low | (fetch_byte << 8)
+      end
+
+      def push(value)
+        @sp = (@sp - 1) & 0xffff
+        write_byte(@sp, value >> 8)
+        @sp = (@sp - 1) & 0xffff
+        write_byte(@sp, value & 0xff)
+      end
+
+      def pop
+        low = read_byte(@sp)
+        high = read_byte((@sp + 1) & 0xffff)
+        @sp = (@sp + 2) & 0xffff
+        low | (high << 8)
+      end
+
+      # The address of an (HL) operand, or of (IX+d), whose displacement is
+      # read from after the opcode and added in 5 T-states inside.
+      def operand_address
+        return hl if @prefix.zero?
+
+        displaced
+        @cycles += 5
+        @wz
+      end
+
+      # Reads the displacement of an (IX+d) or (IY+d) operand and leaves
+      # the address in WZ.
+      def displaced
+        offset = fetch_byte
+        offset -= 256 if offset > 127
+        @wz = (index_register + offset) & 0xffff
+      end
+    end
+  end
+end

data/lib/badline/z80/core.rb

@@ -0,0 +1,113 @@
+# frozen_string_literal: true
+
+require "badline/z80/flags"
+require "badline/z80/registers"
+require "badline/z80/bus_cycles"
+require "badline/z80/arithmetic"
+require "badline/z80/shifts"
+require "badline/z80/loads"
+require "badline/z80/exchanges"
+require "badline/z80/jumps"
+require "badline/z80/main_page"
+require "badline/z80/bit_page"
+require "badline/z80/extended_page"
+require "badline/z80/block_transfers"
+require "badline/z80/block_io"
+require "badline/z80/interrupt_acceptance"
+require "badline/z80/saved_state"
+
+module Badline
+  class Z80
+    # The Z80 core, on whatever bus +bus+ is. The bus answers
+    # fetch(address) for an opcode fetch (M1), read(address) and
+    # write(address, value) for memory, input(port) and output(port, value)
+    # for I/O, and acknowledge for the byte a device puts on the data bus
+    # when the CPU takes a maskable interrupt.
+    #
+    # #step! runs one instruction, prefixes and all, or takes an interrupt,
+    # or idles one opcode fetch while halted. #cycles counts T-states, and
+    # each bus call happens while it holds the T-state its machine cycle
+    # starts on.
+    module Core
+      include Flags
+      include Registers
+      include BusCycles
+      include Arithmetic
+      include Shifts
+      include Loads
+      include Exchanges
+      include Jumps
+      include MainPage
+      include BitPage
+      include ExtendedPage
+      include BlockTransfers
+      include BlockIO
+      include InterruptAcceptance
+      include SavedState
+
+      attr_reader :bus, :cycles, :nmi
+      attr_accessor :int
+
+      def initialize(bus)
+        @bus = bus
+        @cycles = 0
+        @a = @f = 0xff
+        @b = @c = @d = @e = @h = @l = 0xff
+        @af_alt = @bc_alt = @de_alt = @hl_alt = 0xffff
+        @ix = @iy = @sp = 0xffff
+        @wz = @q = @last_q = 0
+        @prefix = 0
+        @int = @nmi = @nmi_pending = false
+        reset!
+      end
+
+      # The RESET line: the program counter, I, R and the interrupt mode go
+      # to 0, and interrupts are disabled.
+      def reset!
+        @pc = @i = @r = @im = 0
+        @iff1 = @iff2 = false
+        @halted = @after_ei = @after_ld_a_ir = false
+        @nmi_pending = false
+      end
+
+      # The NMI line. Asserting it latches an interrupt, taken after the
+      # current instruction, and holding it does nothing more.
+      def nmi=(asserted)
+        @nmi_pending = true if asserted && !@nmi
+        @nmi = asserted
+      end
+
+      # The WAIT line: a bus that holds it during an access lengthens that
+      # machine cycle by +states+ T-states.
+      def wait(states)
+        @cycles += states
+      end
+
+      def step!
+        if @nmi_pending
+          take_nmi
+        elsif @int && @iff1 && !@after_ei
+          take_int
+        else
+          @after_ei = @after_ld_a_ir = false
+          @last_q = @q
+          @q = 0
+          @prefix = 0
+          @halted ? idle_fetch : execute(fetch_opcode)
+        end
+        nil
+      end
+
+      def inspect
+        "Cycles: #{@cycles}, PC: #{hex(@pc)}, SP: #{hex(@sp)}, AF: #{hex(af)}, BC: #{hex(bc)}, " \
+          "DE: #{hex(de)}, HL: #{hex(hl)}, IX: #{hex(@ix)}, IY: #{hex(@iy)}"
+      end
+
+      private
+
+      def hex(value)
+        value.to_s(16).rjust(4, "0")
+      end
+    end
+  end
+end

data/lib/badline/z80/exchanges.rb

@@ -0,0 +1,50 @@
+# frozen_string_literal: true
+
+module Badline
+  class Z80
+    # EX AF,AF', EXX, EX DE,HL and EX (SP),HL. Only the last swaps IX or IY
+    # after a prefix.
+    module Exchanges
+      private
+
+      def exchange_alternates
+        bc_alt = @bc_alt
+        de_alt = @de_alt
+        hl_alt = @hl_alt
+        @bc_alt = bc
+        @de_alt = de
+        @hl_alt = hl
+        self.bc = bc_alt
+        self.de = de_alt
+        self.hl = hl_alt
+      end
+
+      def exchange_af
+        af_alt = @af_alt
+        @af_alt = af
+        self.af = af_alt
+      end
+
+      def exchange_de_hl
+        d = @d
+        e = @e
+        @d = @h
+        @e = @l
+        @h = d
+        @l = e
+      end
+
+      def exchange_stack_top
+        low = read_byte(@sp)
+        high = read_byte((@sp + 1) & 0xffff)
+        @cycles += 1
+        value = hl_or_index
+        write_byte((@sp + 1) & 0xffff, value >> 8)
+        write_byte(@sp, value & 0xff)
+        @cycles += 2
+        @wz = low | (high << 8)
+        self.hl_or_index = @wz
+      end
+    end
+  end
+end