badline 0.1.0

data/lib/badline/instruction_set/inc_dec.rb

@@ -0,0 +1,71 @@
+# frozen_string_literal: true
+
+module Badline
+  module InstructionSet
+    module IncDec
+      # Decrements memory location by one.
+      #
+      # Opcodes:
+      #   $C6 - zeropage   - 5 cycles
+      #   $CE - absolute   - 6 cycles
+      #   $D6 - zeropage_x - 6 cycles
+      #   $DE - absolute_x - 7 cycles
+      def dec(addr, value)
+        v = resolve(value)
+        result = (v - 1) & 0xff
+        write_modified(addr, v, result)
+        update_number_flags(result)
+      end
+
+      # Decrements X register by one.
+      #
+      # Opcodes:
+      #   $CA - implied - 2 cycles
+      def dex(_addr, _value)
+        cycle { @x = (@x - 1) & 0xff }
+        update_number_flags(@x)
+      end
+
+      # Decrements Y register by one.
+      #
+      # Opcodes:
+      #   $88 - implied - 2 cycles
+      def dey(_addr, _value)
+        cycle { @y = (@y - 1) & 0xff }
+        update_number_flags(@y)
+      end
+
+      # Increments memory location by one.
+      #
+      # Opcodes:
+      #   $E6 - zeropage   - 5 cycles
+      #   $EE - absolute   - 6 cycles
+      #   $F6 - zeropage_x - 6 cycles
+      #   $FE - absolute_x - 7 cycles
+      def inc(addr, value)
+        v = resolve(value)
+        result = (v + 1) & 0xff
+        write_modified(addr, v, result)
+        update_number_flags(result)
+      end
+
+      # Increments X register by one.
+      #
+      # Opcodes:
+      #   $E8 - implied - 2 cycles
+      def inx(_addr, _value)
+        cycle { @x = (@x + 1) & 0xff }
+        update_number_flags(@x)
+      end
+
+      # Increments Y register by one.
+      #
+      # Opcodes:
+      #   $C8 - implied - 2 cycles
+      def iny(_addr, _value)
+        cycle { @y = (@y + 1) & 0xff }
+        update_number_flags(@y)
+      end
+    end
+  end
+end

data/lib/badline/instruction_set/stack.rb

@@ -0,0 +1,104 @@
+# frozen_string_literal: true
+
+module Badline
+  module InstructionSet
+    module Stack
+      # Push accumulator onto the stack.
+      #
+      # Opcodes:
+      #   $48 - implied - 3 cycles
+      def pha(_addr, _value)
+        stack_push(@a)
+      end
+
+      # Push processor status onto the stack.
+      #
+      # Opcodes:
+      #   $08 - implied - 3 cycles
+      def php(_addr, _value)
+        stack_push(p | 0b00010000)
+      end
+
+      # Pull accumulator from stack.
+      #
+      # Opcodes:
+      #   $68 - implied - 4 cycles
+      def pla(_addr, _value)
+        cycle { @a = stack_pull }
+        update_number_flags(@a)
+      end
+
+      # Pull processor status from stack.
+      #
+      # Opcodes:
+      #   $28 - implied - 4 cycles
+      def plp(_addr, _value)
+        cycle { status.value = stack_pull & 0b11101111 }
+      end
+
+      # Jump to absolute address.
+      #
+      # Opcodes:
+      #   $4C - absolute - 3 cycles
+      def jmp(addr, _value)
+        @program_counter = addr
+      end
+
+      # Jump to subroutine. The operand high byte is fetched only after the
+      # return address has been pushed, so a JSR executing inside the stack
+      # jumps via the value its own push just wrote.
+      #
+      # Opcodes:
+      #   $20 - absolute - 6 cycles
+      def jsr(addr, _value)
+        return_addr = (program_counter - 1) & 0xffff
+        cycle { @memory.peek(stack_address) } # internal cycle: dummy stack read
+        write_byte(stack_address, high_byte(return_addr))
+        write_byte(stack_address(-1), low_byte(return_addr))
+        @stack_pointer = (@stack_pointer - 2) & 0xff
+        @program_counter = uint16(addr, read_byte(return_addr))
+      end
+
+      # Return from interrupt.
+      #
+      # Opcodes:
+      #   $40 - implied - 6 cycles
+      def rti(_addr, _value)
+        cycle do
+          @stack_pointer = (@stack_pointer + 1) & 0xff
+          @status.value = memory[stack_address]
+          @status.break = false
+        end
+        @program_counter = uint16(stack_pull, stack_pull)
+      end
+
+      # Return from subroutine.
+      #
+      # Opcodes:
+      #   $60 - implied - 6 cycles
+      def rts(_addr, _value)
+        cycle do
+          @program_counter = (uint16(stack_pull, stack_pull) + 1) & 0xffff
+        end
+      end
+
+      private
+
+      def stack_pull
+        cycle { @stack_pointer = (@stack_pointer + 1) & 0xff }
+        read_byte(stack_address)
+      end
+
+      def stack_push(value)
+        write_byte(stack_address, value)
+        cycle { @stack_pointer = (@stack_pointer - 1) & 0xff }
+      end
+
+      def stack_push16(value)
+        write_byte(stack_address, high_byte(value))
+        write_byte(stack_address(-1), low_byte(value))
+        cycle { @stack_pointer = (@stack_pointer - 2) & 0xff }
+      end
+    end
+  end
+end

data/lib/badline/instruction_set/transfer.rb

@@ -0,0 +1,137 @@
+# frozen_string_literal: true
+
+module Badline
+  module InstructionSet
+    module Transfer
+      # +begin_src ruby
+      # Load accumulator with memory.
+      #
+      # Opcodes:
+      #   $A1 - indirect_x - 6 cycles
+      #   $A5 - zeropage   - 3 cycles
+      #   $A9 - immediate  - 2 cycles
+      #   $AD - absolute   - 4 cycles
+      #   $B1 - indirect_y - 5+ cycles
+      #   $B5 - zeropage_x - 4 cycles
+      #   $B9 - absolute_y - 4+ cycles
+      #   $BD - absolute_x - 4+ cycles
+      def lda(_addr, value)
+        @a = resolve(value)
+        update_number_flags(@a)
+      end
+
+      # Load X register with memory.
+      #
+      # Opcodes:
+      #   $A2 - immediate  - 2 cycles
+      #   $A6 - zeropage   - 3 cycles
+      #   $AE - absolute   - 4 cycles
+      #   $B6 - zeropage_y - 4 cycles
+      #   $BE - absolute_y - 4+ cycles
+      def ldx(_addr, value)
+        @x = resolve(value)
+        update_number_flags(@x)
+      end
+
+      # Load Y register with memory.
+      #
+      # Opcodes:
+      #   $A0 - immediate  - 2 cycles
+      #   $A4 - zeropage   - 3 cycles
+      #   $AC - absolute   - 4 cycles
+      #   $B4 - zeropage_x - 4 cycles
+      #   $BC - absolute_x - 4+ cycles
+      def ldy(_addr, value)
+        @y = resolve(value)
+        update_number_flags(@y)
+      end
+
+      # Store accumulator in memory.
+      #
+      # Opcodes:
+      #   $81 - indirect_x - 6 cycles
+      #   $85 - zeropage   - 3 cycles
+      #   $8D - absolute   - 4 cycles
+      #   $91 - indirect_y - 6 cycles
+      #   $95 - zeropage_x - 4 cycles
+      #   $99 - absolute_y - 5 cycles
+      #   $9D - absolute_x - 5 cycles
+      def sta(addr, _value)
+        write_byte(addr, @a)
+      end
+
+      # Store X register in memory.
+      #
+      # Opcodes:
+      #   $86 - zeropage   - 3 cycles
+      #   $8E - absolute   - 4 cycles
+      #   $96 - zeropage_y - 4 cycles
+      def stx(addr, _value)
+        write_byte(addr, @x)
+      end
+
+      # Store Y register in memory.
+      #
+      # Opcodes:
+      #   $84 - zeropage   - 3 cycles
+      #   $8C - absolute   - 4 cycles
+      #   $94 - zeropage_x - 4 cycles
+      def sty(addr, _value)
+        write_byte(addr, @y)
+      end
+
+      # Transfer accumulator to X register.
+      #
+      # Opcodes:
+      #   $AA - implied - 2 cycles
+      def tax(_addr, _value)
+        cycle { @x = a }
+        update_number_flags(@x)
+      end
+
+      # Transfer accumulator to Y register.
+      #
+      # Opcodes:
+      #   $A8 - implied - 2 cycles
+      def tay(_addr, _value)
+        cycle { @y = a }
+        update_number_flags(@y)
+      end
+
+      # Transfer stack pointer to X register.
+      #
+      # Opcodes:
+      #   $BA - implied - 2 cycles
+      def tsx(_addr, _value)
+        cycle { @x = stack_pointer }
+        update_number_flags(@x)
+      end
+
+      # Transfer X register to accumulator.
+      #
+      # Opcodes:
+      #   $8A - implied - 2 cycles
+      def txa(_addr, _operand)
+        cycle { @a = x }
+        update_number_flags(@a)
+      end
+
+      # Transfer X register to stack pointer.
+      #
+      # Opcodes:
+      #   $9A - implied - 2 cycles
+      def txs(_addr, _operand)
+        cycle { @stack_pointer = x }
+      end
+
+      # Transfer Y register to accumulator.
+      #
+      # Opcodes:
+      #   $98 - implied - 2 cycles
+      def tya(_addr, _operand)
+        cycle { @a = y }
+        update_number_flags(@a)
+      end
+    end
+  end
+end

data/lib/badline/instruction_set.rb

@@ -0,0 +1,77 @@
+# frozen_string_literal: true
+
+require "badline/instruction_set/arithmetic"
+require "badline/instruction_set/bitwise"
+require "badline/instruction_set/branch"
+require "badline/instruction_set/inc_dec"
+require "badline/instruction_set/flag"
+require "badline/instruction_set/illegal"
+require "badline/instruction_set/stack"
+require "badline/instruction_set/transfer"
+
+module Badline
+  # http://www.6502.org/tutorials/6502opcodes.html
+  # http://www.e-tradition.net/bytes/6502/6502_instruction_set.html
+  module InstructionSet
+    include InstructionSet::Arithmetic
+    include InstructionSet::Bitwise
+    include InstructionSet::Branch
+    include InstructionSet::IncDec
+    include InstructionSet::Flag
+    include InstructionSet::Illegal
+    include InstructionSet::Stack
+    include InstructionSet::Transfer
+
+    # Forces a software interrupt (break).
+    # Pushes PC+2 and status to stack, sets break flag, and jumps via IRQ vector.
+    #
+    # Opcodes:
+    #   $00 - implied - 7 cycles
+    def brk(_addr, _value)
+      status.break = true
+      handle_interrupt(0xfffe, brk: true, pre_cycles: 1)
+      status.break = false
+    end
+
+    # No operation. Does nothing but consume a clock cycle.
+    #
+    # Opcodes:
+    #   $EA                          - implied    - 2 cycles
+    #   $04, $44, $64                - zeropage   - 3 cycles  (illegal)
+    #   $14, $34, $54, $74, $D4, $F4 - zeropage_x - 4 cycles  (illegal)
+    #   $0C                          - absolute   - 4 cycles  (illegal)
+    #   $1C, $3C, $5C, $7C, $DC, $FC - absolute_x - 4+ cycles (illegal)
+    #   $1A, $3A, $5A, $7A, $DA, $FA - implied    - 2 cycles  (illegal)
+    def nop(_addr, _value)
+      cycle
+    end
+
+    private
+
+    def resolve(value)
+      if value == :lazy
+        realize_value(@instruction, @operand, @address)
+      elsif value.is_a?(Proc)
+        value.call
+      else
+        value
+      end
+    end
+
+    def update_number_flags(value)
+      status.zero = value.zero?
+      status.negative = value.anybits?(0x80)
+      value
+    end
+
+    # Read-modify-write instructions put the unmodified value back on the bus before writing the result.
+    def write_modified(addr, original, result)
+      if addr == :accumulator
+        cycle { @a = result }
+      else
+        write_byte(addr, original)
+        write_byte(addr, result)
+      end
+    end
+  end
+end

data/lib/badline/integer_helper.rb

@@ -0,0 +1,39 @@
+# frozen_string_literal: true
+
+module Badline
+  module IntegerHelper
+    def bcd(number)
+      high, low = number.divmod(10)
+      (high << 4) + low
+    end
+
+    def bcd_to_i(number)
+      (((number & 0xf0) >> 4) * 10) + (number & 0x0f)
+    end
+
+    def format8(number)
+      "0x#{number.to_s(16).rjust(2, '0')}"
+    end
+
+    def format16(number)
+      "0x#{number.to_s(16).rjust(4, '0')}"
+    end
+
+    def high_byte(number)
+      (number >> 8) & 0xff
+    end
+
+    def low_byte(number)
+      number & 0xff
+    end
+
+    def signed_int8(number)
+      uint = number & 0xff
+      uint > 127 ? uint - 256 : uint
+    end
+
+    def uint16(low, high)
+      (high << 8) + low
+    end
+  end
+end

data/lib/badline/joystick.rb

@@ -0,0 +1,25 @@
+# frozen_string_literal: true
+
+module Badline
+  class Joystick
+    DIRECTIONS = { up: 0, down: 1, left: 2, right: 3, fire: 4 }.freeze
+
+    def initialize
+      @pressed = {}
+    end
+
+    def press(direction)
+      @pressed[direction] = true if DIRECTIONS.key?(direction)
+    end
+
+    def release(direction)
+      @pressed.delete(direction)
+    end
+
+    def port_bits
+      bits = 0xff
+      DIRECTIONS.each { |dir, bit| bits &= ~(1 << bit) if @pressed[dir] }
+      bits
+    end
+  end
+end

data/lib/badline/kernal_trap/file.rb

@@ -0,0 +1,54 @@
+# frozen_string_literal: true
+
+module Badline
+  module KernalTrap
+    class File
+      include IntegerHelper
+
+      DEVICE = 8
+
+      MISSING_FILENAME = 0x08
+
+      def initialize(cpu:, bus:, storage:)
+        @cpu = cpu
+        @bus = bus
+        @storage = storage
+      end
+
+      private
+
+      def active?
+        @bus.io_port.kernal? && @bus.peek(0xba) == DEVICE
+      end
+
+      # Filename pointer at $BB/$BC, length at $B7
+      def filename
+        pointer = uint16(@bus.peek(0xbb), @bus.peek(0xbc))
+        bytes = Array.new(@bus.peek(0xb7)) do |i|
+          @bus.peek((pointer + i) & 0xffff)
+        end
+        strip_drive_prefix(Storage.ascii(bytes))
+      end
+
+      # CBM DOS drive prefix — "0:NAME" selects a drive, "@0:NAME" is
+      # save-with-replace
+      def strip_drive_prefix(name)
+        name.sub(/\A@?\d*:/, "")
+      end
+
+      def error(code)
+        @cpu.a = code
+        @cpu.status.carry = true
+      end
+
+      def return_to_caller
+        @cpu.program_counter = (uint16(pull_byte, pull_byte) + 1) & 0xffff
+      end
+
+      def pull_byte
+        @cpu.stack_pointer = (@cpu.stack_pointer + 1) & 0xff
+        @bus.peek(0x0100 + @cpu.stack_pointer)
+      end
+    end
+  end
+end

data/lib/badline/kernal_trap/load.rb

@@ -0,0 +1,63 @@
+# frozen_string_literal: true
+
+module Badline
+  module KernalTrap
+    # PC trap on the KERNAL serial LOAD routine ($F4A5, the default ILOAD
+    # vector target). Serves device 8 requests from a storage backend and
+    # returns to the caller with the routine's register/zeropage contract;
+    # other devices fall through to the ROM.
+    class Load < File
+      ADDRESS = 0xf4a5
+
+      FILE_NOT_FOUND = 0x04
+
+      def call
+        return unless active?
+
+        name = filename
+        if name.empty?
+          error(MISSING_FILENAME)
+        elsif (data = @storage.read_file(name))
+          deliver(data)
+        else
+          error(FILE_NOT_FOUND)
+        end
+        return_to_caller
+      end
+
+      private
+
+      # A=0 is LOAD, A=1 is VERIFY
+      def load?
+        @cpu.a.zero?
+      end
+
+      def deliver(data)
+        addr = load_address(data)
+        payload = data[2..] || []
+        payload = payload[0, 0x10000 - addr] if addr + payload.length > 0x10000
+        @bus.ram.write(addr, payload) if load?
+        finish((addr + payload.length) & 0xffff)
+      end
+
+      # Secondary address $B9 zero relocates to the caller-supplied address
+      # stashed at $C3/$C4 (MEMUSS)
+      def load_address(data)
+        if @bus.peek(0xb9).zero?
+          uint16(@bus.peek(0xc3), @bus.peek(0xc4))
+        else
+          uint16(data[0], data[1])
+        end
+      end
+
+      def finish(end_addr)
+        @bus.poke(0x90, 0x40)
+        @bus.poke(0xae, low_byte(end_addr))
+        @bus.poke(0xaf, high_byte(end_addr))
+        @cpu.x = low_byte(end_addr)
+        @cpu.y = high_byte(end_addr)
+        @cpu.status.carry = false
+      end
+    end
+  end
+end

data/lib/badline/kernal_trap/save.rb

@@ -0,0 +1,42 @@
+# frozen_string_literal: true
+
+module Badline
+  module KernalTrap
+    # PC trap on the KERNAL serial SAVE routine ($F5ED, the default ISAVE
+    # vector target). Writes device 8 saves to a storage backend as a PRG
+    # (load address followed by the memory range); other devices fall
+    # through to the ROM.
+    class Save < File
+      ADDRESS = 0xf5ed
+
+      def call
+        return unless active?
+
+        name = filename
+        if name.empty?
+          error(MISSING_FILENAME)
+        else
+          @storage.write_file(name, payload)
+          finish
+        end
+        return_to_caller
+      end
+
+      private
+
+      # Start address at $C1/$C2 (STAL), end address (exclusive) at
+      # $AE/$AF (EAL)
+      def payload
+        start = uint16(@bus.peek(0xc1), @bus.peek(0xc2))
+        length = (uint16(@bus.peek(0xae), @bus.peek(0xaf)) - start) & 0xffff
+        [low_byte(start), high_byte(start)] +
+          Array.new(length) { |i| @bus.peek((start + i) & 0xffff) }
+      end
+
+      def finish
+        @bus.poke(0x90, 0x00)
+        @cpu.status.carry = false
+      end
+    end
+  end
+end

data/lib/badline/kernal_trap.rb

@@ -0,0 +1,5 @@
+# frozen_string_literal: true
+
+require "badline/kernal_trap/file"
+require "badline/kernal_trap/load"
+require "badline/kernal_trap/save"

data/lib/badline/keyboard.rb

@@ -0,0 +1,58 @@
+# frozen_string_literal: true
+
+module Badline
+  class Keyboard
+    include IntegerHelper
+
+    attr_reader :keys, :matrix
+
+    def initialize
+      @keys = []
+
+      @matrix = [
+        %i[delete return cursor_h f7 f1 f3 cursor_v],
+        %i[3 w a 4 z s e lshift],
+        %i[5 r d 6 c f t x],
+        %i[7 y g 8 b h u v],
+        %i[9 i j 0 m k o n],
+        %i[+ p l - . : @ ,],
+        %i[£ * ; clr_home rshift = up /],
+        %i[1 left control 2 space cbm q run_stop]
+      ]
+    end
+
+    def press(key)
+      @keys << key if valid_key?(key)
+    end
+
+    def read_a(_port_a, _port_b)
+      0xff
+    end
+
+    def read_b(port_a, _port_b)
+      return 0xff unless keys.any?
+
+      output = 0xff
+
+      matrix.each_with_index do |row, a|
+        next unless port_a[a].zero?
+
+        row.each_with_index do |key, b|
+          output -= (1 << b) if keys.include?(key)
+        end
+      end
+
+      output
+    end
+
+    def release(key)
+      @keys.reject! { |k| k == key }
+    end
+
+    private
+
+    def valid_key?(key)
+      matrix.flatten.include?(key)
+    end
+  end
+end