badline 0.1.0

data/lib/badline/instruction_set/arithmetic.rb

@@ -0,0 +1,119 @@
+# frozen_string_literal: true
+
+module Badline
+  module InstructionSet
+    module Arithmetic
+      # Add memory with carry to accumulator.
+      #
+      # Opcodes:
+      #   $61 - indirect_x - 6 cycles
+      #   $65 - zeropage   - 3 cycles
+      #   $69 - immediate  - 2 cycles
+      #   $6D - absolute   - 4 cycles
+      #   $71 - indirect_y - 5+ cycles
+      #   $75 - zeropage_x - 4 cycles
+      #   $79 - absolute_y - 4+ cycles
+      #   $7D - absolute_x - 4+ cycles
+      def adc(_addr, value)
+        v = resolve(value)
+        result = a + v + status.carry
+        status.zero = result.nobits?(0xff)
+
+        if status.decimal?
+          result = (a & 0x0f) + (v & 0x0f) + status.carry
+          result += 0x06 if result > 0x09
+          c = result > 0x0f ? 1 : 0
+          result = (a & 0xf0) + (v & 0xf0) + (c << 4) + (result & 0x0f)
+          update_calculation_flags(v, result)
+          result += 0x60 if result > 0x9f
+        else
+          update_calculation_flags(v, result)
+        end
+
+        status.carry = result > 0xff
+        @a = result & 0xff
+      end
+
+      # Compare memory with accumulator.
+      #
+      # Opcodes:
+      #   $C1 - indirect_x - 6 cycles
+      #   $C5 - zeropage   - 3 cycles
+      #   $C9 - immediate  - 2 cycles
+      #   $CD - absolute   - 4 cycles
+      #   $D1 - indirect_y - 5+ cycles
+      #   $D5 - zeropage_x - 4 cycles
+      #   $D9 - absolute_y - 4+ cycles
+      #   $DD - absolute_x - 4+ cycles
+      def cmp(_addr, value)
+        v = resolve(value)
+        status.carry = (@a >= v)
+        update_number_flags(@a - v)
+      end
+
+      # Compare memory with X register.
+      #
+      # Opcodes:
+      #   $E0 - immediate  - 2 cycles
+      #   $E4 - zeropage   - 3 cycles
+      #   $EC - absolute   - 4 cycles
+      def cpx(_addr, value)
+        v = resolve(value)
+        status.carry = @x >= v
+        update_number_flags(@x - v)
+      end
+
+      # Compare memory with Y register.
+      #
+      # Opcodes:
+      #   $C0 - immediate  - 2 cycles
+      #   $C4 - zeropage   - 3 cycles
+      #   $CC - absolute   - 4 cycles
+      def cpy(_addr, value)
+        v = resolve(value)
+        status.carry = @y >= v
+        update_number_flags(@y - v)
+      end
+
+      # Subtract memory from accumulator with borrow.
+      #
+      # Opcodes:
+      #   $E1 - indirect_x - 6 cycles
+      #   $E5 - zeropage   - 3 cycles
+      #   $E9 - immediate  - 2 cycles
+      #   $ED - absolute   - 4 cycles
+      #   $F1 - indirect_y - 5+ cycles
+      #   $F5 - zeropage_x - 4 cycles
+      #   $F9 - absolute_y - 4+ cycles
+      #   $FD - absolute_x - 4+ cycles
+      def sbc(_addr, value)
+        v = resolve(value)
+        v_inv = ~v & 0xff
+        carry = status.carry? ? 0 : -1
+
+        result = a + v_inv + status.carry
+        status.zero = result.nobits?(0xff)
+        status.carry = result > 0xff
+        update_calculation_flags(v_inv, result)
+
+        if status.decimal?
+          al = (a & 0x0f) - (v & 0x0f) + carry
+          al = ((al - 0x06) & 0x0F) - 0x10 if al.negative?
+
+          result = (a & 0xf0) - (v & 0xf0) + al
+          result -= 0x60 if result.negative?
+        end
+
+        @a = result & 0xff
+      end
+
+      private
+
+      def update_calculation_flags(value, result)
+        status.negative = result.anybits?(0x80)
+        status.overflow = (a ^ value).nobits?(0x80) &&
+                          (a ^ result).anybits?(0x80)
+      end
+    end
+  end
+end

data/lib/badline/instruction_set/bitwise.rb

@@ -0,0 +1,131 @@
+# frozen_string_literal: true
+
+module Badline
+  module InstructionSet
+    module Bitwise
+      # Performs bitwise AND on accumulator with memory.
+      #
+      # Opcodes:
+      #   $21 - indirect_x - 6 cycles
+      #   $25 - zeropage   - 3 cycles
+      #   $29 - immediate  - 2 cycles
+      #   $2D - absolute   - 4 cycles
+      #   $31 - indirect_y - 5+ cycles
+      #   $35 - zeropage_x - 4 cycles
+      #   $39 - absolute_y - 4+ cycles
+      #   $3D - absolute_x - 4+ cycles
+      def and(_addr, value)
+        @a &= resolve(value)
+        update_number_flags(@a)
+      end
+
+      # Arithmetic shift left. Shifts bits left by one position.
+      #
+      # Opcodes:
+      #   $06 - zeropage   - 5 cycles
+      #   $0A - accumulator- 2 cycles
+      #   $0E - absolute   - 6 cycles
+      #   $16 - zeropage_x - 6 cycles
+      #   $1E - absolute_x - 7 cycles
+      def asl(addr, value)
+        v = resolve(value)
+        result = (v << 1) & 0xff
+        status.carry = v[7]
+        write_modified(addr, v, result)
+        update_number_flags(result)
+      end
+
+      # Tests bits in memory with accumulator.
+      #
+      # Opcodes:
+      #   $24 - zeropage - 3 cycles
+      #   $2C - absolute - 4 cycles
+      def bit(_addr, value)
+        v = resolve(value)
+        status.value = ((status.value & 0b00111111) +
+                        (v & 0b11000000)).to_i
+        status.zero = (a & v).nobits?(0xff)
+      end
+
+      # Performs bitwise XOR on accumulator with memory.
+      #
+      # Opcodes:
+      #   $41 - indirect_x - 6 cycles
+      #   $45 - zeropage   - 3 cycles
+      #   $49 - immediate  - 2 cycles
+      #   $4D - absolute   - 4 cycles
+      #   $51 - indirect_y - 5+ cycles
+      #   $55 - zeropage_x - 4 cycles
+      #   $59 - absolute_y - 4+ cycles
+      #   $5D - absolute_x - 4+ cycles
+      def eor(_addr, value)
+        @a = (@a ^ resolve(value)) & 0xff
+        update_number_flags(@a)
+      end
+
+      # Logical shift right. Shifts bits right by one position.
+      #
+      # Opcodes:
+      #   $46 - zeropage   - 5 cycles
+      #   $4A - accumulator- 2 cycles
+      #   $4E - absolute   - 6 cycles
+      #   $56 - zeropage_x - 6 cycles
+      #   $5E - absolute_x - 7 cycles
+      def lsr(addr, value)
+        v = resolve(value)
+        result = (v >> 1) & 0xff
+        status.carry = v[0]
+        write_modified(addr, v, result)
+        update_number_flags(result)
+      end
+
+      # Performs bitwise OR on accumulator with memory.
+      #
+      # Opcodes:
+      #   $01 - indirect_x - 6 cycles
+      #   $05 - zeropage   - 3 cycles
+      #   $09 - immediate  - 2 cycles
+      #   $0D - absolute   - 4 cycles
+      #   $11 - indirect_y - 5+ cycles
+      #   $15 - zeropage_x - 4 cycles
+      #   $19 - absolute_y - 4+ cycles
+      #   $1D - absolute_x - 4+ cycles
+      def ora(_addr, value)
+        @a |= resolve(value)
+        update_number_flags(@a)
+      end
+
+      # Rotate left through carry.
+      #
+      # Opcodes:
+      #   $26 - zeropage   - 5 cycles
+      #   $2A - accumulator- 2 cycles
+      #   $2E - absolute   - 6 cycles
+      #   $36 - zeropage_x - 6 cycles
+      #   $3E - absolute_x - 7 cycles
+      def rol(addr, value)
+        v = resolve(value)
+        result = ((v << 1) + status.carry) & 0xff
+        status.carry = v[7]
+        write_modified(addr, v, result)
+        update_number_flags(result)
+      end
+
+      # Rotate right through carry.
+      #
+      # Opcodes:
+      #   $66 - zeropage   - 5 cycles
+      #   $6A - accumulator- 2 cycles
+      #   $6E - absolute   - 6 cycles
+      #   $76 - zeropage_x - 6 cycles
+      #   $7E - absolute_x - 7 cycles
+      def ror(addr, value)
+        v = resolve(value)
+        result = ((v >> 1) + (status.carry? ? 0x80 : 0)) & 0xff
+        status.carry = v[0]
+        write_modified(addr, v, result)
+        update_number_flags(result)
+      end
+    end
+  end
+end

data/lib/badline/instruction_set/branch.rb

@@ -0,0 +1,78 @@
+# frozen_string_literal: true
+
+module Badline
+  module InstructionSet
+    module Branch
+      # Branch if carry clear (C=0).
+      #
+      # Opcodes:
+      #   $90 - relative - 2+ cycles
+      def bcc(addr, _value)
+        branch(addr) unless status.carry?
+      end
+
+      # Branch if carry set (C=1).
+      #
+      # Opcodes:
+      #   $B0 - relative - 2+ cycles
+      def bcs(addr, _value)
+        branch(addr) if status.carry?
+      end
+
+      # Branch if equal (Z=1).
+      #
+      # Opcodes:
+      #   $F0 - relative - 2+ cycles
+      def beq(addr, _value)
+        branch(addr) if status.zero?
+      end
+
+      # Branch if minus (N=1).
+      #
+      # Opcodes:
+      #   $30 - relative - 2+ cycles
+      def bmi(addr, _value)
+        branch(addr) if status.negative?
+      end
+
+      # Branch if not equal (Z=0).
+      #
+      # Opcodes:
+      #   $D0 - relative - 2+ cycles
+      def bne(addr, _value)
+        branch(addr) unless status.zero?
+      end
+
+      # Branch if plus (N=0).
+      #
+      # Opcodes:
+      #   $10 - relative - 2+ cycles
+      def bpl(addr, _value)
+        branch(addr) unless status.negative?
+      end
+
+      # Branch if overflow clear (V=0).
+      #
+      # Opcodes:
+      #   $50 - relative - 2+ cycles
+      def bvc(addr, _value)
+        branch(addr) unless status.overflow?
+      end
+
+      # Branch if overflow set (V=1).
+      #
+      # Opcodes:
+      #   $70 - relative - 2+ cycles
+      def bvs(addr, _value)
+        branch(addr) if status.overflow?
+      end
+
+      private
+
+      def branch(addr)
+        cycle if high_byte(addr) != high_byte(@program_counter)
+        cycle { @program_counter = addr }
+      end
+    end
+  end
+end

data/lib/badline/instruction_set/flag.rb

@@ -0,0 +1,63 @@
+# frozen_string_literal: true
+
+module Badline
+  module InstructionSet
+    module Flag
+      # Clear carry flag.
+      #
+      # Opcodes:
+      #   $18 - implied - 2 cycles
+      def clc(_addr, _value)
+        cycle { status.carry = false }
+      end
+
+      # Clear decimal mode flag.
+      #
+      # Opcodes:
+      #   $D8 - implied - 2 cycles
+      def cld(_addr, _value)
+        cycle { status.decimal = false }
+      end
+
+      # Clear interrupt disable flag.
+      #
+      # Opcodes:
+      #   $58 - implied - 2 cycles
+      def cli(_addr, _value)
+        cycle { status.interrupt = false }
+      end
+
+      # Clear overflow flag.
+      #
+      # Opcodes:
+      #   $B8 - implied - 2 cycles
+      def clv(_addr, _value)
+        cycle { status.overflow = false }
+      end
+
+      # Set carry flag.
+      #
+      # Opcodes:
+      #   $38 - implied - 2 cycles
+      def sec(_addr, _value)
+        cycle { status.carry = true }
+      end
+
+      # Set decimal mode flag.
+      #
+      # Opcodes:
+      #   $F8 - implied - 2 cycles
+      def sed(_addr, _value)
+        cycle { status.decimal = true }
+      end
+
+      # Set interrupt disable flag.
+      #
+      # Opcodes:
+      #   $78 - implied - 2 cycles
+      def sei(_addr, _value)
+        cycle { status.interrupt = true }
+      end
+    end
+  end
+end

data/lib/badline/instruction_set/illegal.rb

@@ -0,0 +1,278 @@
+# frozen_string_literal: true
+
+module Badline
+  module InstructionSet
+    # Illegal opcodes
+    module Illegal
+      # Combination of AND and LSR.
+      #
+      # Opcodes:
+      #   $4B - immediate - 2 cycles
+      def alr(_addr, value)
+        @a &= resolve(value)
+        status.carry = @a[0]
+        @a = (@a >> 1) & 0xff
+        update_number_flags(@a)
+      end
+
+      # Combination of AND where carry is set to bit 7 of result.
+      #
+      # Opcodes:
+      #   $0B, $2B - immediate - 2 cycles
+      def anc(addr, value)
+        self.and(addr, value)
+        status.carry = status.negative
+      end
+
+      # Unstable instruction. AND's value with A|magic_const and X.
+      # Magic constant varies by CPU.
+      #
+      # Opcodes:
+      #   $8B - immediate - 2 cycles
+      def ane(_addr, value)
+        magic_const = 0xee
+        @a = (a | magic_const) & x & resolve(value)
+        update_number_flags(@a)
+      end
+
+      # Combination of AND and ROR.
+      #
+      # Opcodes:
+      #   $6B - immediate - 2 cycles
+      def arr(_addr, value)
+        tmp = a & resolve(value)
+        result = (tmp >> 1) | (status.carry? ? 0x80 : 0)
+        status.zero = result.zero?
+        status.negative = status.carry
+
+        if status.decimal?
+          status.overflow = (result ^ tmp).anybits?(0x40)
+
+          # Low nibble
+          result = (result & 0xf0) | ((result + 0x06) & 0x0f) if ((tmp & 0x0f) + (tmp & 0x01)) > 0x05
+
+          # High nibble + carry
+          if ((tmp & 0xf0) + (tmp & 0x10)) > 0x50
+            result = (result & 0x0f) | ((result + 0x60) & 0xf0)
+            status.carry = true
+          else
+            status.carry = false
+          end
+        else
+          status.carry = tmp[7] == 1
+          status.overflow = tmp[7] ^ tmp[6]
+        end
+
+        @a = result
+      end
+
+      # Combination of DEC and CMP operations.
+      #
+      # Opcodes:
+      #   $C3 - indirect_x - 8 cycles
+      #   $C7 - zeropage   - 5 cycles
+      #   $CF - absolute   - 6 cycles
+      #   $D3 - indirect_y - 8 cycles
+      #   $D7 - zeropage_x - 6 cycles
+      #   $DB - absolute_y - 7 cycles
+      #   $DF - absolute_x - 7 cycles
+      def dcp(addr, value)
+        cmp(addr, dec(addr, value))
+      end
+
+      # Combination of INC and SBC operations.
+      #
+      # Opcodes:
+      #   $E3 - indirect_x - 8 cycles
+      #   $E7 - zeropage   - 5 cycles
+      #   $EF - absolute   - 6 cycles
+      #   $F3 - indirect_y - 8 cycles
+      #   $F7 - zeropage_x - 6 cycles
+      #   $FB - absolute_y - 7 cycles
+      #   $FF - absolute_x - 7 cycles
+      def isc(addr, value)
+        sbc(addr, inc(addr, value))
+      end
+
+      # Freezes the CPU by forcing an infinite loop.
+      #
+      # Opcodes:
+      #   $02, $12, $22, $32, $42, $52, $62, $72, $92, $B2, $D2, $F2
+      def jam(_addr, _value)
+        # TODO: Handle jam
+        # It is possible to implement with loop { cycle }, but makes
+        # testing problematic.
+        10.times { cycle }
+      end
+
+      # Loads A and S with value AND stack pointer.
+      #
+      # Opcodes:
+      #   $BB - absolute_y - 4 cycles
+      def las(_addr, value)
+        @a = @x = @stack_pointer = resolve(value) & stack_pointer
+        update_number_flags(@a)
+      end
+
+      # Combination of LDA and LDX with same value.
+      #
+      # Opcodes:
+      #   $A3 - indirect_x - 6 cycles
+      #   $A7 - zeropage   - 3 cycles
+      #   $AF - absolute   - 4 cycles
+      #   $B3 - indirect_y - 5+ cycles
+      #   $B7 - zeropage_y - 4 cycles
+      #   $BF - absolute_y - 4+ cycles
+      def lax(_addr, value)
+        @a = @x = resolve(value)
+
+        update_number_flags(@a)
+      end
+
+      # Unstable immediate form of LAX. Loads A and X with
+      # (A | magic_const) AND value. Magic constant varies by CPU.
+      #
+      # Opcodes:
+      #   $AB - immediate - 2 cycles
+      def lxa(_addr, value)
+        magic_const = 0xee
+        @a = @x = (a | magic_const) & resolve(value)
+        update_number_flags(@a)
+      end
+
+      # Special no-operation instruction that does not consume a CPU cycle,
+      # unlike the standard NOP. Used by some illegal opcodes.
+      #
+      # Opcodes:
+      #   $80, $82, $89, $C2, $E2 - immediate - 2 cycles
+      def nop_nocycle(_addr, _value); end
+
+      # Combination of ROL and AND operations.
+      #
+      # Opcodes:
+      #   $23 - indirect_x - 8 cycles
+      #   $27 - zeropage   - 5 cycles
+      #   $2F - absolute   - 6 cycles
+      #   $33 - indirect_y - 8 cycles
+      #   $37 - zeropage_x - 6 cycles
+      #   $3B - absolute_y - 7 cycles
+      #   $3F - absolute_x - 7 cycles
+      def rla(addr, value)
+        self.and(addr, rol(addr, value))
+      end
+
+      # Combination of ROR and ADC operations.
+      #
+      # Opcodes:
+      #   $63 - indirect_x - 8 cycles
+      #   $67 - zeropage   - 5 cycles
+      #   $6F - absolute   - 6 cycles
+      #   $73 - indirect_y - 8 cycles
+      #   $77 - zeropage_x - 6 cycles
+      #   $7B - absolute_y - 7 cycles
+      #   $7F - absolute_x - 7 cycles
+      def rra(addr, value)
+        adc(addr, ror(addr, value))
+      end
+
+      # Store A AND X.
+      #
+      # Opcodes:
+      #   $83 - indirect_x - 6 cycles
+      #   $87 - zeropage   - 3 cycles
+      #   $8F - absolute   - 4 cycles
+      #   $97 - zeropage_y - 4 cycles
+      def sax(addr, _value)
+        write_byte(addr, @a & @x)
+      end
+
+      # AND X register with accumulator and subtract value.
+      #
+      # Opcodes:
+      #   $CB - immediate - 2 cycles
+      def sbx(_addr, value)
+        v = resolve(value)
+        result = (@x & @a) - v
+        status.carry = result >= 0
+        @x = result & 0xff
+        update_number_flags(@x)
+      end
+
+      # Stores A AND X AND (high byte of base address + 1) at addr.
+      #
+      # Opcodes:
+      #   $93 - indirect_y - 6 cycles
+      #   $9F - absolute_y - 5 cycles
+      def sha(addr, _value)
+        store_high_and(a & x, addr)
+      end
+
+      # Stores X AND (high byte of base address + 1) at addr.
+      #
+      # Opcodes:
+      #   $9E - absolute_y - 5 cycles
+      def shx(addr, _value)
+        store_high_and(x, addr)
+      end
+
+      # Stores Y AND (high byte of base address + 1) at addr.
+      #
+      # Opcodes:
+      #   $9C - absolute_x - 5 cycles
+      def shy(addr, _value)
+        store_high_and(y, addr)
+      end
+
+      # Combination of ASL and ORA operations.
+      #
+      # Opcodes:
+      #   $03 - indirect_x - 8 cycles
+      #   $07 - zeropage   - 5 cycles
+      #   $0F - absolute   - 6 cycles
+      #   $13 - indirect_y - 8 cycles
+      #   $17 - zeropage_x - 6 cycles
+      #   $1B - absolute_y - 7 cycles
+      #   $1F - absolute_x - 7 cycles
+      def slo(addr, value)
+        ora(addr, asl(addr, value))
+      end
+
+      # Combination of LSR and EOR operations.
+      #
+      # Opcodes:
+      #   $43 - indirect_x - 8 cycles
+      #   $47 - zeropage   - 5 cycles
+      #   $4F - absolute   - 6 cycles
+      #   $53 - indirect_y - 8 cycles
+      #   $57 - zeropage_x - 6 cycles
+      #   $5B - absolute_y - 7 cycles
+      #   $5F - absolute_x - 7 cycles
+      def sre(addr, value)
+        eor(addr, lsr(addr, value))
+      end
+
+      # Stores A AND X in SP, then stores SP AND (high byte of base + 1) at
+      # addr.
+      #
+      # Opcodes:
+      #   $9B - absolute_y - 5 cycles
+      def tas(addr, _value)
+        @stack_pointer = @a & @x
+        store_high_and(stack_pointer, addr)
+      end
+
+      private
+
+      def store_high_and(register, addr)
+        base_high = if boundary_crossed
+                      (high_byte(addr) - 1) & 0xff
+                    else
+                      high_byte(addr)
+                    end
+        result = register & ((base_high + 1) & 0xff)
+        target = boundary_crossed ? uint16(low_byte(addr), result) : addr
+        write_byte(target, result)
+      end
+    end
+  end
+end