badline 0.1.0

data/lib/badline/cia/timer.rb

@@ -0,0 +1,122 @@
+# frozen_string_literal: true
+
+module Badline
+  class CIA
+    class Timer
+      attr_accessor :counter, :latch
+      attr_reader :control, :underflowed
+
+      def initialize(control)
+        @control = control
+        @counter = @latch = 0x0
+        @pipe = 0
+        @load_delay = 0
+        @reload = false
+        @underflowed = false
+        @oneshot_linger = 0
+        @toggle = true
+      end
+
+      def toggle?
+        @toggle
+      end
+
+      def cycle!(feed, pulse)
+        return @counter -= 1 if feed && pulse && steady?
+
+        if (@pipe | @load_delay).zero? && !@reload
+          @pipe = 0b10 if feed && started?
+          return
+        end
+        run_tick(feed, pulse)
+      end
+
+      def run_tick(feed, pulse)
+        @underflowed = false
+        @oneshot_linger -= 1 if @oneshot_linger.positive?
+        tick(feed && started?, pulse)
+      end
+
+      def write_control(value)
+        @toggle = true if value.anybits?(0x01) && !started?
+        @oneshot_linger = 2 if control.run_mode? && value.nobits?(0x08)
+        control.value = value & ~0x10
+        @load_delay = 3 if value.anybits?(0x10)
+      end
+
+      def write_latch_low(value)
+        @latch = (@latch & 0xff00) | value
+      end
+
+      def write_latch_high(value)
+        @latch = (value << 8) | (@latch & 0xff)
+        @counter = @latch unless started?
+      end
+
+      private
+
+      def started?
+        control.value.anybits?(0x01)
+      end
+
+      def steady?
+        @counter > 1 && @pipe == 0b11 && !@reload &&
+          (@load_delay | @oneshot_linger).zero? && started?
+      end
+
+      def tick(feed, pulse)
+        counting = @pipe.anybits?(0b01) && pulse
+        @pipe = (@pipe >> 1) | (feed ? 0b10 : 0)
+
+        if premature_underflow?(pulse)
+          underflow
+        elsif apply_reload?
+          return
+        elsif counting && @load_delay != 1
+          count
+        end
+
+        forced_load
+      end
+
+      def forced_load
+        return unless @load_delay.positive?
+
+        @load_delay -= 1
+        @counter = @latch if @load_delay == 1
+      end
+
+      # the final pipeline stage, before any pending load lands
+      def premature_underflow?(pulse)
+        @counter.zero? && !@reload && pulse && @pipe.anybits?(0b01) &&
+          started?
+      end
+
+      # An underflow reload consumes the tick after the flag
+      def apply_reload?
+        return false unless @reload
+
+        @reload = false
+        @counter = @latch
+        # A zero latch underflows again on the reload tick while running
+        underflow if @counter.zero? && started?
+        true
+      end
+
+      def count
+        @counter -= 1 if @counter.positive?
+        underflow if @counter.zero? && @pipe.anybits?(0b01)
+      end
+
+      def underflow
+        @underflowed = true
+        @reload = true
+        @toggle = !@toggle
+        return unless control.run_mode? || @oneshot_linger.positive?
+
+        control.start = false
+        @pipe = 0
+      end
+    end
+  end
+end

data/lib/badline/cia.rb

@@ -0,0 +1,189 @@
+# frozen_string_literal: true
+
+require "forwardable"
+require "badline/cia/timer"
+
+module Badline
+  # CIA (Complex Interface Adapter) chip
+  class CIA
+    include Addressable
+    extend Forwardable
+
+    attr_reader :start, :control_a, :control_b, :interrupt_status, :interrupt_control, :peripheral
+
+    def_delegator :@ta, :counter,  :timer_a
+    def_delegator :@ta, :counter=, :timer_a=
+    def_delegator :@ta, :latch,    :timer_a_latch
+    def_delegator :@ta, :latch=,   :timer_a_latch=
+    def_delegator :@tb, :counter,  :timer_b
+    def_delegator :@tb, :counter=, :timer_b=
+    def_delegator :@tb, :latch,    :timer_b_latch
+    def_delegator :@tb, :latch=,   :timer_b_latch=
+
+    def initialize(start: 0, peripheral: nil)
+      addressable_at(start, length: 2**8)
+
+      @peripheral = peripheral
+      @data_port_a = 0xff
+      @data_port_b = 0xff
+      @data_dir_a = 0xff
+      @data_dir_b = 0x0
+      @irq_pending = 0
+      @serial_data = 0x0
+      @tod = TimeOfDay.new
+      @interrupt_control = Status.new([:timer_a, :timer_b, :alarm, :serial,
+                                       :flag, 0, 0, 0])
+      @interrupt_status = Status.new([:timer_a, :timer_b, :alarm, :serial,
+                                      :flag, 0, 0, :interrupt])
+      @control_a = Status.new(%i[start output out_mode run_mode load
+                                 in_mode serial_mode clock_frequency])
+      @control_b = Status.new(%i[start output out_mode run_mode load
+                                 in_cnt in_timer_a alarm])
+      @ta = Timer.new(@control_a)
+      @tb = Timer.new(@control_b)
+    end
+
+    def interrupt!(delay = 1)
+      @irq_pending = @irq_pending.positive? ? [@irq_pending, delay].min : delay
+    end
+
+    def interrupted?
+      interrupt_status.value.anybits?(0x80)
+    end
+
+    def cycle!
+      if @irq_pending.positive?
+        @irq_pending -= 1
+        interrupt_status.interrupt = true if @irq_pending.zero?
+      end
+      update_timers
+      @tod.cycle! { trigger_alarm }
+    end
+
+    def read_port_a
+      pulldown = peripheral ? peripheral.read_a(@data_port_a, @data_port_b) : 0xff
+      driven_lines(@data_port_a, @data_dir_a) & pulldown
+    end
+
+    # Port A as driven by the data/direction registers alone, without
+    # peripheral pulldown. Cheap path for the VIC bank lookup.
+    def port_a_lines
+      driven_lines(@data_port_a, @data_dir_a)
+    end
+
+    def read_port_b
+      pulldown = peripheral ? peripheral.read_b(@data_port_a, @data_port_b) : 0xff
+      value = driven_lines(@data_port_b, @data_dir_b) & pulldown
+      apply_timer_output(value)
+    end
+
+    def peek(addr)
+      case index(addr) & 0x0f
+      when 0x00 then read_port_a
+      when 0x01 then read_port_b
+      when 0x02 then @data_dir_a
+      when 0x03 then @data_dir_b
+      when 0x04 then low_byte(@ta.counter)
+      when 0x05 then high_byte(@ta.counter)
+      when 0x06 then low_byte(@tb.counter)
+      when 0x07 then high_byte(@tb.counter)
+      when 0x08 then @tod.tenths
+      when 0x09 then @tod.seconds
+      when 0x0a then @tod.minutes
+      when 0x0b then @tod.hours
+      when 0x0c then @serial_data
+      when 0x0d
+        value = interrupt_status.value
+        interrupt_status.value = 0x0 # Burn after reading
+        @irq_pending = 0
+        value
+      when 0x0e then control_a.value
+      when 0x0f then control_b.value
+      end
+    end
+
+    def poke(addr, value)
+      case index(addr) & 0x0f
+      when 0x00 then @data_port_a = value
+      when 0x01 then @data_port_b = value
+      when 0x02 then @data_dir_a = value
+      when 0x03 then @data_dir_b = value
+      when 0x04 then @ta.write_latch_low(value)
+      when 0x05 then @ta.write_latch_high(value)
+      when 0x06 then @tb.write_latch_low(value)
+      when 0x07 then @tb.write_latch_high(value)
+      when 0x08 then @tod.write(:tenths, value, alarm: control_b.alarm?)
+      when 0x09 then @tod.write(:seconds, value, alarm: control_b.alarm?)
+      when 0x0a then @tod.write(:minutes, value, alarm: control_b.alarm?)
+      when 0x0b then @tod.write_hours(value, alarm: control_b.alarm?)
+      when 0x0c
+        # TODO: Serial
+      when 0x0d then write_interrupt_control(value)
+      when 0x0e then @ta.write_control(value)
+      when 0x0f then @tb.write_control(value)
+      end
+    end
+
+    private
+
+    def driven_lines(register, direction)
+      # Output bits are driven from the data register; input bits float high.
+      # External peripherals can still pull any line low (wired-AND).
+      (register & direction) | (~direction & 0xff)
+    end
+
+    def apply_timer_output(value)
+      value = with_bit(value, 6, timer_a_output?) if control_a.output?
+      value = with_bit(value, 7, timer_b_output?) if control_b.output?
+      value
+    end
+
+    def timer_a_output?
+      control_a.out_mode? ? @ta.toggle? : @ta.underflowed
+    end
+
+    def timer_b_output?
+      control_b.out_mode? ? @tb.toggle? : @tb.underflowed
+    end
+
+    def with_bit(value, bit, set)
+      set ? value | (1 << bit) : value & ~(1 << bit)
+    end
+
+    def trigger_alarm
+      interrupt_status.alarm = true
+      interrupt! if interrupt_control.alarm?
+    end
+
+    def update_timers
+      @ta.cycle!(@control_a.value.nobits?(0x20), true)
+      crb = @control_b.value
+      if crb.anybits?(0x40)
+        @tb.cycle!(true, @ta.underflowed)
+      else
+        @tb.cycle!(crb.nobits?(0x20), true)
+      end
+      if @ta.underflowed
+        interrupt_status.timer_a = true
+        interrupt! if interrupt_control.timer_a?
+      end
+      return unless @tb.underflowed
+
+      interrupt_status.timer_b = true
+      interrupt! if interrupt_control.timer_b?
+    end
+
+    def write_interrupt_control(value)
+      if value.nobits?(0x80)
+        # Clear interrupts based on bits 0-4
+        interrupt_control.value &= ~(value & 0x1f)
+      else
+        # Set interrupts based on bits 0-4
+        interrupt_control.value |= (value & 0x1f)
+      end
+      return unless interrupt_control.value.anybits?(interrupt_status.value & 0x1f)
+
+      interrupt!(2) unless interrupted?
+    end
+  end
+end

data/lib/badline/color_memory.rb

@@ -0,0 +1,16 @@
+# frozen_string_literal: true
+
+module Badline
+  class ColorMemory < Memory
+    def poke(addr, value)
+      # Only write the lower 4 bits
+      super(addr, value & 0x0f)
+    end
+
+    private
+
+    def blank_value
+      rand(16) << 4
+    end
+  end
+end

data/lib/badline/computer.rb

@@ -0,0 +1,100 @@
+# frozen_string_literal: true
+
+require "forwardable"
+
+module Badline
+  class Computer
+    include IntegerHelper
+    include KeyboardBuffer
+    extend Forwardable
+
+    attr_reader :address_bus, :cpu, :cycles
+
+    def_delegators :address_bus, :vic, :cia1, :cia2, :sid, :ram, :keyboard, :joystick2
+
+    def initialize(debug: false)
+      @address_bus = AddressBus.new
+      @cpu = CPU.new(@address_bus, debug:)
+      @vic = @address_bus.vic
+      @cia1 = @address_bus.cia1
+      @cia2 = @address_bus.cia2
+      @cycles = 0
+      @nmi_asserted = false
+      @init_handlers = []
+      @pending_keys = nil
+    end
+
+    INIT_THRESHOLD = 2_500_000
+
+    def cycle!
+      handle_init if @cycles == INIT_THRESHOLD
+      feed_keyboard if @pending_keys
+
+      @vic.cycle!
+      @cia1.cycle!
+      @cia2.cycle!
+
+      @cpu.irq = @cia1.interrupted? || @vic.interrupted?
+
+      nmi = @cia2.interrupted?
+      @cpu.nmi = true if nmi && !@nmi_asserted
+      @nmi_asserted = nmi
+
+      @cpu.cycle! if @cpu.pending_write? || !@vic.ba_low?
+
+      @cycles += 1
+    end
+
+    def load_prg(data)
+      uint16(data[0], data[1]).tap do |load_addr|
+        ram.write(load_addr, data[2..])
+      end
+    end
+
+    def attach_cartridge(cartridge)
+      address_bus.attach_cartridge(cartridge)
+      cpu.reset!
+    end
+
+    def mount(storage)
+      load_trap = KernalTrap::Load.new(cpu:, bus: address_bus, storage:)
+      cpu.install_trap(KernalTrap::Load::ADDRESS) { load_trap.call }
+      return unless storage.respond_to?(:write_file)
+
+      save_trap = KernalTrap::Save.new(cpu:, bus: address_bus, storage:)
+      cpu.install_trap(KernalTrap::Save::ADDRESS) { save_trap.call }
+    end
+
+    def capture_output
+      @capture_output ||= ChroutTrap.new(cpu:, bus: address_bus).tap do |trap|
+        cpu.install_trap(ChroutTrap::ADDRESS) { trap.call }
+      end
+    end
+
+    def inspect
+      "#<#{self.class.name} cycles=#{@cycles} cpu=(#{@cpu.inspect})>"
+    end
+
+    def on_init(&block)
+      if booting?
+        @init_handlers << block
+      else
+        block.call
+      end
+    end
+
+    private
+
+    def booting?
+      @cycles < init_threshold
+    end
+
+    def handle_init
+      @init_handlers.each(&:call)
+    end
+
+    def init_threshold
+      INIT_THRESHOLD
+    end
+  end
+end

data/lib/badline/control_ports.rb

@@ -0,0 +1,24 @@
+# frozen_string_literal: true
+
+module Badline
+  # CIA 1 peripheral combining the keyboard matrix with the control ports.
+  #
+  # Joystick switches share the same lines as the keyboard matrix and are
+  # wired-AND with it (active low). Port 2 sits on Port A.
+  class ControlPorts
+    attr_reader :keyboard, :joystick2
+
+    def initialize(keyboard:, joystick2:)
+      @keyboard = keyboard
+      @joystick2 = joystick2
+    end
+
+    def read_a(port_a, port_b)
+      keyboard.read_a(port_a, port_b) & joystick2.port_bits
+    end
+
+    def read_b(port_a, port_b)
+      keyboard.read_b(port_a, port_b)
+    end
+  end
+end

data/lib/badline/cpu.rb

@@ -0,0 +1,239 @@
+# frozen_string_literal: true
+
+module Badline
+  class CPU < Cycleable
+    STATUS_FLAGS = [:carry, :zero, :interrupt, :decimal, :break, 1,
+                    :overflow, :negative].freeze
+
+    class InvalidOpcodeError < StandardError; end
+    include IntegerHelper
+    include InstructionSet
+    include Traps
+
+    attr_reader :memory, :instructions, :boundary_crossed
+    attr_accessor :program_counter, :stack_pointer, :status, :a, :x, :y,
+                  :nmi, :irq
+
+    def initialize(memory = nil, debug: false)
+      @debug = debug
+      @memory = memory || Memory.new
+      @status = Status.new(STATUS_FLAGS, value: 0b00100000)
+      reset_registers
+
+      @nmi = @irq = false
+
+      @instructions = 0
+      @traps = nil
+      super()
+    end
+
+    def reset!
+      status.interrupt = true
+      reset_registers
+    end
+
+    def p
+      status.value
+    end
+
+    def p=(new_value)
+      status.value = new_value
+    end
+
+    def step!
+      @loop.resume unless @instruction || @interrupt
+      cycle! while @instruction || @interrupt
+    end
+
+    def inspect
+      "Cycles: #{@cycles}, PC: #{format16(program_counter)}, " \
+        "SP: #{format8(stack_pointer)}, A: #{format8(a)}, X: #{format8(x)}, " \
+        "Y: #{format8(y)}, P: #{format8(p)}"
+    end
+
+    private
+
+    def extra_cycle(instruction)
+      return cycle unless instruction.boundary_cycle?
+
+      boundary_crossed && cycle
+    end
+
+    def handle_interrupt(vector, brk: false, pre_cycles: 2)
+      pre_cycles.times { cycle }
+
+      pc = program_counter
+      pc = (pc + 1) & 0xffff if brk
+
+      write_byte(stack_address, high_byte(pc))
+      @stack_pointer = (@stack_pointer - 1) & 0xff
+      write_byte(stack_address, low_byte(pc))
+      @stack_pointer = (@stack_pointer - 1) & 0xff
+      write_byte(stack_address,
+                 status.clone.tap { |s| s.break = brk }.value)
+      @stack_pointer = (@stack_pointer - 1) & 0xff
+      status.interrupt = true
+      @program_counter = read_word(vector)
+    end
+
+    def handle_interrupts
+      @interrupt = if nmi
+                     0xfffa
+                   elsif irq && !status.interrupt?
+                     0xfffe
+                   end
+
+      handle_interrupt(@interrupt) if @interrupt
+      @interrupt = nil
+      @nmi = @irq = false
+    end
+
+    def read_byte(addr)
+      cycle { @memory.peek(addr) }
+    end
+
+    def read_word(addr)
+      uint16(read_byte(addr),
+             read_byte((addr + 1) & 0xffff))
+    end
+
+    def read_zeropage_word(addr)
+      uint16(read_byte(addr & 0xff),
+             read_byte((addr + 1) & 0xff))
+    end
+
+    def read_instruction
+      Instruction.find(@memory.peek(@program_counter))
+    end
+
+    def read_operand(instruction)
+      return nil unless instruction.operand?
+      # JSR fetches its operand high byte late (see Stack#jsr).
+      return read_byte(program_counter) if instruction.name == :jsr
+      return read_word(program_counter) if instruction.operand_length == 2
+
+      read_byte(program_counter)
+    end
+
+    def reset_registers
+      # The program counter is initialized from the reset vector
+      @program_counter = @memory.peek16(0xfffc)
+      # Stack pointer starts at 0x01ff and grows down
+      @stack_pointer = 0xff
+      @a = @x = @y = 0x0
+    end
+
+    def read_address(instruction, operand)
+      case instruction.addressing_mode
+      when :implied, :immediate
+        nil
+      when :accumulator
+        :accumulator
+      when :relative
+        (@program_counter + signed_int8(operand) + 1) & 0xffff
+      when :zeropage, :absolute
+        operand
+      when :zeropage_x
+        cycle { (operand + @x) & 0xff }
+      when :zeropage_y
+        cycle { (operand + @y) & 0xff }
+      when :absolute_x
+        # Do an extra cycle if page boundary is crossed
+        @boundary_crossed = high_byte(operand + @x) != high_byte(operand)
+        extra_cycle(instruction)
+        (operand + @x) & 0xffff
+      when :absolute_y
+        @boundary_crossed = high_byte(operand + @y) != high_byte(operand)
+        # Do an extra cycle if page boundary is crossed
+        extra_cycle(instruction)
+        (operand + @y) & 0xffff
+      when :indirect
+        # This is only used for JMP. There's no carry associated, so an
+        # indirect jump to $30FF will wrap around on the same page and read
+        # from [0x30ff, 0x3000].
+        uint16(
+          read_byte(operand),
+          read_byte(uint16(
+                      (low_byte(operand) + 1) & 0xff, # Wrap around low byte
+                      high_byte(operand)
+                    ))
+        )
+      when :indirect_x
+        cycle
+        read_zeropage_word(operand + @x)
+      when :indirect_y
+        value = read_zeropage_word(operand)
+        @boundary_crossed = ((value & 0xff) + y) > 0xff
+        # Do an extra cycle if page boundary is crossed
+        extra_cycle(instruction)
+        (value + y) & 0xffff
+      end
+    end
+
+    def realize_value(instruction, operand, address)
+      case instruction.addressing_mode
+      when :implied
+        raise "Implied value can't be realized"
+      when :accumulator
+        @a
+      when :immediate
+        operand
+      else
+        read_byte(address)
+      end
+    end
+
+    def stack_address(offset = 0)
+      uint16((stack_pointer + offset) & 0xff, 0x01)
+    end
+
+    def log(instruction, operand, address)
+      return unless @debug
+
+      pc = (@program_counter - 1) - instruction.operand_length
+      puts(
+        "#{@cycles}: " \
+        "PC: #{pc.to_s(16)} - " \
+        "#{@instruction.name.upcase} #{@instruction.addressing_mode} " \
+        "Operand: #{operand.inspect} Address: #{address.inspect}"
+      )
+    end
+
+    def main_loop
+      if nmi || (irq && !status.interrupt?)
+        handle_interrupts
+      else
+        run_traps
+        @boundary_crossed = false
+        @instruction = read_instruction
+        raise InvalidOpcodeError unless @instruction
+
+        @program_counter = (@program_counter + 1) & 0xffff
+        @cycles += 1
+
+        @operand = operand = read_operand(@instruction)
+        @address = address = read_address(@instruction, operand)
+
+        @program_counter = (@program_counter + @instruction.operand_length) &
+                           0xffff
+
+        log(@instruction, operand, address)
+
+        # Run the instruction; :lazy realizes the value through #resolve
+        send(@instruction.name, address, :lazy)
+
+        @instructions += 1
+        @instruction = nil
+      end
+      Fiber.yield
+    end
+
+    def write_byte(addr, value)
+      if addr == :accumulator
+        @a = value
+      else
+        cycle(write: true) { @memory.poke(addr, value) }
+      end
+    end
+  end
+end