badline 0.1.0 → 0.2.1

data/lib/badline/cartridge/action_replay.rb

@@ -0,0 +1,111 @@
+# frozen_string_literal: true
+
+module Badline
+  class Cartridge
+    # Action Replay v4.2 to v6: four 8K ROM banks and 8K of RAM. A write to
+    # I/O 1 sets the control register:
+    #
+    #   bit 0    pulls GAME low
+    #   bit 1    releases EXROM
+    #   bit 2    switches the register off until the next freeze or reset
+    #   bits 3-4 ROM bank
+    #   bit 5    RAM instead of ROM at ROML and I/O 2
+    #   bit 6    acknowledges a freeze and lets go of NMI
+    #
+    # I/O 2 shows the last page of the RAM or of the ROM bank. The register
+    # doesn't decode R/W, so a read of I/O 1 writes whatever is on the bus
+    # into it. RAM with only EXROM released ($22) selects the cartridge RAM
+    # and the C64's together at ROML. A freeze switches the cartridge back
+    # on, in Ultimax mode with the RAM at ROML and the first bank at ROMH.
+    class ActionReplay < Cartridge
+      include Freezer
+
+      CONTROL_MODES = %i[rom8k rom16k off ultimax].freeze
+      IO2_PAGE = 0x1f00
+
+      def connect(ram:, open_bus:)
+        super
+        @through.backing = ram
+        @contended.backing = ram
+      end
+
+      def readable_io_pages
+        [0xde, 0xdf]
+      end
+
+      def peek(addr)
+        return open_bus(addr) unless @active
+        return io2_peek(addr) if addr >= 0xdf00
+
+        open_bus(addr).tap { |value| control(value) }
+      end
+
+      def poke(addr, value)
+        return unless @active
+
+        if addr < 0xdf00
+          control(value)
+        elsif @io2_ram
+          @ram_data[IO2_PAGE | (addr & 0xff)] = value
+        end
+      end
+
+      def reset
+        @active = true
+        self.nmi = false
+        control(0)
+      end
+
+      def freeze!
+        @active = true
+        @rom = bank(@rom_banks, 0)
+        select(:ultimax, @isolated, io2_ram: true)
+      end
+
+      private
+
+      def io2_peek(addr)
+        @io2_ram ? @ram_data[IO2_PAGE | (addr & 0xff)] : @rom.peek(addr)
+      end
+
+      def control(value)
+        self.nmi = false if value.anybits?(0x40)
+        @rom = bank(@rom_banks, (value >> 3) & 0x03)
+        configure(value)
+        @active = false if value.anybits?(0x04)
+      end
+
+      def configure(value)
+        return select(:rom8k, @contended, io2_ram: true) if (value & 0x23) == 0x22
+
+        configure_standard(value)
+      end
+
+      def configure_standard(value)
+        mode = CONTROL_MODES[value & 0x03]
+        if value.anybits?(0x20)
+          select(mode, mode == :ultimax ? @isolated : @through, io2_ram: true)
+        else
+          select(mode, @rom, io2_ram: false)
+        end
+      end
+
+      def select(mode, roml, io2_ram:, romh: @rom)
+        self.mode = mode
+        @roml = roml
+        @romh = romh
+        @io2_ram = io2_ram
+        changed!
+      end
+
+      def install_chips(chips)
+        @rom_banks = banks_from(chips).first
+        @ram_data = Array.new(BANK_SIZE, 0)
+        @through = RAMBank.new(@ram_data)
+        @isolated = RAMBank.new(@ram_data)
+        @contended = ContendedRAM.new(@ram_data)
+        reset
+      end
+    end
+  end
+end

data/lib/badline/cartridge/atomic_power.rb

@@ -0,0 +1,24 @@
+# frozen_string_literal: true
+
+module Badline
+  class Cartridge
+    # Atomic Power, sold as Nordic Power: an Action Replay 5 with one more
+    # configuration. RAM with only EXROM released and bits 2, 6 and 7 clear
+    # ($22) selects 16K mode with the ROM bank at ROML and the RAM at ROMH
+    # and I/O 2. Writes to that RAM don't reach the C64's. The VIC never
+    # sees Ultimax mode.
+    class AtomicPower < ActionReplay
+      def phi1_ultimax?
+        false
+      end
+
+      private
+
+      def configure(value)
+        return select(:rom16k, @rom, romh: @isolated, io2_ram: true) if (value & 0xe7) == 0x22
+
+        configure_standard(value)
+      end
+    end
+  end
+end

data/lib/badline/cartridge/bank.rb

@@ -0,0 +1,81 @@
+# frozen_string_literal: true
+
+module Badline
+  class Cartridge
+    # One 8K bank of cartridge ROM. The chip decodes only the low address
+    # lines, so the same bank answers at $8000, $A000 or $E000, and a smaller
+    # chip mirrors across the window.
+    class Bank
+      def initialize(data)
+        size = [1 << (data.length - 1).bit_length, 1].max
+        @mask = size - 1
+        @data = (data + ([0xff] * (size - data.length))).freeze
+      end
+
+      def peek(addr)
+        @data[addr & @mask]
+      end
+      alias [] peek
+    end
+
+    # Cartridge RAM mapped into the ROML or ROMH window. Writes land in the
+    # C64's RAM underneath as well, when there is a backing. Banks built on
+    # the same data are views of the same RAM.
+    class RAMBank
+      attr_reader :data
+      attr_writer :backing
+
+      def initialize(data = Array.new(BANK_SIZE, 0))
+        @data = data
+        @backing = nil
+      end
+
+      def peek(addr)
+        @data[addr & 0x1fff]
+      end
+      alias [] peek
+
+      def poke(addr, value)
+        @data[addr & 0x1fff] = value
+        @backing&.poke(addr, value)
+      end
+      alias []= poke
+    end
+
+    # Cartridge RAM the window reads, where the cartridge ignores writes.
+    class RAMReader
+      def initialize(data)
+        @data = data
+      end
+
+      def peek(addr)
+        @data[addr & 0x1fff]
+      end
+      alias [] peek
+    end
+
+    # Cartridge RAM that takes writes while the window reads something else.
+    class WriteOnlyRAM < RAMBank
+      def initialize(data, reader)
+        super(data)
+        @reader = reader
+      end
+
+      def peek(addr)
+        @reader.peek(addr)
+      end
+      alias [] peek
+    end
+
+    # Cartridge RAM selected together with the C64's RAM, both driving the
+    # bus on a read. The result is ORed, as VICE has it.
+    class ContendedRAM < RAMBank
+      def peek(addr)
+        @data[addr & 0x1fff] | @backing.peek(addr)
+      end
+      alias [] peek
+    end
+
+    EMPTY_BANK = Bank.new([0xff])
+  end
+end

data/lib/badline/cartridge/comal80.rb

@@ -0,0 +1,48 @@
+# frozen_string_literal: true
+
+module Badline
+  class Cartridge
+    # Comal-80: four 16K banks, or eight with the extra ROMs. A write to
+    # I/O 1 selects the bank and the memory configuration. The black board
+    # (subtype 0) takes the bank from bits 0-2 and switches the ROM out with
+    # bit 6; the grey one (subtype 1) takes the bank from bits 0-1 and the
+    # configuration from bits 5-6.
+    class Comal80 < Cartridge
+      GREY_MODES = %i[rom16k ultimax rom8k off].freeze
+
+      def initialize(crt)
+        @grey = crt.subtype == 1
+        super
+      end
+
+      def poke(addr, value)
+        return if addr > 0xdeff
+
+        if @grey
+          select(value & 0x03, GREY_MODES[(value >> 5) & 0x03])
+        else
+          select(value & 0x07, value.anybits?(0x40) ? :off : :rom16k)
+        end
+        changed!
+      end
+
+      def reset
+        select(0, :rom16k)
+        changed!
+      end
+
+      private
+
+      def select(number, mode)
+        @roml = bank(@roml_banks, number)
+        @romh = bank(@romh_banks, number)
+        self.mode = mode
+      end
+
+      def install_chips(chips)
+        @roml_banks, @romh_banks = banks_from(chips)
+        reset
+      end
+    end
+  end
+end

data/lib/badline/cartridge/dinamic.rb

@@ -0,0 +1,34 @@
+# frozen_string_literal: true
+
+module Badline
+  class Cartridge
+    # Dinamic: up to 16 8K banks. Reading $DE00-$DE0F selects the bank from
+    # the low address bits.
+    class Dinamic < Cartridge
+      def readable_io_pages
+        [0xde]
+      end
+
+      def peek(addr)
+        if addr < 0xde10
+          @roml = bank(@banks, addr & 0x0f)
+          changed!
+        end
+        open_bus(addr)
+      end
+
+      def reset
+        @roml = bank(@banks, 0)
+        changed!
+      end
+
+      private
+
+      def install_chips(chips)
+        @banks = banks_from(chips).first
+        self.mode = :rom8k
+        reset
+      end
+    end
+  end
+end

data/lib/badline/cartridge/easy_flash.rb

@@ -0,0 +1,122 @@
+# frozen_string_literal: true
+
+module Badline
+  class Cartridge
+    # EasyFlash: two Am29F040B flash chips, one for ROML and one for ROMH,
+    # each 64 banks of 8K, and 256 bytes of RAM at $DF00. $DE00 selects the
+    # bank. $DE02 sets the memory configuration: bit 2 hands the GAME line
+    # to bit 0 (otherwise the boot jumper holds it low), bit 1 pulls EXROM
+    # low and bit 7 drives the LED.
+    #
+    # The flash takes writes in Ultimax mode, at $8000 for ROML and $E000
+    # for ROMH, which is how EAPI programs and erases it. The writes stay in
+    # memory; #save_crt writes the flash out as a new image.
+    #
+    # An image built for EasyFlash carries an EAPI, the flash driver, at $B800
+    # in bank 0 of ROMH. On attach, as in VICE, the bundled Am29F040 EAPI
+    # (roms/eapi) takes its place, so the image drives the flash emulated here.
+    class EasyFlash < Cartridge
+      BANKS = 64
+      EAPI_OFFSET = 0x1800
+      EAPI = File.binread(File.expand_path("../roms/eapi/eapi-am29f040-14", __dir__)).bytes.drop(2).freeze
+
+      attr_reader :low_flash, :high_flash
+
+      def clock=(clock)
+        super
+        [@low_flash, @high_flash].each { |flash| flash.clock = clock }
+      end
+
+      def readable_io_pages
+        [0xdf]
+      end
+
+      def peek(addr)
+        @io_ram[addr & 0xff]
+      end
+
+      def poke(addr, value)
+        if addr >= 0xdf00
+          @io_ram[addr & 0xff] = value
+        elsif addr.nobits?(0x02)
+          @bank = value & 0x3f
+          select_bank
+        else
+          @control = value & 0x87
+          apply_control
+          changed!
+        end
+      end
+
+      def led?
+        @control.anybits?(0x80)
+      end
+
+      # Reset clears both registers, and leaves the flash and the RAM.
+      def reset
+        @bank = 0
+        @control = 0
+        apply_control
+        select_bank
+      end
+
+      # Writes every bank that isn't blank to a CRT image at path.
+      def save_crt(path)
+        chips = (0...BANKS).flat_map do |number|
+          [[@low_flash, 0x8000], [@high_flash, 0xa000]].filter_map do |flash, address|
+            data = flash.data[number * BANK_SIZE, BANK_SIZE]
+            Storage::CRTFile::Chip.new(chip_type: 2, bank: number, address:, data:) if data.any?(0..0xfe)
+          end
+        end
+        image = Storage::CRTFile::Image.new(hardware_type: 32, subtype: 0, exrom: 1, game: 0, name:, chips:)
+        Storage::CRTFile.write(path, image)
+      end
+
+      private
+
+      def select_bank
+        @roml = @low_flash.window(@bank * BANK_SIZE)
+        @romh = @high_flash.window(@bank * BANK_SIZE)
+        changed!
+      end
+
+      def apply_control
+        game = @control.nobits?(0x04) || @control.anybits?(0x01)
+        exrom = @control.anybits?(0x02)
+        @game = game ? 0 : 1
+        @exrom = exrom ? 0 : 1
+      end
+
+      def install_chips(chips)
+        low = Array.new(BANKS * BANK_SIZE, 0xff)
+        high = Array.new(BANKS * BANK_SIZE, 0xff)
+        chips.each do |chip|
+          offset = (chip.bank & 0x3f) * BANK_SIZE
+          if chip.address >= ROMH_START
+            place(high, offset, chip.data)
+          else
+            place(low, offset, chip.data)
+            place(high, offset, chip.data[BANK_SIZE..]) if chip.data.length > BANK_SIZE
+          end
+        end
+        install_eapi(high)
+        @low_flash = Flash.new(low)
+        @high_flash = Flash.new(high)
+        [@low_flash, @high_flash].each { |flash| flash.on_change { select_bank } }
+        @io_ram = Array.new(0x100, 0xff)
+        reset
+      end
+
+      def install_eapi(high)
+        return unless high[EAPI_OFFSET, 4] == "eapi".bytes
+
+        high[EAPI_OFFSET, EAPI.length] = EAPI
+      end
+
+      def place(flash_data, offset, bytes)
+        bytes = bytes.first(BANK_SIZE)
+        flash_data[offset, bytes.length] = bytes
+      end
+    end
+  end
+end

data/lib/badline/cartridge/epyx_fastload.rb

@@ -0,0 +1,71 @@
+# frozen_string_literal: true
+
+module Badline
+  class Cartridge
+    # Epyx FastLoad: 8K. A capacitor holds the ROM in for 512 cycles after
+    # it was last discharged, by reset, a read through ROML or a read of
+    # I/O 1; once it charges, $8000-$9FFF reads RAM. I/O 2 reads the last
+    # 256 bytes of the ROM.
+    class EpyxFastload < Cartridge
+      DISCHARGED_CYCLES = 512
+
+      class Window
+        def initialize(cartridge, rom)
+          @cartridge = cartridge
+          @rom = rom
+        end
+
+        def peek(addr)
+          @cartridge.rom_visible? ? @rom.peek(addr) : @cartridge.ram_peek(addr)
+        end
+      end
+
+      def clock=(clock)
+        super
+        discharge!
+      end
+
+      def readable_io_pages
+        [0xde, 0xdf]
+      end
+
+      def peek(addr)
+        return @rom.peek(addr) if addr >= 0xdf00
+
+        discharge!
+        open_bus(addr)
+      end
+
+      # True while the capacitor holds the ROM in, discharging it again.
+      def rom_visible?
+        return true unless @clock
+        return false if @clock.call - @discharged_at >= DISCHARGED_CYCLES
+
+        discharge!
+        true
+      end
+
+      def ram_peek(addr)
+        @ram.peek(addr)
+      end
+
+      # Reset discharges the capacitor, so the ROM shows.
+      def reset
+        discharge!
+      end
+
+      private
+
+      def discharge!
+        @discharged_at = @clock ? @clock.call : 0
+      end
+
+      def install_chips(chips)
+        @rom = banks_from(chips).first.compact.first
+        @roml = Window.new(self, @rom)
+        @discharged_at = 0
+        self.mode = :rom8k
+      end
+    end
+  end
+end

data/lib/badline/cartridge/final_cartridge3.rb

@@ -0,0 +1,77 @@
+# frozen_string_literal: true
+
+module Badline
+  class Cartridge
+    # The Final Cartridge III: four 16K banks, or sixteen on the III+. I/O 1
+    # and I/O 2 show the last two pages of the selected ROML bank. A write
+    # to $DFFF sets the register:
+    #
+    #   bits 0-1 bank (0-3 on the III+)
+    #   bit 4    EXROM level
+    #   bit 5    GAME level
+    #   bit 6    NMI line, active low
+    #   bit 7    hides the register until the next freeze
+    #
+    # Clearing bit 6 pulls NMI without freezing, and setting it lets go of
+    # NMI after a freeze. A freeze keeps the bank and switches to Ultimax,
+    # which the VIC doesn't see until the register sets it again.
+    class FinalCartridge3 < Cartridge
+      include Freezer
+
+      REGISTER = 0xdfff
+
+      def readable_io_pages
+        [0xde, 0xdf]
+      end
+
+      def peek(addr)
+        @io_bank.peek(addr)
+      end
+
+      def poke(addr, value)
+        return unless addr == REGISTER && @register_visible
+
+        @register_visible = value.nobits?(0x80)
+        self.nmi = value.nobits?(0x40)
+        select(value & @bank_mask)
+        @exrom = (value >> 4) & 0x01
+        @game = (value >> 5) & 0x01
+        @phi1_ultimax = ultimax?
+        changed!
+      end
+
+      def phi1_ultimax?
+        @phi1_ultimax
+      end
+
+      def reset
+        @register_visible = true
+        @phi1_ultimax = false
+        self.nmi = false
+        select(0)
+        self.mode = :rom16k
+        changed!
+      end
+
+      def freeze!
+        @register_visible = true
+        @phi1_ultimax = false
+        self.mode = :ultimax
+        changed!
+      end
+
+      private
+
+      def select(number)
+        @io_bank = @roml = bank(@roml_banks, number)
+        @romh = bank(@romh_banks, number)
+      end
+
+      def install_chips(chips)
+        @roml_banks, @romh_banks = banks_from(chips)
+        @bank_mask = @roml_banks.length > 4 ? 0x0f : 0x03
+        reset
+      end
+    end
+  end
+end