badline 0.1.0 → 0.2.1

data/lib/badline/cia.rb

@@ -1,68 +1,105 @@
 # frozen_string_literal: true
 
-require "forwardable"
+require "badline/cia/interrupt_register"
+require "badline/cia/serial"
 require "badline/cia/timer"
 
 module Badline
   # CIA (Complex Interface Adapter) chip
   class CIA
     include Addressable
-    extend Forwardable
 
-    attr_reader :start, :control_a, :control_b, :interrupt_status, :interrupt_control, :peripheral
+    attr_reader :start, :control_a, :control_b, :peripheral, :serial
 
-    def_delegator :@ta, :counter,  :timer_a
-    def_delegator :@ta, :counter=, :timer_a=
-    def_delegator :@ta, :latch,    :timer_a_latch
-    def_delegator :@ta, :latch=,   :timer_a_latch=
-    def_delegator :@tb, :counter,  :timer_b
-    def_delegator :@tb, :counter=, :timer_b=
-    def_delegator :@tb, :latch,    :timer_b_latch
-    def_delegator :@tb, :latch=,   :timer_b_latch=
+    def interrupt_status = @icr.status
+
+    def interrupt_control = @icr.mask
+
+    def interrupt!(delay = 1) = @icr.assert!(delay)
+
+    def timer_a = @ta.counter
+
+    def timer_a=(value)
+      @ta.counter = value
+    end
+
+    def timer_a_latch = @ta.latch
+
+    def timer_a_latch=(value)
+      @ta.latch = value
+    end
+
+    def timer_b = @tb.counter
+
+    def timer_b=(value)
+      @tb.counter = value
+    end
+
+    def timer_b_latch = @tb.latch
+
+    def timer_b_latch=(value)
+      @tb.latch = value
+    end
 
     def initialize(start: 0, peripheral: nil)
       addressable_at(start, length: 2**8)
 
       @peripheral = peripheral
-      @data_port_a = 0xff
-      @data_port_b = 0xff
-      @data_dir_a = 0xff
-      @data_dir_b = 0x0
-      @irq_pending = 0
-      @serial_data = 0x0
+      @port_b4_handler = nil
+      @port_b4_high = true
+      reset!
+    end
+
+    # The RES line: ports back to inputs, timers stopped with their latches
+    # full, interrupts masked and the TOD clock stopped at 1:00:00.0. The
+    # PB4 level carries over and is resampled on the next cycle.
+    def reset!
+      @data_port_a = 0x00
+      @data_port_b = 0x00
+      @data_dir_a = 0x00
+      @data_dir_b = 0x00
+      @port_b4_driven_high = true
+      @cnt_high = true
+      @cnt_rise = false
       @tod = TimeOfDay.new
-      @interrupt_control = Status.new([:timer_a, :timer_b, :alarm, :serial,
-                                       :flag, 0, 0, 0])
-      @interrupt_status = Status.new([:timer_a, :timer_b, :alarm, :serial,
-                                      :flag, 0, 0, :interrupt])
-      @control_a = Status.new(%i[start output out_mode run_mode load
-                                 in_mode serial_mode clock_frequency])
-      @control_b = Status.new(%i[start output out_mode run_mode load
-                                 in_cnt in_timer_a alarm])
+      @icr = InterruptRegister.new
+      @icr_status = @icr.status
+      @control_a = ControlRegister.new(%i[start output out_mode run_mode load
+                                          in_mode serial_mode clock_frequency])
+      @control_b = ControlRegister.new(%i[start output out_mode run_mode load
+                                          in_cnt in_timer_a alarm])
       @ta = Timer.new(@control_a)
       @tb = Timer.new(@control_b)
+      @serial = Serial.new(@control_a)
     end
 
-    def interrupt!(delay = 1)
-      @irq_pending = @irq_pending.positive? ? [@irq_pending, delay].min : delay
+    # Register a change handler on the PB4 line. On CIA 1, this feeds the
+    # light pen input.
+    def on_port_b4_change(&handler)
+      @port_b4_handler = handler
     end
 
-    def interrupted?
-      interrupt_status.value.anybits?(0x80)
-    end
+    # A falling edge on the FLAG pin. On CIA 1 the datasette's tape read
+    # line drives it, on CIA 2 the serial bus SRQ.
+    def flag! = raise_interrupt(:flag)
+
+    def interrupted? = @icr_status.value >= 0x80
 
     def cycle!
-      if @irq_pending.positive?
-        @irq_pending -= 1
-        interrupt_status.interrupt = true if @irq_pending.zero?
-      end
-      update_timers
+      @icr.cycle! unless @icr.quiet
+      refresh_port_b4 if @port_b4_handler
+      level = @serial.cnt
+      level == @cnt_high ? @cnt_rise = false : cnt_edge(level)
+      underflowed = update_timers
+      @serial.cycle!(underflowed) { trigger_serial } if underflowed || !@serial.idle
       @tod.cycle! { trigger_alarm }
     end
 
     def read_port_a
-      pulldown = peripheral ? peripheral.read_a(@data_port_a, @data_port_b) : 0xff
-      driven_lines(@data_port_a, @data_dir_a) & pulldown
+      lines = driven_lines(@data_port_a, @data_dir_a)
+      return lines unless peripheral
+
+      lines & peripheral.read_a(lines, driven_lines(@data_port_b, @data_dir_b))
     end
 
     # Port A as driven by the data/direction registers alone, without
@@ -72,9 +109,9 @@ module Badline
     end
 
     def read_port_b
-      pulldown = peripheral ? peripheral.read_b(@data_port_a, @data_port_b) : 0xff
-      value = driven_lines(@data_port_b, @data_dir_b) & pulldown
-      apply_timer_output(value)
+      lines = driven_lines(@data_port_b, @data_dir_b)
+      lines &= peripheral.read_b(driven_lines(@data_port_a, @data_dir_a), lines) if peripheral
+      apply_timer_output(lines)
     end
 
     def peek(addr)
@@ -91,12 +128,8 @@ module Badline
       when 0x09 then @tod.seconds
       when 0x0a then @tod.minutes
       when 0x0b then @tod.hours
-      when 0x0c then @serial_data
-      when 0x0d
-        value = interrupt_status.value
-        interrupt_status.value = 0x0 # Burn after reading
-        @irq_pending = 0
-        value
+      when 0x0c then @serial.data
+      when 0x0d then @icr.read
       when 0x0e then control_a.value
       when 0x0f then control_b.value
       end
@@ -105,9 +138,9 @@ module Badline
     def poke(addr, value)
       case index(addr) & 0x0f
       when 0x00 then @data_port_a = value
-      when 0x01 then @data_port_b = value
+      when 0x01 then update_port_b { @data_port_b = value }
       when 0x02 then @data_dir_a = value
-      when 0x03 then @data_dir_b = value
+      when 0x03 then update_port_b { @data_dir_b = value }
       when 0x04 then @ta.write_latch_low(value)
       when 0x05 then @ta.write_latch_high(value)
       when 0x06 then @tb.write_latch_low(value)
@@ -116,16 +149,32 @@ module Badline
       when 0x09 then @tod.write(:seconds, value, alarm: control_b.alarm?)
       when 0x0a then @tod.write(:minutes, value, alarm: control_b.alarm?)
       when 0x0b then @tod.write_hours(value, alarm: control_b.alarm?)
-      when 0x0c
-        # TODO: Serial
-      when 0x0d then write_interrupt_control(value)
-      when 0x0e then @ta.write_control(value)
+      when 0x0c then @serial.write(value)
+      when 0x0d then @icr.write(value)
+      when 0x0e then write_control_a(value)
       when 0x0f then @tb.write_control(value)
       end
     end
 
     private
 
+    def update_port_b
+      yield
+      @port_b4_driven_high = driven_lines(@data_port_b, @data_dir_b).anybits?(0x10)
+      refresh_port_b4 if @port_b4_handler
+    end
+
+    # PB4 is also control port 1's fire line, and a peripheral pulls it low
+    # without any register write, so the level is resampled every cycle rather
+    # than only after a poke.
+    def refresh_port_b4
+      high = @port_b4_driven_high && (peripheral.nil? || peripheral.port_b4_high?)
+      return if high == @port_b4_high
+
+      @port_b4_high = high
+      @port_b4_handler.call(high)
+    end
+
     def driven_lines(register, direction)
       # Output bits are driven from the data register; input bits float high.
       # External peripherals can still pull any line low (wired-AND).
@@ -133,57 +182,58 @@ module Badline
     end
 
     def apply_timer_output(value)
-      value = with_bit(value, 6, timer_a_output?) if control_a.output?
-      value = with_bit(value, 7, timer_b_output?) if control_b.output?
+      value = with_bit(value, 6, @ta.output?) if control_a.output?
+      value = with_bit(value, 7, @tb.output?) if control_b.output?
       value
     end
 
-    def timer_a_output?
-      control_a.out_mode? ? @ta.toggle? : @ta.underflowed
-    end
-
-    def timer_b_output?
-      control_b.out_mode? ? @tb.toggle? : @tb.underflowed
-    end
-
     def with_bit(value, bit, set)
       set ? value | (1 << bit) : value & ~(1 << bit)
     end
 
-    def trigger_alarm
-      interrupt_status.alarm = true
-      interrupt! if interrupt_control.alarm?
+    def trigger_alarm = raise_interrupt(:alarm)
+    def trigger_serial = raise_interrupt(:serial)
+
+    def raise_interrupt(source) = @icr.flag(source)
+
+    # CNT is sampled once a cycle. When the serial port drives it from this
+    # cycle's timer A underflow, the new level is picked up on the next one.
+    def cnt_edge(level)
+      @cnt_high = level
+      @cnt_rise = level
+      @serial.rising_edge! { trigger_serial } if level
     end
 
+    # Returns whether timer A underflowed, which clocks the serial port.
+    #
+    # CRB bits 6-5 pick timer B's source: ø2, CNT edges, timer A
+    # underflows, or timer A underflows gated by the CNT level. Every source
+    # drives the same count-enable line, so a cascaded underflow goes through
+    # the input pipeline exactly as a CNT edge does.
     def update_timers
-      @ta.cycle!(@control_a.value.nobits?(0x20), true)
-      crb = @control_b.value
-      if crb.anybits?(0x40)
-        @tb.cycle!(true, @ta.underflowed)
-      else
-        @tb.cycle!(crb.nobits?(0x20), true)
-      end
-      if @ta.underflowed
+      @ta.cycle!(@control_a.value & 0x20 == 0x20 ? @cnt_rise : true)
+      underflowed = @ta.underflowed
+      @tb.cycle!(
+        case @control_b.value & 0x60
+        when 0x00 then true
+        when 0x20 then @cnt_rise
+        when 0x40 then underflowed
+        else underflowed && @cnt_high
+        end
+      )
+      if underflowed
         interrupt_status.timer_a = true
         interrupt! if interrupt_control.timer_a?
       end
-      return unless @tb.underflowed
-
-      interrupt_status.timer_b = true
-      interrupt! if interrupt_control.timer_b?
+      @icr.timer_b_underflow! if @tb.underflowed
+      underflowed
     end
 
-    def write_interrupt_control(value)
-      if value.nobits?(0x80)
-        # Clear interrupts based on bits 0-4
-        interrupt_control.value &= ~(value & 0x1f)
-      else
-        # Set interrupts based on bits 0-4
-        interrupt_control.value |= (value & 0x1f)
-      end
-      return unless interrupt_control.value.anybits?(interrupt_status.value & 0x1f)
-
-      interrupt!(2) unless interrupted?
+    def write_control_a(value)
+      was_output = control_a.serial_mode?
+      @ta.write_control(value)
+      @serial.reset! { trigger_serial } if control_a.serial_mode? != was_output
+      @tod.fifty_hz = control_a.clock_frequency?
     end
   end
 end

data/lib/badline/color_memory.rb

@@ -1,16 +1,25 @@
 # frozen_string_literal: true
 
 module Badline
+  # Colour RAM is four bits wide. A CPU read takes the upper nibble off the
+  # open data bus, which still holds the byte the VIC fetched in phi1.
   class ColorMemory < Memory
+    def initialize(vic, start: 0xd800, length: 2**10)
+      super(start:, length:)
+      @vic = vic
+    end
+
+    def peek(addr)
+      (@vic.phi1_data & 0xf0) | @storage[index(addr)]
+    end
+
     def poke(addr, value)
-      # Only write the lower 4 bits
       super(addr, value & 0x0f)
     end
 
-    private
-
-    def blank_value
-      rand(16) << 4
+    # The four bits the cell stores, as the VIC's c-access sees them.
+    def nibble(addr)
+      @storage[index(addr)]
     end
   end
 end

data/lib/badline/computer.rb

@@ -1,25 +1,48 @@
 # frozen_string_literal: true
 
-require "forwardable"
-
 module Badline
   class Computer
     include IntegerHelper
     include KeyboardBuffer
-    extend Forwardable
 
     attr_reader :address_bus, :cpu, :cycles
 
-    def_delegators :address_bus, :vic, :cia1, :cia2, :sid, :ram, :keyboard, :joystick2
+    def vic = address_bus.vic
+
+    def cia1 = address_bus.cia1
+
+    def cia2 = address_bus.cia2
+
+    def sid = address_bus.sid
+
+    def ram = address_bus.ram
+
+    def keyboard = address_bus.keyboard
+
+    def joystick1 = address_bus.joystick1
+
+    def joystick2 = address_bus.joystick2
 
-    def initialize(debug: false)
-      @address_bus = AddressBus.new
+    def control_ports = address_bus.control_ports
+
+    def datasette = address_bus.datasette
+
+    def install_debug_register(&) = address_bus.install_debug_register(&)
+
+    def initialize(debug: false, sid_model: :mos6581)
+      @address_bus = AddressBus.new(sid_model:)
       @cpu = CPU.new(@address_bus, debug:)
       @vic = @address_bus.vic
+      @vic.open_bus = -> { @address_bus.ram.peek(@cpu.program_counter) }
       @cia1 = @address_bus.cia1
       @cia2 = @address_bus.cia2
+      @sid = @address_bus.sid
+      @datasette = @address_bus.datasette
       @cycles = 0
       @nmi_asserted = false
+      @cartridge_nmi = false
+      @freezing = false
+      @freeze_writes = 0
       @init_handlers = []
       @pending_keys = nil
     end
@@ -30,17 +53,19 @@ module Badline
       handle_init if @cycles == INIT_THRESHOLD
       feed_keyboard if @pending_keys
 
+      # The chips clock ahead of the CPU, so a register write lands on the
+      # cycle after the one it was issued on.
       @vic.cycle!
       @cia1.cycle!
       @cia2.cycle!
+      @sid.cycle!
+      @datasette.cycle!
 
       @cpu.irq = @cia1.interrupted? || @vic.interrupted?
 
-      nmi = @cia2.interrupted?
-      @cpu.nmi = true if nmi && !@nmi_asserted
-      @nmi_asserted = nmi
-
-      @cpu.cycle! if @cpu.pending_write? || !@vic.ba_low?
+      drive_nmi
+      watch_freeze if @freezing
+      @cpu.pending_write? || !@vic.ba_low? ? @cpu.cycle! : @cpu.stall!
 
       @cycles += 1
     end
@@ -52,13 +77,54 @@ module Badline
     end
 
     def attach_cartridge(cartridge)
+      cartridge.clock = -> { @cycles }
+      cartridge.on_nmi_change { |level| @cartridge_nmi = level }
       address_bus.attach_cartridge(cartridge)
+      power_cycle!
+    end
+
+    # A cartridge goes in with the power off, so attaching one switches the
+    # machine off and on: the VIC and RAM start from their power-on state,
+    # and the RES line resets everything else.
+    def power_cycle!
+      vic.power_on!
+      address_bus.power_on!
+      reset!
+    end
+
+    # The RES line reaches the CPU and its port, both CIAs, the SID and the
+    # cartridge port. The VIC has no reset pin.
+    def reset!
+      address_bus.reset_port!
+      @cia1.reset!
+      @cia2.reset!
+      @sid.reset!
+      address_bus.cartridge&.reset
+      @freezing = false
+      @nmi_asserted = false
       cpu.reset!
     end
 
+    # Presses the cartridge's freeze button. When the press pulls NMI, the
+    # cartridge freezes once the CPU takes the interrupt.
+    def press_cartridge_button
+      cartridge = address_bus.cartridge
+      return unless cartridge
+
+      cartridge.press_button
+      @freezing = cartridge.nmi?
+      @freeze_writes = 0
+    end
+
+    def release_cartridge_button
+      address_bus.cartridge&.release_button
+    end
+
     def mount(storage)
-      load_trap = KernalTrap::Load.new(cpu:, bus: address_bus, storage:)
+      drive = KernalTrap::Drive.new(storage)
+      load_trap = KernalTrap::Load.new(cpu:, bus: address_bus, drive:)
       cpu.install_trap(KernalTrap::Load::ADDRESS) { load_trap.call }
+      KernalTrap::Serial.new(cpu:, bus: address_bus, drive:).install
       return unless storage.respond_to?(:write_file)
 
       save_trap = KernalTrap::Save.new(cpu:, bus: address_bus, storage:)
@@ -85,6 +151,25 @@ module Badline
 
     private
 
+    # The NMI line is wired-OR between CIA 2 and the cartridge, and the CPU
+    # takes an interrupt on its falling edge.
+    def drive_nmi
+      nmi = @cia2.interrupted? || @cartridge_nmi
+      @cpu.nmi = true if nmi && !@nmi_asserted
+      @nmi_asserted = nmi
+    end
+
+    # A freezer counts the CPU's write cycles once it pulls NMI and switches
+    # to Ultimax on the third in a row, the last push of the interrupt
+    # sequence, so the vector fetch that follows reads the cartridge.
+    def watch_freeze
+      @freeze_writes = @cpu.pending_write? ? @freeze_writes + 1 : 0
+      return if @freeze_writes < 3
+
+      @freezing = false
+      address_bus.cartridge.freeze!
+    end
+
     def booting?
       @cycles < init_threshold
     end

data/lib/badline/control_ports.rb

@@ -1,24 +1,69 @@
 # frozen_string_literal: true
 
 module Badline
-  # CIA 1 peripheral combining the keyboard matrix with the control ports.
+  # CIA 1's control ports and the keyboard matrix that spans them.
   #
-  # Joystick switches share the same lines as the keyboard matrix and are
-  # wired-AND with it (active low). Port 2 sits on Port A.
+  # Port A carries the matrix rows together with joystick 2, port B the matrix
+  # columns together with joystick 1. Every switch is active low, so the
+  # joysticks are wired-AND onto the lines *before* the matrix settles: a stick
+  # held in a direction selects rows and columns of its own, which is where
+  # hardware's phantom keypresses come from. Paddles and a 1351 mouse have
+  # buttons on those same lines.
+  #
+  # The ports also carry SID's POTX/POTY lines, which reach them through analog
+  # switches closed by CIA 1 PA6 (port 1) and PA7 (port 2). Close both and the
+  # pots sit in parallel, so SID charges through the lower of the two
+  # resistances; close neither and the lines float high. Reading a pot asks the
+  # CIA for the current select lines, since a program sets them and then goes
+  # straight to SID without touching the ports again.
   class ControlPorts
-    attr_reader :keyboard, :joystick2
+    PORT1_POTS = 0x40
+    PORT2_POTS = 0x80
+    FIRE = 0x10
+
+    attr_reader :keyboard, :joystick1, :joystick2
+    attr_accessor :device1, :device2, :port_a_source
 
-    def initialize(keyboard:, joystick2:)
+    def initialize(keyboard:, joystick1:, joystick2:)
       @keyboard = keyboard
+      @joystick1 = joystick1
       @joystick2 = joystick2
+      @device1 = nil
+      @device2 = nil
+      @port_a_source = nil
+    end
+
+    def read_a(port_a, port_b) = scan(port_a, port_b).first
+
+    def read_b(port_a, port_b) = scan(port_a, port_b).last
+
+    # Control port 1 pin 6 is both the port B fire line and the VIC's light
+    # pen input, so joystick 1's button and a 1351's left button latch
+    # $D013/$D014. The CIA samples this every cycle, so it skips the matrix and
+    # asks only what the port's own devices drive.
+    def port_b4_high? = port_bits(@joystick1, @device1).anybits?(FIRE)
+
+    def pot_x = selected_devices.map(&:pot_x).min || 0xff
+
+    def pot_y = selected_devices.map(&:pot_y).min || 0xff
+
+    private
+
+    def selected_devices
+      lines = @port_a_source&.port_a_lines || 0x00
+      devices = []
+      devices << @device1 if @device1 && lines.anybits?(PORT1_POTS)
+      devices << @device2 if @device2 && lines.anybits?(PORT2_POTS)
+      devices
     end
 
-    def read_a(port_a, port_b)
-      keyboard.read_a(port_a, port_b) & joystick2.port_bits
+    def scan(port_a, port_b)
+      keyboard.scan(port_a & port_bits(@joystick2, @device2),
+                    port_b & port_bits(@joystick1, @device1))
     end
 
-    def read_b(port_a, port_b)
-      keyboard.read_b(port_a, port_b)
+    def port_bits(joystick, device)
+      device ? joystick.port_bits & device.port_bits : joystick.port_bits
     end
   end
 end