badline 0.1.0 → 0.2.0

data/lib/badline/cartridge.rb

@@ -1,33 +1,72 @@
 # frozen_string_literal: true
 
+require "badline/cartridge/bank"
+require "badline/cartridge/flash"
 require "badline/cartridge/standard"
+require "badline/cartridge/simons_basic"
 require "badline/cartridge/ocean"
+require "badline/cartridge/fun_play"
+require "badline/cartridge/super_games"
+require "badline/cartridge/epyx_fastload"
+require "badline/cartridge/westermann"
+require "badline/cartridge/rex_utility"
+require "badline/cartridge/game_system"
+require "badline/cartridge/dinamic"
+require "badline/cartridge/zaxxon"
 require "badline/cartridge/magic_desk"
+require "badline/cartridge/comal80"
+require "badline/cartridge/easy_flash"
+require "badline/cartridge/mach5"
+require "badline/cartridge/pagefox"
+require "badline/cartridge/rgcd"
+require "badline/cartridge/g_mod2"
+require "badline/cartridge/freezer"
+require "badline/cartridge/action_replay"
+require "badline/cartridge/atomic_power"
+require "badline/cartridge/final_cartridge3"
+require "badline/cartridge/retro_replay"
+require "badline/cartridge/kcs_power"
 
 module Badline
   class Cartridge
     class UnsupportedTypeError < StandardError; end
 
-    ROML_START = 0x8000
     ROMH_START = 0xa000
-    ULTIMAX_ROMH_START = 0xe000
     BANK_SIZE = 0x2000
 
-    HARDWARE_TYPES = { 0 => :Standard, 5 => :Ocean, 19 => :MagicDesk }.freeze
+    HARDWARE_TYPES = {
+      0 => :Standard, 1 => :ActionReplay, 2 => :KCSPower, 3 => :FinalCartridge3,
+      4 => :SimonsBasic, 5 => :Ocean, 7 => :FunPlay, 8 => :SuperGames,
+      9 => :AtomicPower, 10 => :EpyxFastload, 11 => :Westermann,
+      12 => :RexUtility, 15 => :GameSystem, 17 => :Dinamic, 18 => :Zaxxon,
+      19 => :MagicDesk, 21 => :Comal80, 32 => :EasyFlash, 36 => :RetroReplay,
+      51 => :Mach5, 53 => :Pagefox, 57 => :RGCD, 60 => :GMod2
+    }.freeze
+
+    # The EXROM and GAME line levels of each memory configuration. The lines
+    # are active low.
+    MODES = {
+      rom8k: [0, 1].freeze, rom16k: [0, 0].freeze,
+      ultimax: [1, 0].freeze, off: [1, 1].freeze
+    }.freeze
 
     attr_reader :name, :exrom, :game, :roml, :romh
 
+    # A callable returning the current cycle, for mappers with timed state.
+    attr_writer :clock
+
     class << self
-      def from_file(path)
-        from_crt(Storage::CRTFile.new(path))
+      # Options set the cartridge's jumpers, for the mappers that have them.
+      def from_file(path, **)
+        from_crt(Storage::CRTFile.new(path), **)
       end
 
-      def from_crt(crt)
+      def from_crt(crt, **)
         type = HARDWARE_TYPES.fetch(crt.hardware_type) do
           raise UnsupportedTypeError,
                 "Unsupported cartridge hardware type #{crt.hardware_type}"
         end
-        const_get(type).new(crt)
+        const_get(type).new(crt, **)
       end
     end
 
@@ -37,6 +76,10 @@ module Badline
       @game = crt.game
       @roml = @romh = nil
       @on_change = nil
+      @on_nmi_change = nil
+      @nmi = false
+      @open_bus = nil
+      @clock = nil
       install_chips(crt.chips)
     end
 
@@ -44,32 +87,105 @@ module Badline
       @on_change = block
     end
 
+    # Called with the level of the cartridge's pull on the NMI line when it
+    # changes. The line is wired-OR with CIA 2's.
+    def on_nmi_change(&block)
+      @on_nmi_change = block
+    end
+
+    def nmi?
+      @nmi
+    end
+
+    # The address bus hands over the C64's RAM, for mappers that write
+    # through to it, and the open bus, for I/O reads the cartridge doesn't
+    # drive.
+    def connect(ram:, open_bus:)
+      @ram = ram
+      @open_bus = open_bus
+    end
+
     def ultimax?
       @game.zero? && @exrom == 1
     end
 
-    # IO1/IO2 reads are open bus unless a mapper says otherwise.
-    def peek(_addr)
-      0xff
+    # Whether the first half of the cycle, where the VIC does most of its
+    # fetching, sees Ultimax mode. Some cartridges drive GAME and EXROM
+    # differently in the two halves; #ultimax? is the second, the CPU's.
+    def phi1_ultimax?
+      ultimax?
+    end
+
+    # The I/O pages ($de, $df) whose reads the mapper drives. Reads of the
+    # others are open bus.
+    def readable_io_pages
+      []
     end
 
     def poke(_addr, _value); end
 
+    # A window taking writes to $E000-$FFFF while reads there see the C64's
+    # memory, for a cartridge that asserts Ultimax on write cycles only.
+    def romh_writes; end
+
+    # A window at $A000-$BFFF in Ultimax mode, where the C64 maps nothing.
+    def ultimax_a000; end
+
+    # The RES line on the expansion port.
+    def reset; end
+
+    # The freeze button, which cartridges without one ignore.
+    def press_button; end
+
+    def release_button; end
+
     private
 
+    def nmi=(level)
+      return if @nmi == level
+
+      @nmi = level
+      @on_nmi_change&.call(level)
+    end
+
     def changed!
       @on_change&.call
     end
 
+    def mode=(mode)
+      @exrom, @game = MODES.fetch(mode)
+    end
+
+    def open_bus(addr)
+      @open_bus ? @open_bus.peek(addr) : 0xff
+    end
+
     def install_chips(_chips)
       raise NotImplementedError
     end
 
-    # Chips smaller than 8K (e.g. 4K Ultimax ROMs) have unconnected upper
-    # address lines and mirror across the full bank.
-    def rom_bank(data, start)
-      data *= BANK_SIZE / data.length if data.length < BANK_SIZE
-      ROM.new(data, length: data.length, start:)
+    def rom_bank(data)
+      Bank.new(data)
+    end
+
+    def bank(banks, number)
+      banks[number] || EMPTY_BANK
+    end
+
+    # Sorts the CHIP packets into ROML and ROMH banks by load address. A 16K
+    # chip at $8000 spans both.
+    def banks_from(chips)
+      roml = []
+      romh = []
+      chips.each do |chip|
+        if chip.address >= ROMH_START
+          romh[chip.bank] = rom_bank(chip.data)
+        else
+          roml[chip.bank] = rom_bank(chip.data[0, BANK_SIZE])
+          romh[chip.bank] = rom_bank(chip.data[BANK_SIZE, BANK_SIZE]) if chip.data.length > BANK_SIZE
+        end
+      end
+      [roml, romh]
     end
   end
 end

data/lib/badline/cia/interrupt_register.rb

@@ -0,0 +1,88 @@
+# frozen_string_literal: true
+
+module Badline
+  class CIA
+    # The interrupt control register: the source flags, their mask and the
+    # IR bit that drives the interrupt line, with the 6526's acknowledge
+    # timing.
+    class InterruptRegister
+      attr_reader :status, :mask, :quiet
+
+      def initialize
+        @mask = Status.new([:timer_a, :timer_b, :alarm, :serial, :flag, 0, 0, 0])
+        @status = Status.new([:timer_a, :timer_b, :alarm, :serial, :flag, 0, 0, :interrupt])
+        @pending = 0
+        @read = @read_last_cycle = @read_two_cycles_ago = nil
+        @timer_b_bug = false
+        @quiet = true
+      end
+
+      # The CIA skips this while quiet: no read is recent enough to matter
+      # and no assert is due.
+      def cycle!
+        @read_two_cycles_ago = @read_last_cycle
+        @read_last_cycle = @read
+        @read = nil
+        if @pending.positive?
+          @pending -= 1
+          status.interrupt = true if @pending.zero?
+        end
+        @quiet = @pending.zero? && @read_last_cycle.nil? && @read_two_cycles_ago.nil?
+      end
+
+      def interrupted? = status.value >= 0x80
+
+      # Schedules IR to rise after delay cycles, keeping an earlier one.
+      def assert!(delay = 1)
+        @pending = @pending.positive? ? [@pending, delay].min : delay
+        @quiet = false
+      end
+
+      # Latch a source, pulling the interrupt line if it is armed.
+      def flag(source)
+        status.public_send(:"#{source}=", true)
+        assert! if mask.public_send(:"#{source}?")
+      end
+
+      # The 6526 timer B bug: an underflow on the cycle after a read still
+      # raises the flag, but the next read drops it unseen.
+      def timer_b_underflow!
+        @timer_b_bug = !@read_last_cycle.nil?
+        flag(:timer_b)
+      end
+
+      # A read releases the interrupt line at once, and cancels an assert
+      # due on the next cycle, but on the 6526 its IR acknowledge lands a
+      # cycle late: the next cycle still reads IR set if it was set, or
+      # about to be.
+      def read
+        status.timer_b = false if @timer_b_bug
+        @timer_b_bug = false
+        value = status.value
+        @read = @pending == 1 ? value | 0x80 : value
+        @quiet = false
+        value |= 0x80 if @read_last_cycle&.anybits?(0x80)
+        status.value = 0x0
+        @pending = 0
+        value
+      end
+
+      # Bit 7 picks between setting and clearing the mask bits given.
+      def write(value)
+        if value.nobits?(0x80)
+          mask.value &= ~(value & 0x1f)
+        else
+          mask.value |= (value & 0x1f)
+        end
+        if mask.value.anybits?(status.value & 0x1f)
+          assert!(2) unless interrupted?
+        elsif @pending == 1 && @read_two_cycles_ago
+          # On the 6526, masking the pending source cancels the assert due
+          # on the next cycle only while a read two cycles back is
+          # acknowledging.
+          @pending = 0
+        end
+      end
+    end
+  end
+end

data/lib/badline/cia/serial.rb

@@ -0,0 +1,219 @@
+# frozen_string_literal: true
+
+module Badline
+  class CIA
+    # The serial shift register and the CNT line that clocks it.
+    #
+    # With CRA bit 6 clear the port is an input: SP is sampled on every
+    # rising CNT edge, and the byte reaches the data register after eight of
+    # them. With the bit set the CIA drives CNT itself, toggling it on every
+    # timer A underflow, so a byte takes sixteen underflows to go out. CNT falls
+    # as each bit is put on SP, and rises again to clock it in.
+    #
+    # The register counts itself empty as soon as the eighth bit is on SP,
+    # fifteen underflows in: the serial flag follows a few cycles later
+    # rather than waiting for the sixteenth underflow, and a byte written
+    # from that point on goes out on the next one.
+    class Serial
+      BITS = 8
+
+      # A byte written to the data register reaches the shift register one
+      # cycle later. The empty countdown starts on the underflow that puts
+      # the eighth bit on SP and is decremented on that same cycle, so the
+      # flag lands four cycles after it.
+      LOAD_DELAY = 1
+      EMPTY_DELAY = 5
+      BUSY_DELAY = 5
+
+      # The logic watching the shift register runs a few cycles behind it,
+      # so the level saying a bit is still on its way out is scheduled
+      # through a delay line: a bit set at position 7 - n takes effect n
+      # cycles later. Putting a bit on SP raises the level after one cycle
+      # and drops it again after two before raising it for good after
+      # three; the eighth bit skips straight to the last of those. CNT
+      # rising over a bit lowers the level four cycles later.
+      IN_FLIGHT = 0x50
+      LAST_IN_FLIGHT = 0x10
+      BOUNCE = 0x20
+      SETTLED = 0x08
+
+      attr_reader :data, :sp_out, :cnt, :cnt_in, :idle
+      attr_accessor :sp_in
+
+      def initialize(control)
+        @control = control
+        @data = 0x0
+        @shift = 0x0
+        @steps = 0
+        @empty_in = nil
+        @busy_in = nil
+        @busy = false
+        @abandoned = false
+        @pending = nil
+        @underflow_high = false
+        @in_flight = false
+        @flight_up = 0x0
+        @flight_down = 0x0
+        @idle = true
+        # Nothing drives the user port, so both lines float high.
+        @cnt = true
+        @cnt_in = true
+        @sp_in = true
+        @sp_out = true
+      end
+
+      def output?
+        @control.serial_mode?
+      end
+
+      def cnt_in=(level)
+        @cnt_in = level
+        @cnt = level unless output?
+      end
+
+      def write(value)
+        @data = value
+        @pending = LOAD_DELAY
+        @idle = false
+      end
+
+      # Clocked every cycle with timer A's underflow line. Yields once the
+      # shift register reports itself empty, which it does without waiting
+      # for the underflow that raises CNT over the eighth bit.
+      def cycle!(underflowed)
+        return if @idle && !underflowed
+
+        shift(underflowed)
+        @pending -= 1 if @pending&.positive?
+        drain_flight
+        count_busy
+        @idle = !underflowed && idle?
+        return if @empty_in.nil?
+
+        @empty_in -= 1
+        return unless @empty_in.zero?
+
+        @empty_in = nil
+        @busy = false
+        yield
+      end
+
+      # Clocked by rising CNT edges while receiving. Yields once a whole
+      # byte has arrived.
+      def rising_edge!
+        return if output?
+
+        @shift = ((@shift << 1) | (@sp_in ? 1 : 0)) & 0xff
+        @steps += 1
+        return unless @steps == BITS
+
+        @steps = 0
+        @data = @shift
+        yield if block_given?
+      end
+
+      # A mode change drops the byte in flight and hands CNT back to
+      # whichever side drives it now, and yields: that byte counts as gone.
+      # Handing the port over as an input tears a transmission down, so a
+      # busy register reports it; the same change latches how far the bit
+      # in flight had got, and taking the port back reports that.
+      def reset!
+        abandoned = output? ? @abandoned : @busy
+        @abandoned = output? ? false : @in_flight
+        @in_flight = false
+        @steps = 0
+        @empty_in = nil
+        @busy_in = nil
+        @busy = false
+        @pending = nil
+        @cnt = output? || @cnt_in
+        yield if abandoned
+      end
+
+      private
+
+      # Without an underflow, a register with nothing counting down and
+      # nothing in the delay lines has nothing to do on a cycle.
+      def idle?
+        !@pending&.positive? && (@flight_up | @flight_down).zero? &&
+          @busy_in.nil? && @empty_in.nil?
+      end
+
+      # The shift register picks up a waiting byte whenever the underflow
+      # line is asserted, but every half-step after that needs a fresh edge
+      # on it. A zero latch holds the line down for good rather than
+      # pulsing it, so such a byte stops after its first bit and never
+      # reaches the data register.
+      def shift(underflowed)
+        edge = underflowed && !@underflow_high
+        @underflow_high = underflowed
+        clock(edge) if underflowed && output?
+      end
+
+      def clock(edge)
+        start if @steps <= 1
+        if @steps.zero?
+          @flight_down |= SETTLED
+        elsif edge || @steps == BITS * 2
+          half_step
+        end
+      end
+
+      def half_step
+        @steps -= 1
+        @cnt = @steps.even?
+        if @cnt
+          @flight_down |= SETTLED
+        else
+          shift_out
+        end
+      end
+
+      # The register reads as busy from a few cycles after the first bit
+      # reaches SP until it reports itself empty over the eighth.
+      def mark_busy
+        case @steps
+        when (BITS * 2) - 1 then @busy_in = BUSY_DELAY
+        when 1
+          @empty_in = EMPTY_DELAY
+          @busy_in = nil
+        end
+      end
+
+      def count_busy
+        return if @busy_in.nil?
+
+        @busy_in -= 1
+        return unless @busy_in.zero?
+
+        @busy_in = nil
+        @busy = true
+      end
+
+      def drain_flight
+        @in_flight = false if @flight_down.anybits?(0x80)
+        @flight_down = (@flight_down << 1) & 0xff
+        @in_flight = true if @flight_up.anybits?(0x80)
+        @flight_up = (@flight_up << 1) & 0xff
+      end
+
+      # A byte only moves out of the data register once the one before it
+      # has put its last bit on SP.
+      def start
+        return unless @pending&.zero?
+
+        @pending = nil
+        @shift = @data
+        @steps = BITS * 2
+      end
+
+      def shift_out
+        @sp_out = @shift.anybits?(0x80)
+        @shift = (@shift << 1) & 0xff
+        mark_busy
+        @flight_up |= @steps == 1 ? LAST_IN_FLIGHT : IN_FLIGHT
+        @flight_down |= BOUNCE
+      end
+    end
+  end
+end

data/lib/badline/cia/timer.rb

@@ -8,33 +8,38 @@ module Badline
 
       def initialize(control)
         @control = control
-        @counter = @latch = 0x0
+        @counter = @latch = 0xffff
         @pipe = 0
         @load_delay = 0
         @reload = false
         @underflowed = false
         @oneshot_linger = 0
         @toggle = true
+        settle
       end
 
-      def toggle?
-        @toggle
+      # The level this timer drives on its port B pin: a square wave that
+      # flips on each underflow, or a single high tick when one happens.
+      def output?
+        control.out_mode? ? @toggle : @underflowed
       end
 
-      def cycle!(feed, pulse)
-        return @counter -= 1 if feed && pulse && steady?
-
-        if (@pipe | @load_delay).zero? && !@reload
-          @pipe = 0b10 if feed && started?
+      def cycle!(feed)
+        feed &&= @control.value & 0x01 != 0
+        if @settled
+          return @counter -= 1 if feed && @counter > 1
+        elsif @empty
+          enter if feed
           return
         end
-        run_tick(feed, pulse)
+        run_tick(feed)
       end
 
-      def run_tick(feed, pulse)
+      def run_tick(feed)
         @underflowed = false
         @oneshot_linger -= 1 if @oneshot_linger.positive?
-        tick(feed && started?, pulse)
+        tick(feed)
+        settle
       end
 
       def write_control(value)
@@ -42,6 +47,7 @@ module Badline
         @oneshot_linger = 2 if control.run_mode? && value.nobits?(0x08)
         control.value = value & ~0x10
         @load_delay = 3 if value.anybits?(0x10)
+        settle
       end
 
       def write_latch_low(value)
@@ -56,23 +62,33 @@ module Badline
       private
 
       def started?
-        control.value.anybits?(0x01)
+        @control.value & 0x01 != 0
+      end
+
+      def enter
+        @pipe = 0b10
+        @empty = false
       end
 
-      def steady?
-        @counter > 1 && @pipe == 0b11 && !@reload &&
-          (@load_delay | @oneshot_linger).zero? && started?
+      # With no load, reload or one-shot linger pending, a full pipe only
+      # counts and an empty one only waits to be fed.
+      def settle
+        quiet = (@load_delay | @oneshot_linger).zero? && !@reload
+        @settled = quiet && @pipe == 0b11
+        @empty = quiet && @pipe.zero?
       end
 
-      def tick(feed, pulse)
-        counting = @pipe.anybits?(0b01) && pulse
+      def tick(feed)
+        counting = @pipe.anybits?(0b01)
         @pipe = (@pipe >> 1) | (feed ? 0b10 : 0)
+        loading = @reload || @load_delay == 1
+        @reload = false
 
-        if premature_underflow?(pulse)
+        if loading
+          reload
+        elsif premature_underflow?
           underflow
-        elsif apply_reload?
-          return
-        elsif counting && @load_delay != 1
+        elsif counting
           count
         end
 
@@ -87,20 +103,15 @@ module Badline
       end
 
       # the final pipeline stage, before any pending load lands
-      def premature_underflow?(pulse)
-        @counter.zero? && !@reload && pulse && @pipe.anybits?(0b01) &&
-          started?
+      def premature_underflow?
+        @counter.zero? && @pipe.anybits?(0b01) && started?
       end
 
-      # An underflow reload consumes the tick after the flag
-      def apply_reload?
-        return false unless @reload
-
-        @reload = false
+      # A load consumes its tick, so the counter never decrements on it
+      def reload
         @counter = @latch
         # A zero latch underflows again on the reload tick while running
-        underflow if @counter.zero? && started?
-        true
+        underflow if @counter.zero? && started? && @pipe.anybits?(0b01)
       end
 
       def count
@@ -111,6 +122,7 @@ module Badline
       def underflow
         @underflowed = true
         @reload = true
+        @counter = @latch
         @toggle = !@toggle
         return unless control.run_mode? || @oneshot_linger.positive?