badline 0.1.0 → 0.2.0

data/lib/badline/time_of_day.rb

@@ -2,100 +2,153 @@
 
 module Badline
   class TimeOfDay
-    include IntegerHelper
-
     CLOCK_HZ = 985_248 # PAL only for now.
+    MAINS_HZ = 50      # The TOD pin is fed from the AC supply.
 
-    def initialize(clock_hz: CLOCK_HZ)
-      # The accumulator advances 10 per cycle, so a tenth of a second has
-      # passed when it reaches clock_hz. Integer math keeps it exact.
-      @cycles_per_tenth = clock_hz
+    def initialize(clock_hz: CLOCK_HZ, mains_hz: MAINS_HZ)
+      # The accumulator advances mains_hz per cycle, so a TOD pin pulse has
+      # arrived when it reaches clock_hz. Integer math keeps it exact.
+      @cycles_per_pulse = clock_hz
+      @mains_hz = mains_hz
       @accumulator = 0
-      @clock = { tenths: 0, seconds: 0, minutes: 0, hours: 12, pm: false }
-      @alarm = { tenths: 0, seconds: 0, minutes: 0, hours: 0, pm: false }
+      @pulses = 0
+      @clock = { tenths: 0x00, seconds: 0x00, minutes: 0x00, hours: 0x01 }
+      @alarm = { tenths: 0x00, seconds: 0x00, minutes: 0x00, hours: 0x00 }
       @latch = nil
-      @stopped = false
+      @stopped = true
+      @alarm_pending = false
+      self.fifty_hz = false
     end
 
-    def cycle!
-      return if @stopped
+    # CRA bit 7 divides the TOD pin by 5 instead of 6. The divider has to
+    # match the pin frequency to keep time, so PAL software selects 50 Hz.
+    def fifty_hz=(enabled)
+      @match = enabled ? 4 : 5
+    end
 
-      @accumulator += 10
-      return if @accumulator < @cycles_per_tenth
+    def cycle!
+      @accumulator += @mains_hz
+      pulse! if @accumulator >= @cycles_per_pulse
+      return unless @alarm_pending
 
-      @accumulator -= @cycles_per_tenth
-      advance
-      yield if block_given? && alarm?
+      @alarm_pending = false
+      yield if block_given?
     end
 
     def tenths
       value = (@latch || @clock)[:tenths]
       @latch = nil
-      bcd(value)
-    end
-
-    def seconds
-      bcd((@latch || @clock)[:seconds])
+      value
     end
 
-    def minutes
-      bcd((@latch || @clock)[:minutes])
-    end
+    def seconds = (@latch || @clock)[:seconds]
+    def minutes = (@latch || @clock)[:minutes]
 
     def hours
       @latch ||= @clock.dup
-      bcd(@latch[:hours]) | (@latch[:pm] ? 0x80 : 0)
+      @latch[:hours]
     end
 
     def write(field, value, alarm:)
-      (alarm ? @alarm : @clock)[field] = bcd_to_i(value)
-      # Start the clock again when writing tenths.
-      resume if field == :tenths && !alarm
+      # The frequency counter is held clear while the clock is stopped, and
+      # starts counting again from the write to tenths that restarts it.
+      if field == :tenths && !alarm && @stopped
+        @pulses = 0
+        @stopped = false
+      end
+      store(field, value & (field == :tenths ? 0x0f : 0x7f), alarm: alarm)
     end
 
     # 12-hour BCD value, bit 7 is the AM/PM flag.
     def write_hours(value, alarm:)
-      target = alarm ? @alarm : @clock
-      target[:hours] = bcd_to_i(value & 0x7f)
-      target[:pm] = value.anybits?(0x80)
+      value &= 0x9f
+      # Writing 12 to the hour register flips the AM/PM bit, the same way a
+      # carry into 12 does. Writing the alarm hours does not.
+      value ^= 0x80 if !alarm && (value & 0x1f) == 0x12
       # Halt the clock when writing hours, so that it doesn't
       # advance mid-update.
       @stopped = true unless alarm
+      store(:hours, value, alarm: alarm)
     end
 
     private
 
-    def resume
-      @stopped = false
-      @accumulator = 0
+    def store(field, value, alarm:)
+      target = alarm ? @alarm : @clock
+      return if target[field] == value
+
+      target[field] = value
+      @alarm_pending = true if alarm?
     end
 
-    def advance
-      @clock[:tenths] += 1
-      return if @clock[:tenths] < 10
+    def pulse!
+      @accumulator -= @cycles_per_pulse
+      return if @stopped
+
+      # A three-bit ring counter with six states, compared against the
+      # divider on each pin pulse rather than on its way past it.
+      if @pulses == @match
+        @pulses = 0
+        advance
+      else
+        @pulses += 1
+        @pulses = 0 if @pulses > 5
+      end
+    end
 
-      @clock[:tenths] = 0
-      @clock[:seconds] += 1
-      return if @clock[:seconds] < 60
+    def advance
+      tenths = (@clock[:tenths] + 1) & 0x0f
+      @clock[:tenths] = tenths == 10 ? 0 : tenths
+      carry_seconds if tenths == 10
+      @alarm_pending = true if alarm?
+    end
 
-      @clock[:seconds] = 0
-      @clock[:minutes] += 1
-      return if @clock[:minutes] < 60
+    def carry_seconds
+      return unless advance_pair(:seconds)
+      return unless advance_pair(:minutes)
 
-      @clock[:minutes] = 0
-      advance_hour
+      advance_hours
     end
 
-    def advance_hour
-      @clock[:hours] += 1
-      @clock[:pm] = !@clock[:pm] if @clock[:hours] == 12
-      @clock[:hours] = 1 if @clock[:hours] > 12
+    # Seconds and minutes hold a four-bit low digit that carries at ten into
+    # a three-bit high digit that carries out at six. Both are plain binary
+    # counters, so out-of-range BCD counts up from where it was written.
+    def advance_pair(field)
+      low = ((@clock[field] & 0x0f) + 1) & 0x0f
+      high = (@clock[field] >> 4) & 0x07
+      carry = false
+
+      if low == 10
+        low = 0
+        high = (high + 1) & 0x07
+        if high == 6
+          high = 0
+          carry = true
+        end
+      end
+
+      @clock[field] = (high << 4) | low
+      carry
     end
 
-    def alarm?
-      %i[tenths seconds minutes hours pm].all? do |field|
-        @clock[field] == @alarm[field]
+    # The hour runs 9 -> 10 and 12 -> 1 by swapping its two digits, and the
+    # AM/PM bit flips as it passes through 12.
+    def advance_hours
+      pm = @clock[:hours] & 0x80
+      high = (@clock[:hours] >> 4) & 0x01
+      low = @clock[:hours] & 0x0f
+
+      if (high == 1 && low == 2) || (high.zero? && low == 9)
+        low = high
+        high ^= 1
+      else
+        low = (low + 1) & 0x0f
+        pm ^= 0x80 if high == 1 && low == 2
       end
+
+      @clock[:hours] = pm | (high << 4) | low
     end
+
+    def alarm? = @clock == @alarm
   end
 end

data/lib/badline/version.rb

@@ -1,5 +1,5 @@
 # frozen_string_literal: true
 
 module Badline
-  VERSION = "0.1.0"
+  VERSION = "0.2.0"
 end

data/lib/badline/vic/bank.rb

@@ -18,7 +18,7 @@ module Badline
       end
 
       def peek(offset)
-        return ultimax_peek(offset) if @address_bus.ultimax
+        return ultimax_peek(offset) if @address_bus.phi1_ultimax
 
         bits = bank_switch_register
         if bits.allbits?(0b01) && (offset & 0xf000) == 0x1000
@@ -28,14 +28,26 @@ module Badline
         end
       end
 
+      # A fetch in the second half of the cycle, the c-access, sees the
+      # memory configuration the CPU does in that half. No cartridge drives
+      # Ultimax mode in the first half alone, so otherwise it reads as #peek.
+      def peek_phi2(offset)
+        @address_bus.ultimax ? ultimax_peek(offset) : peek(offset)
+      end
+
       def peek_color(offset)
-        address_bus.color_ram.peek(0xd800 + offset) & 0x0f
+        address_bus.color_ram.nibble(0xd800 + offset)
       end
 
       def poke(_addr, _value)
         raise ReadOnlyMemoryError
       end
 
+      # True if the VIC reads the character ROM at this offset.
+      def character_rom?(offset)
+        !@address_bus.phi1_ultimax && bank_switch_register.allbits?(0b01) && (offset & 0xf000) == 0x1000
+      end
+
       def start
         BANK_STARTS[bank_switch_register]
       end
@@ -56,10 +68,6 @@ module Badline
       def bank_switch_register
         @address_bus.cia2.port_a_lines & 0b11
       end
-
-      def character_rom?
-        bank_switch_register.allbits?(0b01)
-      end
     end
   end
 end

data/lib/badline/vic/border_mask.rb

@@ -0,0 +1,76 @@
+# frozen_string_literal: true
+
+module Badline
+  class VIC < Cycleable
+    # Border coverage per 8-pixel group, tracked as the sequencer outputs
+    # a line.
+    #
+    # The border is repainted over composited sprites from a snapshot of
+    # the finished line, which keeps mid-line border color splits intact.
+    class BorderMask
+      FULL  = 0
+      NONE  = 1
+      MIXED = 2
+
+      # The group table and per-pixel mask are exposed so the sequencer's
+      # pixel loops can write them without a method call per column.
+      attr_reader :groups, :mask
+
+      def initialize(width)
+        @width = width
+        @groups = Array.new(width / 8, FULL)
+        @mask = Array.new(width, true)
+        @snapshot = Array.new(width, 0)
+      end
+
+      def reset
+        @groups.fill(FULL)
+      end
+
+      def at?(pixel_x)
+        case @groups[pixel_x >> 3]
+        when FULL then true
+        when MIXED then @mask[pixel_x]
+        else false
+        end
+      end
+
+      def snapshot(colors)
+        @snapshot[0, @width] = colors
+      end
+
+      def restore(colors)
+        group = 0
+        while group < @groups.length
+          case @groups[group]
+          when FULL then group = restore_full(colors, group)
+          when MIXED then restore_mixed(colors, group * 8)
+          end
+          group += 1
+        end
+      end
+
+      private
+
+      # Copies a run of full-border groups in one splice and returns its
+      # last group.
+      def restore_full(colors, first)
+        last = first
+        last += 1 while @groups[last + 1] == FULL
+        x_pos = first * 8
+        length = (last - first + 1) * 8
+        colors[x_pos, length] = @snapshot[x_pos, length]
+        last
+      end
+
+      def restore_mixed(colors, x_pos)
+        i = 0
+        while i < 8
+          x = x_pos + i
+          colors[x] = @snapshot[x] if @mask[x]
+          i += 1
+        end
+      end
+    end
+  end
+end

data/lib/badline/vic/collisions.rb

@@ -0,0 +1,104 @@
+# frozen_string_literal: true
+
+module Badline
+  class VIC < Cycleable
+    # = Sprite collisions
+    #
+    # The $D01E/$D01F latches and the per-pixel sprite coverage that feeds
+    # them. Collisions latch as the beam passes each covered pixel, so a
+    # read mid-line sees the pixels drawn before the reading cycle and none
+    # of the ones after it.
+    class Collisions
+      # $D019 latch bits raised by the collision registers.
+      SPRITE_COLLISION_IRQ = 0x04 # IMMC, mirrors $D01E
+      DATA_COLLISION_IRQ   = 0x02 # IMBC, mirrors $D01F
+
+      # A read holds the register's reset asserted past the cycle that
+      # issued it, so the pixels drawn under it never reach the register.
+      # The read still reports only the pixels drawn before its own cycle,
+      # which is why the two numbers do not cancel out.
+      CLEAR_OVERRUN = 12
+
+      # The pixel the last fold reached, so the sprites know whether a read
+      # has anything left to latch.
+      attr_reader :folded
+
+      # One bitmask per pixel of the line, written straight by the sprite
+      # merge and read back here and by the composite.
+      attr_reader :hits
+
+      def initialize(registers, width)
+        @registers = registers
+        @width = width
+        @hits = Array.new(width, 0)
+        @folded = 0
+        @cleared_sprite = 0
+        @cleared_data = 0
+      end
+
+      def start_line
+        @folded = 0
+        @cleared_sprite = carry(@cleared_sprite)
+        @cleared_data = carry(@cleared_data)
+      end
+
+      # Latch every covered pixel between the last fold and the beam. The
+      # sprites' touched span bounds the scan; the coverage is zero outside
+      # it either way.
+      def fold(mask, upto, low, high)
+        from = [@folded, low].max
+        @folded = upto
+        scan(mask, from, [upto, high].min)
+      end
+
+      # A read resets its register for the pixels that follow the reading
+      # cycle as well as for everything before it.
+      def clear(reg, beam_x)
+        if reg == 0x1e
+          @cleared_sprite = beam_x + CLEAR_OVERRUN
+        else
+          @cleared_data = beam_x + CLEAR_OVERRUN
+        end
+      end
+
+      private
+
+      # Two or more sprites on a pixel collide with each other; any sprite
+      # over a foreground pixel collides with the graphics. Pixels still
+      # under a read's reset are dropped rather than latched.
+      def scan(mask, from, upto)
+        sprite_clash = 0
+        data_clash = 0
+        pos = from
+        while pos < upto
+          bits = @hits[pos]
+          unless bits.zero?
+            sprite_clash |= bits if pos >= @cleared_sprite && bits.anybits?(bits - 1)
+            data_clash |= bits if pos >= @cleared_data && mask[pos]
+          end
+          pos += 1
+        end
+        latch(sprite_clash, data_clash)
+      end
+
+      def latch(sprite_clash, data_clash)
+        latch_one(0x1e, sprite_clash, SPRITE_COLLISION_IRQ)
+        latch_one(0x1f, data_clash, DATA_COLLISION_IRQ)
+      end
+
+      # The IRQ is raised on the edge out of an empty register, so a
+      # collision folded on top of an unread one raises nothing.
+      def latch_one(reg, clash, irq)
+        return if clash.zero?
+        return unless @registers.collide!(reg, clash)
+
+        @registers.latch_irq!(irq)
+      end
+
+      # A reset still asserted at the line wrap carries into the new line.
+      def carry(cleared)
+        cleared > @width ? cleared - @width : 0
+      end
+    end
+  end
+end

data/lib/badline/vic/color_patches.rb

@@ -0,0 +1,33 @@
+# frozen_string_literal: true
+
+module Badline
+  class VIC < Cycleable
+    # A mid-line color register write becomes visible one pixel into the
+    # column emitted the cycle after the write. That emit paints the whole
+    # column with the new color, so the boundary pixel is patched back to
+    # the old one before the line is finished.
+    class ColorPatches
+      def initialize(sequencer)
+        @sequencer = sequencer
+        @patches = []
+      end
+
+      def clear = @patches.clear
+
+      def log(reg, old, value, boundary_x)
+        @patches << [boundary_x, reg, old & 0x0f, value & 0x0f]
+      end
+
+      def apply(colors, fg_mask)
+        @patches.each do |(x, reg, old, value)|
+          border = @sequencer.border_at?(x)
+          if reg == 0x20
+            colors[x] = old if border
+          elsif !border && !fg_mask[x] && colors[x] == value
+            colors[x] = old
+          end
+        end
+      end
+    end
+  end
+end

data/lib/badline/vic/display_state.rb

@@ -2,76 +2,139 @@
 
 module Badline
   class VIC < Cycleable
+    # = VIC-II display state
+    #
+    # The bad line condition, the video counters it drives, and the DMA it
+    # starts. A condition that arrives mid-line opens the row late, which is
+    # what makes the screen scroll sideways or lose a column of cells.
     class DisplayState
       FIRST_LINE = 0x30 # 48: bad lines and the DEN-at-$30 latch begin here
       LAST_LINE  = 0xf7 # 247
       COLUMNS_PER_ROW = 40
 
-      attr_reader :vc_base, :rc
+      # The last column of a rasterline already compares against the line
+      # about to start, the same wrap the raster IRQ latch uses.
+      WRAP_COLUMN = 62
+
+      # AEC follows BA three cycles later; the c-accesses before it read
+      # the bus the CPU still drives.
+      BA_DELAY = 3
+
+      # Columns run two ahead of Bauer's cycle numbers: column 10 is his
+      # cycle 12. BA falls on a match in columns 10-52, the c-accesses run
+      # in 13-52 and the g-accesses in 14-53. VC and VMLI reload in column
+      # 12 and the row counter steps in column 56.
+      DMA_FIRST = 10
+      DMA_LAST = 52
+      FETCH_FIRST = 13
+      GRAPHICS_FIRST = 14
+      GRAPHICS_LAST = 53
+      LOAD_COLUMN = 12
+      RC_COLUMN = 56
+
+      GRAPHICS_COLUMNS = Array.new(63) { |column| column.between?(GRAPHICS_FIRST, GRAPHICS_LAST) }.freeze
+
+      attr_reader :vc_base, :vc, :vmli, :rc
 
       def initialize(registers)
         @registers = registers
         @vc_base = 0
+        @vc = 0
+        @vmli = 0
         @rc = 0
         @display = false
         @bad_lines_enabled = false
-        @bad_line = false
+        @matched = false
+        @ba = nil
+        new_line(0)
       end
 
       def display? = @display
       def idle? = !@display
-      def bad_line? = @bad_line
+      def bad_line? = !@ba.nil?
+
+      # The bad line condition as the last column compared it.
+      def bad_line_condition? = @matched
+
+      # True once AEC has followed BA down and the VIC owns the bus.
+      def bus_taken?(column) = @ba ? column >= @ba + BA_DELAY : false
+
+      def fetching?(column)
+        @matched && column >= FETCH_FIRST && column <= DMA_LAST
+      end
 
       def new_frame
         @vc_base = 0
         @bad_lines_enabled = false
       end
 
-      def new_line
-        @bad_line = false
+      def new_line(line)
+        @ba = nil
+        @line_bits = line & 0b111
+        @den_line = line == FIRST_LINE
+        @in_window = line.between?(FIRST_LINE, LAST_LINE)
       end
 
       def cycle(rasterline, column)
-        @bad_lines_enabled = true if rasterline == FIRST_LINE && @registers.display_enabled?
+        match = column == WRAP_COLUMN ? wrap_match(rasterline + 1) : line_match
+        @matched = match
+        if match
+          @display = true
+          @ba = column if @ba.nil? && column >= DMA_FIRST && column <= DMA_LAST
+        end
+        load_counters(match) if column == LOAD_COLUMN
+        check_row_counter(match) if column == RC_COLUMN
+      end
+
+      # A g-access in display state consumes one buffer cell and one video
+      # matrix address. A row that opens mid-line makes fewer of them, and
+      # the shortfall carries into VCBASE.
+      def graphics_column?(column) = GRAPHICS_COLUMNS[column]
+
+      def graphics_access(column)
+        return unless graphics_column?(column)
 
-        load_vc(rasterline) if column == 14
-        trigger_bad_line(rasterline) if column.between?(12, 54)
-        check_row_counter if column == 58
+        @vc = (@vc + 1) & 0x3ff
+        @vmli += 1
       end
 
       private
 
-      def load_vc(rasterline)
-        return unless bad_line_condition?(rasterline)
-
-        @bad_line = true
-        @display = true
-        @rc = 0
+      def line_match
+        latch_den if @den_line
+        @bad_lines_enabled && @in_window && @line_bits == @registers.yscroll
       end
 
-      def trigger_bad_line(rasterline)
-        return if @bad_line
-        return unless bad_line_condition?(rasterline)
+      # The wrap column compares against the line about to start. The DEN
+      # latch is level-sensitive across the counter's increment, so this one
+      # column sees both the line ending and the line starting.
+      def wrap_match(line)
+        latch_den if @den_line || line == FIRST_LINE
+        return false unless line.between?(FIRST_LINE, LAST_LINE)
 
-        @bad_line = true
-        @display = true
+        @bad_lines_enabled && (line & 0b111) == @registers.yscroll
       end
 
-      def bad_line_condition?(rasterline)
-        @bad_lines_enabled &&
-          rasterline.between?(FIRST_LINE, LAST_LINE) &&
-          (rasterline & 0b111) == @registers.yscroll
+      def latch_den
+        @bad_lines_enabled = true if @registers.display_enabled?
       end
 
-      def check_row_counter
-        return unless @display
+      def load_counters(match)
+        @vc = @vc_base
+        @vmli = 0
+        @rc = 0 if match
+      end
 
+      # A condition still standing when the row counter wraps puts the logic
+      # straight back into display state, so a forced row rolls into the
+      # next one instead of leaving the line idle (Bauer 3.7.2 step 5).
+      def check_row_counter(match)
         if @rc == 7
           @display = false
-          @vc_base = (@vc_base + COLUMNS_PER_ROW) & 0x3ff
-        else
-          @rc = (@rc + 1) & 0b111
+          @vc_base = @vc
         end
+        @display ||= match
+        @rc = (@rc + 1) & 0b111 if @display
       end
     end
   end