badline 0.1.0 → 0.2.0

data/lib/badline/instruction_set/branch.rb

@@ -7,71 +7,72 @@ module Badline
       #
       # Opcodes:
       #   $90 - relative - 2+ cycles
-      def bcc(addr, _value)
-        branch(addr) unless status.carry?
+      def bcc(_addr, _value)
+        take_branch unless status.carry?
       end
 
       # Branch if carry set (C=1).
       #
       # Opcodes:
       #   $B0 - relative - 2+ cycles
-      def bcs(addr, _value)
-        branch(addr) if status.carry?
+      def bcs(_addr, _value)
+        take_branch if status.carry?
       end
 
       # Branch if equal (Z=1).
       #
       # Opcodes:
       #   $F0 - relative - 2+ cycles
-      def beq(addr, _value)
-        branch(addr) if status.zero?
+      def beq(_addr, _value)
+        take_branch if status.zero?
       end
 
       # Branch if minus (N=1).
       #
       # Opcodes:
       #   $30 - relative - 2+ cycles
-      def bmi(addr, _value)
-        branch(addr) if status.negative?
+      def bmi(_addr, _value)
+        take_branch if status.negative?
       end
 
       # Branch if not equal (Z=0).
       #
       # Opcodes:
       #   $D0 - relative - 2+ cycles
-      def bne(addr, _value)
-        branch(addr) unless status.zero?
+      def bne(_addr, _value)
+        take_branch unless status.zero?
       end
 
       # Branch if plus (N=0).
       #
       # Opcodes:
       #   $10 - relative - 2+ cycles
-      def bpl(addr, _value)
-        branch(addr) unless status.negative?
+      def bpl(_addr, _value)
+        take_branch unless status.negative?
       end
 
       # Branch if overflow clear (V=0).
       #
       # Opcodes:
       #   $50 - relative - 2+ cycles
-      def bvc(addr, _value)
-        branch(addr) unless status.overflow?
+      def bvc(_addr, _value)
+        take_branch unless status.overflow?
       end
 
       # Branch if overflow set (V=1).
       #
       # Opcodes:
       #   $70 - relative - 2+ cycles
-      def bvs(addr, _value)
-        branch(addr) if status.overflow?
+      def bvs(_addr, _value)
+        take_branch if status.overflow?
       end
 
       private
 
-      def branch(addr)
-        cycle if high_byte(addr) != high_byte(@program_counter)
-        cycle { @program_counter = addr }
+      # Marks the branch as taken. Operations#op_relative reads the flag
+      # and runs the extra cycles.
+      def take_branch
+        @branch_taken = true
       end
     end
   end

data/lib/badline/instruction_set/flag.rb

@@ -8,7 +8,7 @@ module Badline
       # Opcodes:
       #   $18 - implied - 2 cycles
       def clc(_addr, _value)
-        cycle { status.carry = false }
+        status.carry = false
       end
 
       # Clear decimal mode flag.
@@ -16,7 +16,7 @@ module Badline
       # Opcodes:
       #   $D8 - implied - 2 cycles
       def cld(_addr, _value)
-        cycle { status.decimal = false }
+        status.decimal = false
       end
 
       # Clear interrupt disable flag.
@@ -24,7 +24,7 @@ module Badline
       # Opcodes:
       #   $58 - implied - 2 cycles
       def cli(_addr, _value)
-        cycle { status.interrupt = false }
+        status.interrupt = false
       end
 
       # Clear overflow flag.
@@ -32,7 +32,7 @@ module Badline
       # Opcodes:
       #   $B8 - implied - 2 cycles
       def clv(_addr, _value)
-        cycle { status.overflow = false }
+        status.overflow = false
       end
 
       # Set carry flag.
@@ -40,7 +40,7 @@ module Badline
       # Opcodes:
       #   $38 - implied - 2 cycles
       def sec(_addr, _value)
-        cycle { status.carry = true }
+        status.carry = true
       end
 
       # Set decimal mode flag.
@@ -48,7 +48,7 @@ module Badline
       # Opcodes:
       #   $F8 - implied - 2 cycles
       def sed(_addr, _value)
-        cycle { status.decimal = true }
+        status.decimal = true
       end
 
       # Set interrupt disable flag.
@@ -56,7 +56,7 @@ module Badline
       # Opcodes:
       #   $78 - implied - 2 cycles
       def sei(_addr, _value)
-        cycle { status.interrupt = true }
+        status.interrupt = true
       end
     end
   end

data/lib/badline/instruction_set/illegal.rb

@@ -9,7 +9,7 @@ module Badline
       # Opcodes:
       #   $4B - immediate - 2 cycles
       def alr(_addr, value)
-        @a &= resolve(value)
+        @a &= value
         status.carry = @a[0]
         @a = (@a >> 1) & 0xff
         update_number_flags(@a)
@@ -25,13 +25,14 @@ module Badline
       end
 
       # Unstable instruction. AND's value with A|magic_const and X.
-      # Magic constant varies by CPU.
+      # Magic constant varies by CPU. A VIC stall between the opcode and
+      # operand fetches clears its bits 0 and 4.
       #
       # Opcodes:
       #   $8B - immediate - 2 cycles
       def ane(_addr, value)
-        magic_const = 0xee
-        @a = (a | magic_const) & x & resolve(value)
+        magic_const = stalled_before_this_cycle? ? @ane_constant & 0xee : @ane_constant
+        @a = (a | magic_const) & x & value
         update_number_flags(@a)
       end
 
@@ -40,7 +41,7 @@ module Badline
       # Opcodes:
       #   $6B - immediate - 2 cycles
       def arr(_addr, value)
-        tmp = a & resolve(value)
+        tmp = a & value
         result = (tmp >> 1) | (status.carry? ? 0x80 : 0)
         status.zero = result.zero?
         status.negative = status.carry
@@ -94,23 +95,12 @@ module Badline
         sbc(addr, inc(addr, value))
       end
 
-      # Freezes the CPU by forcing an infinite loop.
-      #
-      # Opcodes:
-      #   $02, $12, $22, $32, $42, $52, $62, $72, $92, $B2, $D2, $F2
-      def jam(_addr, _value)
-        # TODO: Handle jam
-        # It is possible to implement with loop { cycle }, but makes
-        # testing problematic.
-        10.times { cycle }
-      end
-
       # Loads A and S with value AND stack pointer.
       #
       # Opcodes:
       #   $BB - absolute_y - 4 cycles
       def las(_addr, value)
-        @a = @x = @stack_pointer = resolve(value) & stack_pointer
+        @a = @x = @stack_pointer = value & stack_pointer
         update_number_flags(@a)
       end
 
@@ -124,7 +114,7 @@ module Badline
       #   $B7 - zeropage_y - 4 cycles
       #   $BF - absolute_y - 4+ cycles
       def lax(_addr, value)
-        @a = @x = resolve(value)
+        @a = @x = value
 
         update_number_flags(@a)
       end
@@ -136,7 +126,7 @@ module Badline
       #   $AB - immediate - 2 cycles
       def lxa(_addr, value)
         magic_const = 0xee
-        @a = @x = (a | magic_const) & resolve(value)
+        @a = @x = (a | magic_const) & value
         update_number_flags(@a)
       end
 
@@ -191,8 +181,7 @@ module Badline
       # Opcodes:
       #   $CB - immediate - 2 cycles
       def sbx(_addr, value)
-        v = resolve(value)
-        result = (@x & @a) - v
+        result = (@x & @a) - value
         status.carry = result >= 0
         @x = result & 0xff
         update_number_flags(@x)
@@ -263,6 +252,9 @@ module Badline
 
       private
 
+      # A VIC stall right before the dummy read, the second-to-last cycle,
+      # drops the & (H+1) from the stored value but not from the high byte
+      # of a page-crossing target.
       def store_high_and(register, addr)
         base_high = if boundary_crossed
                       (high_byte(addr) - 1) & 0xff
@@ -271,7 +263,7 @@ module Badline
                     end
         result = register & ((base_high + 1) & 0xff)
         target = boundary_crossed ? uint16(low_byte(addr), result) : addr
-        write_byte(target, result)
+        write_byte(target, stalled_before_previous_cycle? ? register : result)
       end
     end
   end

data/lib/badline/instruction_set/inc_dec.rb

@@ -11,9 +11,8 @@ module Badline
       #   $D6 - zeropage_x - 6 cycles
       #   $DE - absolute_x - 7 cycles
       def dec(addr, value)
-        v = resolve(value)
-        result = (v - 1) & 0xff
-        write_modified(addr, v, result)
+        result = (value - 1) & 0xff
+        write_modified(addr, result)
         update_number_flags(result)
       end
 
@@ -22,7 +21,7 @@ module Badline
       # Opcodes:
       #   $CA - implied - 2 cycles
       def dex(_addr, _value)
-        cycle { @x = (@x - 1) & 0xff }
+        @x = (@x - 1) & 0xff
         update_number_flags(@x)
       end
 
@@ -31,7 +30,7 @@ module Badline
       # Opcodes:
       #   $88 - implied - 2 cycles
       def dey(_addr, _value)
-        cycle { @y = (@y - 1) & 0xff }
+        @y = (@y - 1) & 0xff
         update_number_flags(@y)
       end
 
@@ -43,9 +42,8 @@ module Badline
       #   $F6 - zeropage_x - 6 cycles
       #   $FE - absolute_x - 7 cycles
       def inc(addr, value)
-        v = resolve(value)
-        result = (v + 1) & 0xff
-        write_modified(addr, v, result)
+        result = (value + 1) & 0xff
+        write_modified(addr, result)
         update_number_flags(result)
       end
 
@@ -54,7 +52,7 @@ module Badline
       # Opcodes:
       #   $E8 - implied - 2 cycles
       def inx(_addr, _value)
-        cycle { @x = (@x + 1) & 0xff }
+        @x = (@x + 1) & 0xff
         update_number_flags(@x)
       end
 
@@ -63,7 +61,7 @@ module Badline
       # Opcodes:
       #   $C8 - implied - 2 cycles
       def iny(_addr, _value)
-        cycle { @y = (@y + 1) & 0xff }
+        @y = (@y + 1) & 0xff
         update_number_flags(@y)
       end
     end

data/lib/badline/instruction_set/stack.rb

@@ -24,7 +24,7 @@ module Badline
       # Opcodes:
       #   $68 - implied - 4 cycles
       def pla(_addr, _value)
-        cycle { @a = stack_pull }
+        @a = stack_pull
         update_number_flags(@a)
       end
 
@@ -33,71 +33,19 @@ module Badline
       # Opcodes:
       #   $28 - implied - 4 cycles
       def plp(_addr, _value)
-        cycle { status.value = stack_pull & 0b11101111 }
-      end
-
-      # Jump to absolute address.
-      #
-      # Opcodes:
-      #   $4C - absolute - 3 cycles
-      def jmp(addr, _value)
-        @program_counter = addr
-      end
-
-      # Jump to subroutine. The operand high byte is fetched only after the
-      # return address has been pushed, so a JSR executing inside the stack
-      # jumps via the value its own push just wrote.
-      #
-      # Opcodes:
-      #   $20 - absolute - 6 cycles
-      def jsr(addr, _value)
-        return_addr = (program_counter - 1) & 0xffff
-        cycle { @memory.peek(stack_address) } # internal cycle: dummy stack read
-        write_byte(stack_address, high_byte(return_addr))
-        write_byte(stack_address(-1), low_byte(return_addr))
-        @stack_pointer = (@stack_pointer - 2) & 0xff
-        @program_counter = uint16(addr, read_byte(return_addr))
-      end
-
-      # Return from interrupt.
-      #
-      # Opcodes:
-      #   $40 - implied - 6 cycles
-      def rti(_addr, _value)
-        cycle do
-          @stack_pointer = (@stack_pointer + 1) & 0xff
-          @status.value = memory[stack_address]
-          @status.break = false
-        end
-        @program_counter = uint16(stack_pull, stack_pull)
-      end
-
-      # Return from subroutine.
-      #
-      # Opcodes:
-      #   $60 - implied - 6 cycles
-      def rts(_addr, _value)
-        cycle do
-          @program_counter = (uint16(stack_pull, stack_pull) + 1) & 0xffff
-        end
+        status.value = stack_pull & 0b11101111
       end
 
       private
 
       def stack_pull
-        cycle { @stack_pointer = (@stack_pointer + 1) & 0xff }
-        read_byte(stack_address)
+        @stack_pointer = (@stack_pointer + 1) & 0xff
+        @memory.peek(stack_address)
       end
 
       def stack_push(value)
         write_byte(stack_address, value)
-        cycle { @stack_pointer = (@stack_pointer - 1) & 0xff }
-      end
-
-      def stack_push16(value)
-        write_byte(stack_address, high_byte(value))
-        write_byte(stack_address(-1), low_byte(value))
-        cycle { @stack_pointer = (@stack_pointer - 2) & 0xff }
+        @stack_pointer = (@stack_pointer - 1) & 0xff
       end
     end
   end

data/lib/badline/instruction_set/transfer.rb

@@ -16,7 +16,7 @@ module Badline
       #   $B9 - absolute_y - 4+ cycles
       #   $BD - absolute_x - 4+ cycles
       def lda(_addr, value)
-        @a = resolve(value)
+        @a = value
         update_number_flags(@a)
       end
 
@@ -29,7 +29,7 @@ module Badline
       #   $B6 - zeropage_y - 4 cycles
       #   $BE - absolute_y - 4+ cycles
       def ldx(_addr, value)
-        @x = resolve(value)
+        @x = value
         update_number_flags(@x)
       end
 
@@ -42,7 +42,7 @@ module Badline
       #   $B4 - zeropage_x - 4 cycles
       #   $BC - absolute_x - 4+ cycles
       def ldy(_addr, value)
-        @y = resolve(value)
+        @y = value
         update_number_flags(@y)
       end
 
@@ -85,7 +85,7 @@ module Badline
       # Opcodes:
       #   $AA - implied - 2 cycles
       def tax(_addr, _value)
-        cycle { @x = a }
+        @x = a
         update_number_flags(@x)
       end
 
@@ -94,7 +94,7 @@ module Badline
       # Opcodes:
       #   $A8 - implied - 2 cycles
       def tay(_addr, _value)
-        cycle { @y = a }
+        @y = a
         update_number_flags(@y)
       end
 
@@ -103,7 +103,7 @@ module Badline
       # Opcodes:
       #   $BA - implied - 2 cycles
       def tsx(_addr, _value)
-        cycle { @x = stack_pointer }
+        @x = stack_pointer
         update_number_flags(@x)
       end
 
@@ -112,7 +112,7 @@ module Badline
       # Opcodes:
       #   $8A - implied - 2 cycles
       def txa(_addr, _operand)
-        cycle { @a = x }
+        @a = x
         update_number_flags(@a)
       end
 
@@ -121,7 +121,7 @@ module Badline
       # Opcodes:
       #   $9A - implied - 2 cycles
       def txs(_addr, _operand)
-        cycle { @stack_pointer = x }
+        @stack_pointer = x
       end
 
       # Transfer Y register to accumulator.
@@ -129,7 +129,7 @@ module Badline
       # Opcodes:
       #   $98 - implied - 2 cycles
       def tya(_addr, _operand)
-        cycle { @a = y }
+        @a = y
         update_number_flags(@a)
       end
     end

data/lib/badline/instruction_set.rb

@@ -22,18 +22,8 @@ module Badline
     include InstructionSet::Stack
     include InstructionSet::Transfer
 
-    # Forces a software interrupt (break).
-    # Pushes PC+2 and status to stack, sets break flag, and jumps via IRQ vector.
-    #
-    # Opcodes:
-    #   $00 - implied - 7 cycles
-    def brk(_addr, _value)
-      status.break = true
-      handle_interrupt(0xfffe, brk: true, pre_cycles: 1)
-      status.break = false
-    end
-
-    # No operation. Does nothing but consume a clock cycle.
+    # No operation. The illegal forms with an operand still read it, in
+    # the steps before this is called.
     #
     # Opcodes:
     #   $EA                          - implied    - 2 cycles
@@ -42,35 +32,23 @@ module Badline
     #   $0C                          - absolute   - 4 cycles  (illegal)
     #   $1C, $3C, $5C, $7C, $DC, $FC - absolute_x - 4+ cycles (illegal)
     #   $1A, $3A, $5A, $7A, $DA, $FA - implied    - 2 cycles  (illegal)
-    def nop(_addr, _value)
-      cycle
-    end
+    def nop(_addr, _value); end
 
     private
 
-    def resolve(value)
-      if value == :lazy
-        realize_value(@instruction, @operand, @address)
-      elsif value.is_a?(Proc)
-        value.call
-      else
-        value
-      end
-    end
-
     def update_number_flags(value)
       status.zero = value.zero?
-      status.negative = value.anybits?(0x80)
+      status.negative = value & 0x80 != 0
       value
     end
 
-    # Read-modify-write instructions put the unmodified value back on the bus before writing the result.
-    def write_modified(addr, original, result)
+    # Stores a read-modify-write result. For memory, the write happens in
+    # the steps that follow (see Operations#op_rmw_read).
+    def write_modified(addr, result)
       if addr == :accumulator
-        cycle { @a = result }
+        @a = result
       else
-        write_byte(addr, original)
-        write_byte(addr, result)
+        @rmw_result = result
       end
     end
   end

data/lib/badline/interrupts.rb

@@ -0,0 +1,104 @@
+# frozen_string_literal: true
+
+module Badline
+  module Interrupts
+    BREAK_MASK = 0x10
+
+    private
+
+    # Samples the IRQ line and the NMI latch once per cycle. An instruction
+    # boundary commits the sample taken on its second-to-last cycle.
+    def poll
+      if @skip_poll
+        @skip_poll = false
+        return
+      end
+      @irq_pending = @irq_sample
+      @nmi_pending = @nmi_sample
+      @irq_sample = @irq && !@status.interrupt?
+      @nmi_sample = @nmi
+    end
+
+    # A cycle the VIC stalls through BA keeps sampling the lines, OR-ed with
+    # the sample it already holds, but the boundary pipeline doesn't advance
+    # and a skipped poll stays owed to the next real cycle.
+    def sample_while_stalled
+      @irq_sample ||= @irq && !interrupt_disabled_after_stall?
+      @nmi_sample = true if @nmi
+    end
+
+    # A stalled CLI or SEI execute cycle masks with the I it is about to
+    # set. Every other step masks with the current I, PLP included: its
+    # pulled I only arrives with the stalled stack read.
+    def interrupt_disabled_after_stall?
+      return @status.interrupt? unless @plan.equal?(CPU::IMPLIED_PLAN)
+
+      case @operation
+      when :cli then false
+      when :sei then true
+      else @status.interrupt?
+      end
+    end
+
+    # Runs in the opcode fetch cycle in place of the fetch, with no bus
+    # access, and switches to the interrupt plan.
+    def start_interrupt
+      @interrupt = @boundary_nmi ? 0xfffa : 0xfffe
+      @brk = false
+      @plan = CPU::INTERRUPT_PLAN
+      @writes = CPU::INTERRUPT_WRITES
+      @index = 1
+    end
+
+    # BRK reads the byte after its opcode and ignores it, and selects the
+    # IRQ vector.
+    def op_brk_dummy
+      @memory.peek(@program_counter)
+      @interrupt = 0xfffe
+      @brk = true
+    end
+
+    def op_int_push_pch
+      @address = @brk ? (@program_counter + 1) & 0xffff : @program_counter
+      @memory.poke(stack_address, high_byte(@address))
+      @stack_pointer = (@stack_pointer - 1) & 0xff
+    end
+
+    def op_int_push_pcl
+      @memory.poke(stack_address, low_byte(@address))
+      @stack_pointer = (@stack_pointer - 1) & 0xff
+    end
+
+    def op_int_push_status
+      value = @brk ? @status.value | BREAK_MASK : @status.value & ~BREAK_MASK
+      @memory.poke(stack_address, value)
+      @stack_pointer = (@stack_pointer - 1) & 0xff
+      @status.interrupt = true
+      # An NMI that arrives before cycle 4 of a BRK or IRQ takes it over:
+      # the sequence finishes with the NMI vector.
+      @interrupt = 0xfffa if @interrupt == 0xfffe && @nmi_pending
+      @nmi = false if @interrupt == 0xfffa
+    end
+
+    def op_int_vector_low
+      @address = @memory.peek(@interrupt)
+    end
+
+    # Clears any interrupt that is pending, so the handler's first
+    # instruction always runs before the next interrupt. This applies to
+    # BRK too.
+    def op_int_vector_high
+      high = @memory.peek((@interrupt + 1) & 0xffff)
+      @program_counter = @address | (high << 8)
+      @irq_sample = @irq_pending = false
+      @nmi_sample = @nmi_pending = false
+      @interrupt = nil
+      if @brk
+        @status.break = false
+        end_instruction
+      else
+        end_sequence
+      end
+    end
+  end
+end

data/lib/badline/joystick.rb

@@ -4,22 +4,22 @@ module Badline
   class Joystick
     DIRECTIONS = { up: 0, down: 1, left: 2, right: 3, fire: 4 }.freeze
 
+    # Kept up to date as switches move, since the CIA samples the fire line
+    # every cycle to drive the light pen input.
+    attr_reader :port_bits
+
     def initialize
-      @pressed = {}
+      @port_bits = 0xff
     end
 
     def press(direction)
-      @pressed[direction] = true if DIRECTIONS.key?(direction)
+      bit = DIRECTIONS[direction]
+      @port_bits &= ~(1 << bit) if bit
     end
 
     def release(direction)
-      @pressed.delete(direction)
-    end
-
-    def port_bits
-      bits = 0xff
-      DIRECTIONS.each { |dir, bit| bits &= ~(1 << bit) if @pressed[dir] }
-      bits
+      bit = DIRECTIONS[direction]
+      @port_bits |= 1 << bit if bit
     end
   end
 end