axi_tdl 0.2.5 → 0.2.10
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.github/workflows/gem-push.yml +21 -48
- data/.github/workflows/ruby.yml +1 -1
- data/lib/axi/AXI4/axi4_combin_wr_rd_batch.sv +0 -0
- data/lib/axi/AXI4/axi4_direct.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_A1.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_B1.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_algin_addr_step.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_verc.sv +0 -0
- data/lib/axi/AXI4/axi4_dpram_cache.rb +0 -0
- data/lib/axi/AXI4/axi4_dpram_cache.sv +0 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide.sv +0 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv +0 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv +2 -1
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv +0 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_pipe.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_pipe_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_ram_cache.rb +0 -0
- data/lib/axi/AXI4/axi4_ram_cache.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A2.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_burst_track.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_aux_bind_data.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_gen.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_gen_without_resp.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_burst_track.sv +0 -0
- data/lib/axi/AXI4/axi_stream_add_addr_len.sv +0 -0
- data/lib/axi/AXI4/axi_stream_to_axi4_wr.sv +54 -8
- data/lib/axi/AXI4/axi_stream_to_axi4_wr_verb.sv.bak +0 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +0 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +0 -0
- data/lib/axi/AXI4/full_axi4_to_axis.sv +0 -0
- data/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv +0 -0
- data/lib/axi/AXI4/id_record.sv +0 -0
- data/lib/axi/AXI4/idata_pool_axi4.sv +0 -0
- data/lib/axi/AXI4/interconnect/AXI4_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv.bak +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A1.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak +0 -0
- data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +0 -0
- data/lib/axi/AXI4/long_axis_to_axi4_wr.sv +1 -1
- data/lib/axi/AXI4/odata_pool_axi4.sv +0 -0
- data/lib/axi/AXI4/odata_pool_axi4_A1.sv +0 -0
- data/lib/axi/AXI4/odata_pool_axi4_A2.sv +0 -0
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +0 -0
- data/lib/axi/AXI4/odata_pool_axi4_A4.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_B1.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_verb.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo_A1.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo_A1.sv +12 -4
- data/lib/axi/AXI4/packet_merge/axi4_merge.sv +0 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge_rd.sv +0 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge_wr.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_OD.sv +3 -2
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_OD.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +16 -7
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +13 -9
- data/lib/axi/AXI4/packet_partition/axi4_partition_wr.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_wr_OD.sv +11 -10
- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +0 -0
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
- data/lib/axi/AXI4/packet_partition/data_inf_partition_A1.rb +298 -0
- data/lib/axi/AXI4/packet_partition/data_inf_partition_A1.sv +316 -0
- data/lib/axi/AXI4/vcs_axi4_array_comptable.sv +0 -0
- data/lib/axi/AXI4/vcs_axi4_comptable.sv +0 -0
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +0 -0
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb.bk +150 -0
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +2 -2
- data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe.sv +0 -0
- data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv +0 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert.sv +0 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv +0 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert_verb.sv +0 -0
- data/lib/axi/AXI4/width_convert/data_combin.sv +0 -0
- data/lib/axi/AXI4/width_convert/data_combin.sv.bak +0 -0
- data/lib/axi/AXI4/width_convert/data_destruct.sv +0 -0
- data/lib/axi/AXI4/width_convert/feed_check.sv +0 -0
- data/lib/axi/AXI4/width_convert/len_convert.sv.bak +0 -0
- data/lib/axi/AXI4/width_convert/odd_width_convert.sv +0 -0
- data/lib/axi/AXI4/width_convert/odd_width_convert_verb.sv +0 -0
- data/lib/axi/AXI4/width_convert/simple_data_pipe.sv +0 -0
- data/lib/axi/AXI4/width_convert/simple_data_pipe_slaver.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_combin.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_convert.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_convert_verb.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_destruct.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_destruct_A1.sv +0 -0
- data/lib/axi/AXI_BFM/AXI_BFM_PKG.sv +0 -0
- data/lib/axi/AXI_BFM/Data_C_BFM_PKG.sv +0 -0
- data/lib/axi/AXI_BFM/axi4_error_chk.sv +0 -0
- data/lib/axi/AXI_BFM/axi4_illegal_bfm_pkg.sv +0 -0
- data/lib/axi/AXI_BFM/axi_lite_master.sv +0 -0
- data/lib/axi/AXI_BFM/axi_lite_tb.sv +0 -0
- data/lib/axi/AXI_BFM/axi_master.sv +0 -0
- data/lib/axi/AXI_BFM/axi_mirror.sv +0 -0
- data/lib/axi/AXI_BFM/axi_mm_tb.sv +0 -0
- data/lib/axi/AXI_BFM/axi_slaver.sv.bak +0 -0
- data/lib/axi/AXI_BFM/axistreambfm.sv +0 -0
- data/lib/axi/AXI_Lite/axi4_to_lite.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_configure.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_configure_inf2.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_configure_verb.sv.bck +0 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv +4 -5
- data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv.bak +0 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M_verb.sv +322 -0
- data/lib/axi/AXI_Lite/axi_lite_master_empty.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_slaver_empty.sv +0 -0
- data/lib/axi/AXI_Lite/axil_direct.sv +0 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv +0 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv.bak +0 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv +0 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl.sv +0 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_C1.sv +0 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verb.sv +0 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verc.sv +0 -0
- data/lib/axi/AXI_Lite/wr_lite_to_axis.sv +0 -0
- data/lib/axi/AXI_Lite/wr_lite_to_axis.sv.bak +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_cpVCS.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_auto.sv +26 -5
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_info.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_keep.sv.bak +0 -0
- data/lib/axi/AXI_stream/axi_stream_latency.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_packet_fifo_with_info.sv.bak +0 -0
- data/lib/axi/AXI_stream/axi_stream_partition.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_partition_A1.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_planer.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +0 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +26 -26
- data/lib/axi/AXI_stream/axi_streams_combin.sv +0 -0
- data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +0 -0
- data/lib/axi/AXI_stream/axi_streams_scaler.sv +0 -0
- data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_append.sv +0 -0
- data/lib/axi/AXI_stream/axis_append_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_base_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_A1.sv.bak +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_left_shift.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_right_shift.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_right_shift_verb.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_with_info.sv +0 -0
- data/lib/axi/AXI_stream/axis_direct.sv +0 -0
- data/lib/axi/AXI_stream/axis_direct_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_ex_status.sv +97 -0
- data/lib/axi/AXI_stream/axis_ex_status.sv.bk +97 -0
- data/lib/axi/AXI_stream/axis_filter.sv +0 -0
- data/lib/axi/AXI_stream/axis_full_to_data_c.sv +0 -0
- data/lib/axi/AXI_stream/axis_head_cut.sv +0 -0
- data/lib/axi/AXI_stream/axis_head_cut_verb.sv +0 -0
- data/lib/axi/AXI_stream/axis_head_cut_verc.rb +0 -0
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +6 -6
- data/lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv +0 -0
- data/lib/axi/AXI_stream/axis_insert_copy.rb +0 -0
- data/lib/axi/AXI_stream/axis_insert_copy.sv +0 -0
- data/lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv +0 -0
- data/lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv +0 -0
- data/lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_length_cut.sv +1 -1
- data/lib/axi/AXI_stream/axis_length_fill.sv +0 -0
- data/lib/axi/AXI_stream/axis_length_fill_verb.sv +195 -0
- data/lib/axi/AXI_stream/axis_length_split.sv +0 -0
- data/lib/axi/AXI_stream/axis_length_split_with_addr.sv +0 -0
- data/lib/axi/AXI_stream/axis_length_split_with_addr_A1.sv +128 -0
- data/lib/axi/AXI_stream/axis_length_split_with_user.sv +0 -0
- data/lib/axi/AXI_stream/axis_link_trigger.sv +0 -0
- data/lib/axi/AXI_stream/axis_master_empty.sv +0 -0
- data/lib/axi/AXI_stream/axis_mirror_to_master.sv +0 -0
- data/lib/axi/AXI_stream/axis_mirror_to_master_verb.sv +141 -0
- data/lib/axi/AXI_stream/axis_mirrors.sv +0 -0
- data/lib/axi/AXI_stream/axis_orthogonal.sv +0 -0
- data/lib/axi/AXI_stream/axis_padding.rb +44 -0
- data/lib/axi/AXI_stream/axis_padding.sv +65 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.rb +0 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +0 -0
- data/lib/axi/AXI_stream/axis_ram_buffer.sv +0 -0
- data/lib/axi/AXI_stream/axis_rom_contect.rb +0 -0
- data/lib/axi/AXI_stream/axis_rom_contect.sv +0 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +0 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +0 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.rb +0 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.sv +0 -0
- data/lib/axi/AXI_stream/axis_sim_slaver_model.rb +0 -0
- data/lib/axi/AXI_stream/axis_sim_verify_by_coe.sv +0 -0
- data/lib/axi/AXI_stream/axis_slaver_empty.sv +0 -0
- data/lib/axi/AXI_stream/axis_slaver_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_slaver_pipe_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_slaver_vector_empty.sv +0 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.rb +0 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +3 -3
- data/lib/axi/AXI_stream/axis_to_axi4_or_lite.rb +0 -0
- data/lib/axi/AXI_stream/axis_to_axi4_or_lite.sv +0 -0
- data/lib/axi/AXI_stream/axis_to_data_inf.sv +0 -0
- data/lib/axi/AXI_stream/axis_to_lite_rd.sv +0 -0
- data/lib/axi/AXI_stream/axis_to_lite_wr.sv +0 -0
- data/lib/axi/AXI_stream/axis_uncompress.sv +0 -0
- data/lib/axi/AXI_stream/axis_uncompress_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_uncompress_verb.rb +0 -0
- data/lib/axi/AXI_stream/axis_uncompress_verb.sv +0 -0
- data/lib/axi/AXI_stream/axis_valve.sv +0 -0
- data/lib/axi/AXI_stream/axis_valve_with_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_vector_master_empty.rb +0 -0
- data/lib/axi/AXI_stream/axis_vector_master_empty.sv +0 -0
- data/lib/axi/AXI_stream/axis_vector_slaver_empty.rb +0 -0
- data/lib/axi/AXI_stream/axis_vector_slaver_empty.sv +0 -0
- data/lib/axi/AXI_stream/check_stream_crc.sv +0 -0
- data/lib/axi/AXI_stream/data_c_to_axis_full.sv +0 -0
- data/lib/axi/AXI_stream/data_to_axis_inf.sv +0 -0
- data/lib/axi/AXI_stream/data_to_axis_inf_A1.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_combin.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_convert.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_destruct.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv +0 -0
- data/lib/axi/AXI_stream/gen_big_field_table.sv +0 -0
- data/lib/axi/AXI_stream/gen_common_frame_table.sv +0 -0
- data/lib/axi/AXI_stream/gen_common_frame_table_bind_tuser.sv +0 -0
- data/lib/axi/AXI_stream/gen_origin_axis.sv +0 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A1.sv +0 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A2.sv +0 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A3.sv +0 -0
- data/lib/axi/AXI_stream/gen_simple_axis.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv +8 -5
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo_verb.sv +9 -7
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1F.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_verb.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_with_info.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +5 -4
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo_A1.sv +221 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_wide_fifo.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep.sv +0 -0
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- data/lib/tdl/Logic/clock_rst_verb_auto.rb +0 -0
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- data/lib/tdl/SDL/axi4/axi4_data_combin_aflag_pipe_sdl.rb +0 -0
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- data/lib/tdl/SDL/axi4/axi4_partition_wr_OD_sdl.rb +0 -0
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- data/lib/tdl/SDL/axi4/axi4_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_pipe_verb_sdl.rb +0 -0
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- data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_burst_track_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A2_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_packet_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_pipe_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_aux_bind_data_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_batch_gen_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_without_resp_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_burst_track_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_mix_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_packet_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_pipe_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi_stream_add_addr_len_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi_stream_to_axi4_wr_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/data_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/data_destruct_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/feed_check_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/full_axi4_to_axis_partition_wr_rd_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/full_axi4_to_axis_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/id_record_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/idata_pool_axi4_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_A2_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odd_width_convert_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odd_width_convert_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/simple_data_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/simple_data_pipe_slaver_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable.rb +0 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_comptable.rb +0 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_comptable_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_convert_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_convert_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_destruct_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_destruct_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_35bit_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_36_71bit_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_with_keep_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_96_143bit_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_B1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_mirror_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A2_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_bind_tuser_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_noaddr_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_with_addr_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_auto_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_cache_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_fifo_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1E_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_with_info_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_partition_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_partition_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_wide_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_streams_combin_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_streams_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_streams_scaler_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_streams_scaler_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_append_A1_sdl.rb +0 -0
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- data/lib/tdl/SDL/axistream/axis_base_pipe_sdl.rb +0 -0
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- data/lib/tdl/SDL/axistream/axis_connect_pipe_right_shift_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_sdl.rb +0 -0
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- data/lib/tdl/SDL/axistream/axis_ex_status_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_filter_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_full_to_data_c_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_head_cut_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_inct_s2m_with_flag_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_intc_M2S_with_addr_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_intc_S2M_with_addr_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_interconnect_S2M_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_cut_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_fill_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_split_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_split_with_addr_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_split_writh_user_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_link_trigger_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_master_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_mirror_to_master_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_mirrors_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_orthogonal_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_ram_buffer_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_slaver_empty_sdl.rb +0 -0
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- data/lib/tdl/SDL/axistream/axis_slaver_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_slaver_vector_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_to_data_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_to_lite_rd_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_to_lite_wr_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_uncompress_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_uncompress_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_valve_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_valve_with_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_combin_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_convert_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_destruct_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_destruct_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/check_stream_crc_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/data_c_to_axis_full_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/data_to_axis_inf_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/data_to_axis_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_big_field_table_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_common_frame_table_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_origin_axis_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_origin_axis_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_simple_axis_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_A1_sdl.rb +0 -0
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- data/lib/tdl/SDL/axistream/parse_big_field_table_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/stream_crc_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/vcs_axis_comptable.rb +0 -0
- data/lib/tdl/SDL/axistream/vcs_axis_comptable_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_bind_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_cache_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_direct_mirror_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_direct_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_intc_M2S_force_robin_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_bind_data_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_right_shift_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_latency_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_scaler_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_scaler_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_tmp_cache_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_condition_mirror_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_condition_valve_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_connect_pipe_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_connect_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_A2B_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_B2A_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_M2S_with_addr_and_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_M2S_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_with_lazy_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_pipe_condition_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_cross_clk_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_force_addr_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_noaddr_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_with_id_noaddr_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_planer_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_planer_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_ticktock_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_intc_M2S_force_robin_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_mirrors_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_A2_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_combin_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_scaler_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_uncompress_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_valve_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/datainf_c_master_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/datainf_c_slaver_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/datainf_master_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/datainf_slaver_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/latency_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/next_prio_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/part_data_pair_map_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/trigger_ready_ctrl_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/common_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/common_stack_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/independent_clock_fifo_a1_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/independent_clock_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/independent_stack_sdl.rb +0 -0
- data/lib/tdl/SDL/path_lib.rb +0 -0
- data/lib/tdl/SDL/vcs_axi4_comptable.rb +0 -0
- data/lib/tdl/SDL/vcs_axis_comptable.rb +0 -0
- data/lib/tdl/SDL/vcs_data_c_comptable.rb +0 -0
- data/lib/tdl/VideoInf/simple_video_gen.rb +0 -0
- data/lib/tdl/VideoInf/video_from_axi4.rb +0 -0
- data/lib/tdl/VideoInf/video_lib.rb +0 -0
- data/lib/tdl/VideoInf/video_stream_2_axi_stream.rb +0 -0
- data/lib/tdl/VideoInf/video_to_axi4.rb +0 -0
- data/lib/tdl/auto_script/auto_gen_tdl.rb +0 -0
- data/lib/tdl/auto_script/autogensdl.rb +0 -0
- data/lib/tdl/auto_script/autogentdl_a2.rb +0 -0
- data/lib/tdl/auto_script/import_hdl.rb +0 -0
- data/lib/tdl/auto_script/import_sdl.rb +0 -0
- data/lib/tdl/auto_script/test_autogensdl.rb +0 -0
- data/lib/tdl/auto_script/tmp.rb +0 -0
- data/lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_direct.rb +0 -0
- data/lib/tdl/axi4/axi4_direct_A1_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_direct_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_direct_verb_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +24 -10
- data/lib/tdl/axi4/axi4_lib.rb +0 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_A1_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_verb_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_packet_fifo_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_pipe_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_pipe_verb_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_rd_auxiliary_gen_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_wr_auxiliary_gen_without_resp_auto.rb +0 -0
- data/lib/tdl/axi4/axis_to_axi4_wr_auto.rb +0 -0
- data/lib/tdl/axi4/bak/__axi4_wr_auxiliary_gen_without_resp.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_combin_wr_rd_batch_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_data_convert.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_direct_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_direct_verb_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_interconnect.rb.bak +0 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_A1_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_verb_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_packet_fifo.rb.bak +0 -0
- data/lib/tdl/axi4/bak/axi4_packet_fifo_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_partition_od.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_pipe_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_wr_auxiliary_gen_without_resp_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axis_to_axi4_wr_auto.rb +0 -0
- data/lib/tdl/axi4/bak/ddr3.rb +0 -0
- data/lib/tdl/axi4/bak/idata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi4/bak/odata_pool_axi4_A1_auto.rb +0 -0
- data/lib/tdl/axi4/bak/odata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi4/idata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi4/odata_pool_axi4_A1_auto.rb +0 -0
- data/lib/tdl/axi4/odata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi4/wide_axis_to_axi4_wr.rb +0 -0
- data/lib/tdl/axi4/wide_axis_to_axi4_wr_auto.rb +0 -0
- data/lib/tdl/axi_lite/axi_lite_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_lite/axi_lite_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_lite/bak/axi_lite_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_lite/bak/axi_lite_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_lite/bak/jtag_to_axilite_wrapper_auto.rb +0 -0
- data/lib/tdl/axi_lite/jtag_to_axilite_wrapper_auto.rb +0 -0
- data/lib/tdl/axi_lite/lite_cmd.rb +0 -0
- data/lib/tdl/axi_lite/prj_lib.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_35bit_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_72_95bit_with_keep_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_B1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_mirror_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_verb_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_A1.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_bind_tuser_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_auto_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_with_keep.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_lib.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_long_cache_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_long_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_long_fifo_verb_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_packet_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_packet_fifo_with_info_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_partition_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_partition_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_wide_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_streams_combin_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_streams_combin_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_streams_scaler_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_streams_scaler_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_append_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_append_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_combin_with_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_connect_pipe_A1.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_connect_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_connect_pipe_with_info_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_direct_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_filter_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_full_to_data_c_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_head_cut_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_length_fill_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_length_split_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_length_split_with_addr_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_length_split_writh_user_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_link_trigger_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_mirror_to_master_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_mirrors_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_padding.rb +44 -0
- data/lib/tdl/axi_stream/axis_pkt_fifo_filter_keep_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_pkt_fifo_filter_keep_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_ram_buffer_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_slaver_pipe_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_slaver_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_to_axi4_or_lite_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_to_data_inf_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_to_lite_rd_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_to_lite_wr_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_uncompress_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_valve_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_valve_with_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_combin_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_combin_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_convert_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_destruct_A1.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_destruct_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/__axi_stream_interconnect_S2M.rb +0 -0
- data/lib/tdl/axi_stream/bak/_axis_mirrors.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi4_to_native_for_ddr_ip_verb_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_S2M.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_35bit_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_72_95bit_with_keep_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_B1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_mirror_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_verb_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_interconnect_S2M_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_interconnect_S2M_with_keep.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_long_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_packet_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_packet_fifo_with_info_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_partition_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_partition_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_streams_combin_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_streams_scaler.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_streams_scaler_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_append_A1.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_append_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_append_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_combin_with_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe.rb.bak +0 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe_A1.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe_with_info_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_direct_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_filter_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_length_fill_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_length_split_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_length_split_with_addr_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_mirrors_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_pkt_fifo_filter_keep_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_ram_buffer_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_slaver_pipe_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_slaver_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_to_axi4_wr_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_to_data_inf_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_uncompress_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_valve_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_valve_with_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_width_combin_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_width_convert_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_width_destruct_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_wrapper_oled_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/check_stream_crc_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/data_to_axis_inf_A1.rb +0 -0
- data/lib/tdl/axi_stream/bak/data_to_axis_inf_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/data_to_axis_inf_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/datainf_c_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/datainf_c_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/datainf_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/datainf_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/dynamic_port_cfg_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/dynnamic_addr_cfg_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/gen_big_field_table_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/gen_origin_axis_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/gen_simple_axis_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/idata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/parse_big_field_table_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/parse_big_field_table_A2_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/parse_big_field_table_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/part_data_pair_map_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/simple_video_gen_A2.rb +0 -0
- data/lib/tdl/axi_stream/bak/simple_video_gen_A2_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/stream_crc_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/udp_server_bfm_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/udp_server_ctrl_bfm_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/video_to_VDMA.rb +0 -0
- data/lib/tdl/axi_stream/bak/video_to_VDMA_auto.rb +0 -0
- data/lib/tdl/axi_stream/check_stream_crc_auto.rb +0 -0
- data/lib/tdl/axi_stream/data_c_to_axis_full_auto.rb +0 -0
- data/lib/tdl/axi_stream/data_to_axis_inf_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/data_to_axis_inf_auto.rb +0 -0
- data/lib/tdl/axi_stream/gen_big_field_table_auto.rb +0 -0
- data/lib/tdl/axi_stream/gen_origin_axis_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/gen_origin_axis_auto.rb +0 -0
- data/lib/tdl/axi_stream/gen_simple_axis_auto.rb +0 -0
- data/lib/tdl/axi_stream/parse_big_field_table_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/parse_big_field_table_A2_auto.rb +0 -0
- data/lib/tdl/axi_stream/parse_big_field_table_auto.rb +0 -0
- data/lib/tdl/axi_stream/stream_crc_auto.rb +0 -0
- data/lib/tdl/basefunc.rb +0 -0
- data/lib/tdl/bfm/axi4_illegal_bfm.rb +0 -0
- data/lib/tdl/bfm/axi_stream/axi_stream_bfm.rb +0 -0
- data/lib/tdl/bfm/axi_stream/axis_bfm_exp.yml +0 -0
- data/lib/tdl/bfm/axi_stream/axis_bfm_module_build.rb +0 -0
- data/lib/tdl/bfm/axi_stream/axis_bfm_parse.rb +0 -0
- data/lib/tdl/bfm/axi_stream/axis_slice_to_logic.rb +0 -0
- data/lib/tdl/bfm/bfm_lib.rb +0 -0
- data/lib/tdl/bfm/logic_initial_block.rb +0 -0
- data/lib/tdl/cfg.yml +0 -0
- data/lib/tdl/class_hdl/hdl_always_comb.rb +0 -0
- data/lib/tdl/class_hdl/hdl_always_ff.rb +0 -0
- data/lib/tdl/class_hdl/hdl_assign.rb +0 -0
- data/lib/tdl/class_hdl/hdl_block_ifelse.rb +0 -0
- data/lib/tdl/class_hdl/hdl_data.rb +0 -0
- data/lib/tdl/class_hdl/hdl_ex_defarraychain.rb +0 -0
- data/lib/tdl/class_hdl/hdl_foreach.rb +0 -0
- data/lib/tdl/class_hdl/hdl_function.rb +0 -0
- data/lib/tdl/class_hdl/hdl_generate.rb +0 -0
- data/lib/tdl/class_hdl/hdl_initial.rb +0 -0
- data/lib/tdl/class_hdl/hdl_module_def.rb +16 -0
- data/lib/tdl/class_hdl/hdl_package.rb +0 -0
- data/lib/tdl/class_hdl/hdl_parameter.rb +0 -0
- data/lib/tdl/class_hdl/hdl_random.rb +0 -0
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +18 -1
- data/lib/tdl/class_hdl/hdl_struct.rb +0 -0
- data/lib/tdl/class_hdl/hdl_verify.rb +0 -0
- data/lib/tdl/data_inf/_data_mirrors.rb +0 -0
- data/lib/tdl/data_inf/bak/_data_mirrors.rb +0 -0
- data/lib/tdl/data_inf/bak/common_fifo_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_bind_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_c_direct_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_c_direct_mirror_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_c_tmp_cache_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_condition_mirror_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_condition_valve_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_connect_pipe.rb +0 -0
- data/lib/tdl/data_inf/bak/data_connect_pipe_inf_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_c_interconnect.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_c_pipe_condition_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_cross_clk.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_interconnect.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_planer.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_ticktack.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_ticktock_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_mirrors_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_mirrors_verb.sv_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_uncompress_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_valve_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/datainf_c_master_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/datainf_c_slaver_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/datainf_master_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/datainf_slaver_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/independent_clock_fifo_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/part_data_pair_map_auto.rb +0 -0
- data/lib/tdl/data_inf/common_fifo_auto.rb +0 -0
- data/lib/tdl/data_inf/data_bind_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_cache_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_direct_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_direct_mirror_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_interconnect.rb +0 -0
- data/lib/tdl/data_inf/data_c_pipe_force_vld_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_pipe_inf_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_pipe_intc_M2S_verc_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_tmp_cache_auto.rb +0 -0
- data/lib/tdl/data_inf/data_condition_mirror_auto.rb +0 -0
- data/lib/tdl/data_inf/data_condition_valve_auto.rb +0 -0
- data/lib/tdl/data_inf/data_connect_pipe_inf_auto.rb +0 -0
- data/lib/tdl/data_inf/data_inf_c_pipe_condition_auto.rb +0 -0
- data/lib/tdl/data_inf/data_mirrors_auto.rb +0 -0
- data/lib/tdl/data_inf/data_mirrors_verb.sv_auto.rb +0 -0
- data/lib/tdl/data_inf/data_uncompress_auto.rb +0 -0
- data/lib/tdl/data_inf/data_valve_auto.rb +0 -0
- data/lib/tdl/data_inf/datainf_c_master_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/datainf_c_slaver_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/datainf_master_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/datainf_slaver_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/independent_clock_fifo_auto.rb +0 -0
- data/lib/tdl/data_inf/part_data_pair_map_auto.rb +0 -0
- data/lib/tdl/data_inf/path_lib.rb +0 -0
- data/lib/tdl/elements/Reset.rb +0 -0
- data/lib/tdl/elements/axi4.rb +0 -0
- data/lib/tdl/elements/axi_lite.rb +0 -0
- data/lib/tdl/elements/axi_stream.rb +0 -0
- data/lib/tdl/elements/clock.rb +0 -0
- data/lib/tdl/elements/common_configure_reg.rb +0 -0
- data/lib/tdl/elements/data_inf.rb +0 -0
- data/lib/tdl/elements/logic.rb +0 -2
- data/lib/tdl/elements/mail_box.rb +0 -0
- data/lib/tdl/elements/originclass.rb +0 -0
- data/lib/tdl/elements/parameter.rb +0 -0
- data/lib/tdl/elements/track_inf.rb +0 -0
- data/lib/tdl/elements/videoinf.rb +0 -0
- data/lib/tdl/examples/10_random/exp_random.rb +0 -0
- data/lib/tdl/examples/10_random/exp_random.sv +0 -0
- data/lib/tdl/examples/11_logic_latency/test_logic_latency.rb +0 -0
- data/lib/tdl/examples/11_logic_latency/test_logic_latency.sv +0 -0
- data/lib/tdl/examples/11_test_unit/dve.tcl +0 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +0 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +0 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit_constraints.xdc +0 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +0 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +0 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +0 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +0 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +0 -0
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +0 -0
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +0 -0
- data/lib/tdl/examples/11_test_unit/tu0.sv +0 -0
- data/lib/tdl/examples/11_test_unit/tu1.sv +0 -0
- data/lib/tdl/examples/1_define_module/example1.rb +0 -0
- data/lib/tdl/examples/1_define_module/exmple_md.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/always_comb.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/always_ff.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/case.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/foreach.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/function.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/generate.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/module_def.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/module_head_import_package.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/module_instance_test.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/package.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/package2.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/simple_assign.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/state_case.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/struct.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/struct_function.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_axi4_M2S.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_initial_assert.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_module_port.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_module_var.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/init_module.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/port_module.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_axi4_M2S.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/vcs_string.rb +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/hdl_test.sv +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/main.rb +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_test.rb +0 -0
- data/lib/tdl/examples/4_generate/example.rb +0 -0
- data/lib/tdl/examples/4_generate/test_generate.sv +0 -0
- data/lib/tdl/examples/5_logic_combin/login_combin.rb +0 -0
- data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +0 -0
- data/lib/tdl/examples/6_module_with_interface/example.rb +0 -0
- data/lib/tdl/examples/6_module_with_interface/example_interface.sv +0 -0
- data/lib/tdl/examples/6_module_with_interface/inf_collect.rb +0 -0
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +0 -0
- data/lib/tdl/examples/7_module_with_package/body_package.rb +0 -0
- data/lib/tdl/examples/7_module_with_package/body_package.sv +0 -0
- data/lib/tdl/examples/7_module_with_package/example_pkg.rb +0 -0
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +0 -0
- data/lib/tdl/examples/7_module_with_package/head_package.rb +0 -0
- data/lib/tdl/examples/7_module_with_package/head_package.sv +0 -0
- data/lib/tdl/examples/8_top_module/dve.tcl +0 -0
- data/lib/tdl/examples/8_top_module/example.rb +0 -0
- data/lib/tdl/examples/8_top_module/pins.yml +0 -0
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +0 -0
- data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +0 -0
- data/lib/tdl/examples/8_top_module/test_top.sv +26 -7
- data/lib/tdl/examples/8_top_module/test_top_constraints.xdc +8 -8
- data/lib/tdl/examples/8_top_module/test_top_sim.sv +7 -26
- data/lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv +0 -0
- data/lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb +0 -0
- data/lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/tu_ClockManage_test_clock_bb.sv +0 -0
- data/lib/tdl/examples/9_itegration/dve.tcl +0 -0
- data/lib/tdl/examples/9_itegration/pins.yml +0 -0
- data/lib/tdl/examples/9_itegration/tb_test_top.sv +0 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +0 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +1 -1
- data/lib/tdl/examples/9_itegration/test_top.sv +0 -0
- data/lib/tdl/examples/9_itegration/test_top_constraints.xdc +0 -0
- data/lib/tdl/examples/9_itegration/test_tttop.sv +0 -0
- data/lib/tdl/examples/9_itegration/test_tttop_constraints.xdc +0 -0
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +1 -1
- data/lib/tdl/examples/9_itegration/top.rb +2 -2
- data/lib/tdl/examples/readme.md +0 -0
- data/lib/tdl/exlib/axis_eth_ex.rb +0 -0
- data/lib/tdl/exlib/axis_verify.rb +0 -0
- data/lib/tdl/exlib/clock_reset_verify.rb +0 -0
- data/lib/tdl/exlib/common_cfg_reg_inf.rb +0 -0
- data/lib/tdl/exlib/constraints.rb +0 -0
- data/lib/tdl/exlib/constraints_verb.rb +4 -4
- data/lib/tdl/exlib/dve_tcl.rb +0 -0
- data/lib/tdl/exlib/element_class_vars.rb +0 -0
- data/lib/tdl/exlib/global_param.rb +0 -0
- data/lib/tdl/exlib/integral_test/bak/integral_test.rb +0 -0
- data/lib/tdl/exlib/integral_test/clock_itest.rb +0 -0
- data/lib/tdl/exlib/integral_test/diff_clock_itest.rb +0 -0
- data/lib/tdl/exlib/integral_test/io_itest.rb +0 -0
- data/lib/tdl/exlib/integral_test/reset_itest.rb +0 -0
- data/lib/tdl/exlib/integral_test/simple_logic_itest.rb +0 -0
- data/lib/tdl/exlib/itegration.rb +0 -0
- data/lib/tdl/exlib/itegration_test_unit.rb +0 -0
- data/lib/tdl/exlib/itegration_verb.rb +129 -13
- data/lib/tdl/exlib/logic_verify.rb +0 -0
- data/lib/tdl/exlib/parse_argv.rb +0 -0
- data/lib/tdl/exlib/sdlmodule_sim.bak.rb +0 -0
- data/lib/tdl/exlib/test_point.rb +4 -4
- data/lib/tdl/exlib/test_point.rb.bak +0 -0
- data/lib/tdl/global_scan.rb +0 -0
- data/lib/tdl/rebuild_ele/axi4.rb +0 -0
- data/lib/tdl/rebuild_ele/axi_lite.rb +0 -0
- data/lib/tdl/rebuild_ele/axi_stream.rb +0 -0
- data/lib/tdl/rebuild_ele/cm_ram_inf.sv +0 -0
- data/lib/tdl/rebuild_ele/cm_ram_inf_define.rb +0 -0
- data/lib/tdl/rebuild_ele/data_inf.rb +0 -0
- data/lib/tdl/rebuild_ele/data_inf_c.rb +0 -0
- data/lib/tdl/rebuild_ele/ele_base.rb +0 -0
- data/lib/tdl/rebuild_ele/readme.md +0 -0
- data/lib/tdl/sdlimplement/resource.yml +0 -0
- data/lib/tdl/sdlimplement/sdl_impl_module.rb +0 -0
- data/lib/tdl/sdlimplement/sdl_impl_param.rb +0 -0
- data/lib/tdl/sdlimplement/test.rb +0 -0
- data/lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb +0 -0
- data/lib/tdl/sdlmodule/generator_block_module.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodlule_path_db.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_head_logo.txt +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +3 -3
- data/lib/tdl/sdlmodule/sdlmodule_varible.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +0 -0
- data/lib/tdl/sdlmodule/techbench_module.rb +0 -0
- data/lib/tdl/sdlmodule/test_unit_module.rb +13 -3
- data/lib/tdl/sdlmodule/test_unit_module.rb.bak +0 -0
- data/lib/tdl/sdlmodule/top_module.rb +0 -0
- data/lib/tdl/sdlmodule/top_module.rb.bak +0 -0
- data/lib/tdl/tdl.rb +0 -0
- data/lib/tdl/tdlerror/tdlerror.rb +0 -0
- data/lib/tdl/testunit/test_all.rb +0 -0
- data/lib/tdl/testunit/test_array_chain.rb +0 -0
- data/lib/tdl/testunit/test_tmp.rb +0 -0
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/**********************************************
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_______________________________________
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___________ Cook Darwin __________
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_______________________________________
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descript: 通用报文格式解析器
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author : Cook.Darwin
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Version: VERA.0.1
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add out valid signal
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Version: VERA.1.0
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add enable signal
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Version: VERA.2.0 2017/12/11
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if stream length == need,It should be work,Like stream_length = 1,FIELD_TOTLE=1
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Version: VERA.2.1 2018-4-11 11:36:33
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add out_valid_record
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when length=2,old version cant parse axis_tlast for cm_tb_m,so I create `last_part_ok_q`
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creaded: 2016/12/16
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madified:2017/1/3
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***********************************************/
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`timescale 1ns/1ps
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module parse_common_frame_table_slaver #(
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parameter FIELD_TOTLE = 11, // MAX 16 :: default IP Frame
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parameter DSIZE = 8,
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//Field 0
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//---------------------
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parameter F0_LEN = 1,
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parameter F2_NAME = "totle length",
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parameter F4_NAME = "flag + offset MSB",
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+
//Field 5
|
|
44
|
+
//---------------------
|
|
45
|
+
parameter F5_LEN = 1,
|
|
46
|
+
parameter F5_NAME = "offset LSB",
|
|
47
|
+
//Field 6
|
|
48
|
+
//---------------------
|
|
49
|
+
parameter F6_LEN = 1,
|
|
50
|
+
parameter F6_NAME = "TTL",
|
|
51
|
+
//Field 7
|
|
52
|
+
//---------------------
|
|
53
|
+
parameter F7_LEN = 1,
|
|
54
|
+
parameter F7_NAME = "sub protocol",
|
|
55
|
+
//Field 8
|
|
56
|
+
//---------------------
|
|
57
|
+
parameter F8_LEN = 2,
|
|
58
|
+
parameter F8_NAME = "head CRC",
|
|
59
|
+
//Field 9
|
|
60
|
+
//---------------------
|
|
61
|
+
parameter F9_LEN = 4,
|
|
62
|
+
parameter F9_NAME = "source ip addr",
|
|
63
|
+
//Field 10
|
|
64
|
+
//---------------------
|
|
65
|
+
parameter F10_LEN = 4,
|
|
66
|
+
parameter F10_NAME = "destination ip addr",
|
|
67
|
+
//Field 11
|
|
68
|
+
//---------------------
|
|
69
|
+
parameter F11_LEN = 1,
|
|
70
|
+
parameter F11_NAME = "Filed 11",
|
|
71
|
+
//Field 12
|
|
72
|
+
//---------------------
|
|
73
|
+
parameter F12_LEN = 1,
|
|
74
|
+
parameter F12_NAME = "Filed 12",
|
|
75
|
+
//Field 13
|
|
76
|
+
//---------------------
|
|
77
|
+
parameter F13_LEN = 1,
|
|
78
|
+
parameter F13_NAME = "Field 13",
|
|
79
|
+
//Field 14
|
|
80
|
+
//---------------------
|
|
81
|
+
parameter F14_LEN = 1,
|
|
82
|
+
parameter F14_NAME = "Field 14",
|
|
83
|
+
//Field 15
|
|
84
|
+
//---------------------
|
|
85
|
+
parameter F15_LEN = 1,
|
|
86
|
+
parameter F15_NAME = "Field 15"
|
|
87
|
+
)(
|
|
88
|
+
input enable,
|
|
89
|
+
output logic [F0_LEN *DSIZE-1:0] f0_value,
|
|
90
|
+
output logic [F1_LEN *DSIZE-1:0] f1_value,
|
|
91
|
+
output logic [F2_LEN *DSIZE-1:0] f2_value,
|
|
92
|
+
output logic [F3_LEN *DSIZE-1:0] f3_value,
|
|
93
|
+
output logic [F4_LEN *DSIZE-1:0] f4_value,
|
|
94
|
+
output logic [F5_LEN *DSIZE-1:0] f5_value,
|
|
95
|
+
output logic [F6_LEN *DSIZE-1:0] f6_value,
|
|
96
|
+
output logic [F7_LEN *DSIZE-1:0] f7_value,
|
|
97
|
+
output logic [F8_LEN *DSIZE-1:0] f8_value,
|
|
98
|
+
output logic [F9_LEN *DSIZE-1:0] f9_value,
|
|
99
|
+
output logic [F10_LEN*DSIZE-1:0] f10_value,
|
|
100
|
+
output logic [F11_LEN*DSIZE-1:0] f11_value,
|
|
101
|
+
output logic [F12_LEN*DSIZE-1:0] f12_value,
|
|
102
|
+
output logic [F13_LEN*DSIZE-1:0] f13_value,
|
|
103
|
+
output logic [F14_LEN*DSIZE-1:0] f14_value,
|
|
104
|
+
output logic [F15_LEN*DSIZE-1:0] f15_value,
|
|
105
|
+
output logic out_valid,
|
|
106
|
+
axi_stream_inf.slaver cm_tb_s,
|
|
107
|
+
axi_stream_inf.master cm_tb_m
|
|
108
|
+
);
|
|
109
|
+
|
|
110
|
+
localparam TRY_PARSE = "OFF"; // just check frame, bypass data
|
|
111
|
+
|
|
112
|
+
import SystemPkg::*;
|
|
113
|
+
import DataInterfacePkg::*;
|
|
114
|
+
|
|
115
|
+
wire clock,rst_n,clken;
|
|
116
|
+
|
|
117
|
+
axi_stream_inf #(.DSIZE(DSIZE)) parse_stream (.aclk(clock),.aresetn(rst_n),.aclken(clken));
|
|
118
|
+
|
|
119
|
+
|
|
120
|
+
|
|
121
|
+
assign clock = cm_tb_s.aclk;
|
|
122
|
+
assign rst_n = cm_tb_s.aresetn;
|
|
123
|
+
assign clken = cm_tb_s.aclken;
|
|
124
|
+
|
|
125
|
+
|
|
126
|
+
assign parse_stream.axis_tkeep = cm_tb_s.axis_tkeep ;
|
|
127
|
+
assign parse_stream.axis_tuser = cm_tb_s.axis_tuser ;
|
|
128
|
+
assign parse_stream.axis_tlast = cm_tb_s.axis_tlast ;
|
|
129
|
+
assign parse_stream.axis_tdata = cm_tb_s.axis_tdata ;
|
|
130
|
+
assign parse_stream.axis_tvalid= cm_tb_s.axis_tvalid;
|
|
131
|
+
assign parse_stream.axis_tready= cm_tb_m.axis_tready;
|
|
132
|
+
assign cm_tb_s.axis_tready = cm_tb_m.axis_tready;
|
|
133
|
+
|
|
134
|
+
|
|
135
|
+
assign cm_tb_m.axis_tkeep = {(DSIZE/8){1'b1}};
|
|
136
|
+
assign cm_tb_m.axis_tuser = 1'b0;
|
|
137
|
+
|
|
138
|
+
import DataInterfacePkg::*;
|
|
139
|
+
|
|
140
|
+
localparam F0_SUM_LEN = F0_LEN;
|
|
141
|
+
localparam F1_SUM_LEN = F0_SUM_LEN + F1_LEN;
|
|
142
|
+
localparam F2_SUM_LEN = F1_SUM_LEN + F2_LEN;
|
|
143
|
+
localparam F3_SUM_LEN = F2_SUM_LEN + F3_LEN;
|
|
144
|
+
localparam F4_SUM_LEN = F3_SUM_LEN + F4_LEN;
|
|
145
|
+
localparam F5_SUM_LEN = F4_SUM_LEN + F5_LEN;
|
|
146
|
+
localparam F6_SUM_LEN = F5_SUM_LEN + F6_LEN;
|
|
147
|
+
localparam F7_SUM_LEN = F6_SUM_LEN + F7_LEN;
|
|
148
|
+
|
|
149
|
+
localparam F8_SUM_LEN = F7_SUM_LEN + F8_LEN;
|
|
150
|
+
localparam F9_SUM_LEN = F8_SUM_LEN + F9_LEN;
|
|
151
|
+
localparam F10_SUM_LEN = F9_SUM_LEN + F10_LEN;
|
|
152
|
+
localparam F11_SUM_LEN = F10_SUM_LEN+ F11_LEN;
|
|
153
|
+
localparam F12_SUM_LEN = F11_SUM_LEN+ F12_LEN;
|
|
154
|
+
localparam F13_SUM_LEN = F12_SUM_LEN+ F13_LEN;
|
|
155
|
+
localparam F14_SUM_LEN = F13_SUM_LEN+ F14_LEN;
|
|
156
|
+
localparam F15_SUM_LEN = F14_SUM_LEN+ F15_LEN;
|
|
157
|
+
|
|
158
|
+
localparam FIELD_LENGTH = FIELD_TOTLE==1 ? F0_SUM_LEN :
|
|
159
|
+
FIELD_TOTLE==2 ? F1_SUM_LEN :
|
|
160
|
+
FIELD_TOTLE==3 ? F2_SUM_LEN :
|
|
161
|
+
FIELD_TOTLE==4 ? F3_SUM_LEN :
|
|
162
|
+
FIELD_TOTLE==5 ? F4_SUM_LEN :
|
|
163
|
+
FIELD_TOTLE==6 ? F5_SUM_LEN :
|
|
164
|
+
FIELD_TOTLE==7 ? F6_SUM_LEN :
|
|
165
|
+
FIELD_TOTLE==8 ? F7_SUM_LEN :
|
|
166
|
+
FIELD_TOTLE==9 ? F8_SUM_LEN :
|
|
167
|
+
FIELD_TOTLE==10? F9_SUM_LEN :
|
|
168
|
+
FIELD_TOTLE==11? F10_SUM_LEN :
|
|
169
|
+
FIELD_TOTLE==12? F11_SUM_LEN :
|
|
170
|
+
FIELD_TOTLE==13? F12_SUM_LEN :
|
|
171
|
+
FIELD_TOTLE==14? F13_SUM_LEN :
|
|
172
|
+
FIELD_TOTLE==15? F14_SUM_LEN : F15_SUM_LEN ;
|
|
173
|
+
|
|
174
|
+
|
|
175
|
+
typedef enum {IDLE,START,F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,F14,F15,DONE,DLAST} STATUS;
|
|
176
|
+
|
|
177
|
+
STATUS cstate,nstate;
|
|
178
|
+
|
|
179
|
+
|
|
180
|
+
logic f0_pack_ok;
|
|
181
|
+
logic f1_pack_ok;
|
|
182
|
+
logic f2_pack_ok;
|
|
183
|
+
logic f3_pack_ok;
|
|
184
|
+
logic f4_pack_ok;
|
|
185
|
+
logic f5_pack_ok;
|
|
186
|
+
logic f6_pack_ok;
|
|
187
|
+
logic f7_pack_ok;
|
|
188
|
+
logic f8_pack_ok;
|
|
189
|
+
logic f9_pack_ok;
|
|
190
|
+
logic f10_pack_ok;
|
|
191
|
+
logic f11_pack_ok;
|
|
192
|
+
logic f12_pack_ok;
|
|
193
|
+
logic f13_pack_ok;
|
|
194
|
+
logic f14_pack_ok;
|
|
195
|
+
logic f15_pack_ok;
|
|
196
|
+
|
|
197
|
+
logic force_jump;
|
|
198
|
+
|
|
199
|
+
logic last_part_ok,last_part_ok_q;
|
|
200
|
+
logic no_data;
|
|
201
|
+
|
|
202
|
+
always@(posedge clock,negedge rst_n)
|
|
203
|
+
if(~rst_n) cstate <= IDLE;
|
|
204
|
+
else cstate <= nstate;
|
|
205
|
+
|
|
206
|
+
always@(*)
|
|
207
|
+
case(cstate)
|
|
208
|
+
IDLE:
|
|
209
|
+
if(parse_stream.axis_tvalid && enable)
|
|
210
|
+
// if(parse_stream.axis_tvalid)
|
|
211
|
+
nstate = F0;
|
|
212
|
+
else nstate = IDLE;
|
|
213
|
+
F0 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f0_pack_ok) begin nstate = (FIELD_TOTLE!= 1)? F1 : DONE; end else nstate = F0;
|
|
214
|
+
F1 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f1_pack_ok) begin nstate = (FIELD_TOTLE!= 2)? F2 : DONE; end else nstate = F1;
|
|
215
|
+
F2 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f2_pack_ok) begin nstate = (FIELD_TOTLE!= 3)? F3 : DONE; end else nstate = F2;
|
|
216
|
+
F3 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f3_pack_ok) begin nstate = (FIELD_TOTLE!= 4)? F4 : DONE; end else nstate = F3;
|
|
217
|
+
F4 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f4_pack_ok) begin nstate = (FIELD_TOTLE!= 5)? F5 : DONE; end else nstate = F4;
|
|
218
|
+
F5 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f5_pack_ok) begin nstate = (FIELD_TOTLE!= 6)? F6 : DONE; end else nstate = F5;
|
|
219
|
+
F6 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f6_pack_ok) begin nstate = (FIELD_TOTLE!= 7)? F7 : DONE; end else nstate = F6;
|
|
220
|
+
F7 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f7_pack_ok) begin nstate = (FIELD_TOTLE!= 8)? F8 : DONE; end else nstate = F7;
|
|
221
|
+
F8 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f8_pack_ok) begin nstate = (FIELD_TOTLE!= 9)? F9 : DONE; end else nstate = F8;
|
|
222
|
+
F9 : if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f9_pack_ok) begin nstate = (FIELD_TOTLE!=10)? F10 : DONE; end else nstate = F9;
|
|
223
|
+
F10: if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f10_pack_ok)begin nstate = (FIELD_TOTLE!=11)? F11 : DONE; end else nstate = F10;
|
|
224
|
+
F11: if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f11_pack_ok)begin nstate = (FIELD_TOTLE!=12)? F12 : DONE; end else nstate = F11;
|
|
225
|
+
F12: if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f12_pack_ok)begin nstate = (FIELD_TOTLE!=13)? F13 : DONE; end else nstate = F12;
|
|
226
|
+
F13: if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f13_pack_ok)begin nstate = (FIELD_TOTLE!=14)? F14 : DONE; end else nstate = F13;
|
|
227
|
+
F14: if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f14_pack_ok)begin nstate = (FIELD_TOTLE!=15)? F15 : DONE; end else nstate = F14;
|
|
228
|
+
F15: if(force_jump) nstate = (TRY_PARSE=="ON")? DLAST : IDLE ;else if(f15_pack_ok)begin nstate = DONE ; end else nstate = F15;
|
|
229
|
+
DONE:
|
|
230
|
+
if(last_part_ok)
|
|
231
|
+
nstate = DLAST;
|
|
232
|
+
else if(last_part_ok_q)
|
|
233
|
+
nstate = IDLE;
|
|
234
|
+
else nstate = DONE;
|
|
235
|
+
DLAST:
|
|
236
|
+
if(TRY_PARSE=="ON")begin
|
|
237
|
+
if(parse_stream.axis_tvalid && enable)
|
|
238
|
+
nstate = F0;
|
|
239
|
+
else nstate = IDLE;
|
|
240
|
+
// else if(force_jump && parse_stream.aclken)
|
|
241
|
+
// nstate = IDLE;
|
|
242
|
+
// else if(cm_tb_m.axis_tvalid && cm_tb_m.axis_tready && cm_tb_m.axis_tlast && cm_tb_m.aclken)
|
|
243
|
+
// else if(cm_tb_m.axis_tvalid && cm_tb_m.axis_tready && cm_tb_m.aclken)
|
|
244
|
+
// nstate = IDLE;
|
|
245
|
+
end else if(cm_tb_m.axis_tvalid && cm_tb_m.axis_tready && cm_tb_m.aclken )begin
|
|
246
|
+
if(parse_stream.axis_tvalid)
|
|
247
|
+
nstate = F0;
|
|
248
|
+
else nstate = IDLE;
|
|
249
|
+
end else nstate = DLAST;
|
|
250
|
+
default:nstate = IDLE;
|
|
251
|
+
endcase
|
|
252
|
+
|
|
253
|
+
//---->> STATUS SEQUEN CTRL <<---------------------
|
|
254
|
+
localparam CSIZE = FIELD_LENGTH <= 8 ? 3 :
|
|
255
|
+
FIELD_LENGTH <= 16 ? 4 :
|
|
256
|
+
FIELD_LENGTH <= 32 ? 5 :
|
|
257
|
+
FIELD_LENGTH <= 64 ? 6 :
|
|
258
|
+
FIELD_LENGTH <= 128? 7 :
|
|
259
|
+
FIELD_LENGTH <= 512? 8 :
|
|
260
|
+
FIELD_LENGTH <= 1024?9 : 16;
|
|
261
|
+
|
|
262
|
+
logic[CSIZE-1:0] cnt;
|
|
263
|
+
reg[2:0] subcnt;
|
|
264
|
+
|
|
265
|
+
always@(posedge clock/*,negedge rst_n*/)
|
|
266
|
+
if(~rst_n) cnt <= {CSIZE{1'b0}};
|
|
267
|
+
else
|
|
268
|
+
case(nstate)
|
|
269
|
+
IDLE,DLAST:
|
|
270
|
+
cnt <= {CSIZE{1'b0}};
|
|
271
|
+
default:begin
|
|
272
|
+
if(parse_stream.axis_tready && parse_stream.axis_tvalid && parse_stream.aclken && enable && cnt == '0)
|
|
273
|
+
cnt <= cnt + 1'b1;
|
|
274
|
+
else if(parse_stream.axis_tready && parse_stream.axis_tvalid && parse_stream.aclken && cnt != '0)
|
|
275
|
+
cnt <= cnt + 1'b1;
|
|
276
|
+
else cnt <= cnt;
|
|
277
|
+
end
|
|
278
|
+
endcase
|
|
279
|
+
|
|
280
|
+
always@(posedge clock/*,negedge rst_n*/)begin
|
|
281
|
+
f0_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F0_SUM_LEN - 1;
|
|
282
|
+
f1_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F1_SUM_LEN - 1;
|
|
283
|
+
f2_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F2_SUM_LEN - 1;
|
|
284
|
+
f3_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F3_SUM_LEN - 1;
|
|
285
|
+
f4_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F4_SUM_LEN - 1;
|
|
286
|
+
f5_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F5_SUM_LEN - 1;
|
|
287
|
+
f6_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F6_SUM_LEN - 1;
|
|
288
|
+
f7_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F7_SUM_LEN - 1;
|
|
289
|
+
f8_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F8_SUM_LEN - 1;
|
|
290
|
+
f9_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F9_SUM_LEN - 1;
|
|
291
|
+
f10_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F10_SUM_LEN- 1;
|
|
292
|
+
f11_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F11_SUM_LEN- 1;
|
|
293
|
+
f12_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F12_SUM_LEN- 1;
|
|
294
|
+
f13_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F13_SUM_LEN- 1;
|
|
295
|
+
f14_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F14_SUM_LEN- 1;
|
|
296
|
+
f15_pack_ok <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F15_SUM_LEN- 1;
|
|
297
|
+
end
|
|
298
|
+
|
|
299
|
+
assign last_part_ok = (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && parse_stream.axis_tlast) || no_data;
|
|
300
|
+
|
|
301
|
+
always@(posedge clock/*,negedge rst_n*/)
|
|
302
|
+
if(~rst_n) last_part_ok_q <= 1'b0;
|
|
303
|
+
else last_part_ok_q <= last_part_ok;
|
|
304
|
+
|
|
305
|
+
always@(posedge clock/*,negedge rst_n*/)
|
|
306
|
+
if(~rst_n) force_jump <= 1'b0;
|
|
307
|
+
else begin
|
|
308
|
+
if(last_part_ok)
|
|
309
|
+
force_jump <= 1'b1;
|
|
310
|
+
else if(parse_stream.aclken)
|
|
311
|
+
force_jump <= 1'b0;
|
|
312
|
+
else force_jump <= force_jump;
|
|
313
|
+
end
|
|
314
|
+
|
|
315
|
+
always@(posedge clock/*,negedge rst_n*/)
|
|
316
|
+
if(~rst_n) no_data <= 1'b0;
|
|
317
|
+
else
|
|
318
|
+
case(nstate)
|
|
319
|
+
IDLE: no_data <= 1'b0;
|
|
320
|
+
F0 ,
|
|
321
|
+
F1 ,
|
|
322
|
+
F2 ,
|
|
323
|
+
F3 ,
|
|
324
|
+
F4 ,
|
|
325
|
+
F5 ,
|
|
326
|
+
F6 ,
|
|
327
|
+
F7 ,
|
|
328
|
+
F8 ,
|
|
329
|
+
F9 ,
|
|
330
|
+
F10,
|
|
331
|
+
F11,
|
|
332
|
+
F12,
|
|
333
|
+
F13,
|
|
334
|
+
F14,
|
|
335
|
+
F15: no_data <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && parse_stream.axis_tlast;
|
|
336
|
+
default: no_data <= no_data;
|
|
337
|
+
endcase
|
|
338
|
+
|
|
339
|
+
//----<< STATUS SEQUEN CTRL >>---------------------
|
|
340
|
+
//---->> SUB SEQUEN CTRL <<------------------------
|
|
341
|
+
|
|
342
|
+
always@(posedge clock/*,negedge rst_n*/)
|
|
343
|
+
if(~rst_n) subcnt <= 3'd0;
|
|
344
|
+
else begin
|
|
345
|
+
if( parse_stream.aclken)begin
|
|
346
|
+
case(nstate)
|
|
347
|
+
IDLE,DONE,DLAST:
|
|
348
|
+
subcnt <= 3'd0;
|
|
349
|
+
default:begin
|
|
350
|
+
if(parse_stream.axis_tready && parse_stream.axis_tvalid)begin
|
|
351
|
+
if(~parse_stream.axis_tlast)begin
|
|
352
|
+
case(cnt)
|
|
353
|
+
(F0_SUM_LEN - 1),
|
|
354
|
+
(F1_SUM_LEN - 1),
|
|
355
|
+
(F2_SUM_LEN - 1),
|
|
356
|
+
(F3_SUM_LEN - 1),
|
|
357
|
+
(F4_SUM_LEN - 1),
|
|
358
|
+
(F5_SUM_LEN - 1),
|
|
359
|
+
(F6_SUM_LEN - 1),
|
|
360
|
+
(F7_SUM_LEN - 1),
|
|
361
|
+
(F8_SUM_LEN - 1),
|
|
362
|
+
(F9_SUM_LEN - 1),
|
|
363
|
+
(F10_SUM_LEN- 1),
|
|
364
|
+
(F11_SUM_LEN- 1),
|
|
365
|
+
(F12_SUM_LEN- 1),
|
|
366
|
+
(F13_SUM_LEN- 1),
|
|
367
|
+
(F14_SUM_LEN- 1),
|
|
368
|
+
(F15_SUM_LEN- 1): subcnt <= 3'd0;
|
|
369
|
+
default: subcnt <= subcnt + 1'b1;
|
|
370
|
+
endcase
|
|
371
|
+
end else subcnt <= 3'd0;
|
|
372
|
+
end else subcnt <= subcnt;
|
|
373
|
+
end
|
|
374
|
+
endcase
|
|
375
|
+
end else subcnt <= subcnt;
|
|
376
|
+
end
|
|
377
|
+
//----<< SUB SEQUEN CTRL >>------------------------
|
|
378
|
+
//---->> RD DATA <<--------------------------------
|
|
379
|
+
|
|
380
|
+
always@(posedge clock/*,negedge rst_n*/)
|
|
381
|
+
if(~rst_n) begin
|
|
382
|
+
f0_value <= '0;
|
|
383
|
+
f1_value <= '0;
|
|
384
|
+
f2_value <= '0;
|
|
385
|
+
f3_value <= '0;
|
|
386
|
+
f4_value <= '0;
|
|
387
|
+
f5_value <= '0;
|
|
388
|
+
f6_value <= '0;
|
|
389
|
+
f7_value <= '0;
|
|
390
|
+
f8_value <= '0;
|
|
391
|
+
f9_value <= '0;
|
|
392
|
+
f10_value <= '0;
|
|
393
|
+
f11_value <= '0;
|
|
394
|
+
f12_value <= '0;
|
|
395
|
+
f13_value <= '0;
|
|
396
|
+
f14_value <= '0;
|
|
397
|
+
f15_value <= '0;
|
|
398
|
+
end else
|
|
399
|
+
if(parse_stream.axis_tready && parse_stream.axis_tvalid)begin
|
|
400
|
+
case(nstate)
|
|
401
|
+
F0 : f0_value[(F0_LEN-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f0_value[(F0_LEN-subcnt)*DSIZE-1-:DSIZE] ;
|
|
402
|
+
F1 : f1_value[( F1_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f1_value[( F1_LEN-0-subcnt)*DSIZE-1-:DSIZE];
|
|
403
|
+
F2 : f2_value[( F2_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f2_value[( F2_LEN-0-subcnt)*DSIZE-1-:DSIZE];
|
|
404
|
+
F3 : f3_value[( F3_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f3_value[( F3_LEN-0-subcnt)*DSIZE-1-:DSIZE];
|
|
405
|
+
F4 : f4_value[( F4_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f4_value[( F4_LEN-0-subcnt)*DSIZE-1-:DSIZE];
|
|
406
|
+
F5 : f5_value[( F5_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f5_value[( F5_LEN-0-subcnt)*DSIZE-1-:DSIZE];
|
|
407
|
+
F6 : f6_value[( F6_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f6_value[( F6_LEN-0-subcnt)*DSIZE-1-:DSIZE];
|
|
408
|
+
F7 : f7_value[( F7_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f7_value[( F7_LEN-0-subcnt)*DSIZE-1-:DSIZE];
|
|
409
|
+
F8 : f8_value[( F8_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f8_value[( F8_LEN-0-subcnt)*DSIZE-1-:DSIZE];
|
|
410
|
+
F9 : f9_value[( F9_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f9_value[( F9_LEN-0-subcnt)*DSIZE-1-:DSIZE];
|
|
411
|
+
F10: f10_value[(F10_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f10_value[(F10_LEN-0-subcnt)*DSIZE-1-:DSIZE];
|
|
412
|
+
F11: f11_value[(F11_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f11_value[(F11_LEN-0-subcnt)*DSIZE-1-:DSIZE];
|
|
413
|
+
F12: f12_value[(F12_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f12_value[(F12_LEN-0-subcnt)*DSIZE-1-:DSIZE];
|
|
414
|
+
F13: f13_value[(F13_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f13_value[(F13_LEN-0-subcnt)*DSIZE-1-:DSIZE];
|
|
415
|
+
F14: f14_value[(F14_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f14_value[(F14_LEN-0-subcnt)*DSIZE-1-:DSIZE];
|
|
416
|
+
F15: f15_value[(F15_LEN-0-subcnt)*DSIZE-1-:DSIZE] <= enable? parse_stream.axis_tdata : f15_value[(F15_LEN-0-subcnt)*DSIZE-1-:DSIZE];
|
|
417
|
+
default:;
|
|
418
|
+
endcase
|
|
419
|
+
end else begin
|
|
420
|
+
;
|
|
421
|
+
end
|
|
422
|
+
|
|
423
|
+
//----<< RD DATA >>--------------------------------
|
|
424
|
+
// ---->> AXI STREAM <<-----------------------------
|
|
425
|
+
always@(posedge clock/*,negedge rst_n*/)
|
|
426
|
+
if(~rst_n) cm_tb_m.axis_tdata <= 8'd0;
|
|
427
|
+
else
|
|
428
|
+
case(nstate)
|
|
429
|
+
DONE,DLAST:begin
|
|
430
|
+
if(parse_stream.axis_tvalid && parse_stream.axis_tready && parse_stream.aclken)
|
|
431
|
+
cm_tb_m.axis_tdata <= parse_stream.axis_tdata;
|
|
432
|
+
else cm_tb_m.axis_tdata <= cm_tb_m.axis_tdata;
|
|
433
|
+
end
|
|
434
|
+
default:;
|
|
435
|
+
endcase
|
|
436
|
+
|
|
437
|
+
//
|
|
438
|
+
always@(posedge clock/*,negedge rst_n*/)
|
|
439
|
+
if(~rst_n) cm_tb_m.axis_tlast <= 1'd0;
|
|
440
|
+
else
|
|
441
|
+
// if(cm_tb_m.axis_tvalid && cm_tb_m.axis_tready && cm_tb_m.aclken)
|
|
442
|
+
case(nstate)
|
|
443
|
+
DONE:begin
|
|
444
|
+
if(last_part_ok)
|
|
445
|
+
cm_tb_m.axis_tlast <= 1'd1;
|
|
446
|
+
else cm_tb_m.axis_tlast <= 1'd0;
|
|
447
|
+
end
|
|
448
|
+
DLAST:begin
|
|
449
|
+
cm_tb_m.axis_tlast <= 1'd1;
|
|
450
|
+
end
|
|
451
|
+
default:cm_tb_m.axis_tlast <= 1'd0;
|
|
452
|
+
endcase
|
|
453
|
+
// else cm_tb_m.axis_tlast <= cm_tb_m.axis_tlast;
|
|
454
|
+
|
|
455
|
+
always@(posedge clock/*,negedge rst_n*/)
|
|
456
|
+
if(~rst_n) cm_tb_m.axis_tvalid <= 1'd0;
|
|
457
|
+
else begin
|
|
458
|
+
// if(cm_tb_m.axis_tvalid && cm_tb_m.axis_tready && cm_tb_m.aclken)begin
|
|
459
|
+
case(nstate)
|
|
460
|
+
DONE,DLAST:begin
|
|
461
|
+
if(cm_tb_m.aclken)
|
|
462
|
+
cm_tb_m.axis_tvalid <= pipe_valid_func(parse_stream.axis_tvalid,cm_tb_m.axis_tready,cm_tb_m.axis_tvalid);
|
|
463
|
+
else cm_tb_m.axis_tvalid <= cm_tb_m.axis_tvalid;
|
|
464
|
+
end
|
|
465
|
+
default:cm_tb_m.axis_tvalid <= 1'd0;
|
|
466
|
+
endcase
|
|
467
|
+
// end else cm_tb_m.axis_tvalid <= cm_tb_m.axis_tvalid;
|
|
468
|
+
end
|
|
469
|
+
// ---->> AXI STREAM <<-----------------------------
|
|
470
|
+
//----->> OUTD VALID <<-----------------------------
|
|
471
|
+
logic last_record;
|
|
472
|
+
always@(posedge clock/*,negedge rst_n*/)
|
|
473
|
+
if(~rst_n) last_record <= 1'b0;
|
|
474
|
+
else last_record <= parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && parse_stream.axis_tlast;
|
|
475
|
+
|
|
476
|
+
logic out_valid_record;
|
|
477
|
+
always@(posedge clock/*,negedge rst_n*/)
|
|
478
|
+
if(~rst_n) out_valid_record <= 1'b0;
|
|
479
|
+
else begin
|
|
480
|
+
case(nstate)
|
|
481
|
+
IDLE: out_valid_record <= 1'b0;
|
|
482
|
+
default: begin
|
|
483
|
+
if(parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && parse_stream.axis_tlast)
|
|
484
|
+
out_valid_record <= 1'b0;
|
|
485
|
+
else if(out_valid)
|
|
486
|
+
out_valid_record <= 1'b1;
|
|
487
|
+
else out_valid_record <= out_valid_record;
|
|
488
|
+
end
|
|
489
|
+
endcase
|
|
490
|
+
end
|
|
491
|
+
|
|
492
|
+
always@(posedge clock/*,negedge rst_n*/)
|
|
493
|
+
if(~rst_n) out_valid <= 1'b0;
|
|
494
|
+
else begin
|
|
495
|
+
if(out_valid || last_record)
|
|
496
|
+
// if(parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && parse_stream.axis_tlast)
|
|
497
|
+
out_valid <= 1'b0;
|
|
498
|
+
else if(!out_valid_record)
|
|
499
|
+
case(FIELD_TOTLE)
|
|
500
|
+
1 : out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F0_SUM_LEN - 1)/* || out_valid*/;
|
|
501
|
+
2 : out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F1_SUM_LEN - 1)/* || out_valid*/;
|
|
502
|
+
3 : out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F2_SUM_LEN - 1)/* || out_valid*/;
|
|
503
|
+
4 : out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F3_SUM_LEN - 1)/* || out_valid*/;
|
|
504
|
+
5 : out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F4_SUM_LEN - 1)/* || out_valid*/;
|
|
505
|
+
6 : out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F5_SUM_LEN - 1)/* || out_valid*/;
|
|
506
|
+
7 : out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F6_SUM_LEN - 1)/* || out_valid*/;
|
|
507
|
+
8 : out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F7_SUM_LEN - 1)/* || out_valid*/;
|
|
508
|
+
9 : out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F8_SUM_LEN - 1)/* || out_valid*/;
|
|
509
|
+
10: out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F9_SUM_LEN - 1)/* || out_valid*/;
|
|
510
|
+
11: out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F10_SUM_LEN- 1)/* || out_valid*/;
|
|
511
|
+
12: out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F11_SUM_LEN- 1)/* || out_valid*/;
|
|
512
|
+
13: out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F12_SUM_LEN- 1)/* || out_valid*/;
|
|
513
|
+
14: out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F13_SUM_LEN- 1)/* || out_valid*/;
|
|
514
|
+
15: out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F14_SUM_LEN- 1)/* || out_valid*/;
|
|
515
|
+
16: out_valid <= (parse_stream.aclken && parse_stream.axis_tready && parse_stream.axis_tvalid && cnt==F15_SUM_LEN- 1)/* || out_valid*/;
|
|
516
|
+
default:;
|
|
517
|
+
endcase
|
|
518
|
+
else out_valid <= 1'b0;
|
|
519
|
+
end
|
|
520
|
+
//-----<< OUTD VALID >>-----------------------------
|
|
521
|
+
//--->> SIM <<--------------------------------------
|
|
522
|
+
// string str = "";
|
|
523
|
+
//
|
|
524
|
+
// always@(*)
|
|
525
|
+
// case(cstate)
|
|
526
|
+
// F0 : str = F0_NAME;
|
|
527
|
+
// F1 : str = F1_NAME;
|
|
528
|
+
// F2 : str = F2_NAME;
|
|
529
|
+
// F3 : str = F3_NAME;
|
|
530
|
+
// F4 : str = F4_NAME;
|
|
531
|
+
// F5 : str = F5_NAME;
|
|
532
|
+
// F6 : str = F6_NAME;
|
|
533
|
+
// F7 : str = F7_NAME;
|
|
534
|
+
// F8 : str = F8_NAME;
|
|
535
|
+
// F9 : str = F9_NAME;
|
|
536
|
+
// F10: str = F10_NAME;
|
|
537
|
+
// F11: str = F11_NAME;
|
|
538
|
+
// F12: str = F12_NAME;
|
|
539
|
+
// F13: str = F13_NAME;
|
|
540
|
+
// F14: str = F14_NAME;
|
|
541
|
+
// F15: str = F15_NAME;
|
|
542
|
+
// default:str = "IDLE";
|
|
543
|
+
// endcase
|
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544
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+
//---<< SIM >>--------------------------------------
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545
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+
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546
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+
endmodule
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@@ -56,7 +56,7 @@ FIFO_DUALCLOCK_MACRO #(
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56
56
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.RDERR (), // 1-bit output read error
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57
57
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.WRCOUNT (), // Output write count, width determined by FIFO depth
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58
58
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.WRERR (), // 1-bit output write error
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59
|
-
.DI ({
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59
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+
.DI ({axis_out.axis_tlast,axis_int.axis_tdata } ), // Input data, width defined by DATA_WIDTH parameter
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60
60
|
.RDCLK (axis_out.aclk ), // 1-bit input read clock
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61
61
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.RDEN ((axis_out.axis_tready && axis_out.aclken) ), // 1-bit input read enable
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62
62
|
.RST (RST), // 1-bit input reset
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@@ -0,0 +1,58 @@
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1
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+
/**********************************************
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2
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+
_______________________________________
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3
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+
___________ Cook Darwin __________
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4
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+
_______________________________________
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5
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+
descript:
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6
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+
author : Cook.Darwin
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7
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+
Version: VERB.0.0 2017/9/28
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8
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+
use fifo
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|
9
|
+
compatible ku
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|
10
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+
keep valid
|
|
11
|
+
creaded: 2017/2/28
|
|
12
|
+
madified:
|
|
13
|
+
***********************************************/
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|
14
|
+
`timescale 1ns/1ps
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|
15
|
+
(* axi_stream = "true" *)
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|
16
|
+
module axi_stream_cache_compact_verb (
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|
17
|
+
(* up_stream = "true" *)
|
|
18
|
+
axi_stream_inf.slaver axis_in,
|
|
19
|
+
(* down_stream = "true" *)
|
|
20
|
+
axi_stream_inf.master axis_out
|
|
21
|
+
);
|
|
22
|
+
|
|
23
|
+
|
|
24
|
+
initial begin
|
|
25
|
+
assert(axis_in.DSIZE == axis_out.DSIZE)
|
|
26
|
+
else begin
|
|
27
|
+
$error("\nSLAVER DSIZE[%d] MUST EQL MASTER DSIZE[%d]\n",axis_in.DSIZE,axis_out.DSIZE);
|
|
28
|
+
$finish;
|
|
29
|
+
end
|
|
30
|
+
end
|
|
31
|
+
|
|
32
|
+
logic empty;
|
|
33
|
+
logic full;
|
|
34
|
+
|
|
35
|
+
|
|
36
|
+
xilinx_fifo_verb #(
|
|
37
|
+
.DSIZE (axis_in.DSIZE+1 ),
|
|
38
|
+
.LENGTH (2**(11 - (axis_in.DSIZE/24+(axis_in.DSIZE%24 != 0)) ) )
|
|
39
|
+
)xilinx_fifo_verb_inst(
|
|
40
|
+
/* input */ .wr_clk (axis_in.aclk ),
|
|
41
|
+
/* input */ .wr_rst (!axis_in.aresetn ),
|
|
42
|
+
/* input */ .rd_clk (axis_out.aclk ),
|
|
43
|
+
/* input */ .rd_rst (!axis_out.aresetn ),
|
|
44
|
+
/* input [DSIZE-1:0] */ .din ({axis_in.axis_tlast,axis_in.axis_tdata} ),
|
|
45
|
+
/* input */ .wr_en ((axis_in.axis_tvalid && !full) ),
|
|
46
|
+
/* input */ .rd_en ((axis_out.axis_tready && !empty) ),
|
|
47
|
+
/* output [DSIZE-1:0] */ .dout ({axis_out.axis_tlast,axis_out.axis_tdata} ),
|
|
48
|
+
/* output */ .full (full ),
|
|
49
|
+
/* output */ .empty (empty )
|
|
50
|
+
);
|
|
51
|
+
|
|
52
|
+
assign axis_in.axis_tready = !full;
|
|
53
|
+
assign axis_out.axis_tvalid = !empty;
|
|
54
|
+
|
|
55
|
+
assign axis_out.axis_tuser = '0;
|
|
56
|
+
// assign axis_out.axis_tkeep = '1;
|
|
57
|
+
|
|
58
|
+
endmodule
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data/lib/axi/LICENSE
CHANGED
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data/lib/axi/ReadME.md
CHANGED
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