axi_tdl 0.2.5 → 0.2.10
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.github/workflows/gem-push.yml +21 -48
- data/.github/workflows/ruby.yml +1 -1
- data/lib/axi/AXI4/axi4_combin_wr_rd_batch.sv +0 -0
- data/lib/axi/AXI4/axi4_direct.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_A1.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_B1.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_algin_addr_step.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_verc.sv +0 -0
- data/lib/axi/AXI4/axi4_dpram_cache.rb +0 -0
- data/lib/axi/AXI4/axi4_dpram_cache.sv +0 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide.sv +0 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv +0 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv +2 -1
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv +0 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_pipe.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_pipe_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_ram_cache.rb +0 -0
- data/lib/axi/AXI4/axi4_ram_cache.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A2.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_burst_track.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_aux_bind_data.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_gen.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_gen_without_resp.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_burst_track.sv +0 -0
- data/lib/axi/AXI4/axi_stream_add_addr_len.sv +0 -0
- data/lib/axi/AXI4/axi_stream_to_axi4_wr.sv +54 -8
- data/lib/axi/AXI4/axi_stream_to_axi4_wr_verb.sv.bak +0 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +0 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +0 -0
- data/lib/axi/AXI4/full_axi4_to_axis.sv +0 -0
- data/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv +0 -0
- data/lib/axi/AXI4/id_record.sv +0 -0
- data/lib/axi/AXI4/idata_pool_axi4.sv +0 -0
- data/lib/axi/AXI4/interconnect/AXI4_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv.bak +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A1.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak +0 -0
- data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +0 -0
- data/lib/axi/AXI4/long_axis_to_axi4_wr.sv +1 -1
- data/lib/axi/AXI4/odata_pool_axi4.sv +0 -0
- data/lib/axi/AXI4/odata_pool_axi4_A1.sv +0 -0
- data/lib/axi/AXI4/odata_pool_axi4_A2.sv +0 -0
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +0 -0
- data/lib/axi/AXI4/odata_pool_axi4_A4.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_B1.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_verb.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo_A1.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo_A1.sv +12 -4
- data/lib/axi/AXI4/packet_merge/axi4_merge.sv +0 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge_rd.sv +0 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge_wr.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_OD.sv +3 -2
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_OD.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +16 -7
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +13 -9
- data/lib/axi/AXI4/packet_partition/axi4_partition_wr.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_wr_OD.sv +11 -10
- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +0 -0
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
- data/lib/axi/AXI4/packet_partition/data_inf_partition_A1.rb +298 -0
- data/lib/axi/AXI4/packet_partition/data_inf_partition_A1.sv +316 -0
- data/lib/axi/AXI4/vcs_axi4_array_comptable.sv +0 -0
- data/lib/axi/AXI4/vcs_axi4_comptable.sv +0 -0
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +0 -0
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb.bk +150 -0
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +2 -2
- data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe.sv +0 -0
- data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv +0 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert.sv +0 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv +0 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert_verb.sv +0 -0
- data/lib/axi/AXI4/width_convert/data_combin.sv +0 -0
- data/lib/axi/AXI4/width_convert/data_combin.sv.bak +0 -0
- data/lib/axi/AXI4/width_convert/data_destruct.sv +0 -0
- data/lib/axi/AXI4/width_convert/feed_check.sv +0 -0
- data/lib/axi/AXI4/width_convert/len_convert.sv.bak +0 -0
- data/lib/axi/AXI4/width_convert/odd_width_convert.sv +0 -0
- data/lib/axi/AXI4/width_convert/odd_width_convert_verb.sv +0 -0
- data/lib/axi/AXI4/width_convert/simple_data_pipe.sv +0 -0
- data/lib/axi/AXI4/width_convert/simple_data_pipe_slaver.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_combin.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_convert.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_convert_verb.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_destruct.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_destruct_A1.sv +0 -0
- data/lib/axi/AXI_BFM/AXI_BFM_PKG.sv +0 -0
- data/lib/axi/AXI_BFM/Data_C_BFM_PKG.sv +0 -0
- data/lib/axi/AXI_BFM/axi4_error_chk.sv +0 -0
- data/lib/axi/AXI_BFM/axi4_illegal_bfm_pkg.sv +0 -0
- data/lib/axi/AXI_BFM/axi_lite_master.sv +0 -0
- data/lib/axi/AXI_BFM/axi_lite_tb.sv +0 -0
- data/lib/axi/AXI_BFM/axi_master.sv +0 -0
- data/lib/axi/AXI_BFM/axi_mirror.sv +0 -0
- data/lib/axi/AXI_BFM/axi_mm_tb.sv +0 -0
- data/lib/axi/AXI_BFM/axi_slaver.sv.bak +0 -0
- data/lib/axi/AXI_BFM/axistreambfm.sv +0 -0
- data/lib/axi/AXI_Lite/axi4_to_lite.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_configure.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_configure_inf2.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_configure_verb.sv.bck +0 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv +4 -5
- data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv.bak +0 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M_verb.sv +322 -0
- data/lib/axi/AXI_Lite/axi_lite_master_empty.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_slaver_empty.sv +0 -0
- data/lib/axi/AXI_Lite/axil_direct.sv +0 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv +0 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv.bak +0 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv +0 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl.sv +0 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_C1.sv +0 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verb.sv +0 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verc.sv +0 -0
- data/lib/axi/AXI_Lite/wr_lite_to_axis.sv +0 -0
- data/lib/axi/AXI_Lite/wr_lite_to_axis.sv.bak +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_cpVCS.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_auto.sv +26 -5
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_info.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_keep.sv.bak +0 -0
- data/lib/axi/AXI_stream/axi_stream_latency.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_packet_fifo_with_info.sv.bak +0 -0
- data/lib/axi/AXI_stream/axi_stream_partition.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_partition_A1.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_planer.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +0 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +26 -26
- data/lib/axi/AXI_stream/axi_streams_combin.sv +0 -0
- data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +0 -0
- data/lib/axi/AXI_stream/axi_streams_scaler.sv +0 -0
- data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_append.sv +0 -0
- data/lib/axi/AXI_stream/axis_append_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_base_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_A1.sv.bak +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_left_shift.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_right_shift.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_right_shift_verb.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_with_info.sv +0 -0
- data/lib/axi/AXI_stream/axis_direct.sv +0 -0
- data/lib/axi/AXI_stream/axis_direct_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_ex_status.sv +97 -0
- data/lib/axi/AXI_stream/axis_ex_status.sv.bk +97 -0
- data/lib/axi/AXI_stream/axis_filter.sv +0 -0
- data/lib/axi/AXI_stream/axis_full_to_data_c.sv +0 -0
- data/lib/axi/AXI_stream/axis_head_cut.sv +0 -0
- data/lib/axi/AXI_stream/axis_head_cut_verb.sv +0 -0
- data/lib/axi/AXI_stream/axis_head_cut_verc.rb +0 -0
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +6 -6
- data/lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv +0 -0
- data/lib/axi/AXI_stream/axis_insert_copy.rb +0 -0
- data/lib/axi/AXI_stream/axis_insert_copy.sv +0 -0
- data/lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv +0 -0
- data/lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv +0 -0
- data/lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_length_cut.sv +1 -1
- data/lib/axi/AXI_stream/axis_length_fill.sv +0 -0
- data/lib/axi/AXI_stream/axis_length_fill_verb.sv +195 -0
- data/lib/axi/AXI_stream/axis_length_split.sv +0 -0
- data/lib/axi/AXI_stream/axis_length_split_with_addr.sv +0 -0
- data/lib/axi/AXI_stream/axis_length_split_with_addr_A1.sv +128 -0
- data/lib/axi/AXI_stream/axis_length_split_with_user.sv +0 -0
- data/lib/axi/AXI_stream/axis_link_trigger.sv +0 -0
- data/lib/axi/AXI_stream/axis_master_empty.sv +0 -0
- data/lib/axi/AXI_stream/axis_mirror_to_master.sv +0 -0
- data/lib/axi/AXI_stream/axis_mirror_to_master_verb.sv +141 -0
- data/lib/axi/AXI_stream/axis_mirrors.sv +0 -0
- data/lib/axi/AXI_stream/axis_orthogonal.sv +0 -0
- data/lib/axi/AXI_stream/axis_padding.rb +44 -0
- data/lib/axi/AXI_stream/axis_padding.sv +65 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.rb +0 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +0 -0
- data/lib/axi/AXI_stream/axis_ram_buffer.sv +0 -0
- data/lib/axi/AXI_stream/axis_rom_contect.rb +0 -0
- data/lib/axi/AXI_stream/axis_rom_contect.sv +0 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +0 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +0 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.rb +0 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.sv +0 -0
- data/lib/axi/AXI_stream/axis_sim_slaver_model.rb +0 -0
- data/lib/axi/AXI_stream/axis_sim_verify_by_coe.sv +0 -0
- data/lib/axi/AXI_stream/axis_slaver_empty.sv +0 -0
- data/lib/axi/AXI_stream/axis_slaver_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_slaver_pipe_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_slaver_vector_empty.sv +0 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.rb +0 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +3 -3
- data/lib/axi/AXI_stream/axis_to_axi4_or_lite.rb +0 -0
- data/lib/axi/AXI_stream/axis_to_axi4_or_lite.sv +0 -0
- data/lib/axi/AXI_stream/axis_to_data_inf.sv +0 -0
- data/lib/axi/AXI_stream/axis_to_lite_rd.sv +0 -0
- data/lib/axi/AXI_stream/axis_to_lite_wr.sv +0 -0
- data/lib/axi/AXI_stream/axis_uncompress.sv +0 -0
- data/lib/axi/AXI_stream/axis_uncompress_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_uncompress_verb.rb +0 -0
- data/lib/axi/AXI_stream/axis_uncompress_verb.sv +0 -0
- data/lib/axi/AXI_stream/axis_valve.sv +0 -0
- data/lib/axi/AXI_stream/axis_valve_with_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_vector_master_empty.rb +0 -0
- data/lib/axi/AXI_stream/axis_vector_master_empty.sv +0 -0
- data/lib/axi/AXI_stream/axis_vector_slaver_empty.rb +0 -0
- data/lib/axi/AXI_stream/axis_vector_slaver_empty.sv +0 -0
- data/lib/axi/AXI_stream/check_stream_crc.sv +0 -0
- data/lib/axi/AXI_stream/data_c_to_axis_full.sv +0 -0
- data/lib/axi/AXI_stream/data_to_axis_inf.sv +0 -0
- data/lib/axi/AXI_stream/data_to_axis_inf_A1.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_combin.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_convert.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_destruct.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv +0 -0
- data/lib/axi/AXI_stream/gen_big_field_table.sv +0 -0
- data/lib/axi/AXI_stream/gen_common_frame_table.sv +0 -0
- data/lib/axi/AXI_stream/gen_common_frame_table_bind_tuser.sv +0 -0
- data/lib/axi/AXI_stream/gen_origin_axis.sv +0 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A1.sv +0 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A2.sv +0 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A3.sv +0 -0
- data/lib/axi/AXI_stream/gen_simple_axis.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv +8 -5
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo_verb.sv +9 -7
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1F.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_verb.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_with_info.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +5 -4
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo_A1.sv +221 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_wide_fifo.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep.sv +0 -0
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- data/lib/tdl/Logic/clock_rst_verb_auto.rb +0 -0
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- data/lib/tdl/SDL/axi4/axi4_data_combin_aflag_pipe_sdl.rb +0 -0
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- data/lib/tdl/SDL/axi4/axi4_partition_wr_OD_sdl.rb +0 -0
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- data/lib/tdl/SDL/axi4/axi4_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_pipe_verb_sdl.rb +0 -0
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- data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_burst_track_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A2_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_packet_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_pipe_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_aux_bind_data_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_batch_gen_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_without_resp_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_burst_track_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_mix_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_packet_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_pipe_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi_stream_add_addr_len_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi_stream_to_axi4_wr_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/data_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/data_destruct_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/feed_check_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/full_axi4_to_axis_partition_wr_rd_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/full_axi4_to_axis_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/id_record_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/idata_pool_axi4_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_A2_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odd_width_convert_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odd_width_convert_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/simple_data_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/simple_data_pipe_slaver_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable.rb +0 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_comptable.rb +0 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_comptable_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_convert_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_convert_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_destruct_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_destruct_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_35bit_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_36_71bit_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_with_keep_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_96_143bit_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_B1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_mirror_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A2_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_bind_tuser_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_noaddr_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_with_addr_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_auto_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_cache_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_fifo_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1E_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_with_info_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_partition_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_partition_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_wide_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_streams_combin_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_streams_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_streams_scaler_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_streams_scaler_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_append_A1_sdl.rb +0 -0
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- data/lib/tdl/SDL/axistream/axis_base_pipe_sdl.rb +0 -0
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- data/lib/tdl/SDL/axistream/axis_connect_pipe_right_shift_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_sdl.rb +0 -0
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- data/lib/tdl/SDL/axistream/axis_ex_status_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_filter_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_full_to_data_c_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_head_cut_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_inct_s2m_with_flag_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_intc_M2S_with_addr_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_intc_S2M_with_addr_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_interconnect_S2M_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_cut_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_fill_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_split_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_split_with_addr_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_split_writh_user_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_link_trigger_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_master_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_mirror_to_master_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_mirrors_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_orthogonal_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_ram_buffer_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_slaver_empty_sdl.rb +0 -0
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- data/lib/tdl/SDL/axistream/axis_slaver_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_slaver_vector_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_to_data_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_to_lite_rd_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_to_lite_wr_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_uncompress_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_uncompress_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_valve_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_valve_with_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_combin_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_convert_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_destruct_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_destruct_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/check_stream_crc_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/data_c_to_axis_full_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/data_to_axis_inf_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/data_to_axis_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_big_field_table_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_common_frame_table_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_origin_axis_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_origin_axis_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_simple_axis_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_A1_sdl.rb +0 -0
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- data/lib/tdl/SDL/axistream/parse_big_field_table_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/stream_crc_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/vcs_axis_comptable.rb +0 -0
- data/lib/tdl/SDL/axistream/vcs_axis_comptable_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_bind_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_cache_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_direct_mirror_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_direct_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_intc_M2S_force_robin_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_bind_data_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_right_shift_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_latency_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_scaler_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_scaler_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_tmp_cache_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_condition_mirror_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_condition_valve_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_connect_pipe_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_connect_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_A2B_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_B2A_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_M2S_with_addr_and_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_M2S_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_with_lazy_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_pipe_condition_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_cross_clk_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_force_addr_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_noaddr_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_with_id_noaddr_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_planer_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_planer_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_ticktock_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_intc_M2S_force_robin_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_mirrors_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_A2_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_combin_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_scaler_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_uncompress_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_valve_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/datainf_c_master_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/datainf_c_slaver_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/datainf_master_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/datainf_slaver_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/latency_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/next_prio_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/part_data_pair_map_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/trigger_ready_ctrl_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/common_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/common_stack_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/independent_clock_fifo_a1_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/independent_clock_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/independent_stack_sdl.rb +0 -0
- data/lib/tdl/SDL/path_lib.rb +0 -0
- data/lib/tdl/SDL/vcs_axi4_comptable.rb +0 -0
- data/lib/tdl/SDL/vcs_axis_comptable.rb +0 -0
- data/lib/tdl/SDL/vcs_data_c_comptable.rb +0 -0
- data/lib/tdl/VideoInf/simple_video_gen.rb +0 -0
- data/lib/tdl/VideoInf/video_from_axi4.rb +0 -0
- data/lib/tdl/VideoInf/video_lib.rb +0 -0
- data/lib/tdl/VideoInf/video_stream_2_axi_stream.rb +0 -0
- data/lib/tdl/VideoInf/video_to_axi4.rb +0 -0
- data/lib/tdl/auto_script/auto_gen_tdl.rb +0 -0
- data/lib/tdl/auto_script/autogensdl.rb +0 -0
- data/lib/tdl/auto_script/autogentdl_a2.rb +0 -0
- data/lib/tdl/auto_script/import_hdl.rb +0 -0
- data/lib/tdl/auto_script/import_sdl.rb +0 -0
- data/lib/tdl/auto_script/test_autogensdl.rb +0 -0
- data/lib/tdl/auto_script/tmp.rb +0 -0
- data/lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_direct.rb +0 -0
- data/lib/tdl/axi4/axi4_direct_A1_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_direct_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_direct_verb_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +24 -10
- data/lib/tdl/axi4/axi4_lib.rb +0 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_A1_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_verb_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_packet_fifo_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_pipe_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_pipe_verb_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_rd_auxiliary_gen_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_wr_auxiliary_gen_without_resp_auto.rb +0 -0
- data/lib/tdl/axi4/axis_to_axi4_wr_auto.rb +0 -0
- data/lib/tdl/axi4/bak/__axi4_wr_auxiliary_gen_without_resp.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_combin_wr_rd_batch_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_data_convert.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_direct_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_direct_verb_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_interconnect.rb.bak +0 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_A1_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_verb_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_packet_fifo.rb.bak +0 -0
- data/lib/tdl/axi4/bak/axi4_packet_fifo_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_partition_od.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_pipe_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_wr_auxiliary_gen_without_resp_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axis_to_axi4_wr_auto.rb +0 -0
- data/lib/tdl/axi4/bak/ddr3.rb +0 -0
- data/lib/tdl/axi4/bak/idata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi4/bak/odata_pool_axi4_A1_auto.rb +0 -0
- data/lib/tdl/axi4/bak/odata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi4/idata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi4/odata_pool_axi4_A1_auto.rb +0 -0
- data/lib/tdl/axi4/odata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi4/wide_axis_to_axi4_wr.rb +0 -0
- data/lib/tdl/axi4/wide_axis_to_axi4_wr_auto.rb +0 -0
- data/lib/tdl/axi_lite/axi_lite_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_lite/axi_lite_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_lite/bak/axi_lite_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_lite/bak/axi_lite_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_lite/bak/jtag_to_axilite_wrapper_auto.rb +0 -0
- data/lib/tdl/axi_lite/jtag_to_axilite_wrapper_auto.rb +0 -0
- data/lib/tdl/axi_lite/lite_cmd.rb +0 -0
- data/lib/tdl/axi_lite/prj_lib.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_35bit_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_72_95bit_with_keep_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_B1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_mirror_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_verb_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_A1.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_bind_tuser_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_auto_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_with_keep.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_lib.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_long_cache_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_long_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_long_fifo_verb_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_packet_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_packet_fifo_with_info_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_partition_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_partition_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_wide_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_streams_combin_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_streams_combin_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_streams_scaler_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_streams_scaler_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_append_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_append_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_combin_with_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_connect_pipe_A1.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_connect_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_connect_pipe_with_info_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_direct_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_filter_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_full_to_data_c_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_head_cut_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_length_fill_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_length_split_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_length_split_with_addr_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_length_split_writh_user_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_link_trigger_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_mirror_to_master_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_mirrors_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_padding.rb +44 -0
- data/lib/tdl/axi_stream/axis_pkt_fifo_filter_keep_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_pkt_fifo_filter_keep_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_ram_buffer_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_slaver_pipe_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_slaver_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_to_axi4_or_lite_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_to_data_inf_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_to_lite_rd_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_to_lite_wr_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_uncompress_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_valve_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_valve_with_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_combin_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_combin_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_convert_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_destruct_A1.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_destruct_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/__axi_stream_interconnect_S2M.rb +0 -0
- data/lib/tdl/axi_stream/bak/_axis_mirrors.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi4_to_native_for_ddr_ip_verb_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_S2M.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_35bit_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_72_95bit_with_keep_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_B1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_mirror_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_verb_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_interconnect_S2M_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_interconnect_S2M_with_keep.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_long_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_packet_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_packet_fifo_with_info_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_partition_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_partition_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_streams_combin_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_streams_scaler.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_streams_scaler_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_append_A1.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_append_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_append_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_combin_with_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe.rb.bak +0 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe_A1.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe_with_info_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_direct_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_filter_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_length_fill_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_length_split_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_length_split_with_addr_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_mirrors_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_pkt_fifo_filter_keep_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_ram_buffer_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_slaver_pipe_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_slaver_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_to_axi4_wr_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_to_data_inf_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_uncompress_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_valve_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_valve_with_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_width_combin_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_width_convert_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_width_destruct_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_wrapper_oled_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/check_stream_crc_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/data_to_axis_inf_A1.rb +0 -0
- data/lib/tdl/axi_stream/bak/data_to_axis_inf_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/data_to_axis_inf_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/datainf_c_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/datainf_c_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/datainf_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/datainf_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/dynamic_port_cfg_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/dynnamic_addr_cfg_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/gen_big_field_table_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/gen_origin_axis_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/gen_simple_axis_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/idata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/parse_big_field_table_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/parse_big_field_table_A2_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/parse_big_field_table_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/part_data_pair_map_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/simple_video_gen_A2.rb +0 -0
- data/lib/tdl/axi_stream/bak/simple_video_gen_A2_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/stream_crc_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/udp_server_bfm_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/udp_server_ctrl_bfm_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/video_to_VDMA.rb +0 -0
- data/lib/tdl/axi_stream/bak/video_to_VDMA_auto.rb +0 -0
- data/lib/tdl/axi_stream/check_stream_crc_auto.rb +0 -0
- data/lib/tdl/axi_stream/data_c_to_axis_full_auto.rb +0 -0
- data/lib/tdl/axi_stream/data_to_axis_inf_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/data_to_axis_inf_auto.rb +0 -0
- data/lib/tdl/axi_stream/gen_big_field_table_auto.rb +0 -0
- data/lib/tdl/axi_stream/gen_origin_axis_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/gen_origin_axis_auto.rb +0 -0
- data/lib/tdl/axi_stream/gen_simple_axis_auto.rb +0 -0
- data/lib/tdl/axi_stream/parse_big_field_table_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/parse_big_field_table_A2_auto.rb +0 -0
- data/lib/tdl/axi_stream/parse_big_field_table_auto.rb +0 -0
- data/lib/tdl/axi_stream/stream_crc_auto.rb +0 -0
- data/lib/tdl/basefunc.rb +0 -0
- data/lib/tdl/bfm/axi4_illegal_bfm.rb +0 -0
- data/lib/tdl/bfm/axi_stream/axi_stream_bfm.rb +0 -0
- data/lib/tdl/bfm/axi_stream/axis_bfm_exp.yml +0 -0
- data/lib/tdl/bfm/axi_stream/axis_bfm_module_build.rb +0 -0
- data/lib/tdl/bfm/axi_stream/axis_bfm_parse.rb +0 -0
- data/lib/tdl/bfm/axi_stream/axis_slice_to_logic.rb +0 -0
- data/lib/tdl/bfm/bfm_lib.rb +0 -0
- data/lib/tdl/bfm/logic_initial_block.rb +0 -0
- data/lib/tdl/cfg.yml +0 -0
- data/lib/tdl/class_hdl/hdl_always_comb.rb +0 -0
- data/lib/tdl/class_hdl/hdl_always_ff.rb +0 -0
- data/lib/tdl/class_hdl/hdl_assign.rb +0 -0
- data/lib/tdl/class_hdl/hdl_block_ifelse.rb +0 -0
- data/lib/tdl/class_hdl/hdl_data.rb +0 -0
- data/lib/tdl/class_hdl/hdl_ex_defarraychain.rb +0 -0
- data/lib/tdl/class_hdl/hdl_foreach.rb +0 -0
- data/lib/tdl/class_hdl/hdl_function.rb +0 -0
- data/lib/tdl/class_hdl/hdl_generate.rb +0 -0
- data/lib/tdl/class_hdl/hdl_initial.rb +0 -0
- data/lib/tdl/class_hdl/hdl_module_def.rb +16 -0
- data/lib/tdl/class_hdl/hdl_package.rb +0 -0
- data/lib/tdl/class_hdl/hdl_parameter.rb +0 -0
- data/lib/tdl/class_hdl/hdl_random.rb +0 -0
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +18 -1
- data/lib/tdl/class_hdl/hdl_struct.rb +0 -0
- data/lib/tdl/class_hdl/hdl_verify.rb +0 -0
- data/lib/tdl/data_inf/_data_mirrors.rb +0 -0
- data/lib/tdl/data_inf/bak/_data_mirrors.rb +0 -0
- data/lib/tdl/data_inf/bak/common_fifo_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_bind_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_c_direct_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_c_direct_mirror_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_c_tmp_cache_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_condition_mirror_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_condition_valve_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_connect_pipe.rb +0 -0
- data/lib/tdl/data_inf/bak/data_connect_pipe_inf_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_c_interconnect.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_c_pipe_condition_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_cross_clk.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_interconnect.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_planer.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_ticktack.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_ticktock_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_mirrors_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_mirrors_verb.sv_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_uncompress_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_valve_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/datainf_c_master_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/datainf_c_slaver_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/datainf_master_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/datainf_slaver_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/independent_clock_fifo_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/part_data_pair_map_auto.rb +0 -0
- data/lib/tdl/data_inf/common_fifo_auto.rb +0 -0
- data/lib/tdl/data_inf/data_bind_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_cache_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_direct_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_direct_mirror_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_interconnect.rb +0 -0
- data/lib/tdl/data_inf/data_c_pipe_force_vld_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_pipe_inf_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_pipe_intc_M2S_verc_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_tmp_cache_auto.rb +0 -0
- data/lib/tdl/data_inf/data_condition_mirror_auto.rb +0 -0
- data/lib/tdl/data_inf/data_condition_valve_auto.rb +0 -0
- data/lib/tdl/data_inf/data_connect_pipe_inf_auto.rb +0 -0
- data/lib/tdl/data_inf/data_inf_c_pipe_condition_auto.rb +0 -0
- data/lib/tdl/data_inf/data_mirrors_auto.rb +0 -0
- data/lib/tdl/data_inf/data_mirrors_verb.sv_auto.rb +0 -0
- data/lib/tdl/data_inf/data_uncompress_auto.rb +0 -0
- data/lib/tdl/data_inf/data_valve_auto.rb +0 -0
- data/lib/tdl/data_inf/datainf_c_master_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/datainf_c_slaver_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/datainf_master_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/datainf_slaver_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/independent_clock_fifo_auto.rb +0 -0
- data/lib/tdl/data_inf/part_data_pair_map_auto.rb +0 -0
- data/lib/tdl/data_inf/path_lib.rb +0 -0
- data/lib/tdl/elements/Reset.rb +0 -0
- data/lib/tdl/elements/axi4.rb +0 -0
- data/lib/tdl/elements/axi_lite.rb +0 -0
- data/lib/tdl/elements/axi_stream.rb +0 -0
- data/lib/tdl/elements/clock.rb +0 -0
- data/lib/tdl/elements/common_configure_reg.rb +0 -0
- data/lib/tdl/elements/data_inf.rb +0 -0
- data/lib/tdl/elements/logic.rb +0 -2
- data/lib/tdl/elements/mail_box.rb +0 -0
- data/lib/tdl/elements/originclass.rb +0 -0
- data/lib/tdl/elements/parameter.rb +0 -0
- data/lib/tdl/elements/track_inf.rb +0 -0
- data/lib/tdl/elements/videoinf.rb +0 -0
- data/lib/tdl/examples/10_random/exp_random.rb +0 -0
- data/lib/tdl/examples/10_random/exp_random.sv +0 -0
- data/lib/tdl/examples/11_logic_latency/test_logic_latency.rb +0 -0
- data/lib/tdl/examples/11_logic_latency/test_logic_latency.sv +0 -0
- data/lib/tdl/examples/11_test_unit/dve.tcl +0 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +0 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +0 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit_constraints.xdc +0 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +0 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +0 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +0 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +0 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +0 -0
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +0 -0
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +0 -0
- data/lib/tdl/examples/11_test_unit/tu0.sv +0 -0
- data/lib/tdl/examples/11_test_unit/tu1.sv +0 -0
- data/lib/tdl/examples/1_define_module/example1.rb +0 -0
- data/lib/tdl/examples/1_define_module/exmple_md.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/always_comb.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/always_ff.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/case.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/foreach.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/function.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/generate.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/module_def.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/module_head_import_package.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/module_instance_test.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/package.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/package2.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/simple_assign.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/state_case.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/struct.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/struct_function.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_axi4_M2S.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_initial_assert.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_module_port.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_module_var.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/init_module.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/port_module.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_axi4_M2S.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/vcs_string.rb +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/hdl_test.sv +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/main.rb +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_test.rb +0 -0
- data/lib/tdl/examples/4_generate/example.rb +0 -0
- data/lib/tdl/examples/4_generate/test_generate.sv +0 -0
- data/lib/tdl/examples/5_logic_combin/login_combin.rb +0 -0
- data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +0 -0
- data/lib/tdl/examples/6_module_with_interface/example.rb +0 -0
- data/lib/tdl/examples/6_module_with_interface/example_interface.sv +0 -0
- data/lib/tdl/examples/6_module_with_interface/inf_collect.rb +0 -0
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +0 -0
- data/lib/tdl/examples/7_module_with_package/body_package.rb +0 -0
- data/lib/tdl/examples/7_module_with_package/body_package.sv +0 -0
- data/lib/tdl/examples/7_module_with_package/example_pkg.rb +0 -0
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +0 -0
- data/lib/tdl/examples/7_module_with_package/head_package.rb +0 -0
- data/lib/tdl/examples/7_module_with_package/head_package.sv +0 -0
- data/lib/tdl/examples/8_top_module/dve.tcl +0 -0
- data/lib/tdl/examples/8_top_module/example.rb +0 -0
- data/lib/tdl/examples/8_top_module/pins.yml +0 -0
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +0 -0
- data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +0 -0
- data/lib/tdl/examples/8_top_module/test_top.sv +26 -7
- data/lib/tdl/examples/8_top_module/test_top_constraints.xdc +8 -8
- data/lib/tdl/examples/8_top_module/test_top_sim.sv +7 -26
- data/lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv +0 -0
- data/lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb +0 -0
- data/lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/tu_ClockManage_test_clock_bb.sv +0 -0
- data/lib/tdl/examples/9_itegration/dve.tcl +0 -0
- data/lib/tdl/examples/9_itegration/pins.yml +0 -0
- data/lib/tdl/examples/9_itegration/tb_test_top.sv +0 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +0 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +1 -1
- data/lib/tdl/examples/9_itegration/test_top.sv +0 -0
- data/lib/tdl/examples/9_itegration/test_top_constraints.xdc +0 -0
- data/lib/tdl/examples/9_itegration/test_tttop.sv +0 -0
- data/lib/tdl/examples/9_itegration/test_tttop_constraints.xdc +0 -0
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +1 -1
- data/lib/tdl/examples/9_itegration/top.rb +2 -2
- data/lib/tdl/examples/readme.md +0 -0
- data/lib/tdl/exlib/axis_eth_ex.rb +0 -0
- data/lib/tdl/exlib/axis_verify.rb +0 -0
- data/lib/tdl/exlib/clock_reset_verify.rb +0 -0
- data/lib/tdl/exlib/common_cfg_reg_inf.rb +0 -0
- data/lib/tdl/exlib/constraints.rb +0 -0
- data/lib/tdl/exlib/constraints_verb.rb +4 -4
- data/lib/tdl/exlib/dve_tcl.rb +0 -0
- data/lib/tdl/exlib/element_class_vars.rb +0 -0
- data/lib/tdl/exlib/global_param.rb +0 -0
- data/lib/tdl/exlib/integral_test/bak/integral_test.rb +0 -0
- data/lib/tdl/exlib/integral_test/clock_itest.rb +0 -0
- data/lib/tdl/exlib/integral_test/diff_clock_itest.rb +0 -0
- data/lib/tdl/exlib/integral_test/io_itest.rb +0 -0
- data/lib/tdl/exlib/integral_test/reset_itest.rb +0 -0
- data/lib/tdl/exlib/integral_test/simple_logic_itest.rb +0 -0
- data/lib/tdl/exlib/itegration.rb +0 -0
- data/lib/tdl/exlib/itegration_test_unit.rb +0 -0
- data/lib/tdl/exlib/itegration_verb.rb +129 -13
- data/lib/tdl/exlib/logic_verify.rb +0 -0
- data/lib/tdl/exlib/parse_argv.rb +0 -0
- data/lib/tdl/exlib/sdlmodule_sim.bak.rb +0 -0
- data/lib/tdl/exlib/test_point.rb +4 -4
- data/lib/tdl/exlib/test_point.rb.bak +0 -0
- data/lib/tdl/global_scan.rb +0 -0
- data/lib/tdl/rebuild_ele/axi4.rb +0 -0
- data/lib/tdl/rebuild_ele/axi_lite.rb +0 -0
- data/lib/tdl/rebuild_ele/axi_stream.rb +0 -0
- data/lib/tdl/rebuild_ele/cm_ram_inf.sv +0 -0
- data/lib/tdl/rebuild_ele/cm_ram_inf_define.rb +0 -0
- data/lib/tdl/rebuild_ele/data_inf.rb +0 -0
- data/lib/tdl/rebuild_ele/data_inf_c.rb +0 -0
- data/lib/tdl/rebuild_ele/ele_base.rb +0 -0
- data/lib/tdl/rebuild_ele/readme.md +0 -0
- data/lib/tdl/sdlimplement/resource.yml +0 -0
- data/lib/tdl/sdlimplement/sdl_impl_module.rb +0 -0
- data/lib/tdl/sdlimplement/sdl_impl_param.rb +0 -0
- data/lib/tdl/sdlimplement/test.rb +0 -0
- data/lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb +0 -0
- data/lib/tdl/sdlmodule/generator_block_module.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodlule_path_db.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_head_logo.txt +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +3 -3
- data/lib/tdl/sdlmodule/sdlmodule_varible.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +0 -0
- data/lib/tdl/sdlmodule/techbench_module.rb +0 -0
- data/lib/tdl/sdlmodule/test_unit_module.rb +13 -3
- data/lib/tdl/sdlmodule/test_unit_module.rb.bak +0 -0
- data/lib/tdl/sdlmodule/top_module.rb +0 -0
- data/lib/tdl/sdlmodule/top_module.rb.bak +0 -0
- data/lib/tdl/tdl.rb +0 -0
- data/lib/tdl/tdlerror/tdlerror.rb +0 -0
- data/lib/tdl/testunit/test_all.rb +0 -0
- data/lib/tdl/testunit/test_array_chain.rb +0 -0
- data/lib/tdl/testunit/test_tmp.rb +0 -0
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@@ -60,13 +60,16 @@ class Axi4
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end
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def <<(*up_streams)
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require_shdl 'axi4_direct_algin_addr_step'
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unless respond_to? :axi4_direct_algin_addr_step
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up_streams.each do |up_stream|
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## e is a Vector
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if up_stream.is_a? Axi4
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if up_stream.dimension && up_stream.dimension[0].is_a?(Integer) && up_stream.dimension[0] > 1
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self.belong_to_module.instance_exec(self,up_stream) do |curr_axi4_inst,up_stream|
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_algin_addrs = up_stream.copy(
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dimension:up_stream.dimension)
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@@ -80,14 +83,16 @@ class Axi4
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80
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h.param.SLAVER_MODE up_stream.mode
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81
84
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h.param.MASTER_MODE up_stream.mode
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82
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h.port.axi_inf.slaver.slaver_inf up_stream[kk]
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83
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-
h.port.axi_inf.master.master_inf curr_axi4_inst.belong_to_module.signal("#{up_stream.inst_name}_algin_addr")[kk]
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86
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+
# h.port.axi_inf.master.master_inf curr_axi4_inst.belong_to_module.signal("#{up_stream.inst_name}_algin_addr")[kk]
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87
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+
h.port.axi_inf.master.master_inf _algin_addrs[kk]
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84
88
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end
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85
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end
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86
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-
curr_axi4_inst.old_append( signal("#{up_stream.inst_name}_algin_addr") )
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90
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+
# curr_axi4_inst.old_append( signal("#{up_stream.inst_name}_algin_addr") )
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91
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+
curr_axi4_inst.old_append( _algin_addrs )
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87
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end
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88
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else
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curr_axi4_inst = self
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90
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-
up_stream.copy(
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95
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+
up_stream_copy = up_stream.copy(
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91
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name: "#{up_stream.inst_name}_algin_addr",
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92
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addr_step: curr_axi4_inst.addr_step*up_stream.dsize/curr_axi4_inst.dsize)
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98
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@@ -98,11 +103,15 @@ class Axi4
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98
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h.param.MODE "#{up_stream.mode}_to_#{up_stream.mode}" #//ONLY_READ to BOTH,ONLY_WRITE to BOTH,BOTH to BOTH,BOTH to ONLY_READ,BOTH to ONLY_WRITE
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99
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h.param.SLAVER_MODE up_stream.mode
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100
105
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h.param.MASTER_MODE up_stream.mode
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106
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+
# puts h.origin.module_name
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107
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+
# puts h.port.axi_inf.slaver.origin.module_name
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108
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+
# puts h.inst_port_hash
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101
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h.port.axi_inf.slaver.slaver_inf up_stream
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102
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-
h.port.axi_inf.master.master_inf self.belong_to_module.signal("#{up_stream.inst_name}_algin_addr")
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103
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-
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110
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+
# h.port.axi_inf.master.master_inf self.belong_to_module.signal("#{up_stream.inst_name}_algin_addr")
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111
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+
h.port.axi_inf.master.master_inf up_stream_copy
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104
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end
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105
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-
curr_axi4_inst.old_append( self.belong_to_module.signal("#{up_stream.inst_name}_algin_addr") )
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113
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+
# curr_axi4_inst.old_append( self.belong_to_module.signal("#{up_stream.inst_name}_algin_addr") )
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114
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+
curr_axi4_inst.old_append( up_stream_copy )
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end
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else
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self.old_append(up_stream)
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@@ -239,12 +248,14 @@ class Axi4
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239
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TopModule.contain_hdl 'axi4_packet_fifo_B1.sv','axi4_rd_packet_fifo_A1.sv','axi4_wr_packet_fifo_A1.sv','axi_stream_packet_fifo_B1F.sv'
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240
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242
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-
belong_to_module.Instance(:axi4_long_to_axi4_wide_B1,"axi4_long_to_axi4_wide_B1_#{index}_inst") do |h|
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251
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+
belong_to_module.Instance(:axi4_long_to_axi4_wide_B1,"axi4_long_to_axi4_wide_B1_#{index}_#{globle_random_name_flag('rand')}_inst") do |h|
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243
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h[:PARTITION] = "ON"
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h[:PIPE] = (@interconnect_pipe ? "ON" : "OFF")
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h[:MODE] = "#{e.mode}_TO_#{new_master.mode}"
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h[:SLAVER_MODE] = e.mode
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h[:MASTER_MODE] = new_master.mode
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257
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+
# h[:MAX_DATA_LEN] = 2**(e.lsize+1)
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258
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+
h[:MAX_DATA_LEN] = 2**(self.lsize+1)
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248
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h[:slaver_inf] = e
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h[:master_inf] = new_master
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end
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@@ -270,6 +281,8 @@ class Axi4
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h[:MODE] = "#{e.mode}_to_#{new_master.mode}"
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h[:SLAVER_MODE] = e.mode
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272
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h[:MASTER_MODE] = new_master.mode
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284
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+
# h[:MAX_DATA_LEN] = 2**(e.lsize+1)
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285
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h[:MAX_DATA_LEN] = 2**(self.lsize+1)
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h[:slaver_inf] = e
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h[:master_inf] = new_master
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end
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@@ -397,7 +410,8 @@ class Axi4
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if @sub_num > 1
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398
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str =
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399
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"\naxi4_mix_interconnect_M2S #(
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400
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-
.NUM
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413
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.NUM (#{@sub_num}),
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414
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.MASTER_IDSIZE (#{self.idsize})
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401
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)interconnect_#{name}_inst(
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/* axi_inf.slaver */ .slaver (sub_axi_#{name}_inf), //[NUM-1:0],
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403
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/* axi_inf.master */ .master (#{name})
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data/lib/tdl/axi4/axi4_lib.rb
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data/lib/tdl/axi4/bak/ddr3.rb
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data/lib/tdl/axi_lite/prj_lib.rb
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@@ -0,0 +1,44 @@
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1
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TdlBuild.axis_padding(__dir__) do
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2
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parameter.NUM 8
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3
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port.axis.slaver - 'axis_in'
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4
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port.axis.master - 'axis_out'
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5
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6
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axis_in.clock_reset_taps('clock','rst_n')
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7
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8
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logic - 'padding'
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9
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logic[clog2(param.NUM+1)] - 'pad_cnt'
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10
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+
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11
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always_ff(posedge: clock) do
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12
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IF ~rst_n do
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padding <= 1.b0
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pad_cnt <= 0.A
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15
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end
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16
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ELSE do
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IF axis_in.vld_rdy_last do
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padding <= 1.b1
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end
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ELSE do
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padding <= pad_cnt > 0.A
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end
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IF axis_in.vld_rdy_last do
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pad_cnt <= param.NUM
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end
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27
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ELSE do
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28
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IF pad_cnt > 0.A do
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pad_cnt <= pad_cnt - 1.b1
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30
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end
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31
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ELSE do
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32
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pad_cnt <= 0.A
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33
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end
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34
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end
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35
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end
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36
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end
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37
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axis_valve.axis_valve_inst do |h|
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39
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h.input.button ~padding # //[1] OPEN ; [0] CLOSE
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40
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h.port.axis.slaver.axis_in axis_in
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h.port.axis.master.axis_out axis_out
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end
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43
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end
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