axi_tdl 0.2.5 → 0.2.10
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.github/workflows/gem-push.yml +21 -48
- data/.github/workflows/ruby.yml +1 -1
- data/lib/axi/AXI4/axi4_combin_wr_rd_batch.sv +0 -0
- data/lib/axi/AXI4/axi4_direct.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_A1.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_B1.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_algin_addr_step.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_direct_verc.sv +0 -0
- data/lib/axi/AXI4/axi4_dpram_cache.rb +0 -0
- data/lib/axi/AXI4/axi4_dpram_cache.sv +0 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide.sv +0 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_A1.sv +0 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_B1.sv +2 -1
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_track.sv +0 -0
- data/lib/axi/AXI4/axi4_long_to_axi4_wide_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_pipe.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_pipe_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_rd_pipe_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe.sv +0 -0
- data/lib/axi/AXI4/axi4_pipe/axi4_wr_pipe_verb.sv +0 -0
- data/lib/axi/AXI4/axi4_ram_cache.rb +0 -0
- data/lib/axi/AXI4/axi4_ram_cache.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_batch_gen.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A1.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_auxiliary_gen_A2.sv +0 -0
- data/lib/axi/AXI4/axi4_rd_burst_track.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_aux_bind_data.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_batch_gen.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_gen.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_auxiliary_gen_without_resp.sv +0 -0
- data/lib/axi/AXI4/axi4_wr_burst_track.sv +0 -0
- data/lib/axi/AXI4/axi_stream_add_addr_len.sv +0 -0
- data/lib/axi/AXI4/axi_stream_to_axi4_wr.sv +54 -8
- data/lib/axi/AXI4/axi_stream_to_axi4_wr_verb.sv.bak +0 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +0 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +0 -0
- data/lib/axi/AXI4/full_axi4_to_axis.sv +0 -0
- data/lib/axi/AXI4/full_axi4_to_axis_partition_wr_rd.sv +0 -0
- data/lib/axi/AXI4/id_record.sv +0 -0
- data/lib/axi/AXI4/idata_pool_axi4.sv +0 -0
- data/lib/axi/AXI4/interconnect/AXI4_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_mix_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S.sv.bak +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A1.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_rd_mix_interconnect_M2S_A2.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_interconnect_M2S_A1.sv +0 -0
- data/lib/axi/AXI4/interconnect/axi4_wr_mix_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI4/long_axi4_to_wide_axi4.sv.bak +0 -0
- data/lib/axi/AXI4/long_axis_to_axi4_wr.rb +0 -0
- data/lib/axi/AXI4/long_axis_to_axi4_wr.sv +1 -1
- data/lib/axi/AXI4/odata_pool_axi4.sv +0 -0
- data/lib/axi/AXI4/odata_pool_axi4_A1.sv +0 -0
- data/lib/axi/AXI4/odata_pool_axi4_A2.sv +0 -0
- data/lib/axi/AXI4/odata_pool_axi4_A3.sv +0 -0
- data/lib/axi/AXI4/odata_pool_axi4_A4.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_B1.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_packet_fifo_verb.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_rd_packet_fifo_A1.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo.sv +0 -0
- data/lib/axi/AXI4/packet_fifo/axi4_wr_packet_fifo_A1.sv +12 -4
- data/lib/axi/AXI4/packet_merge/axi4_merge.sv +0 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge_rd.sv +0 -0
- data/lib/axi/AXI4/packet_merge/axi4_merge_wr.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_OD.sv +3 -2
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_OD.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.rb +16 -7
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +13 -9
- data/lib/axi/AXI4/packet_partition/axi4_partition_wr.sv +0 -0
- data/lib/axi/AXI4/packet_partition/axi4_partition_wr_OD.sv +11 -10
- data/lib/axi/AXI4/packet_partition/data_inf_partition.rb +0 -0
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
- data/lib/axi/AXI4/packet_partition/data_inf_partition_A1.rb +298 -0
- data/lib/axi/AXI4/packet_partition/data_inf_partition_A1.sv +316 -0
- data/lib/axi/AXI4/vcs_axi4_array_comptable.sv +0 -0
- data/lib/axi/AXI4/vcs_axi4_comptable.sv +0 -0
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb +0 -0
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.rb.bk +150 -0
- data/lib/axi/AXI4/wide_axis_to_axi4_wr.sv +2 -2
- data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe.sv +0 -0
- data/lib/axi/AXI4/width_convert/axi4_data_combin_aflag_pipe_A1.sv +0 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert.sv +0 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert_A1.sv +0 -0
- data/lib/axi/AXI4/width_convert/axi4_data_convert_verb.sv +0 -0
- data/lib/axi/AXI4/width_convert/data_combin.sv +0 -0
- data/lib/axi/AXI4/width_convert/data_combin.sv.bak +0 -0
- data/lib/axi/AXI4/width_convert/data_destruct.sv +0 -0
- data/lib/axi/AXI4/width_convert/feed_check.sv +0 -0
- data/lib/axi/AXI4/width_convert/len_convert.sv.bak +0 -0
- data/lib/axi/AXI4/width_convert/odd_width_convert.sv +0 -0
- data/lib/axi/AXI4/width_convert/odd_width_convert_verb.sv +0 -0
- data/lib/axi/AXI4/width_convert/simple_data_pipe.sv +0 -0
- data/lib/axi/AXI4/width_convert/simple_data_pipe_slaver.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_combin.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_convert.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_convert_verb.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_destruct.sv +0 -0
- data/lib/axi/AXI4/width_convert/width_destruct_A1.sv +0 -0
- data/lib/axi/AXI_BFM/AXI_BFM_PKG.sv +0 -0
- data/lib/axi/AXI_BFM/Data_C_BFM_PKG.sv +0 -0
- data/lib/axi/AXI_BFM/axi4_error_chk.sv +0 -0
- data/lib/axi/AXI_BFM/axi4_illegal_bfm_pkg.sv +0 -0
- data/lib/axi/AXI_BFM/axi_lite_master.sv +0 -0
- data/lib/axi/AXI_BFM/axi_lite_tb.sv +0 -0
- data/lib/axi/AXI_BFM/axi_master.sv +0 -0
- data/lib/axi/AXI_BFM/axi_mirror.sv +0 -0
- data/lib/axi/AXI_BFM/axi_mm_tb.sv +0 -0
- data/lib/axi/AXI_BFM/axi_slaver.sv.bak +0 -0
- data/lib/axi/AXI_BFM/axistreambfm.sv +0 -0
- data/lib/axi/AXI_Lite/axi4_to_lite.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_configure.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_configure_inf2.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_configure_verb.sv.bck +0 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv +4 -5
- data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M.sv.bak +0 -0
- data/lib/axi/AXI_Lite/axi_lite_interconnect_S2M_verb.sv +322 -0
- data/lib/axi/AXI_Lite/axi_lite_master_empty.sv +0 -0
- data/lib/axi/AXI_Lite/axi_lite_slaver_empty.sv +0 -0
- data/lib/axi/AXI_Lite/axil_direct.sv +0 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv +0 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/common_configure_reg_interface.sv.bak +0 -0
- data/lib/axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv +0 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl.sv +0 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_C1.sv +0 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verb.sv +0 -0
- data/lib/axi/AXI_Lite/gen_axi_lite_ctrl_verc.sv +0 -0
- data/lib/axi/AXI_Lite/wr_lite_to_axis.sv +0 -0
- data/lib/axi/AXI_Lite/wr_lite_to_axis.sv.bak +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A1.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_A2.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_bind_tuser.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_cpVCS.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_noaddr.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_M2S_with_addr.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_auto.sv +26 -5
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_info.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_keep.sv.bak +0 -0
- data/lib/axi/AXI_stream/axi_stream_latency.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_packet_fifo_with_info.sv.bak +0 -0
- data/lib/axi/AXI_stream/axi_stream_partition.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_partition_A1.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_planer.sv +0 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.rb +0 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +26 -26
- data/lib/axi/AXI_stream/axi_streams_combin.sv +0 -0
- data/lib/axi/AXI_stream/axi_streams_combin_A1.sv +0 -0
- data/lib/axi/AXI_stream/axi_streams_scaler.sv +0 -0
- data/lib/axi/AXI_stream/axi_streams_scaler_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_append.sv +0 -0
- data/lib/axi/AXI_stream/axis_append_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_base_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_combin_with_fifo.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_A1.sv.bak +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_left_shift.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_right_shift.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_right_shift_verb.sv +0 -0
- data/lib/axi/AXI_stream/axis_connect_pipe_with_info.sv +0 -0
- data/lib/axi/AXI_stream/axis_direct.sv +0 -0
- data/lib/axi/AXI_stream/axis_direct_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_ex_status.sv +97 -0
- data/lib/axi/AXI_stream/axis_ex_status.sv.bk +97 -0
- data/lib/axi/AXI_stream/axis_filter.sv +0 -0
- data/lib/axi/AXI_stream/axis_full_to_data_c.sv +0 -0
- data/lib/axi/AXI_stream/axis_head_cut.sv +0 -0
- data/lib/axi/AXI_stream/axis_head_cut_verb.sv +0 -0
- data/lib/axi/AXI_stream/axis_head_cut_verc.rb +0 -0
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +6 -6
- data/lib/axi/AXI_stream/axis_inct_s2m_with_flag.sv +0 -0
- data/lib/axi/AXI_stream/axis_insert_copy.rb +0 -0
- data/lib/axi/AXI_stream/axis_insert_copy.sv +0 -0
- data/lib/axi/AXI_stream/axis_intc_M2S_with_addr_inf.sv +0 -0
- data/lib/axi/AXI_stream/axis_intc_S2M_with_addr_inf.sv +0 -0
- data/lib/axi/AXI_stream/axis_interconnect_S2M_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_length_cut.sv +1 -1
- data/lib/axi/AXI_stream/axis_length_fill.sv +0 -0
- data/lib/axi/AXI_stream/axis_length_fill_verb.sv +195 -0
- data/lib/axi/AXI_stream/axis_length_split.sv +0 -0
- data/lib/axi/AXI_stream/axis_length_split_with_addr.sv +0 -0
- data/lib/axi/AXI_stream/axis_length_split_with_addr_A1.sv +128 -0
- data/lib/axi/AXI_stream/axis_length_split_with_user.sv +0 -0
- data/lib/axi/AXI_stream/axis_link_trigger.sv +0 -0
- data/lib/axi/AXI_stream/axis_master_empty.sv +0 -0
- data/lib/axi/AXI_stream/axis_mirror_to_master.sv +0 -0
- data/lib/axi/AXI_stream/axis_mirror_to_master_verb.sv +141 -0
- data/lib/axi/AXI_stream/axis_mirrors.sv +0 -0
- data/lib/axi/AXI_stream/axis_orthogonal.sv +0 -0
- data/lib/axi/AXI_stream/axis_padding.rb +44 -0
- data/lib/axi/AXI_stream/axis_padding.sv +65 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.rb +0 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +0 -0
- data/lib/axi/AXI_stream/axis_ram_buffer.sv +0 -0
- data/lib/axi/AXI_stream/axis_rom_contect.rb +0 -0
- data/lib/axi/AXI_stream/axis_rom_contect.sv +0 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.rb +0 -0
- data/lib/axi/AXI_stream/axis_rom_contect_sim.sv +0 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.rb +0 -0
- data/lib/axi/AXI_stream/axis_sim_master_model.sv +0 -0
- data/lib/axi/AXI_stream/axis_sim_slaver_model.rb +0 -0
- data/lib/axi/AXI_stream/axis_sim_verify_by_coe.sv +0 -0
- data/lib/axi/AXI_stream/axis_slaver_empty.sv +0 -0
- data/lib/axi/AXI_stream/axis_slaver_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_slaver_pipe_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_slaver_vector_empty.sv +0 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.rb +0 -0
- data/lib/axi/AXI_stream/axis_split_channel_verb.sv +3 -3
- data/lib/axi/AXI_stream/axis_to_axi4_or_lite.rb +0 -0
- data/lib/axi/AXI_stream/axis_to_axi4_or_lite.sv +0 -0
- data/lib/axi/AXI_stream/axis_to_data_inf.sv +0 -0
- data/lib/axi/AXI_stream/axis_to_lite_rd.sv +0 -0
- data/lib/axi/AXI_stream/axis_to_lite_wr.sv +0 -0
- data/lib/axi/AXI_stream/axis_uncompress.sv +0 -0
- data/lib/axi/AXI_stream/axis_uncompress_A1.sv +0 -0
- data/lib/axi/AXI_stream/axis_uncompress_verb.rb +0 -0
- data/lib/axi/AXI_stream/axis_uncompress_verb.sv +0 -0
- data/lib/axi/AXI_stream/axis_valve.sv +0 -0
- data/lib/axi/AXI_stream/axis_valve_with_pipe.sv +0 -0
- data/lib/axi/AXI_stream/axis_vector_master_empty.rb +0 -0
- data/lib/axi/AXI_stream/axis_vector_master_empty.sv +0 -0
- data/lib/axi/AXI_stream/axis_vector_slaver_empty.rb +0 -0
- data/lib/axi/AXI_stream/axis_vector_slaver_empty.sv +0 -0
- data/lib/axi/AXI_stream/check_stream_crc.sv +0 -0
- data/lib/axi/AXI_stream/data_c_to_axis_full.sv +0 -0
- data/lib/axi/AXI_stream/data_to_axis_inf.sv +0 -0
- data/lib/axi/AXI_stream/data_to_axis_inf_A1.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_combin.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_combin_A1.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_convert.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_convert_verb.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_destruct.sv +0 -0
- data/lib/axi/AXI_stream/data_width/axis_width_destruct_A1.sv +0 -0
- data/lib/axi/AXI_stream/gen_big_field_table.sv +0 -0
- data/lib/axi/AXI_stream/gen_common_frame_table.sv +0 -0
- data/lib/axi/AXI_stream/gen_common_frame_table_bind_tuser.sv +0 -0
- data/lib/axi/AXI_stream/gen_origin_axis.sv +0 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A1.sv +0 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A2.sv +0 -0
- data/lib/axi/AXI_stream/gen_origin_axis_A3.sv +0 -0
- data/lib/axi/AXI_stream/gen_simple_axis.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo.sv +8 -5
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_long_fifo_verb.sv +9 -7
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1E.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_B1F.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_verb.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_fifo_with_info.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +5 -4
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo_A1.sv +221 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_wide_fifo.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep.sv +0 -0
- data/lib/axi/AXI_stream/packet_fifo/axis_pkt_fifo_filter_keep_A1.sv +0 -0
- data/lib/axi/AXI_stream/parse_big_field_table.sv +0 -0
- data/lib/axi/AXI_stream/parse_big_field_table_A1.sv +0 -0
- data/lib/axi/AXI_stream/parse_big_field_table_A2.sv +0 -0
- data/lib/axi/AXI_stream/parse_big_field_table_main.sv +0 -0
- data/lib/axi/AXI_stream/parse_big_field_table_mirror.sv +0 -0
- data/lib/axi/AXI_stream/parse_big_field_table_slaver.sv +162 -0
- data/lib/axi/AXI_stream/parse_big_field_table_verb.sv +0 -0
- data/lib/axi/AXI_stream/parse_common_frame_table.sv +0 -0
- data/lib/axi/AXI_stream/parse_common_frame_table_A1.sv +0 -0
- data/lib/axi/AXI_stream/parse_common_frame_table_A2.sv +0 -0
- data/lib/axi/AXI_stream/parse_common_frame_table_slaver.sv +546 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache.sv +0 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_35bit.sv +0 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_36_71bit.sv +1 -1
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit.sv +0 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_72_95bit_with_keep.sv +0 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_96_143bit.sv +0 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_A1.sv +0 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_B1.sv +0 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_compact_verb.sv +58 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_mirror.sv +0 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_cache_verb.sv +0 -0
- data/lib/axi/AXI_stream/stream_cache/axi_stream_long_cache.sv +0 -0
- data/lib/axi/AXI_stream/stream_crc.sv +0 -0
- data/lib/axi/AXI_stream/vcs_axis_comptable.sv +0 -0
- data/lib/axi/LICENSE +0 -0
- data/lib/axi/ReadME.md +0 -0
- data/lib/axi/SIM/tb_axi4_partition_20201105.sv +0 -0
- data/lib/axi/SIM/tb_axis_bfm_0504.sv +0 -0
- data/lib/axi/SIM/tb_axis_partitiom_0929.sv +0 -0
- data/lib/axi/SIM/tb_axis_s2m_pipe_1023.sv +0 -0
- data/lib/axi/SIM/tb_axis_to_axi4_0925.sv +0 -0
- data/lib/axi/SIM/tb_data_c_m2s_inf_20200114.sv +0 -0
- data/lib/axi/SIM/tb_data_c_m2s_inf_20201103.sv +0 -0
- data/lib/axi/SIM/tb_data_c_pipe_inf_20180417.sv +0 -0
- data/lib/axi/SIM/tb_wide_axis_to_axi4_wr.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C1.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_C2.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_verb.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/axi4_to_native_for_ddr_ip_verc.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_native_to_axi4.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr3_ip_wrapper_sim.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_axi4_to_axis.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A1.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_A2.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_B1.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/ddr_native_fifo_verb.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/model_ddr_ip_app.sv +0 -0
- data/lib/axi/axi4_to_xilinx_ddr_native/tb_ddr3_ip_wrapper_sim.sv +0 -0
- data/lib/axi/cfg.yml +0 -0
- data/lib/axi/common/ClockSameDomain.sv +0 -0
- data/lib/axi/common/common_ram_sim_wrapper.rb +0 -0
- data/lib/axi/common/common_ram_sim_wrapper.sv +0 -0
- data/lib/axi/common/common_ram_wrapper.rb +0 -0
- data/lib/axi/common/common_ram_wrapper.sv +2 -2
- data/lib/axi/common/data_c_interface_dram.rb +0 -0
- data/lib/axi/common/data_c_interface_dram.sv +0 -0
- data/lib/axi/common/mem_format.coe +0 -0
- data/lib/axi/common/pipe_vld.sv +0 -0
- data/lib/axi/common/test_write_mem.sv +0 -0
- data/lib/axi/common/xilinx_hdl_dpram.sv +0 -0
- data/lib/axi/common/xilinx_hdl_dpram_sim.sv +0 -0
- data/lib/axi/common_fifo/common_fifo.sv +2 -1
- data/lib/axi/common_fifo/common_stack.sv +0 -0
- data/lib/axi/common_fifo/independent_clock_fifo.sv +0 -0
- data/lib/axi/common_fifo/independent_clock_fifo_a1.sv +0 -0
- data/lib/axi/common_fifo/independent_stack.sv +0 -0
- data/lib/axi/data_interface/data_connect_pipe.sv +0 -0
- data/lib/axi/data_interface/data_inf_A2B.sv +0 -0
- data/lib/axi/data_interface/data_inf_B2A.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_bind.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_cache.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_direct.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_direct_mirror.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_intc_M2S_force_robin.rb.bak +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_intc_M2S_force_robin.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_A1.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_left_shift.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_right_shift.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_inf_right_shift_verb.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_C1.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_C1_with_id.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_last.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_best_robin.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_robin.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_robin_with_id.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_id.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_latency.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.rb +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +13 -13
- data/lib/axi/data_interface/data_inf_c/data_c_scaler.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_sim_master_model.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_sim_slaver_model.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_c_tmp_cache.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_condition_mirror.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_condition_valve.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_connect_pipe_inf.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_M2S_with_addr_and_id.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_M2S_with_id.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_A1.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_intc_S2M_with_lazy.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_interconnect_M2S.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_pipe_condition.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_planer.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_inf_c_planer_A1.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_intc_M2S_force_robin.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_mirrors.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_mirrors_verb.sv.bak +0 -0
- data/lib/axi/data_interface/data_inf_c/data_uncompress.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/data_valve.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/logic_sim_model.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/next_prio.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/trigger_data_inf_c.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/trigger_data_inf_c_A1.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/trigger_ready_ctrl.sv +0 -0
- data/lib/axi/data_interface/data_inf_c/vcs_data_c_comptable.sv +0 -0
- data/lib/axi/data_interface/data_inf_cross_clk.sv +0 -0
- data/lib/axi/data_interface/data_inf_intc_M2S_force_addr_with_id.sv +0 -0
- data/lib/axi/data_interface/data_inf_intc_M2S_prio.sv +0 -0
- data/lib/axi/data_interface/data_inf_intc_M2S_prio_with_id.sv +0 -0
- data/lib/axi/data_interface/data_inf_interconnect_M2S_noaddr.sv +0 -0
- data/lib/axi/data_interface/data_inf_interconnect_M2S_with_id_noaddr.sv +0 -0
- data/lib/axi/data_interface/data_inf_planer.sv +0 -0
- data/lib/axi/data_interface/data_inf_planer_A1.sv +0 -0
- data/lib/axi/data_interface/data_inf_ticktock.sv +0 -0
- data/lib/axi/data_interface/data_interface.sv +0 -0
- data/lib/axi/data_interface/data_interface_pkg.sv +0 -0
- data/lib/axi/data_interface/data_pair_map.sv +0 -0
- data/lib/axi/data_interface/data_pair_map_A1.sv +0 -0
- data/lib/axi/data_interface/data_pair_map_A2.sv +0 -0
- data/lib/axi/data_interface/data_pipe_intc_M2S_addr.sv.bak +0 -0
- data/lib/axi/data_interface/data_pipe_interconnect.sv +0 -0
- data/lib/axi/data_interface/data_pipe_interconnect_M2S.sv +0 -0
- data/lib/axi/data_interface/data_pipe_interconnect_M2S.sv.bak1012 +0 -0
- data/lib/axi/data_interface/data_pipe_interconnect_M2S_A1.sv +0 -0
- data/lib/axi/data_interface/data_pipe_interconnect_M2S_verb.sv +0 -0
- data/lib/axi/data_interface/data_pipe_interconnect_M2S_verb.sv.bad_work +0 -0
- data/lib/axi/data_interface/data_pipe_interconnect_S2M.sv +0 -0
- data/lib/axi/data_interface/data_pipe_interconnect_S2M_A1.sv +0 -0
- data/lib/axi/data_interface/data_pipe_interconnect_S2M_verb.sv +0 -0
- data/lib/axi/data_interface/data_streams_combin.sv +0 -0
- data/lib/axi/data_interface/data_streams_combin_A1.sv +0 -0
- data/lib/axi/data_interface/data_streams_scaler.sv +0 -0
- data/lib/axi/data_interface/datainf_c_master_empty.sv +0 -0
- data/lib/axi/data_interface/datainf_c_slaver_empty.sv +0 -0
- data/lib/axi/data_interface/datainf_master_empty.sv +0 -0
- data/lib/axi/data_interface/datainf_slaver_empty.sv +0 -0
- data/lib/axi/data_interface/part_data_pair_map.sv +0 -0
- data/lib/axi/interface_define/axi_aux_inf.sv +0 -0
- data/lib/axi/interface_define/axi_inf.sv +0 -0
- data/lib/axi/interface_define/axi_inf_verb.sv +0 -0
- data/lib/axi/interface_define/axi_interface_instance.svo +0 -0
- data/lib/axi/interface_define/axi_lite_inf.sv +0 -0
- data/lib/axi/interface_define/axi_stream_inf.sv +0 -0
- data/lib/axi/interface_define/bak/axi_aux_inf.sv +0 -0
- data/lib/axi/interface_define/bak/axi_inf_verb.sv +0 -0
- data/lib/axi/interface_define/bak/axi_interface_instance.svo +0 -0
- data/lib/axi/interface_define/bak/microblaze_inf.sv +0 -0
- data/lib/axi/interface_define/bak/xilinx_axi4_to_axi4.sv +0 -0
- data/lib/axi/interface_define/bak/xilinx_lite_to_lite.sv +0 -0
- data/lib/axi/interface_define/lite_inf2_to_inf.sv +0 -0
- data/lib/axi/interface_define/xilinx_axi4_to_axi4.sv +0 -0
- data/lib/axi/interface_define/xilinx_lite_to_lite.sv +0 -0
- data/lib/axi/macro/RTL/define_macro.sv +0 -0
- data/lib/axi/macro/SIM/define_macro.sv +0 -0
- data/lib/axi/macro/axil_macro.sv +0 -0
- data/lib/axi/macro/bak/axi4_base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/axi_macro.sv +0 -0
- data/lib/axi/macro/bak/axis_base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/data_inf_base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/lite_inf_base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/standard_tcl.rb +0 -0
- data/lib/axi/macro/bak/system_macro.sv +0 -0
- data/lib/axi/macro/bak/tcl_axi4_base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/tcl_axis_base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/tcl_base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/tcl_data_inf_base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/tcl_lite_inf_base_files_add_to_vivado.tcl +0 -0
- data/lib/axi/macro/bak/tcl_tmp.tcl +0 -0
- data/lib/axi/macro/bak/tmp.tcl +0 -0
- data/lib/axi/platform_ip/fifo_10_18bit_long.sv +0 -0
- data/lib/axi/platform_ip/fifo_145_216bit_A1.sv +0 -0
- data/lib/axi/platform_ip/fifo_217_288bit_A1.sv +0 -0
- data/lib/axi/platform_ip/fifo_36bit.sv +0 -0
- data/lib/axi/platform_ip/fifo_36bit_A1.sv +0 -0
- data/lib/axi/platform_ip/fifo_36kb_long.sv +11 -5
- data/lib/axi/platform_ip/fifo_37_72bit.sv +0 -0
- data/lib/axi/platform_ip/fifo_505_576bit_A1.sv +0 -0
- data/lib/axi/platform_ip/fifo_73_96bit.sv +0 -0
- data/lib/axi/platform_ip/fifo_97_144bit.sv +0 -0
- data/lib/axi/platform_ip/fifo_97_144bit_A1.sv +0 -0
- data/lib/axi/platform_ip/fifo_ku.sv +0 -0
- data/lib/axi/platform_ip/fifo_ku.sv.bak +0 -0
- data/lib/axi/platform_ip/fifo_ku_18bit.sv +0 -0
- data/lib/axi/platform_ip/fifo_ku_36bit.sv +0 -0
- data/lib/axi/platform_ip/fifo_ku_36kb_long.sv +0 -0
- data/lib/axi/platform_ip/fifo_ku_xbit_8192.sv.bak +0 -0
- data/lib/axi/platform_ip/fifo_wr_rd_mark.sv +0 -0
- data/lib/axi/platform_ip/ku_long_fifo_4bit.sv +0 -0
- data/lib/axi/platform_ip/long_fifo.sv +0 -0
- data/lib/axi/platform_ip/long_fifo_4bit.sv +0 -0
- data/lib/axi/platform_ip/long_fifo_4bit_8192.sv +0 -0
- data/lib/axi/platform_ip/long_fifo_4bit_SL8192.sv +0 -0
- data/lib/axi/platform_ip/long_fifo_9bit_SL4096.sv.new +138 -0
- data/lib/axi/platform_ip/long_fifo_verb.sv +0 -0
- data/lib/axi/platform_ip/long_fifo_xbit.sv.new +132 -0
- data/lib/axi/platform_ip/long_fifo_xbit_SL.sv.new +147 -0
- data/lib/axi/platform_ip/wide_fifo.sv +0 -0
- data/lib/axi/platform_ip/wide_fifo_7series.sv +0 -0
- data/lib/axi/platform_ip/xilinx_fifo.sv +0 -0
- data/lib/axi/platform_ip/xilinx_fifo_A1.sv +0 -0
- data/lib/axi/platform_ip/xilinx_fifo_verb.sv +0 -0
- data/lib/axi/platform_ip/xilinx_fifo_verc.sv +0 -0
- data/lib/axi/platform_ip/xilinx_stream_packet_fifo_ip.sv +0 -0
- data/lib/axi/techbench/tb_axi_stream_split_channel.rb +0 -0
- data/lib/axi/techbench/tb_axi_stream_split_channel.sv +0 -0
- data/lib/axi/techbench/tb_axis_split_channel_verb.rb +0 -0
- data/lib/axi/techbench/tb_axis_split_channel_verb.sv +0 -0
- data/lib/axi/top/axi4_data_convert_2_20_tb.sv +0 -0
- data/lib/axi/top/axi4_data_convert_5_24_tb.sv +0 -0
- data/lib/axi/top/axi4_interconnnect_2_24_tb.sv +0 -0
- data/lib/axi/top/axi4_interconnnect_5_23_tb.sv +0 -0
- data/lib/axi/top/axi4_merge_tb_0331.sv +0 -0
- data/lib/axi/top/axi4_packet_fifo_2_28_tb.sv +0 -0
- data/lib/axi/top/axi4_partition_2_23_tb.sv +0 -0
- data/lib/axi/top/axi_stream_packet_fifo_2_28_tb.sv +0 -0
- data/lib/axi/top/axis_length_cut_2_28_tb.sv +0 -0
- data/lib/axi/top/axis_length_fill_8_18_tb.sv +0 -0
- data/lib/axi/top/common_fifo_2_27_tb.sv +0 -0
- data/lib/axi/top/data_convert_2_16_tb.sv +0 -0
- data/lib/axi/top/independent_fifo_2_27_tb.sv +0 -0
- data/lib/axi/top/long_to_wide_3_1_tb.sv +0 -0
- data/lib/axi/top/odd_width_convert_tb_420.sv +0 -0
- data/lib/axi/top/tb_axis_m2s_A1_0115.sv +0 -0
- data/lib/axi/top/tb_axis_width_combin_0913.sv +0 -0
- data/lib/axi/top/tb_axis_width_test_0914.sv +0 -0
- data/lib/axi/top/tb_data_c_inf_M2S_0823.sv +0 -0
- data/lib/axi/top/tb_data_c_inf_M2S_addr_0824.sv +0 -0
- data/lib/axi/top/tb_data_c_pipe_force_vld_1228.sv +0 -0
- data/lib/axi/top/tb_data_c_scaler_20180413.sv +0 -0
- data/lib/axi/top/tb_data_intc_S2M_0807.sv +0 -0
- data/lib/axi/top/tb_test_ku_fifo_0919.sv +0 -0
- data/lib/axi/top/width_convert_verb_tb_523.sv +0 -0
- data/lib/axi/video/video_stream_2_axi_stream.sv +0 -0
- data/lib/axi/video_interface/video_interface.sv +0 -0
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/axi_tdl.rb +3 -0
- data/lib/public_atom_module/CheckPClock.sv +0 -0
- data/lib/public_atom_module/LICENSE.md +0 -0
- data/lib/public_atom_module/altera_xilinx_always_block_sw.rb +0 -0
- data/lib/public_atom_module/bits_decode.sv +0 -0
- data/lib/public_atom_module/bits_decode_verb.sv +0 -0
- data/lib/public_atom_module/bits_decode_verb_sdl.rb +0 -0
- data/lib/public_atom_module/broaden.v +0 -0
- data/lib/public_atom_module/broaden_and_cross_clk.v +0 -0
- data/lib/public_atom_module/ceiling.v +0 -0
- data/lib/public_atom_module/ceiling_A1.v +0 -0
- data/lib/public_atom_module/clock_rst.sv +0 -0
- data/lib/public_atom_module/cross_clk_sync.v +0 -0
- data/lib/public_atom_module/edge_generator.v +0 -0
- data/lib/public_atom_module/flooring.v +0 -0
- data/lib/public_atom_module/latch_data.v +0 -0
- data/lib/public_atom_module/latency.v +0 -0
- data/lib/public_atom_module/latency_dynamic.v +0 -0
- data/lib/public_atom_module/latency_long.v +0 -0
- data/lib/public_atom_module/latency_verb.v +0 -0
- data/lib/public_atom_module/once_event.sv +0 -0
- data/lib/public_atom_module/pipe_reg.v +0 -0
- data/lib/public_atom_module/pipe_reg_2write_ports.v +0 -0
- data/lib/public_atom_module/sim/clock_rst_verb.sv +0 -0
- data/lib/public_atom_module/sim/clock_rst_verc.sv +0 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv +0 -0
- data/lib/public_atom_module/sim/latency_long_tb.sv.bak +0 -0
- data/lib/public_atom_module/sim_system_pkg.sv +0 -0
- data/lib/public_atom_module/synth_system_pkg.sv +0 -0
- data/lib/tdl/LICENSE +0 -0
- data/lib/tdl/Logic/Logic.tar.gz +0 -0
- data/lib/tdl/Logic/clock_rst_verb_auto.rb +0 -0
- data/lib/tdl/Logic/logic_edge.rb +0 -0
- data/lib/tdl/Logic/logic_latency.rb +0 -0
- data/lib/tdl/Logic/logic_main.rb +0 -0
- data/lib/tdl/Logic/logic_operator.rb.bak +0 -0
- data/lib/tdl/Logic/mdio_model_auto.rb +0 -0
- data/lib/tdl/Logic/path_lib.rb +0 -0
- data/lib/tdl/Logic/redefine_operator.rb +0 -0
- data/lib/tdl/ReadMe.md +0 -0
- data/lib/tdl/SDL/axi4/AXI4_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_combin_wr_rd_batch_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_data_combin_aflag_pipe_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_data_combin_aflag_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_data_convert_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_data_convert_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_direct_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_direct_B1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_direct_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_direct_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_direct_verc_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_track_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_long_to_axi4_wide_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_merge_rd_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_merge_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_merge_wr_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_mix_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_packet_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_partition_OD_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_partition_rd_OD_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_partition_rd_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_partition_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_partition_wr_OD_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_partition_wr_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_pipe_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_batch_gen_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_auxiliary_gen_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_burst_track_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_A2_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_mix_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_packet_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_rd_pipe_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_aux_bind_data_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_batch_gen_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_auxiliary_gen_without_resp_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_burst_track_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_mix_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_packet_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi4_wr_pipe_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi_stream_add_addr_len_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/axi_stream_to_axi4_wr_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/data_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/data_destruct_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/feed_check_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/full_axi4_to_axis_partition_wr_rd_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/full_axi4_to_axis_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/id_record_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/idata_pool_axi4_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_A2_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odata_pool_axi4_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odd_width_convert_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/odd_width_convert_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/simple_data_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/simple_data_pipe_slaver_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable.rb +0 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_array_comptable_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_comptable.rb +0 -0
- data/lib/tdl/SDL/axi4/vcs_axi4_comptable_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_convert_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_convert_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_destruct_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axi4/width_destruct_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_35bit_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_36_71bit_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_72_95bit_with_keep_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_96_143bit_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_B1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_mirror_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_cache_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_A2_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_bind_tuser_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_noaddr_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_M2S_with_addr_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_auto_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_interconnect_S2M_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_cache_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_long_fifo_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1E_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_B1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_fifo_with_info_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_partition_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_partition_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_stream_wide_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_streams_combin_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_streams_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_streams_scaler_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axi_streams_scaler_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_append_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_append_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_base_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_combin_with_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_right_shift_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_connect_pipe_with_info_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_direct_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_direct_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_ex_status_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_filter_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_full_to_data_c_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_head_cut_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_inct_s2m_with_flag_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_intc_M2S_with_addr_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_intc_S2M_with_addr_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_interconnect_S2M_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_cut_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_fill_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_split_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_split_with_addr_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_length_split_writh_user_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_link_trigger_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_master_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_mirror_to_master_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_mirrors_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_orthogonal_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_pkt_fifo_filter_keep_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_ram_buffer_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_slaver_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_slaver_pipe_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_slaver_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_slaver_vector_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_to_data_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_to_lite_rd_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_to_lite_wr_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_uncompress_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_uncompress_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_valve_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_valve_with_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_combin_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_convert_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_destruct_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/axis_width_destruct_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/check_stream_crc_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/data_c_to_axis_full_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/data_to_axis_inf_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/data_to_axis_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_big_field_table_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_common_frame_table_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_origin_axis_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_origin_axis_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/gen_simple_axis_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_A2_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/parse_big_field_table_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/stream_crc_sdl.rb +0 -0
- data/lib/tdl/SDL/axistream/vcs_axis_comptable.rb +0 -0
- data/lib/tdl/SDL/axistream/vcs_axis_comptable_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_bind_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_cache_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_direct_mirror_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_direct_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_intc_M2S_force_robin_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_bind_data_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_force_vld_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_right_shift_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_C1_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_intc_M2S_verc_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_pipe_latency_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_scaler_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_scaler_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_c_tmp_cache_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_condition_mirror_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_condition_valve_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_connect_pipe_inf_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_connect_pipe_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_A2B_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_B2A_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_M2S_with_addr_and_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_M2S_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_intc_S2M_with_lazy_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_pipe_condition_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_c_planer_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_cross_clk_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_force_addr_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_intc_M2S_prio_with_id_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_noaddr_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_interconnect_M2S_with_id_noaddr_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_planer_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_planer_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_inf_ticktock_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_intc_M2S_force_robin_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_mirrors_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_A2_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pair_map_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_M2S_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_S2M_verb_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_pipe_interconnect_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_combin_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_combin_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_streams_scaler_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_uncompress_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/data_valve_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/datainf_c_master_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/datainf_c_slaver_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/datainf_master_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/datainf_slaver_empty_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/latency_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/next_prio_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/part_data_pair_map_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_A1_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/trigger_data_inf_c_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/trigger_ready_ctrl_sdl.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable.rb +0 -0
- data/lib/tdl/SDL/data_inf_c/vcs_data_c_comptable_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/common_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/common_stack_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/independent_clock_fifo_a1_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/independent_clock_fifo_sdl.rb +0 -0
- data/lib/tdl/SDL/fifo/independent_stack_sdl.rb +0 -0
- data/lib/tdl/SDL/path_lib.rb +0 -0
- data/lib/tdl/SDL/vcs_axi4_comptable.rb +0 -0
- data/lib/tdl/SDL/vcs_axis_comptable.rb +0 -0
- data/lib/tdl/SDL/vcs_data_c_comptable.rb +0 -0
- data/lib/tdl/VideoInf/simple_video_gen.rb +0 -0
- data/lib/tdl/VideoInf/video_from_axi4.rb +0 -0
- data/lib/tdl/VideoInf/video_lib.rb +0 -0
- data/lib/tdl/VideoInf/video_stream_2_axi_stream.rb +0 -0
- data/lib/tdl/VideoInf/video_to_axi4.rb +0 -0
- data/lib/tdl/auto_script/auto_gen_tdl.rb +0 -0
- data/lib/tdl/auto_script/autogensdl.rb +0 -0
- data/lib/tdl/auto_script/autogentdl_a2.rb +0 -0
- data/lib/tdl/auto_script/import_hdl.rb +0 -0
- data/lib/tdl/auto_script/import_sdl.rb +0 -0
- data/lib/tdl/auto_script/test_autogensdl.rb +0 -0
- data/lib/tdl/auto_script/tmp.rb +0 -0
- data/lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_direct.rb +0 -0
- data/lib/tdl/axi4/axi4_direct_A1_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_direct_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_direct_verb_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_interconnect_verb.rb +24 -10
- data/lib/tdl/axi4/axi4_lib.rb +0 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_A1_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_long_to_axi4_wide_verb_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_packet_fifo_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_pipe_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_pipe_verb_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_rd_auxiliary_gen_auto.rb +0 -0
- data/lib/tdl/axi4/axi4_wr_auxiliary_gen_without_resp_auto.rb +0 -0
- data/lib/tdl/axi4/axis_to_axi4_wr_auto.rb +0 -0
- data/lib/tdl/axi4/bak/__axi4_wr_auxiliary_gen_without_resp.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_combin_wr_rd_batch_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_data_convert.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_direct_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_direct_verb_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_interconnect.rb.bak +0 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_A1_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_long_to_axi4_wide_verb_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_packet_fifo.rb.bak +0 -0
- data/lib/tdl/axi4/bak/axi4_packet_fifo_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_partition_od.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_pipe_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axi4_wr_auxiliary_gen_without_resp_auto.rb +0 -0
- data/lib/tdl/axi4/bak/axis_to_axi4_wr_auto.rb +0 -0
- data/lib/tdl/axi4/bak/ddr3.rb +0 -0
- data/lib/tdl/axi4/bak/idata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi4/bak/odata_pool_axi4_A1_auto.rb +0 -0
- data/lib/tdl/axi4/bak/odata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi4/idata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi4/odata_pool_axi4_A1_auto.rb +0 -0
- data/lib/tdl/axi4/odata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi4/wide_axis_to_axi4_wr.rb +0 -0
- data/lib/tdl/axi4/wide_axis_to_axi4_wr_auto.rb +0 -0
- data/lib/tdl/axi_lite/axi_lite_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_lite/axi_lite_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_lite/bak/axi_lite_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_lite/bak/axi_lite_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_lite/bak/jtag_to_axilite_wrapper_auto.rb +0 -0
- data/lib/tdl/axi_lite/jtag_to_axilite_wrapper_auto.rb +0 -0
- data/lib/tdl/axi_lite/lite_cmd.rb +0 -0
- data/lib/tdl/axi_lite/prj_lib.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_35bit_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_72_95bit_with_keep_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_B1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_mirror_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_cache_verb_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_A1.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_M2S_bind_tuser_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_auto_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_interconnect_S2M_with_keep.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_lib.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_long_cache_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_long_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_long_fifo_verb_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_packet_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_packet_fifo_with_info_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_partition_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_partition_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_stream_wide_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_streams_combin_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_streams_combin_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_streams_scaler_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axi_streams_scaler_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_append_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_append_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_combin_with_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_connect_pipe_A1.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_connect_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_connect_pipe_with_info_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_direct_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_filter_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_full_to_data_c_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_head_cut_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_length_fill_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_length_split_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_length_split_with_addr_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_length_split_writh_user_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_link_trigger_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_mirror_to_master_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_mirrors_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_padding.rb +44 -0
- data/lib/tdl/axi_stream/axis_pkt_fifo_filter_keep_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_pkt_fifo_filter_keep_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_ram_buffer_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_slaver_pipe_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_slaver_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_to_axi4_or_lite_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_to_data_inf_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_to_lite_rd_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_to_lite_wr_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_uncompress_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_valve_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_valve_with_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_combin_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_combin_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_convert_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_destruct_A1.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/axis_width_destruct_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/__axi_stream_interconnect_S2M.rb +0 -0
- data/lib/tdl/axi_stream/bak/_axis_mirrors.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi4_to_native_for_ddr_ip_verb_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_S2M.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_35bit_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_72_95bit_with_keep_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_B1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_mirror_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_cache_verb_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_interconnect_S2M_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_interconnect_S2M_with_keep.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_long_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_packet_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_packet_fifo_with_info_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_partition_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_stream_partition_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_streams_combin_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_streams_scaler.rb +0 -0
- data/lib/tdl/axi_stream/bak/axi_streams_scaler_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_append_A1.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_append_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_append_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_combin_with_fifo_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe.rb.bak +0 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe_A1.sv_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_connect_pipe_with_info_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_direct_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_filter_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_length_fill_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_length_split_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_length_split_with_addr_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_mirrors_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_pkt_fifo_filter_keep_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_ram_buffer_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_slaver_pipe_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_slaver_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_to_axi4_wr_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_to_data_inf_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_uncompress_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_valve_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_valve_with_pipe_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_width_combin_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_width_convert_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_width_destruct_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/axis_wrapper_oled_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/check_stream_crc_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/data_to_axis_inf_A1.rb +0 -0
- data/lib/tdl/axi_stream/bak/data_to_axis_inf_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/data_to_axis_inf_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/datainf_c_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/datainf_c_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/datainf_master_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/datainf_slaver_empty_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/dynamic_port_cfg_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/dynnamic_addr_cfg_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/gen_big_field_table_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/gen_origin_axis_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/gen_simple_axis_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/idata_pool_axi4_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/parse_big_field_table_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/parse_big_field_table_A2_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/parse_big_field_table_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/part_data_pair_map_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/simple_video_gen_A2.rb +0 -0
- data/lib/tdl/axi_stream/bak/simple_video_gen_A2_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/stream_crc_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/udp_server_bfm_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/udp_server_ctrl_bfm_auto.rb +0 -0
- data/lib/tdl/axi_stream/bak/video_to_VDMA.rb +0 -0
- data/lib/tdl/axi_stream/bak/video_to_VDMA_auto.rb +0 -0
- data/lib/tdl/axi_stream/check_stream_crc_auto.rb +0 -0
- data/lib/tdl/axi_stream/data_c_to_axis_full_auto.rb +0 -0
- data/lib/tdl/axi_stream/data_to_axis_inf_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/data_to_axis_inf_auto.rb +0 -0
- data/lib/tdl/axi_stream/gen_big_field_table_auto.rb +0 -0
- data/lib/tdl/axi_stream/gen_origin_axis_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/gen_origin_axis_auto.rb +0 -0
- data/lib/tdl/axi_stream/gen_simple_axis_auto.rb +0 -0
- data/lib/tdl/axi_stream/parse_big_field_table_A1_auto.rb +0 -0
- data/lib/tdl/axi_stream/parse_big_field_table_A2_auto.rb +0 -0
- data/lib/tdl/axi_stream/parse_big_field_table_auto.rb +0 -0
- data/lib/tdl/axi_stream/stream_crc_auto.rb +0 -0
- data/lib/tdl/basefunc.rb +0 -0
- data/lib/tdl/bfm/axi4_illegal_bfm.rb +0 -0
- data/lib/tdl/bfm/axi_stream/axi_stream_bfm.rb +0 -0
- data/lib/tdl/bfm/axi_stream/axis_bfm_exp.yml +0 -0
- data/lib/tdl/bfm/axi_stream/axis_bfm_module_build.rb +0 -0
- data/lib/tdl/bfm/axi_stream/axis_bfm_parse.rb +0 -0
- data/lib/tdl/bfm/axi_stream/axis_slice_to_logic.rb +0 -0
- data/lib/tdl/bfm/bfm_lib.rb +0 -0
- data/lib/tdl/bfm/logic_initial_block.rb +0 -0
- data/lib/tdl/cfg.yml +0 -0
- data/lib/tdl/class_hdl/hdl_always_comb.rb +0 -0
- data/lib/tdl/class_hdl/hdl_always_ff.rb +0 -0
- data/lib/tdl/class_hdl/hdl_assign.rb +0 -0
- data/lib/tdl/class_hdl/hdl_block_ifelse.rb +0 -0
- data/lib/tdl/class_hdl/hdl_data.rb +0 -0
- data/lib/tdl/class_hdl/hdl_ex_defarraychain.rb +0 -0
- data/lib/tdl/class_hdl/hdl_foreach.rb +0 -0
- data/lib/tdl/class_hdl/hdl_function.rb +0 -0
- data/lib/tdl/class_hdl/hdl_generate.rb +0 -0
- data/lib/tdl/class_hdl/hdl_initial.rb +0 -0
- data/lib/tdl/class_hdl/hdl_module_def.rb +16 -0
- data/lib/tdl/class_hdl/hdl_package.rb +0 -0
- data/lib/tdl/class_hdl/hdl_parameter.rb +0 -0
- data/lib/tdl/class_hdl/hdl_random.rb +0 -0
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +18 -1
- data/lib/tdl/class_hdl/hdl_struct.rb +0 -0
- data/lib/tdl/class_hdl/hdl_verify.rb +0 -0
- data/lib/tdl/data_inf/_data_mirrors.rb +0 -0
- data/lib/tdl/data_inf/bak/_data_mirrors.rb +0 -0
- data/lib/tdl/data_inf/bak/common_fifo_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_bind_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_c_direct_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_c_direct_mirror_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_c_tmp_cache_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_condition_mirror_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_condition_valve_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_connect_pipe.rb +0 -0
- data/lib/tdl/data_inf/bak/data_connect_pipe_inf_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_c_interconnect.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_c_pipe_condition_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_cross_clk.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_interconnect.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_planer.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_ticktack.rb +0 -0
- data/lib/tdl/data_inf/bak/data_inf_ticktock_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_mirrors_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_mirrors_verb.sv_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_uncompress_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/data_valve_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/datainf_c_master_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/datainf_c_slaver_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/datainf_master_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/datainf_slaver_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/independent_clock_fifo_auto.rb +0 -0
- data/lib/tdl/data_inf/bak/part_data_pair_map_auto.rb +0 -0
- data/lib/tdl/data_inf/common_fifo_auto.rb +0 -0
- data/lib/tdl/data_inf/data_bind_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_cache_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_direct_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_direct_mirror_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_interconnect.rb +0 -0
- data/lib/tdl/data_inf/data_c_pipe_force_vld_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_pipe_inf_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_pipe_intc_M2S_verc_auto.rb +0 -0
- data/lib/tdl/data_inf/data_c_tmp_cache_auto.rb +0 -0
- data/lib/tdl/data_inf/data_condition_mirror_auto.rb +0 -0
- data/lib/tdl/data_inf/data_condition_valve_auto.rb +0 -0
- data/lib/tdl/data_inf/data_connect_pipe_inf_auto.rb +0 -0
- data/lib/tdl/data_inf/data_inf_c_pipe_condition_auto.rb +0 -0
- data/lib/tdl/data_inf/data_mirrors_auto.rb +0 -0
- data/lib/tdl/data_inf/data_mirrors_verb.sv_auto.rb +0 -0
- data/lib/tdl/data_inf/data_uncompress_auto.rb +0 -0
- data/lib/tdl/data_inf/data_valve_auto.rb +0 -0
- data/lib/tdl/data_inf/datainf_c_master_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/datainf_c_slaver_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/datainf_master_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/datainf_slaver_empty_auto.rb +0 -0
- data/lib/tdl/data_inf/independent_clock_fifo_auto.rb +0 -0
- data/lib/tdl/data_inf/part_data_pair_map_auto.rb +0 -0
- data/lib/tdl/data_inf/path_lib.rb +0 -0
- data/lib/tdl/elements/Reset.rb +0 -0
- data/lib/tdl/elements/axi4.rb +0 -0
- data/lib/tdl/elements/axi_lite.rb +0 -0
- data/lib/tdl/elements/axi_stream.rb +0 -0
- data/lib/tdl/elements/clock.rb +0 -0
- data/lib/tdl/elements/common_configure_reg.rb +0 -0
- data/lib/tdl/elements/data_inf.rb +0 -0
- data/lib/tdl/elements/logic.rb +0 -2
- data/lib/tdl/elements/mail_box.rb +0 -0
- data/lib/tdl/elements/originclass.rb +0 -0
- data/lib/tdl/elements/parameter.rb +0 -0
- data/lib/tdl/elements/track_inf.rb +0 -0
- data/lib/tdl/elements/videoinf.rb +0 -0
- data/lib/tdl/examples/10_random/exp_random.rb +0 -0
- data/lib/tdl/examples/10_random/exp_random.sv +0 -0
- data/lib/tdl/examples/11_logic_latency/test_logic_latency.rb +0 -0
- data/lib/tdl/examples/11_logic_latency/test_logic_latency.sv +0 -0
- data/lib/tdl/examples/11_test_unit/dve.tcl +0 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.rb +0 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit.sv +0 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit_constraints.xdc +0 -0
- data/lib/tdl/examples/11_test_unit/exp_test_unit_sim.sv +0 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.rb +0 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md0.sv +0 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.rb +0 -0
- data/lib/tdl/examples/11_test_unit/modules/sub_md1.sv +0 -0
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit.sv +0 -0
- data/lib/tdl/examples/11_test_unit/tb_exp_test_unit_sim.sv +0 -0
- data/lib/tdl/examples/11_test_unit/tu0.sv +0 -0
- data/lib/tdl/examples/11_test_unit/tu1.sv +0 -0
- data/lib/tdl/examples/1_define_module/example1.rb +0 -0
- data/lib/tdl/examples/1_define_module/exmple_md.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/always_comb.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/always_ff.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/case.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/foreach.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/function.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/generate.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/module_def.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/module_head_import_package.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/module_instance_test.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/package.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/package2.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/simple_assign.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/state_case.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/struct.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/struct_function.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_axi4_M2S.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_initial_assert.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_module_port.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/test_module_var.rb +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/always_comb_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/case_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/head_pkg_module.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/init_module.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/module_instance_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/port_module.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/simple_assign_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/state_case_test.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_axi4_M2S.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_foreach.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_initial_assert.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_inst_sugar.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_port.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_module_var.sv +2 -2
- data/lib/tdl/examples/2_hdl_class/tmp/test_package.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_package2.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_struct_function.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/tmp/test_vcs_string.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/text_generate.sv +0 -0
- data/lib/tdl/examples/2_hdl_class/vcs_string.rb +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/hdl_test.sv +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/main.rb +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/main_md.sv +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_md.sv +0 -0
- data/lib/tdl/examples/3_hdl_sdl_instance/sdl_test.rb +0 -0
- data/lib/tdl/examples/4_generate/example.rb +0 -0
- data/lib/tdl/examples/4_generate/test_generate.sv +0 -0
- data/lib/tdl/examples/5_logic_combin/login_combin.rb +0 -0
- data/lib/tdl/examples/5_logic_combin/test_logic_combin.sv +0 -0
- data/lib/tdl/examples/6_module_with_interface/example.rb +0 -0
- data/lib/tdl/examples/6_module_with_interface/example_interface.sv +0 -0
- data/lib/tdl/examples/6_module_with_interface/inf_collect.rb +0 -0
- data/lib/tdl/examples/6_module_with_interface/inf_collect.sv +0 -0
- data/lib/tdl/examples/7_module_with_package/body_package.rb +0 -0
- data/lib/tdl/examples/7_module_with_package/body_package.sv +0 -0
- data/lib/tdl/examples/7_module_with_package/example_pkg.rb +0 -0
- data/lib/tdl/examples/7_module_with_package/example_pkg.sv +0 -0
- data/lib/tdl/examples/7_module_with_package/head_package.rb +0 -0
- data/lib/tdl/examples/7_module_with_package/head_package.sv +0 -0
- data/lib/tdl/examples/8_top_module/dve.tcl +0 -0
- data/lib/tdl/examples/8_top_module/example.rb +0 -0
- data/lib/tdl/examples/8_top_module/pins.yml +0 -0
- data/lib/tdl/examples/8_top_module/tb_test_top.sv +0 -0
- data/lib/tdl/examples/8_top_module/tb_test_top_sim.sv +0 -0
- data/lib/tdl/examples/8_top_module/test_top.sv +26 -7
- data/lib/tdl/examples/8_top_module/test_top_constraints.xdc +8 -8
- data/lib/tdl/examples/8_top_module/test_top_sim.sv +7 -26
- data/lib/tdl/examples/9_itegration/A_itgt/a_test_md.sv +0 -0
- data/lib/tdl/examples/9_itegration/A_itgt/a_test_module.rb +0 -0
- data/lib/tdl/examples/9_itegration/A_itgt/itgt_module_a_block.rb +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/itgt_module_clock_manage.rb +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.rb +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/simple_clock.sv +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/test_clock_bb.sv +0 -0
- data/lib/tdl/examples/9_itegration/clock_manage/tu_ClockManage_test_clock_bb.sv +0 -0
- data/lib/tdl/examples/9_itegration/dve.tcl +0 -0
- data/lib/tdl/examples/9_itegration/pins.yml +0 -0
- data/lib/tdl/examples/9_itegration/tb_test_top.sv +0 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop.sv +0 -0
- data/lib/tdl/examples/9_itegration/tb_test_tttop_sim.sv +1 -1
- data/lib/tdl/examples/9_itegration/test_top.sv +0 -0
- data/lib/tdl/examples/9_itegration/test_top_constraints.xdc +0 -0
- data/lib/tdl/examples/9_itegration/test_tttop.sv +0 -0
- data/lib/tdl/examples/9_itegration/test_tttop_constraints.xdc +0 -0
- data/lib/tdl/examples/9_itegration/test_tttop_sim.sv +1 -1
- data/lib/tdl/examples/9_itegration/top.rb +2 -2
- data/lib/tdl/examples/readme.md +0 -0
- data/lib/tdl/exlib/axis_eth_ex.rb +0 -0
- data/lib/tdl/exlib/axis_verify.rb +0 -0
- data/lib/tdl/exlib/clock_reset_verify.rb +0 -0
- data/lib/tdl/exlib/common_cfg_reg_inf.rb +0 -0
- data/lib/tdl/exlib/constraints.rb +0 -0
- data/lib/tdl/exlib/constraints_verb.rb +4 -4
- data/lib/tdl/exlib/dve_tcl.rb +0 -0
- data/lib/tdl/exlib/element_class_vars.rb +0 -0
- data/lib/tdl/exlib/global_param.rb +0 -0
- data/lib/tdl/exlib/integral_test/bak/integral_test.rb +0 -0
- data/lib/tdl/exlib/integral_test/clock_itest.rb +0 -0
- data/lib/tdl/exlib/integral_test/diff_clock_itest.rb +0 -0
- data/lib/tdl/exlib/integral_test/io_itest.rb +0 -0
- data/lib/tdl/exlib/integral_test/reset_itest.rb +0 -0
- data/lib/tdl/exlib/integral_test/simple_logic_itest.rb +0 -0
- data/lib/tdl/exlib/itegration.rb +0 -0
- data/lib/tdl/exlib/itegration_test_unit.rb +0 -0
- data/lib/tdl/exlib/itegration_verb.rb +129 -13
- data/lib/tdl/exlib/logic_verify.rb +0 -0
- data/lib/tdl/exlib/parse_argv.rb +0 -0
- data/lib/tdl/exlib/sdlmodule_sim.bak.rb +0 -0
- data/lib/tdl/exlib/test_point.rb +4 -4
- data/lib/tdl/exlib/test_point.rb.bak +0 -0
- data/lib/tdl/global_scan.rb +0 -0
- data/lib/tdl/rebuild_ele/axi4.rb +0 -0
- data/lib/tdl/rebuild_ele/axi_lite.rb +0 -0
- data/lib/tdl/rebuild_ele/axi_stream.rb +0 -0
- data/lib/tdl/rebuild_ele/cm_ram_inf.sv +0 -0
- data/lib/tdl/rebuild_ele/cm_ram_inf_define.rb +0 -0
- data/lib/tdl/rebuild_ele/data_inf.rb +0 -0
- data/lib/tdl/rebuild_ele/data_inf_c.rb +0 -0
- data/lib/tdl/rebuild_ele/ele_base.rb +0 -0
- data/lib/tdl/rebuild_ele/readme.md +0 -0
- data/lib/tdl/sdlimplement/resource.yml +0 -0
- data/lib/tdl/sdlimplement/sdl_impl_module.rb +0 -0
- data/lib/tdl/sdlimplement/sdl_impl_param.rb +0 -0
- data/lib/tdl/sdlimplement/test.rb +0 -0
- data/lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb +0 -0
- data/lib/tdl/sdlmodule/generator_block_module.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodlule_path_db.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_arraychain.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_head_logo.txt +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_instance.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_port_define.rb +3 -3
- data/lib/tdl/sdlmodule/sdlmodule_varible.rb +0 -0
- data/lib/tdl/sdlmodule/sdlmodule_vcs_comptable.rb +0 -0
- data/lib/tdl/sdlmodule/techbench_module.rb +0 -0
- data/lib/tdl/sdlmodule/test_unit_module.rb +13 -3
- data/lib/tdl/sdlmodule/test_unit_module.rb.bak +0 -0
- data/lib/tdl/sdlmodule/top_module.rb +0 -0
- data/lib/tdl/sdlmodule/top_module.rb.bak +0 -0
- data/lib/tdl/tdl.rb +0 -0
- data/lib/tdl/tdlerror/tdlerror.rb +0 -0
- data/lib/tdl/testunit/test_all.rb +0 -0
- data/lib/tdl/testunit/test_array_chain.rb +0 -0
- data/lib/tdl/testunit/test_tmp.rb +0 -0
- metadata +25 -6
|
@@ -0,0 +1,150 @@
|
|
|
1
|
+
# require_relative "../prj_lib"
|
|
2
|
+
require_hdl "axis_length_split_with_addr.sv"
|
|
3
|
+
require_hdl 'axi_stream_wide_fifo.sv'
|
|
4
|
+
new_m = SdlModule.new(name:File.basename(__FILE__,".rb"),out_sv_path:__dir__)
|
|
5
|
+
new_m.target_class = AxiStream
|
|
6
|
+
|
|
7
|
+
new_m.instance_exec do
|
|
8
|
+
Input :addr,dsize:32
|
|
9
|
+
Input :max_length,dsize:32
|
|
10
|
+
# AxiStream().slaver :axis_in
|
|
11
|
+
# Axi4().master_wr :axi_wr
|
|
12
|
+
port.axis.slaver - 'axis_in'
|
|
13
|
+
port.axi4.master_wr - 'axi_wr'
|
|
14
|
+
|
|
15
|
+
Def().logic(name: "addr_cur",dsize:32)
|
|
16
|
+
|
|
17
|
+
axis_length_split_with_addr.axis_length_split_with_addr_inst do |h|
|
|
18
|
+
h.param.ADDR_STEP axi_wr.ADDR_STEP
|
|
19
|
+
h.origin_addr addr
|
|
20
|
+
h.length max_length
|
|
21
|
+
h.band_addr addr_cur
|
|
22
|
+
h.axis_in axis_in
|
|
23
|
+
h.axis_out axis_in.copy(name: 'split_out')
|
|
24
|
+
end
|
|
25
|
+
|
|
26
|
+
|
|
27
|
+
# split_out = AxiStream.axis_length_split_with_addr(
|
|
28
|
+
# addr_step: axi_wr.ADDR_STEP,
|
|
29
|
+
# length:max_length,
|
|
30
|
+
# up_stream:axis_in,
|
|
31
|
+
# origin_addr:addr,
|
|
32
|
+
# band_addr:addr_cur,
|
|
33
|
+
# belong_to_module: self)
|
|
34
|
+
|
|
35
|
+
# AxiStream.axi_stream_wide_fifo(
|
|
36
|
+
# depth: 4,
|
|
37
|
+
# axis_in: split_out,
|
|
38
|
+
# axis_out: split_out.copy(name:'fifo_axis',clock:axi_wr.axi_aclk,reset:axi_wr.axi_aresetn,dsize:axis_in.DSIZE),
|
|
39
|
+
# belong_to_module:self
|
|
40
|
+
# )
|
|
41
|
+
|
|
42
|
+
axi_stream_wide_fifo.axi_stream_wide_fifo_inst do |h|
|
|
43
|
+
h.parameter.DEPTH 4
|
|
44
|
+
h.axis_in split_out
|
|
45
|
+
h.axis_out split_out.copy(name:'fifo_axis',clock:axi_wr.axi_aclk,reset:axi_wr.axi_aresetn,dsize:axis_in.DSIZE)
|
|
46
|
+
end
|
|
47
|
+
|
|
48
|
+
Def().logic(name: :id,dsize:axi_wr.idsize)
|
|
49
|
+
Def().logic(name: :addr_s,dsize:axi_wr.asize)
|
|
50
|
+
Def().logic(name: :len_s,dsize:axi_wr.lsize)
|
|
51
|
+
|
|
52
|
+
Instance(:independent_clock_fifo,"independent_clock_fifo_inst") do |h|
|
|
53
|
+
h[:DEPTH] = 4
|
|
54
|
+
h[:DSIZE] = NqString.new("#{axi_wr.idsize} + #{axi_wr.asize} + #{axi_wr.lsize}")
|
|
55
|
+
h[:wr_clk] = axis_in.aclk
|
|
56
|
+
h[:wr_rst_n] = axis_in.aresetn
|
|
57
|
+
h[:rd_clk] = axi_wr.axi_aclk
|
|
58
|
+
h[:rd_rst_n] = axi_wr.axi_aresetn
|
|
59
|
+
h[:wdata] = "{#{id.s},#{addr_s.s},#{len_s.s}}".to_nq
|
|
60
|
+
h[:wr_en] = split_out.vld_rdy_last
|
|
61
|
+
h[:rdata] = Def().logic(name:"fifo_rdata",dsize:h[:DSIZE])
|
|
62
|
+
h[:rd_en] = Def().logic(name:"fifo_rd_en")
|
|
63
|
+
h[:empty] = Def().logic(name:"fifo_empty")
|
|
64
|
+
h[:full] = Def().logic(name:"fifo_full")
|
|
65
|
+
end
|
|
66
|
+
|
|
67
|
+
# AxiStream.axi4_wr_auxiliary_gen_without_resp(
|
|
68
|
+
# stream_en: Def().logic(name:"stream_en"),
|
|
69
|
+
# id_add_len_in: Def().axi_stream(name:"id_add_len_in",clock:axi_wr.axi_aclk,reset:axi_wr.axi_aresetn,dsize:"#{axi_wr.idsize} + #{axi_wr.asize} + #{axi_wr.lsize}"),
|
|
70
|
+
# axi_wr_aux: axi_wr,
|
|
71
|
+
# belong_to_module: self
|
|
72
|
+
# )
|
|
73
|
+
|
|
74
|
+
Instance(:axi4_wr_auxiliary_gen_without_resp,"axi4_wr_auxiliary_gen_without_resp_inst") do |h|
|
|
75
|
+
h[:stream_en] = Def().logic(name: "stream_en")
|
|
76
|
+
# h[:id_add_len_in] = Def().axi_stream(name:"id_add_len_in",clock:axi_wr.axi_aclk,reset:axi_wr.axi_aresetn,dsize:"#{axi_wr.idsize} + #{axi_wr.asize} + #{axi_wr.lsize}")
|
|
77
|
+
h[:id_add_len_in] = axi_stream_inf(clock:axi_wr.axi_aclk,reset:axi_wr.axi_aresetn,dsize:"#{axi_wr.idsize} + #{axi_wr.asize} + #{axi_wr.lsize}".to_nq).id_add_len_in
|
|
78
|
+
h[:axi_wr_aux] = axi_wr
|
|
79
|
+
end
|
|
80
|
+
|
|
81
|
+
Always(posedge:axis_in.aclk,negedge:axis_in.aresetn) do
|
|
82
|
+
IF ~axis_in.aresetn do
|
|
83
|
+
id <= 0
|
|
84
|
+
end
|
|
85
|
+
ELSIF split_out.vld_rdy_last do
|
|
86
|
+
id <= id + 1
|
|
87
|
+
end
|
|
88
|
+
ELSE do
|
|
89
|
+
id <= id
|
|
90
|
+
end
|
|
91
|
+
end
|
|
92
|
+
|
|
93
|
+
Assign do
|
|
94
|
+
addr_s <= addr_cur
|
|
95
|
+
len_s <= split_out.axis_tcnt
|
|
96
|
+
id_add_len_in.axis_tvalid <= ~independent_clock_fifo_inst[:empty]
|
|
97
|
+
id_add_len_in.axis_tdata <= independent_clock_fifo_inst[:rdata]
|
|
98
|
+
id_add_len_in.axis_tlast <= 1.b1
|
|
99
|
+
independent_clock_fifo_inst[:rd_en] <= id_add_len_in.axis_tready
|
|
100
|
+
end
|
|
101
|
+
|
|
102
|
+
# pipe_axis = AxiStream.axis_valve_with_pipe(
|
|
103
|
+
# mode: "OUT",
|
|
104
|
+
# button: stream_en,
|
|
105
|
+
# up_stream: fifo_axis,
|
|
106
|
+
# belong_to_module:self)
|
|
107
|
+
|
|
108
|
+
axis_valve_with_pipe.axis_valve_with_pipe_inst do |h|
|
|
109
|
+
h.parameter.MODE "OUT"
|
|
110
|
+
h.input.button stream_en # //[1] OPEN ; [0] CLOSE
|
|
111
|
+
h.axis_in fifo_axis
|
|
112
|
+
h.axis_out fifo_axis.copy(name: 'pipe_axis')
|
|
113
|
+
end
|
|
114
|
+
|
|
115
|
+
Assign do
|
|
116
|
+
axi_wr.axi_wdata <= pipe_axis.axis_tdata
|
|
117
|
+
axi_wr.axi_wstrb <= ~pipe_axis.axis_tkeep
|
|
118
|
+
axi_wr.axi_wvalid <= pipe_axis.axis_tvalid
|
|
119
|
+
axi_wr.axi_wlast <= pipe_axis.axis_tlast
|
|
120
|
+
pipe_axis.axis_tready <= axi_wr.axi_wready
|
|
121
|
+
axi_wr.axi_bready <= "1'b1".to_nq
|
|
122
|
+
end
|
|
123
|
+
|
|
124
|
+
self.ex_up_code =
|
|
125
|
+
%Q{
|
|
126
|
+
//int MAX_LENGTH;
|
|
127
|
+
//assign MAX_LENGTH = (axis_in.DSIZE <= 8)? 2**11 :
|
|
128
|
+
// (axis_in.DSIZE <= 16)? 2**10 :
|
|
129
|
+
// (axis_in.DSIZE <= 32)? 2**9 :
|
|
130
|
+
// (axis_in.DSIZE <= 64)? 2**8 :
|
|
131
|
+
// (axis_in.DSIZE <= 128)? 2**7 :
|
|
132
|
+
// (axis_in.DSIZE <= 256)? 2**6 :
|
|
133
|
+
// (axis_in.DSIZE <= 512)? 2**5 : 2**4;
|
|
134
|
+
|
|
135
|
+
initial begin
|
|
136
|
+
assert(#{axis_in}.DSIZE == #{axi_wr}.DSIZE)
|
|
137
|
+
else begin
|
|
138
|
+
$error("STREAM DSIZE should eql AXI4 DSIZE");
|
|
139
|
+
$finish;
|
|
140
|
+
end
|
|
141
|
+
// assert(#{axi_wr}.LSIZE >= $clog2(MAX_LENGTH))
|
|
142
|
+
// else begin
|
|
143
|
+
// $error("AXIS LSIZE is too smaller");
|
|
144
|
+
// $finish;
|
|
145
|
+
// end
|
|
146
|
+
end
|
|
147
|
+
}
|
|
148
|
+
end
|
|
149
|
+
|
|
150
|
+
new_m.gen_sv_module
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
@@ -96,7 +96,6 @@ assign s_wcmd_inf.data = s00.axi_awaddr;
|
|
|
96
96
|
assign s00.axi_awready = s_wcmd_inf.ready;
|
|
97
97
|
|
|
98
98
|
data_pipe_interconnect_S2M_verb #(
|
|
99
|
-
.DSIZE (s00.ASIZE-NSIZE ),
|
|
100
99
|
.NUM (NUM )
|
|
101
100
|
)wr_cmd_pipe_interconnect_S2M_inst(
|
|
102
101
|
/* input */ .clock (clock ),
|
|
@@ -124,7 +123,7 @@ assign s_wlock_inf.data = s00.axi_awlock;
|
|
|
124
123
|
// assign s00.axi_awready = s_wlock_inf.ready;
|
|
125
124
|
|
|
126
125
|
data_pipe_interconnect_S2M_verb #(
|
|
127
|
-
.DSIZE (1 ),
|
|
126
|
+
// .DSIZE (1 ),
|
|
128
127
|
.NUM (NUM )
|
|
129
128
|
)wr_lock_pipe_interconnect_S2M_inst(
|
|
130
129
|
/* input */ .clock (clock ),
|
|
@@ -154,7 +153,7 @@ assign s00.axi_arready = s_rcmd_inf.ready;
|
|
|
154
153
|
|
|
155
154
|
|
|
156
155
|
data_pipe_interconnect_S2M_verb #(
|
|
157
|
-
.DSIZE (s00.ASIZE-NSIZE ),
|
|
156
|
+
// .DSIZE (s00.ASIZE-NSIZE ),
|
|
158
157
|
.NUM (NUM )
|
|
159
158
|
)rd_cmd_pipe_interconnect_S2M_inst(
|
|
160
159
|
/* input */ .clock (clock ),
|
|
@@ -182,7 +181,7 @@ assign s_rlock_inf.data = s00.axi_arlock;
|
|
|
182
181
|
// assign s00.axi_awready = s_wlock_inf.ready;
|
|
183
182
|
|
|
184
183
|
data_pipe_interconnect_S2M_verb #(
|
|
185
|
-
.DSIZE (1 ),
|
|
184
|
+
// .DSIZE (1 ),
|
|
186
185
|
.NUM (NUM )
|
|
187
186
|
)rd_lock_pipe_interconnect_S2M_inst(
|
|
188
187
|
/* input */ .clock (clock ),
|
|
@@ -212,7 +211,7 @@ assign s_wdata_inf.data = s00.axi_wdata;
|
|
|
212
211
|
assign s00.axi_wready = s_wdata_inf.ready;
|
|
213
212
|
|
|
214
213
|
data_pipe_interconnect_S2M_verb #(
|
|
215
|
-
.DSIZE (s00.DSIZE ),
|
|
214
|
+
// .DSIZE (s00.DSIZE ),
|
|
216
215
|
.NUM (NUM )
|
|
217
216
|
)wr_data_pipe_interconnect_S2M_inst(
|
|
218
217
|
/* input */ .clock (clock ),
|
|
File without changes
|
|
@@ -0,0 +1,322 @@
|
|
|
1
|
+
/**********************************************
|
|
2
|
+
_______________________________________
|
|
3
|
+
___________ Cook Darwin __________
|
|
4
|
+
_______________________________________
|
|
5
|
+
descript:
|
|
6
|
+
author : Cook.Darwin
|
|
7
|
+
Version: VERA.0.0
|
|
8
|
+
creaded: 2016/12/27
|
|
9
|
+
madified:
|
|
10
|
+
***********************************************/
|
|
11
|
+
`timescale 1ns/1ps
|
|
12
|
+
module axi_lite_interconnect_S2M_verb #(
|
|
13
|
+
parameter NUM = 4,
|
|
14
|
+
parameter SLAVER_ASIZE = 32
|
|
15
|
+
)(
|
|
16
|
+
axi_lite_inf.slaver s00,
|
|
17
|
+
axi_lite_inf.master m00 [NUM-1:0]
|
|
18
|
+
);
|
|
19
|
+
localparam NSIZE = $clog2(NUM);
|
|
20
|
+
//--->> STREAM CLOCK AND RESET <<-------------------
|
|
21
|
+
wire clock,rst_n;
|
|
22
|
+
assign clock = s00.axi_aclk;
|
|
23
|
+
assign rst_n = s00.axi_aresetn;
|
|
24
|
+
//---<< STREAM CLOCK AND RESET >>-------------------
|
|
25
|
+
|
|
26
|
+
import SystemPkg::*;
|
|
27
|
+
|
|
28
|
+
initial begin
|
|
29
|
+
assert(s00.ASIZE == (m00[0].ASIZE+NSIZE) )
|
|
30
|
+
else begin
|
|
31
|
+
$error("Lite S2M ASIZE ERROR!!!");
|
|
32
|
+
$stop;
|
|
33
|
+
end
|
|
34
|
+
|
|
35
|
+
assert(s00.ASIZE == SLAVER_ASIZE )
|
|
36
|
+
else begin
|
|
37
|
+
$error("Lite S2M ASIZE ERROR!!!");
|
|
38
|
+
$stop;
|
|
39
|
+
end
|
|
40
|
+
end
|
|
41
|
+
//--->> WR CMD CHANNEL <<--------------------
|
|
42
|
+
|
|
43
|
+
|
|
44
|
+
genvar KK;
|
|
45
|
+
|
|
46
|
+
|
|
47
|
+
data_inf #(.DSIZE(SLAVER_ASIZE-NSIZE) ) m_wcmd_inf [NUM-1:0] ();
|
|
48
|
+
data_inf #(.DSIZE(SLAVER_ASIZE-NSIZE) ) s_wcmd_inf ();
|
|
49
|
+
|
|
50
|
+
generate
|
|
51
|
+
for(KK=0;KK<NUM;KK++)begin
|
|
52
|
+
assign m00[KK].axi_awvalid = m_wcmd_inf[KK].valid;
|
|
53
|
+
assign m00[KK].axi_awaddr = m_wcmd_inf[KK].data;
|
|
54
|
+
assign m_wcmd_inf[KK].ready = m00[KK].axi_awready;
|
|
55
|
+
end
|
|
56
|
+
endgenerate
|
|
57
|
+
|
|
58
|
+
assign s_wcmd_inf.valid = s00.axi_awvalid;
|
|
59
|
+
assign s_wcmd_inf.data = s00.axi_awaddr;
|
|
60
|
+
assign s00.axi_awready = s_wcmd_inf.ready;
|
|
61
|
+
|
|
62
|
+
data_pipe_interconnect_S2M_verb #(
|
|
63
|
+
.NUM (NUM )
|
|
64
|
+
)wr_cmd_pipe_interconnect_S2M_inst(
|
|
65
|
+
/* input */ .clock (clock ),
|
|
66
|
+
/* input */ .rst_n (rst_n ),
|
|
67
|
+
/* input */ .clk_en (1'b1 ),
|
|
68
|
+
/* input [2:0] */ .addr (s00.axi_awaddr[SLAVER_ASIZE-1-:NSIZE] ), // sync to s00.valid
|
|
69
|
+
/* data_inf.master */ .m00 (m_wcmd_inf[NUM-1:0] ),//[NUM-1:0]
|
|
70
|
+
/* data_inf.slaver */ .s00 (s_wcmd_inf )
|
|
71
|
+
);
|
|
72
|
+
//---<< WR CMD CHANNEL >>--------------------
|
|
73
|
+
//--->> WR LOCK <<---------------------------
|
|
74
|
+
data_inf #(.DSIZE(1) ) m_wlock_inf [NUM-1:0] ();
|
|
75
|
+
data_inf #(.DSIZE(1) ) s_wlock_inf ();
|
|
76
|
+
|
|
77
|
+
generate
|
|
78
|
+
for(KK=0;KK<NUM;KK++)begin:WLOCK_GEN
|
|
79
|
+
// assign m00[KK].axi_awvalid = m_wlock_inf[KK].valid;
|
|
80
|
+
assign m00[KK].axi_awlock = m_wlock_inf[KK].data && m_wlock_inf[KK].valid;
|
|
81
|
+
assign m_wlock_inf[KK].ready = m00[KK].axi_awready || 1'b1;
|
|
82
|
+
end
|
|
83
|
+
endgenerate
|
|
84
|
+
|
|
85
|
+
assign s_wlock_inf.valid = s00.axi_awlock;
|
|
86
|
+
assign s_wlock_inf.data = s00.axi_awlock;
|
|
87
|
+
// assign s00.axi_awready = s_wlock_inf.ready;
|
|
88
|
+
|
|
89
|
+
data_pipe_interconnect_S2M_verb #(
|
|
90
|
+
.DSIZE (1 ),
|
|
91
|
+
.NUM (NUM )
|
|
92
|
+
)wr_lock_pipe_interconnect_S2M_inst(
|
|
93
|
+
/* input */ .clock (clock ),
|
|
94
|
+
/* input */ .rst_n (rst_n ),
|
|
95
|
+
/* input */ .clk_en (1'b1 ),
|
|
96
|
+
/* input [2:0] */ .addr (s00.axi_awaddr[SLAVER_ASIZE-1-:NSIZE] ), // sync to s00.valid
|
|
97
|
+
/* data_inf.master */ .m00 (m_wlock_inf[NUM-1:0] ),//[NUM-1:0]
|
|
98
|
+
/* data_inf.slaver */ .s00 (s_wlock_inf )
|
|
99
|
+
);
|
|
100
|
+
//---<< WR LOCK >>---------------------------
|
|
101
|
+
//--->> RD CMD CHANNEL <<--------------------
|
|
102
|
+
|
|
103
|
+
data_inf #(.DSIZE(SLAVER_ASIZE-NSIZE) ) m_rcmd_inf [NUM-1:0] ();
|
|
104
|
+
data_inf #(.DSIZE(SLAVER_ASIZE-NSIZE) ) s_rcmd_inf ();
|
|
105
|
+
|
|
106
|
+
generate
|
|
107
|
+
for(KK=0;KK<NUM;KK++)begin
|
|
108
|
+
assign m00[KK].axi_arvalid = m_rcmd_inf[KK].valid;
|
|
109
|
+
assign m00[KK].axi_araddr = m_rcmd_inf[KK].data;
|
|
110
|
+
assign m_rcmd_inf[KK].ready = m00[KK].axi_arready;
|
|
111
|
+
end
|
|
112
|
+
endgenerate
|
|
113
|
+
|
|
114
|
+
assign s_rcmd_inf.valid = s00.axi_arvalid;
|
|
115
|
+
assign s_rcmd_inf.data = s00.axi_araddr;
|
|
116
|
+
assign s00.axi_arready = s_rcmd_inf.ready;
|
|
117
|
+
|
|
118
|
+
|
|
119
|
+
data_pipe_interconnect_S2M_verb #(
|
|
120
|
+
.DSIZE (SLAVER_ASIZE-NSIZE ),
|
|
121
|
+
.NUM (NUM )
|
|
122
|
+
)rd_cmd_pipe_interconnect_S2M_inst(
|
|
123
|
+
/* input */ .clock (clock ),
|
|
124
|
+
/* input */ .rst_n (rst_n ),
|
|
125
|
+
/* input */ .clk_en (1'b1 ),
|
|
126
|
+
/* input [2:0] */ .addr (s00.axi_araddr[SLAVER_ASIZE-1-:NSIZE] ), // sync to s00.valid
|
|
127
|
+
/* data_inf.master */ .m00 (m_rcmd_inf[NUM-1:0] ),//[NUM-1:0]
|
|
128
|
+
/* data_inf.slaver */ .s00 (s_rcmd_inf )
|
|
129
|
+
);
|
|
130
|
+
//---<< RD CMD CHANNEL >>--------------------
|
|
131
|
+
//--->> RD LOCK <<---------------------------
|
|
132
|
+
data_inf #(.DSIZE(1) ) m_rlock_inf [NUM-1:0] ();
|
|
133
|
+
data_inf #(.DSIZE(1) ) s_rlock_inf ();
|
|
134
|
+
|
|
135
|
+
generate
|
|
136
|
+
for(KK=0;KK<NUM;KK++)begin:RLOCK_GEN
|
|
137
|
+
// assign m00[KK].axi_awvalid = m_wlock_inf[KK].valid;
|
|
138
|
+
assign m00[KK].axi_arlock = m_rlock_inf[KK].data && m_rlock_inf[KK].valid;
|
|
139
|
+
assign m_rlock_inf[KK].ready = m00[KK].axi_arready || 1'b1;
|
|
140
|
+
end
|
|
141
|
+
endgenerate
|
|
142
|
+
|
|
143
|
+
assign s_rlock_inf.valid = s00.axi_arlock;
|
|
144
|
+
assign s_rlock_inf.data = s00.axi_arlock;
|
|
145
|
+
// assign s00.axi_awready = s_wlock_inf.ready;
|
|
146
|
+
|
|
147
|
+
data_pipe_interconnect_S2M_verb #(
|
|
148
|
+
.DSIZE (1 ),
|
|
149
|
+
.NUM (NUM )
|
|
150
|
+
)rd_lock_pipe_interconnect_S2M_inst(
|
|
151
|
+
/* input */ .clock (clock ),
|
|
152
|
+
/* input */ .rst_n (rst_n ),
|
|
153
|
+
/* input */ .clk_en (1'b1 ),
|
|
154
|
+
/* input [2:0] */ .addr (s00.axi_araddr[SLAVER_ASIZE-1-:NSIZE] ), // sync to s00.valid
|
|
155
|
+
/* data_inf.master */ .m00 (m_rlock_inf[NUM-1:0] ),//[NUM-1:0]
|
|
156
|
+
/* data_inf.slaver */ .s00 (s_rlock_inf )
|
|
157
|
+
);
|
|
158
|
+
//---<< RD LOCK >>---------------------------
|
|
159
|
+
//--->> LOCK WR DATA CHANNEL <<--------------
|
|
160
|
+
//---<< LOCK WR DATA CHANNEL >>--------------
|
|
161
|
+
//--->> WR DATA CHANNEL <<-------------------
|
|
162
|
+
data_inf #(.DSIZE(s00.DSIZE) ) m_wdata_inf [NUM-1:0] ();
|
|
163
|
+
data_inf #(.DSIZE(s00.DSIZE) ) s_wdata_inf ();
|
|
164
|
+
|
|
165
|
+
generate
|
|
166
|
+
for(KK=0;KK<NUM;KK++)begin
|
|
167
|
+
assign m00[KK].axi_wvalid = m_wdata_inf[KK].valid;
|
|
168
|
+
assign m00[KK].axi_wdata = m_wdata_inf[KK].data;
|
|
169
|
+
assign m_wdata_inf[KK].ready = m00[KK].axi_wready;
|
|
170
|
+
end
|
|
171
|
+
endgenerate
|
|
172
|
+
|
|
173
|
+
assign s_wdata_inf.valid = s00.axi_wvalid;
|
|
174
|
+
assign s_wdata_inf.data = s00.axi_wdata;
|
|
175
|
+
assign s00.axi_wready = s_wdata_inf.ready;
|
|
176
|
+
|
|
177
|
+
data_pipe_interconnect_S2M_verb #(
|
|
178
|
+
.DSIZE (s00.DSIZE ),
|
|
179
|
+
.NUM (NUM )
|
|
180
|
+
)wr_data_pipe_interconnect_S2M_inst(
|
|
181
|
+
/* input */ .clock (clock ),
|
|
182
|
+
/* input */ .rst_n (rst_n ),
|
|
183
|
+
/* input */ .clk_en (1'b1 ),
|
|
184
|
+
/* input [2:0] */ .addr (s00.axi_awaddr[SLAVER_ASIZE-1-:NSIZE] ), // sync to s00.valid
|
|
185
|
+
/* data_inf.master */ .m00 (m_wdata_inf[NUM-1:0] ),//[NUM-1:0]
|
|
186
|
+
/* data_inf.slaver */ .s00 (s_wdata_inf )
|
|
187
|
+
);
|
|
188
|
+
//---<< WR DATA CHANNEL >>-------------------
|
|
189
|
+
//--->> RD DATA CHANNEL <<-------------------
|
|
190
|
+
logic [NSIZE-1:0] sw_path;
|
|
191
|
+
logic sw_vld;
|
|
192
|
+
|
|
193
|
+
always@(posedge clock,negedge rst_n)
|
|
194
|
+
if(~rst_n) sw_path <= {NSIZE{1'b0}};
|
|
195
|
+
else begin
|
|
196
|
+
if(s00.axi_arvalid && s00.axi_arready)
|
|
197
|
+
sw_path <= s00.axi_araddr[SLAVER_ASIZE-1-:NSIZE];
|
|
198
|
+
else sw_path <= sw_path;
|
|
199
|
+
end
|
|
200
|
+
|
|
201
|
+
always@(posedge clock,negedge rst_n)
|
|
202
|
+
if(~rst_n) sw_vld <= 1'd0;
|
|
203
|
+
else begin
|
|
204
|
+
if(s00.axi_arvalid && s00.axi_arready)
|
|
205
|
+
sw_vld <= 1'b1;
|
|
206
|
+
else if(s00.axi_rvalid && s00.axi_rready)
|
|
207
|
+
sw_vld <= 1'b0;
|
|
208
|
+
else sw_vld <= sw_vld;
|
|
209
|
+
end
|
|
210
|
+
|
|
211
|
+
data_inf #(.DSIZE(s00.DSIZE) ) s00_rdata_inf [NUM-1:0]();
|
|
212
|
+
data_inf #(.DSIZE(s00.DSIZE) ) m00_rdata_inf ();
|
|
213
|
+
|
|
214
|
+
generate
|
|
215
|
+
for(KK=0;KK<NUM;KK++)begin
|
|
216
|
+
assign s00_rdata_inf[KK].data = m00[KK].axi_rdata;
|
|
217
|
+
assign s00_rdata_inf[KK].valid = m00[KK].axi_rvalid;
|
|
218
|
+
assign m00[KK].axi_rready = s00_rdata_inf[KK].ready ;
|
|
219
|
+
end
|
|
220
|
+
endgenerate
|
|
221
|
+
|
|
222
|
+
assign s00.axi_rdata = m00_rdata_inf.data;
|
|
223
|
+
assign s00.axi_rvalid = m00_rdata_inf.valid;
|
|
224
|
+
assign m00_rdata_inf.ready = s00.axi_rready;
|
|
225
|
+
|
|
226
|
+
data_pipe_interconnect_M2S #(
|
|
227
|
+
// .DSIZE (s00.DSIZE ),
|
|
228
|
+
.NUM (NUM )
|
|
229
|
+
)rd_data_pipe_interconnect_M2S(
|
|
230
|
+
/* input */ .clock (clock ),
|
|
231
|
+
/* input */ .rst_n (rst_n ),
|
|
232
|
+
/* input */ .clk_en (1'b1 ),
|
|
233
|
+
/* input */ .vld_sw (sw_vld ),
|
|
234
|
+
/* input [2:0] */ .sw (sw_path ),
|
|
235
|
+
/* output logic[2:0] */ .curr_path (),
|
|
236
|
+
|
|
237
|
+
/* data_inf.slaver */ .s00/* [NUM-1:0],*/(s00_rdata_inf[NUM-1:0] ),
|
|
238
|
+
/* data_inf.master */ .m00 (m00_rdata_inf )
|
|
239
|
+
);
|
|
240
|
+
|
|
241
|
+
//---<< RD DATA CHANNEL >>-------------------
|
|
242
|
+
//--->> RESP DATA CHANNEL <<-------------------
|
|
243
|
+
//--->> LOCK <<------------
|
|
244
|
+
logic wstatus;
|
|
245
|
+
logic awlock_raising;
|
|
246
|
+
logic awlock_falling;
|
|
247
|
+
|
|
248
|
+
always@(posedge clock,negedge rst_n)
|
|
249
|
+
if(~rst_n) wstatus <= 1'b0;
|
|
250
|
+
else begin
|
|
251
|
+
if(s00.axi_awvalid && s00.axi_awready)
|
|
252
|
+
wstatus <= 1'b1;
|
|
253
|
+
else if(s00.axi_bvalid && s00.axi_bready)
|
|
254
|
+
wstatus <= 1'b0;
|
|
255
|
+
else wstatus <= wstatus;
|
|
256
|
+
end
|
|
257
|
+
|
|
258
|
+
edge_generator aw_edge_generator_inst(
|
|
259
|
+
/* input */ .clk (s00.axi_aclk ),
|
|
260
|
+
/* input */ .rst_n (s00.axi_aresetn ),
|
|
261
|
+
/* input */ .in (s00.axi_awlock ),
|
|
262
|
+
/* output */ .raising (awlock_raising ),
|
|
263
|
+
/* output */ .falling (awlock_falling )
|
|
264
|
+
);
|
|
265
|
+
|
|
266
|
+
//---<< LOCK >>------------
|
|
267
|
+
logic [NSIZE-1:0] bsw_path;
|
|
268
|
+
logic bsw_vld;
|
|
269
|
+
|
|
270
|
+
always@(posedge clock,negedge rst_n)
|
|
271
|
+
if(~rst_n) bsw_path <= {NSIZE{1'd0}};
|
|
272
|
+
else begin
|
|
273
|
+
if(s00.axi_awvalid && s00.axi_awready)
|
|
274
|
+
bsw_path <= {1'b0,s00.axi_awaddr[SLAVER_ASIZE-1-:NSIZE]};
|
|
275
|
+
else bsw_path <= bsw_path;
|
|
276
|
+
end
|
|
277
|
+
|
|
278
|
+
always@(posedge clock,negedge rst_n)
|
|
279
|
+
if(~rst_n) bsw_vld <= 1'd0;
|
|
280
|
+
else begin
|
|
281
|
+
if(s00.axi_awvalid && s00.axi_awready)
|
|
282
|
+
bsw_vld <= 1'b1;
|
|
283
|
+
else if(s00.axi_bvalid && s00.axi_bready && !s00.axi_awlock)
|
|
284
|
+
bsw_vld <= 1'b0;
|
|
285
|
+
else if(awlock_falling && !wstatus)
|
|
286
|
+
bsw_vld <= 1'b0;
|
|
287
|
+
else bsw_vld <= bsw_vld;
|
|
288
|
+
end
|
|
289
|
+
|
|
290
|
+
data_inf #(.DSIZE(2) ) s00_bdata_inf [NUM-1:0]();
|
|
291
|
+
data_inf #(.DSIZE(2) ) m00_bdata_inf ();
|
|
292
|
+
|
|
293
|
+
generate
|
|
294
|
+
for(KK=0;KK<NUM;KK++)begin
|
|
295
|
+
assign s00_bdata_inf[KK].data = m00[KK].axi_bresp;
|
|
296
|
+
assign s00_bdata_inf[KK].valid = m00[KK].axi_bvalid;
|
|
297
|
+
assign m00[KK].axi_bready = s00_bdata_inf[KK].ready ;
|
|
298
|
+
end
|
|
299
|
+
endgenerate
|
|
300
|
+
|
|
301
|
+
assign s00.axi_bresp = m00_bdata_inf.data;
|
|
302
|
+
assign s00.axi_bvalid = m00_bdata_inf.valid;
|
|
303
|
+
assign m00_bdata_inf.ready = s00.axi_bready;
|
|
304
|
+
|
|
305
|
+
data_pipe_interconnect_M2S #(
|
|
306
|
+
.NUM (NUM )
|
|
307
|
+
// .DSIZE (2 )
|
|
308
|
+
)resp_data_pipe_interconnect_inst(
|
|
309
|
+
/* input */ .clock (clock ),
|
|
310
|
+
/* input */ .rst_n (rst_n ),
|
|
311
|
+
/* input */ .clk_en (1'b1 ),
|
|
312
|
+
/* input */ .vld_sw (bsw_vld ),
|
|
313
|
+
/* input [2:0] */ .sw (bsw_path ),
|
|
314
|
+
/* output logic[2:0] */ .curr_path (),
|
|
315
|
+
|
|
316
|
+
/* data_inf.slaver */ .s00 (s00_bdata_inf[NUM-1:0] ),
|
|
317
|
+
/* data_inf.master */ .m00 (m00_bdata_inf )
|
|
318
|
+
);
|
|
319
|
+
|
|
320
|
+
//---<< RD DATA CHANNEL >>-------------------
|
|
321
|
+
|
|
322
|
+
endmodule
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|
|
File without changes
|