axi_tdl 0.0.8 → 0.0.15

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Files changed (49) hide show
  1. checksums.yaml +4 -4
  2. data/.github/workflows/gem-push.yml +42 -0
  3. data/.github/workflows/ruby.yml +35 -0
  4. data/.gitignore +3 -1
  5. data/.travis.yml +9 -0
  6. data/Gemfile +4 -0
  7. data/README.EN.md +322 -0
  8. data/README.md +25 -20
  9. data/Rakefile +2 -6
  10. data/axi_tdl.gemspec +5 -5
  11. data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
  12. data/lib/axi/AXI4/axi4_dpram_cache.sv +4 -4
  13. data/lib/axi/AXI4/axis_to_axi4_wr.rb +5 -0
  14. data/lib/axi/AXI4/axis_to_axi4_wr.sv +7 -7
  15. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +1 -1
  16. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
  17. data/lib/axi/AXI_stream/axi_stream_latency.sv +56 -0
  18. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +20 -20
  19. data/lib/axi/AXI_stream/axis_head_cut_verc.rb +98 -42
  20. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +36 -39
  21. data/lib/axi/AXI_stream/axis_insert_copy.sv +1 -1
  22. data/lib/axi/AXI_stream/axis_length_split_with_user.sv +87 -0
  23. data/lib/axi/AXI_stream/axis_pipe_sync_seam.rb +41 -0
  24. data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
  25. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +37 -16
  26. data/lib/axi/AXI_stream/parse_big_field_table_A2.sv +3 -2
  27. data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv +1 -1
  28. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync.sv +70 -0
  29. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.rb +49 -0
  30. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +84 -0
  31. data/lib/axi_tdl.rb +12 -0
  32. data/lib/axi_tdl/version.rb +1 -1
  33. data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +1 -0
  34. data/lib/tdl/SDL/path_lib.rb +1 -1
  35. data/lib/tdl/SDL/vcs_axi4_comptable.rb +9 -0
  36. data/lib/tdl/SDL/vcs_axis_comptable.rb +17 -0
  37. data/lib/tdl/SDL/vcs_data_c_comptable.rb +9 -0
  38. data/lib/tdl/class_hdl/hdl_always_ff.rb +1 -1
  39. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +15 -3
  40. data/lib/tdl/examples/2_hdl_class/module_def.rb +2 -1
  41. data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +3 -1
  42. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +1 -1
  43. data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +2 -2
  44. data/lib/tdl/sdlmodule/sdlmodule.rb +64 -0
  45. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +2 -1
  46. data/lib/tdl/sdlmodule/top_module.rb +1 -0
  47. data/lib/tdl/tdl.rb +14 -2
  48. metadata +128 -28
  49. data/Gemfile.lock +0 -28
@@ -0,0 +1,49 @@
1
+ require_hdl 'data_c_pipe_sync.sv'
2
+
3
+ TdlBuild.data_c_pipe_sync_seam(__dir__) do
4
+ parameter.LAT 4
5
+ parameter.DSIZE 32
6
+ ## as like: hdl```
7
+ ## assign in_datas[0] = in_inf.data + 1;
8
+ ## assign in_datas[1] = out_datas[0]+1;```
9
+ input[param.LAT,param.DSIZE] - 'in_datas'
10
+ output[param.LAT,param.DSIZE] - 'out_datas'
11
+ port.data_inf_c.slaver - 'in_inf'
12
+ port.data_inf_c.master - 'out_inf'
13
+
14
+ same_clock_domain(in_inf, out_inf)
15
+
16
+ in_inf.copy(name: 'in_inf_array', dimension: [param.LAT])
17
+ out_inf.copy(name: 'out_inf_array', dimension: [param.LAT])
18
+
19
+ generate(param.LAT) do |kk|
20
+ data_c_pipe_sync.data_c_pipe_sync_inst do |h|
21
+ h.parameter.DSIZE param.DSIZE
22
+ h.input['DSIZE'].in_data in_datas[kk] ##// as like: hdl``` assign in_data = in_inf.data + 1;
23
+ h.output['DSIZE'].out_data out_datas[kk]
24
+ h.port.data_inf_c.slaver.in_inf in_inf_array[kk]
25
+ h.port.data_inf_c.master.out_inf out_inf_array[kk]
26
+ end
27
+
28
+ IF kk != 0 do
29
+ Assign do
30
+ in_inf_array[kk].valid <= out_inf_array[kk-1].valid
31
+ in_inf_array[kk].data <= out_inf_array[kk-1].data
32
+ out_inf_array[kk-1].ready <= in_inf_array[kk].ready
33
+ end
34
+ end
35
+ end
36
+
37
+ Assign do
38
+ in_inf_array[0].valid <= in_inf.valid
39
+ in_inf_array[0].data <= in_inf.data
40
+ in_inf.ready <= in_inf_array[0].ready
41
+ end
42
+
43
+ Assign do
44
+ out_inf.data <= out_inf_array[param.LAT-1].data
45
+ out_inf.valid <= out_inf_array[param.LAT-1].valid
46
+ out_inf_array[param.LAT-1].ready <= out_inf.ready
47
+ end
48
+
49
+ end
@@ -0,0 +1,84 @@
1
+ /**********************************************
2
+ _______________________________________
3
+ ___________ Cook Darwin __________
4
+ _______________________________________
5
+ descript:
6
+ author : Cook.Darwin
7
+ Version: VERA.0.0
8
+ created: xxxx.xx.xx
9
+ madified:
10
+ ***********************************************/
11
+ `timescale 1ns/1ps
12
+
13
+ module data_c_pipe_sync_seam #(
14
+ parameter LAT = 4,
15
+ parameter DSIZE = 32
16
+ )(
17
+ input [ DSIZE-1:0] in_datas [LAT-1:0],
18
+ output [ DSIZE-1:0] out_datas [LAT-1:0],
19
+ data_inf_c.slaver in_inf,
20
+ data_inf_c.master out_inf
21
+ );
22
+
23
+ //==========================================================================
24
+ //-------- define ----------------------------------------------------------
25
+
26
+ data_inf_c #(.DSIZE(in_inf.DSIZE)) in_inf_array[LAT-1:0] (.clock(in_inf.clock),.rst_n(in_inf.rst_n)) ;
27
+ data_inf_c #(.DSIZE(out_inf.DSIZE)) out_inf_array[LAT-1:0] (.clock(out_inf.clock),.rst_n(out_inf.rst_n)) ;
28
+ //==========================================================================
29
+ //-------- instance --------------------------------------------------------
30
+
31
+ //==========================================================================
32
+ //-------- expression ------------------------------------------------------
33
+ generate
34
+ for(genvar KK0=0;KK0 < LAT;KK0++)begin
35
+ data_c_pipe_sync #(
36
+ .DSIZE (DSIZE )
37
+ )data_c_pipe_sync_inst(
38
+ /* input */.in_data (in_datas[ KK0] ),
39
+ /* output */.out_data (out_datas[ KK0] ),
40
+ /* data_inf_c.slaver */.in_inf (in_inf_array[ KK0] ),
41
+ /* data_inf_c.master */.out_inf (out_inf_array[ KK0] )
42
+ );
43
+ if( KK0!=0)begin
44
+ assign in_inf_array[ KK0].valid = out_inf_array[ KK0-1].valid;
45
+ assign in_inf_array[ KK0].data = out_inf_array[ KK0-1].data;
46
+ assign out_inf_array[ KK0-1].ready = in_inf_array[ KK0].ready;
47
+ end end
48
+ endgenerate
49
+ //-------- CLOCKs Total 2 ----------------------
50
+ //--->> CheckClock <<----------------
51
+ logic cc_done_10,cc_same_10;
52
+ integer cc_afreq_10,cc_bfreq_10;
53
+ ClockSameDomain CheckPClock_inst_10(
54
+ /* input */ .aclk (in_inf.clock ),
55
+ /* input */ .bclk (out_inf.clock ),
56
+ /* output logic */ .done (cc_done_10),
57
+ /* output logic */ .same (cc_same_10),
58
+ /* output integer */ .aFreqK (cc_afreq_10),
59
+ /* output integer */ .bFreqK (cc_bfreq_10)
60
+ );
61
+
62
+ initial begin
63
+ wait(cc_done_10);
64
+ assert(cc_same_10)
65
+ else begin
66
+ $error("--- Error : `data_c_pipe_sync_seam` clock is not same, in_inf.clock< %0f M> != out_inf.clock<%0f M>",1000000.0/cc_afreq_10, 1000000.0/cc_bfreq_10);
67
+ repeat(10)begin
68
+ @(posedge in_inf.clock);
69
+ end
70
+ $stop;
71
+ end
72
+ end
73
+ //---<< CheckClock >>----------------
74
+
75
+ //======== CLOCKs Total 2 ======================
76
+ assign in_inf_array[0].valid = in_inf.valid;
77
+ assign in_inf_array[0].data = in_inf.data;
78
+ assign in_inf.ready = in_inf_array[0].ready;
79
+
80
+ assign out_inf.data = out_inf_array[ LAT-1].data;
81
+ assign out_inf.valid = out_inf_array[ LAT-1].valid;
82
+ assign out_inf_array[ LAT-1].ready = out_inf.ready;
83
+
84
+ endmodule
data/lib/axi_tdl.rb CHANGED
@@ -8,8 +8,20 @@ end
8
8
 
9
9
 
10
10
  add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI_stream"))
11
+ add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI_stream/data_width"))
11
12
  add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI_stream/stream_cache"))
13
+ add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI_stream/packet_fifo"))
12
14
  add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI4"))
15
+ add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI4/axi4_pipe"))
16
+ add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI4/interconnect"))
17
+ add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI4/width_convert"))
13
18
  add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/AXI4/packet_partition"))
19
+ add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/common_fifo"))
14
20
  add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/common"))
15
21
  add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/data_interface"))
22
+ add_to_tdl_paths File.expand_path(File.join(__dir__, "axi/data_interface/data_inf_c"))
23
+
24
+ ## base require
25
+ require_hdl 'axis_master_empty.sv'
26
+ require_hdl 'axis_slaver_empty.sv'
27
+
@@ -1,3 +1,3 @@
1
1
  module AxiTdl
2
- VERSION = "0.0.8"
2
+ VERSION = "0.0.15"
3
3
  end
@@ -6,6 +6,7 @@ self.real_sv_path = '/home/CookDarwin/work/fpga/axi/AXI_stream/packet_fifo/axi_s
6
6
  self.path = File.expand_path(__FILE__)
7
7
  parameter.DEPTH 2
8
8
  parameter.BYTE_DEPTH 8096
9
+ parameter.USE_KEEP "OFF"
9
10
  port.axi_stream_inf.slaver - 'axis_in'
10
11
  port.axi_stream_inf.master - 'axis_out'
11
12
  end
@@ -2,5 +2,5 @@
2
2
  require_relative "./../global_scan"
3
3
  curr = File.expand_path(__FILE__)
4
4
  curr_path = File.dirname(curr)
5
- require_path(curr_path)
5
+ # require_path(curr_path)
6
6
  # require_path_and_ignore(curr_path,"logic_condition.rb")
@@ -0,0 +1,9 @@
1
+ sm = SdlModule.new(name:File.basename(__FILE__,".rb"))
2
+
3
+ sm.Parameter("ORIGIN",'master')
4
+ sm.Parameter("TO",'slaver')
5
+ sm.Input("origin")
6
+ sm.Output("to")
7
+
8
+ sm.origin_sv = true
9
+ sm.real_sv_path = File.expand_path(File.join(__dir__, "../../axi/AXI4/vcs_axi4_comptable.sv"))
@@ -0,0 +1,17 @@
1
+ # sm = SdlModule.new(name:File.basename(__FILE__,".rb"))
2
+
3
+ # sm.Parameter("ORIGIN",'master')
4
+ # sm.Parameter("TO",'slaver')
5
+ # sm.Input("origin")
6
+ # sm.Output("to")
7
+
8
+ # sm.origin_sv = true
9
+
10
+ sm = TdlBuild.vcs_axis_comptable do
11
+ parameter.ORIGIN 'master'
12
+ parameter.TO 'slaver'
13
+ input - 'origin'
14
+ output - 'to'
15
+ end
16
+
17
+ sm.real_sv_path = File.expand_path(File.join(__dir__, "../../axi/AXI_stream/vcs_axis_comptable.sv"))
@@ -0,0 +1,9 @@
1
+ sm = SdlModule.new(name:File.basename(__FILE__,".rb"))
2
+
3
+ sm.Parameter("ORIGIN",'master')
4
+ sm.Parameter("TO",'slaver')
5
+ sm.Input("origin")
6
+ sm.Output("to")
7
+
8
+ sm.origin_sv = true
9
+ sm.real_sv_path = File.expand_path(File.join(__dir__, "../../axi/data_interface/data_inf_c/vcs_data_c_comptable.sv"))
@@ -153,7 +153,7 @@ class SdlModule
153
153
 
154
154
  def always_ff(*args,&block)
155
155
  if args[0].is_a? Hash
156
- return Always(args[0],&block)
156
+ return Always(**args[0],&block)
157
157
  end
158
158
  posedge_list = []
159
159
  negedge_list = []
@@ -58,9 +58,21 @@ module ClassHDL
58
58
  # 计算生成新的OpertorChain 是 self 也需要抛弃
59
59
  self.slaver = true
60
60
  # return self
61
- new_op = OpertorChain.new
62
- new_op.tree = new_op.tree + self.tree
63
- new_op.tree.push [b,os]
61
+ new_op = nil
62
+ AssignDefOpertor.with_rollback_opertors(:old) do
63
+ if tree.size == 2 && tree.last[1].to_s == "<="
64
+ new_op = OpertorChain.new
65
+ new_op.tree = new_op.tree + self.tree
66
+ new_op.tree.push [b,os]
67
+ elsif tree.size >= 2 && (!['*',"/","~"].include?(tree.last[1].to_s))
68
+ new_op = brackets
69
+ new_op.tree.push [b,os]
70
+ else
71
+ new_op = OpertorChain.new
72
+ new_op.tree = new_op.tree + self.tree
73
+ new_op.tree.push [b,os]
74
+ end
75
+ end
64
76
 
65
77
  if ClassHDL::AssignDefOpertor.curr_assign_block
66
78
  ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op)
@@ -1,5 +1,6 @@
1
- require_relative '../../tdl.rb'
1
+ require 'axi_tdl'
2
2
  # require_relative "./../../class_hdl/hdl_module_def.rb"
3
+ require_hdl 'axi_stream_cache_35bit.sv'
3
4
 
4
5
  TdlBuild.test_module(File.join(__dir__,"tmp")) do
5
6
  input.clock - 'clock'
@@ -1,4 +1,6 @@
1
- require_relative '../../tdl.rb'
1
+ require 'axi_tdl'
2
+ require_hdl 'axi_stream_cache.sv'
3
+ require_hdl 'axis_append_A1.sv'
2
4
 
3
5
  TdlBuild.test_inst_sugar(File.join(__dir__,"tmp")) do
4
6
 
@@ -29,7 +29,7 @@ data_inf_c #(.DSIZE(8)) c_inf [2:0][6:0][7:0] (.clock(dclk),.rst_n(drstn)) ;
29
29
  //==========================================================================
30
30
  //-------- expression ------------------------------------------------------
31
31
  always_ff@(posedge clock,negedge rst_n) begin
32
- 32*2- 5- 6;
32
+ ( 32*2- 5)-6;
33
33
  end
34
34
 
35
35
  endmodule
@@ -35,7 +35,7 @@ function status(input [7:0] code,output logic [15:0] pl);
35
35
  endfunction:status
36
36
 
37
37
  function logic status_xp(input [7:0] code,output logic [15:0] pl);
38
- status_xp = ( inm!=0| ( inm!=1));
38
+ status_xp = ( ( inm!=0)|( inm!=1));
39
39
  endfunction:status_xp
40
40
 
41
41
  function SE_STATE_ctrl pre_status(input [7:0] code,output logic [15:0] pl,input SE_STATE_ctrl ll);
@@ -47,6 +47,6 @@ endfunction:pre_status
47
47
 
48
48
  assign gp = status(67, gp+1,opop);
49
49
  assign gp = pre_status();
50
- assign gp = ( inm!=0| ( inm!=1));
50
+ assign gp = ( ( inm!=0)|( inm!=1));
51
51
 
52
52
  endmodule
@@ -404,4 +404,68 @@ class SdlModule
404
404
 
405
405
  Clock.same_clock(self, *objs_clks)
406
406
  end
407
+ end
408
+
409
+ ## 获取 引用的所有文件
410
+ class SdlModule
411
+
412
+ def __ref_children_modules__
413
+ curr_refs = []
414
+
415
+ @_import_packages_ ||= []
416
+ curr_refs << @_import_packages_
417
+
418
+ instance_and_children_module.values.each do |pm|
419
+ curr_refs << [pm, pm.__ref_children_modules__()]
420
+ end
421
+
422
+ return curr_refs
423
+ end
424
+
425
+ def ref_modules
426
+
427
+ curr_refs = __ref_children_modules__.flatten.uniq.reject do |e|
428
+ e.is_a?(ClassHDL::ClearSdlModule)
429
+ end
430
+ curr_refs << self
431
+ end
432
+
433
+ def self.base_hdl_ref
434
+ ## 基本接口引用
435
+ _base_refs = []
436
+ _base_refs << ['axi_inf', File.expand_path(File.join(__dir__, "../../axi/interface_define/axi_inf.sv"))]
437
+ _base_refs << ['axi_lite_inf', File.expand_path(File.join(__dir__, "../../axi/interface_define/axi_lite_inf.sv"))]
438
+ _base_refs << ['axi_stream', File.expand_path(File.join(__dir__, "../../axi/interface_define/axi_stream_inf.sv"))]
439
+ _base_refs << ['data_inf', File.expand_path(File.join(__dir__, "../../axi/data_interface/data_interface.sv"))]
440
+ _base_refs << ['data_inf_c', File.expand_path(File.join(__dir__, "../../axi/data_interface/data_interface_pkg.sv"))]
441
+ _base_refs << ['axi_bfm_pkg', File.expand_path(File.join(__dir__, "../../axi/AXI_BFM/AXI_BFM_PKG.sv"))]
442
+ _base_refs << ['cm_ram_inf', File.expand_path(File.join(__dir__, "../../tdl/rebuild_ele/cm_ram_inf.sv"))]
443
+ _base_refs << ['Lite_Addr_Data_CMD', File.expand_path(File.join(__dir__, "../../axi/AXI_Lite/gen_axi_lite_ctrl.sv"))]
444
+ _base_refs
445
+ end
446
+
447
+ def pretty_ref_hdl_moduls_echo
448
+ index = 1
449
+ _indexs = []
450
+ _names = []
451
+ _paths = []
452
+ max_size = 0
453
+ ref_modules.each do |e|
454
+ _indexs << index
455
+ _names << e.module_name
456
+ _paths << File.expand_path(e.real_sv_path)
457
+ index += 1
458
+ if e.module_name.size > max_size
459
+ max_size = e.module_name.size
460
+ end
461
+ end
462
+ puts(pagination(" Modules of <#{module_name}> reference"))
463
+
464
+ # fstr = "[%#{index.to_s.size}d] %-#{ _names.map do |e| e.size end.max }s %s"
465
+ fstr = "[%#{index.to_s.size}d] %-#{ max_size }s %s"
466
+
467
+ (index-1).times do |xi|
468
+ puts (fstr % [_indexs[xi], _names[xi], _paths[xi]])
469
+ end
470
+ end
407
471
  end
@@ -6,11 +6,12 @@ class Tdl
6
6
  end
7
7
 
8
8
  def self.head_logo=(a)
9
+ $__sdlmodule_head_logo__ = a
9
10
  @@__head_logo__ = a
10
11
  end
11
12
  end
12
13
 
13
- $__sdlmodule_head_logo__ = Tdl.head_logo || File.open(File.join(__dir__,"sdlmodule_head_logo.txt")).read
14
+ $__sdlmodule_head_logo__ = File.open(File.join(__dir__,"sdlmodule_head_logo.txt")).read
14
15
 
15
16
  class SdlModule
16
17
  attr_accessor :origin_sv
@@ -541,3 +541,4 @@ class SdlModule
541
541
  end
542
542
 
543
543
 
544
+
data/lib/tdl/tdl.rb CHANGED
@@ -89,7 +89,11 @@ require_relative "./exlib/itegration"
89
89
  require_relative "./exlib/itegration_verb"
90
90
  require_relative "./exlib/parse_argv"
91
91
  # require_relative "./tdlmodule_ex"
92
- require_relative "./SDL/path_lib" # require sdlmodule
92
+ # require_relative "./SDL/path_lib" # require sdlmodule
93
+ ## VSC COMPATABLE support
94
+ require_relative "./SDL/vcs_axi4_comptable.rb"
95
+ require_relative "./SDL/vcs_data_c_comptable.rb"
96
+ require_relative "./SDL/vcs_axis_comptable.rb"
93
97
 
94
98
  ## 添加 M2S方法
95
99
  require_relative "./axi_stream/axi_stream_interconnect.rb"
@@ -123,7 +127,7 @@ require_relative "./exlib/dve_tcl.rb"
123
127
 
124
128
  ## === INIT BLOCK Methods =====
125
129
  $argvs_hash = {}
126
- $argvs_hash = Parser.parse($TdlARGV || ARGV) unless $_child_argv_
130
+ $argvs_hash = Parser.parse($TdlARGV || ARGV)
127
131
  TopModule.sim = $argvs_hash[:sim]
128
132
 
129
133
  class Tdl
@@ -254,6 +258,14 @@ class Tdl
254
258
  puts TopModule.current.test_unit.echo_units if TopModule.current
255
259
  puts(pagination("SUMMARY"))
256
260
  puts "#{TopModule.sim ? 'SIM' : 'SYNTH'} RUN SPEND #{Time.now - $__start_time__} sec @ TIME : #{Time.now}"
261
+
262
+ ## -----------
263
+ # TopModule.current.ref_modules.uniq.each do |e|
264
+ # unless e.is_a? ClassHDL::ClearSdlModule
265
+ # puts "#{e.real_sv_path}: #{e.module_name}"
266
+ # end
267
+ # end
268
+ ## ===========
257
269
  end
258
270
 
259
271
  end
metadata CHANGED
@@ -1,29 +1,15 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: axi_tdl
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.0.8
4
+ version: 0.0.15
5
5
  platform: ruby
6
6
  authors:
7
7
  - Cook.Darwin
8
8
  autorequire:
9
9
  bindir: exe
10
10
  cert_chain: []
11
- date: 2021-02-23 00:00:00.000000000 Z
11
+ date: 2021-03-14 00:00:00.000000000 Z
12
12
  dependencies:
13
- - !ruby/object:Gem::Dependency
14
- name: bundler
15
- requirement: !ruby/object:Gem::Requirement
16
- requirements:
17
- - - "~>"
18
- - !ruby/object:Gem::Version
19
- version: '1.16'
20
- type: :development
21
- prerelease: false
22
- version_requirements: !ruby/object:Gem::Requirement
23
- requirements:
24
- - - "~>"
25
- - !ruby/object:Gem::Version
26
- version: '1.16'
27
13
  - !ruby/object:Gem::Dependency
28
14
  name: rake
29
15
  requirement: !ruby/object:Gem::Requirement
@@ -42,43 +28,46 @@ dependencies:
42
28
  name: pry
43
29
  requirement: !ruby/object:Gem::Requirement
44
30
  requirements:
45
- - - ">="
31
+ - - "~>"
46
32
  - !ruby/object:Gem::Version
47
- version: '0'
33
+ version: '0.11'
48
34
  type: :development
49
35
  prerelease: false
50
36
  version_requirements: !ruby/object:Gem::Requirement
51
37
  requirements:
52
- - - ">="
38
+ - - "~>"
53
39
  - !ruby/object:Gem::Version
54
- version: '0'
40
+ version: '0.11'
55
41
  - !ruby/object:Gem::Dependency
56
42
  name: minitest
57
43
  requirement: !ruby/object:Gem::Requirement
58
44
  requirements:
59
- - - ">="
45
+ - - "~>"
60
46
  - !ruby/object:Gem::Version
61
- version: '0'
47
+ version: '5.10'
62
48
  type: :development
63
49
  prerelease: false
64
50
  version_requirements: !ruby/object:Gem::Requirement
65
51
  requirements:
66
- - - ">="
52
+ - - "~>"
67
53
  - !ruby/object:Gem::Version
68
- version: '0'
69
- description: 'tdl is a hardware Construction language, it like chisel, but more intresting.
70
- It is a DSL and base on ruby. Finally, it convert to systemverilog. '
54
+ version: '5.10'
55
+ description: 'tdl 是一种硬件构造语言, chisel类似, 但是更加有趣, 他是一种基于Ruby的DSL. 最终它会编译输出systemverilog
56
+ '
71
57
  email:
72
58
  - cook_darwin@hotmail.com
73
59
  executables: []
74
60
  extensions: []
75
61
  extra_rdoc_files: []
76
62
  files:
63
+ - ".github/workflows/gem-push.yml"
64
+ - ".github/workflows/ruby.yml"
77
65
  - ".gitignore"
66
+ - ".travis.yml"
78
67
  - CODE_OF_CONDUCT.md
79
68
  - Gemfile
80
- - Gemfile.lock
81
69
  - LICENSE
70
+ - README.EN.md
82
71
  - README.md
83
72
  - Rakefile
84
73
  - axi_tdl.gemspec
@@ -214,6 +203,7 @@ files:
214
203
  - lib/axi/AXI_stream/axi_stream_interconnect_S2M_auto.sv
215
204
  - lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_info.sv
216
205
  - lib/axi/AXI_stream/axi_stream_interconnect_S2M_with_keep.sv.bak
206
+ - lib/axi/AXI_stream/axi_stream_latency.sv
217
207
  - lib/axi/AXI_stream/axi_stream_packet_fifo_with_info.sv.bak
218
208
  - lib/axi/AXI_stream/axi_stream_partition.sv
219
209
  - lib/axi/AXI_stream/axi_stream_partition_A1.sv
@@ -252,12 +242,15 @@ files:
252
242
  - lib/axi/AXI_stream/axis_length_fill.sv
253
243
  - lib/axi/AXI_stream/axis_length_split.sv
254
244
  - lib/axi/AXI_stream/axis_length_split_with_addr.sv
245
+ - lib/axi/AXI_stream/axis_length_split_with_user.sv
255
246
  - lib/axi/AXI_stream/axis_length_split_writh_user.sv
256
247
  - lib/axi/AXI_stream/axis_link_trigger.sv
257
248
  - lib/axi/AXI_stream/axis_master_empty.sv
258
249
  - lib/axi/AXI_stream/axis_mirror_to_master.sv
259
250
  - lib/axi/AXI_stream/axis_mirrors.sv
260
251
  - lib/axi/AXI_stream/axis_orthogonal.sv
252
+ - lib/axi/AXI_stream/axis_pipe_sync_seam.rb
253
+ - lib/axi/AXI_stream/axis_pipe_sync_seam.sv
261
254
  - lib/axi/AXI_stream/axis_ram_buffer.sv
262
255
  - lib/axi/AXI_stream/axis_rom_contect.rb
263
256
  - lib/axi/AXI_stream/axis_rom_contect.sv
@@ -399,6 +392,9 @@ files:
399
392
  - lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_addr.sv
400
393
  - lib/axi/data_interface/data_inf_c/data_c_pipe_intc_M2S_verc_with_id.sv
401
394
  - lib/axi/data_interface/data_inf_c/data_c_pipe_latency.sv
395
+ - lib/axi/data_interface/data_inf_c/data_c_pipe_sync.sv
396
+ - lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.rb
397
+ - lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv
402
398
  - lib/axi/data_interface/data_inf_c/data_c_scaler.sv
403
399
  - lib/axi/data_interface/data_inf_c/data_c_scaler_A1.sv
404
400
  - lib/axi/data_interface/data_inf_c/data_c_tmp_cache.sv
@@ -807,6 +803,9 @@ files:
807
803
  - lib/tdl/SDL/fifo/independent_clock_fifo_sdl.rb
808
804
  - lib/tdl/SDL/fifo/independent_stack_sdl.rb
809
805
  - lib/tdl/SDL/path_lib.rb
806
+ - lib/tdl/SDL/vcs_axi4_comptable.rb
807
+ - lib/tdl/SDL/vcs_axis_comptable.rb
808
+ - lib/tdl/SDL/vcs_data_c_comptable.rb
810
809
  - lib/tdl/VideoInf/simple_video_gen.rb
811
810
  - lib/tdl/VideoInf/video_from_axi4.rb
812
811
  - lib/tdl/VideoInf/video_lib.rb
@@ -819,7 +818,108 @@ files:
819
818
  - lib/tdl/auto_script/import_sdl.rb
820
819
  - lib/tdl/auto_script/test_autogensdl.rb
821
820
  - lib/tdl/auto_script/tmp.rb
821
+ - lib/tdl/auto_script/tmp/TPU_reprogram_wrapper_verb_sdl.rb
822
+ - lib/tdl/auto_script/tmp/acce_iic_bus_upgrade_sdl.rb
823
+ - lib/tdl/auto_script/tmp/arp_tpu_wrapper_sdl.rb
824
+ - lib/tdl/auto_script/tmp/axi4_direct_verc_sdl.rb
825
+ - lib/tdl/auto_script/tmp/axi4_rd_mix_interconnect_M2S_A2_sdl.rb
826
+ - lib/tdl/auto_script/tmp/axi4_wr_auxiliary_gen_without_resp_sdl.rb
827
+ - lib/tdl/auto_script/tmp/axi4_wr_pipe_sdl.rb
828
+ - lib/tdl/auto_script/tmp/axi_stream_cache_35bit_sdl.rb
829
+ - lib/tdl/auto_script/tmp/axi_stream_cache_A1_sdl.rb
830
+ - lib/tdl/auto_script/tmp/axi_stream_cache_sdl.rb
831
+ - lib/tdl/auto_script/tmp/axi_stream_interconnect_M2S_A1_sdl.rb
832
+ - lib/tdl/auto_script/tmp/axi_stream_interconnect_M2S_bind_tuser_sdl.rb
833
+ - lib/tdl/auto_script/tmp/axi_stream_interconnect_S2M_sdl.rb
834
+ - lib/tdl/auto_script/tmp/axi_stream_latency_sdl.rb
835
+ - lib/tdl/auto_script/tmp/axi_stream_long_fifo_sdl.rb
836
+ - lib/tdl/auto_script/tmp/axi_stream_long_fifo_verb_sdl.rb
837
+ - lib/tdl/auto_script/tmp/axi_stream_packet_fifo_sdl.rb
838
+ - lib/tdl/auto_script/tmp/axi_stream_packet_long_fifo_sdl.rb
839
+ - lib/tdl/auto_script/tmp/axi_stream_planer_sdl.rb
840
+ - lib/tdl/auto_script/tmp/axi_streams_scaler_A1_sdl.rb
841
+ - lib/tdl/auto_script/tmp/axis_append_A1_sdl.rb
842
+ - lib/tdl/auto_script/tmp/axis_connect_pipe_right_shift_sdl.rb
843
+ - lib/tdl/auto_script/tmp/axis_connect_pipe_right_shift_verb_sdl.rb
844
+ - lib/tdl/auto_script/tmp/axis_connect_pipe_sdl.rb
845
+ - lib/tdl/auto_script/tmp/axis_connect_pipe_with_info_sdl.rb
846
+ - lib/tdl/auto_script/tmp/axis_direct_sdl.rb
847
+ - lib/tdl/auto_script/tmp/axis_head_cut_sdl.rb
848
+ - lib/tdl/auto_script/tmp/axis_head_cut_verb_sdl.rb
849
+ - lib/tdl/auto_script/tmp/axis_intc_S2M_with_addr_inf_sdl.rb
850
+ - lib/tdl/auto_script/tmp/axis_length_cut_sdl.rb
851
+ - lib/tdl/auto_script/tmp/axis_length_split_with_addr_sdl.rb
852
+ - lib/tdl/auto_script/tmp/axis_length_split_with_user_sdl.rb
853
+ - lib/tdl/auto_script/tmp/axis_master_empty_sdl.rb
854
+ - lib/tdl/auto_script/tmp/axis_mirror_to_master_sdl.rb
855
+ - lib/tdl/auto_script/tmp/axis_pkt_fifo_filter_keep_A1_sdl.rb
856
+ - lib/tdl/auto_script/tmp/axis_pkt_fifo_filter_keep_sdl.rb
857
+ - lib/tdl/auto_script/tmp/axis_slaver_empty_sdl.rb
858
+ - lib/tdl/auto_script/tmp/axis_uncompress_A1_sdl.rb
859
+ - lib/tdl/auto_script/tmp/axis_valve_sdl.rb
860
+ - lib/tdl/auto_script/tmp/axis_valve_with_pipe_sdl.rb
861
+ - lib/tdl/auto_script/tmp/axis_vector_slaver_empty_sdl.rb
862
+ - lib/tdl/auto_script/tmp/axis_width_combin_A1_sdl.rb
863
+ - lib/tdl/auto_script/tmp/axis_width_convert_sdl.rb
864
+ - lib/tdl/auto_script/tmp/axis_width_destruct_sdl.rb
865
+ - lib/tdl/auto_script/tmp/bits_decode_nc_verb_sdl.rb
866
+ - lib/tdl/auto_script/tmp/bits_decode_verb_sdl.rb
867
+ - lib/tdl/auto_script/tmp/clock_rst_verb_sdl.rb
868
+ - lib/tdl/auto_script/tmp/clock_rst_verc_sdl.rb
869
+ - lib/tdl/auto_script/tmp/common_fifo_sdl.rb
870
+ - lib/tdl/auto_script/tmp/data_c_cache_sdl.rb
871
+ - lib/tdl/auto_script/tmp/data_c_pipe_force_vld_bind_data_sdl.rb
872
+ - lib/tdl/auto_script/tmp/data_c_pipe_sync_sdl.rb
873
+ - lib/tdl/auto_script/tmp/data_inf_c_intc_S2M_sdl.rb
874
+ - lib/tdl/auto_script/tmp/data_inf_c_planer_A1_sdl.rb
875
+ - lib/tdl/auto_script/tmp/data_mirrors_sdl.rb
876
+ - lib/tdl/auto_script/tmp/data_valve_sdl.rb
877
+ - lib/tdl/auto_script/tmp/ethernet_wrapper_sdl.rb
878
+ - lib/tdl/auto_script/tmp/full_axi4_to_axis_partition_wr_rd_sdl.rb
879
+ - lib/tdl/auto_script/tmp/full_axi4_to_axis_sdl.rb
880
+ - lib/tdl/auto_script/tmp/gen_big_field_table_sdl.rb
881
+ - lib/tdl/auto_script/tmp/gen_common_frame_table_sdl.rb
882
+ - lib/tdl/auto_script/tmp/general_tap_ack_A3_sdl.rb
883
+ - lib/tdl/auto_script/tmp/general_tap_ack_sdl.rb
884
+ - lib/tdl/auto_script/tmp/general_tap_no_ack_sdl.rb
885
+ - lib/tdl/auto_script/tmp/gvi_k7_ddr3_ip_wrapper_sdl.rb
822
886
  - lib/tdl/auto_script/tmp/hdl_test_sdl.rb
887
+ - lib/tdl/auto_script/tmp/independent_clock_fifo_sdl.rb
888
+ - lib/tdl/auto_script/tmp/inf_time_delay_ctrl_verb_sdl.rb
889
+ - lib/tdl/auto_script/tmp/init_mac_sdl.rb
890
+ - lib/tdl/auto_script/tmp/ip_check_sum_sdl.rb
891
+ - lib/tdl/auto_script/tmp/k7_ethernet_10g_api_mask_shift_sdl.rb
892
+ - lib/tdl/auto_script/tmp/k7_ethernet_10g_api_sdl.rb
893
+ - lib/tdl/auto_script/tmp/mac_to_file_64b_sdl.rb
894
+ - lib/tdl/auto_script/tmp/mac_to_file_sdl.rb
895
+ - lib/tdl/auto_script/tmp/mdio_model_sdl.rb
896
+ - lib/tdl/auto_script/tmp/odata_pool_axi4_A2_sdl.rb
897
+ - lib/tdl/auto_script/tmp/odata_pool_axi4_A3_sdl.rb
898
+ - lib/tdl/auto_script/tmp/pack_ip_mac_B1_sdl.rb
899
+ - lib/tdl/auto_script/tmp/pack_ip_mac_verb_sdl.rb
900
+ - lib/tdl/auto_script/tmp/parse_big_field_table_A2_sdl.rb
901
+ - lib/tdl/auto_script/tmp/parse_big_field_table_sdl.rb
902
+ - lib/tdl/auto_script/tmp/parse_common_frame_table_A1_sdl.rb
903
+ - lib/tdl/auto_script/tmp/sensor_array_ddr_lvds_wrapper_sdl.rb
904
+ - lib/tdl/auto_script/tmp/sim_arp_tpu_sdl.rb
905
+ - lib/tdl/auto_script/tmp/sim_tpu_update_file_sdl.rb
906
+ - lib/tdl/auto_script/tmp/tcp_check_sum_sdl.rb
907
+ - lib/tdl/auto_script/tmp/tcp_option_split_sdl.rb
908
+ - lib/tdl/auto_script/tmp/time_step_module_A1_sdl.rb
909
+ - lib/tdl/auto_script/tmp/tpu_simple_boot_sdl.rb
910
+ - lib/tdl/auto_script/tmp/trigger_data_inf_c_sdl.rb
911
+ - lib/tdl/auto_script/tmp/udp_check_sum_sdl.rb
912
+ - lib/tdl/auto_script/tmp/udp_ctrl_set_A1_sdl.rb
913
+ - lib/tdl/auto_script/tmp/udp_fpga_ports_route_sdl.rb
914
+ - lib/tdl/auto_script/tmp/udp_socket_ddr_pump_A3_sdl.rb
915
+ - lib/tdl/auto_script/tmp/udp_socket_ddr_pump_verb_sdl.rb
916
+ - lib/tdl/auto_script/tmp/unpack_mac_ip_udp_D1_sdl.rb
917
+ - lib/tdl/auto_script/tmp/unpack_mac_ip_udp_tcp_sdl.rb
918
+ - lib/tdl/auto_script/tmp/unpack_mac_ip_udp_verd_sdl.rb
919
+ - lib/tdl/auto_script/tmp/wide_axis_to_axi4_wr_sdl.rb
920
+ - lib/tdl/auto_script/tmp/width_convert_verb_sdl.rb
921
+ - lib/tdl/auto_script/tmp/xilinx_hdl_dpram_sdl.rb
922
+ - lib/tdl/auto_script/tmp/xilinx_hdl_dpram_sim_sdl.rb
823
923
  - lib/tdl/axi4/axi4_combin_wr_rd_batch_auto.rb
824
924
  - lib/tdl/axi4/axi4_direct.rb
825
925
  - lib/tdl/axi4/axi4_direct_A1_auto.rb
@@ -1283,5 +1383,5 @@ requirements: []
1283
1383
  rubygems_version: 3.0.6
1284
1384
  signing_key:
1285
1385
  specification_version: 4
1286
- summary: Axi is a light weight axi library. Tdl is a hardware Construction language
1386
+ summary: Axi 是一个轻量级的AXI4库. Tdl 是一种硬件构造语言
1287
1387
  test_files: []