axi_tdl 0.0.8 → 0.0.15

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Files changed (49) hide show
  1. checksums.yaml +4 -4
  2. data/.github/workflows/gem-push.yml +42 -0
  3. data/.github/workflows/ruby.yml +35 -0
  4. data/.gitignore +3 -1
  5. data/.travis.yml +9 -0
  6. data/Gemfile +4 -0
  7. data/README.EN.md +322 -0
  8. data/README.md +25 -20
  9. data/Rakefile +2 -6
  10. data/axi_tdl.gemspec +5 -5
  11. data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
  12. data/lib/axi/AXI4/axi4_dpram_cache.sv +4 -4
  13. data/lib/axi/AXI4/axis_to_axi4_wr.rb +5 -0
  14. data/lib/axi/AXI4/axis_to_axi4_wr.sv +7 -7
  15. data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +1 -1
  16. data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
  17. data/lib/axi/AXI_stream/axi_stream_latency.sv +56 -0
  18. data/lib/axi/AXI_stream/axi_stream_split_channel.sv +20 -20
  19. data/lib/axi/AXI_stream/axis_head_cut_verc.rb +98 -42
  20. data/lib/axi/AXI_stream/axis_head_cut_verc.sv +36 -39
  21. data/lib/axi/AXI_stream/axis_insert_copy.sv +1 -1
  22. data/lib/axi/AXI_stream/axis_length_split_with_user.sv +87 -0
  23. data/lib/axi/AXI_stream/axis_pipe_sync_seam.rb +41 -0
  24. data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
  25. data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +37 -16
  26. data/lib/axi/AXI_stream/parse_big_field_table_A2.sv +3 -2
  27. data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv +1 -1
  28. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync.sv +70 -0
  29. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.rb +49 -0
  30. data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +84 -0
  31. data/lib/axi_tdl.rb +12 -0
  32. data/lib/axi_tdl/version.rb +1 -1
  33. data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +1 -0
  34. data/lib/tdl/SDL/path_lib.rb +1 -1
  35. data/lib/tdl/SDL/vcs_axi4_comptable.rb +9 -0
  36. data/lib/tdl/SDL/vcs_axis_comptable.rb +17 -0
  37. data/lib/tdl/SDL/vcs_data_c_comptable.rb +9 -0
  38. data/lib/tdl/class_hdl/hdl_always_ff.rb +1 -1
  39. data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +15 -3
  40. data/lib/tdl/examples/2_hdl_class/module_def.rb +2 -1
  41. data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +3 -1
  42. data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +1 -1
  43. data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +2 -2
  44. data/lib/tdl/sdlmodule/sdlmodule.rb +64 -0
  45. data/lib/tdl/sdlmodule/sdlmodule_draw.rb +2 -1
  46. data/lib/tdl/sdlmodule/top_module.rb +1 -0
  47. data/lib/tdl/tdl.rb +14 -2
  48. metadata +128 -28
  49. data/Gemfile.lock +0 -28
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@@ -0,0 +1,42 @@
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+ name: Ruby Gem
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+
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+ on:
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+ push:
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+ branches: [ main ]
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+ pull_request:
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+ branches: [ main ]
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+
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+ jobs:
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+ build:
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+ name: Build + Publish
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+ runs-on: ubuntu-latest
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+
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+ steps:
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+ - uses: actions/checkout@v2
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+ - name: Set up Ruby 2.6
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+ uses: actions/setup-ruby@v1
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+ with:
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+ ruby-version: 2.6.x
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+
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+ - name: Publish to GPR
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+ run: |
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+ mkdir -p $HOME/.gem
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+ touch $HOME/.gem/credentials
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+ chmod 0600 $HOME/.gem/credentials
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+ printf -- "---\n:github: ${GEM_HOST_API_KEY}\n" > $HOME/.gem/credentials
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+ gem build *.gemspec
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+ gem push --KEY github --host https://rubygems.pkg.github.com/${OWNER} *.gem
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+ env:
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+ GEM_HOST_API_KEY: "Bearer ${{secrets.GITHUB_TOKEN}}"
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+ OWNER: ${{ github.repository_owner }}
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+
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+ - name: Publish to RubyGems
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+ run: |
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+ mkdir -p $HOME/.gem
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+ touch $HOME/.gem/credentials
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+ chmod 0600 $HOME/.gem/credentials
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+ printf -- "---\n:rubygems_api_key: ${GEM_HOST_API_KEY}\n" > $HOME/.gem/credentials
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+ gem build *.gemspec
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+ gem push *.gem
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+ env:
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+ GEM_HOST_API_KEY: "${{secrets.RUBYGEMS_AUTH_TOKEN}}"
@@ -0,0 +1,35 @@
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+ # This workflow uses actions that are not certified by GitHub.
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+ # They are provided by a third-party and are governed by
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+ # separate terms of service, privacy policy, and support
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+ # documentation.
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+ # This workflow will download a prebuilt Ruby version, install dependencies and run tests with Rake
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+ # For more information see: https://github.com/marketplace/actions/setup-ruby-jruby-and-truffleruby
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+
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+ name: Ruby
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+
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+ on:
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+ push:
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+ branches: [ main ]
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+ pull_request:
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+ branches: [ main ]
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+
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+ jobs:
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+ test:
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+
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+ runs-on: ubuntu-latest
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+ strategy:
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+ matrix:
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+ ruby-version: ['2.6', '2.7', '3.0']
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+
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+ steps:
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+ - uses: actions/checkout@v2
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+ - name: Set up Ruby
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+ # To automatically get bug fixes and new Ruby versions for ruby/setup-ruby,
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+ # change this to (see https://github.com/ruby/setup-ruby#versioning):
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+ # uses: ruby/setup-ruby@v1
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+ uses: ruby/setup-ruby@473e4d8fe5dd94ee328fdfca9f8c9c7afc9dae5e
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+ with:
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+ ruby-version: ${{ matrix.ruby-version }}
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+ bundler-cache: true # runs 'bundle install' and caches installed gems automatically
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+ - name: Run tests
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+ run: bundle exec rake test
data/.gitignore CHANGED
@@ -7,4 +7,6 @@
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  /spec/reports/
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  /tmp/
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  .rake_tasks~
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- lib/tdl/auto_script/tmp/
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+ lib/tdl/auto_script/tmp/
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+ /*.gem
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+ Gemfile.lock
data/.travis.yml ADDED
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+ language: ruby
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+ before_install:
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+ - gem install bundler
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+
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+ rvm:
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+ - 2.6
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+ - 3.0
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+
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+ script: rake test
data/Gemfile CHANGED
@@ -4,3 +4,7 @@ git_source(:github) {|repo_name| "https://github.com/#{repo_name}" }
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  # Specify your gem's dependencies in axi_tdl.gemspec
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  gemspec
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+
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+ gem 'rake'
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+ # gem 'minitest',"~> 5.10"
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+ # gem 'pry',"~> 0.11"
data/README.EN.md ADDED
@@ -0,0 +1,322 @@
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+
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+ # AxiTdl
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+ [![Gem Version](https://badge.fury.io/rb/axi_tdl.svg)](https://badge.fury.io/rb/axi_tdl)
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+ [![Build Status](https://travis-ci.com/CookDarwin/axi_tdl.svg?branch=main)](https://travis-ci.com/CookDarwin/axi_tdl)
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+
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+ ## Axi
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+   It is a wonderful library of axi4, but it is not full axi4, It is designed by systemverilog. I compact axi4 and add something to it.
8
+
9
+   axi hdl path
10
+ ```ruby
11
+ require 'axi_tdl'
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+ AxiTdl::AXI_PATH
13
+ ```
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+ ## Other
15
+   It contain a simple interface that only define three signals, `valid`, `ready`, and `data`. I think it is useful for design.
16
+
17
+ ## What is tdl?
18
+   tdl is a hardware Construction language, it like chisel, but more intresting. It is a DSL and base on ruby. Finally, it convert to systemverilog. And it depend on the axi library of my other github respo.
19
+
20
+ ## What tdl can do?
21
+   When you write RTL code by tdl, it look like systemverilog. And not only that, you can verify design by tdl. Even more, you can construct `Logic System`, I think it is main difference between tdl and other hardware Construction languages.
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+
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+ ## Installation
24
+
25
+ Add this line to your application's Gemfile:
26
+
27
+ ```ruby
28
+ gem 'axi_tdl'
29
+ ```
30
+
31
+ And then execute:
32
+
33
+ $ bundle
34
+
35
+ Or install it yourself as:
36
+
37
+ $ gem install axi_tdl
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+
39
+ ## Code Example
40
+
41
+ ### 1. define module
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+ It will create a module of systemverilog that name is `test_module` in current dir.
43
+ ```ruby
44
+ TdlBuild.test_module(__dir__) do
45
+ ## Other code
46
+ end
47
+ ```
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+ the sv file look like this
49
+ ```systemverilog
50
+ `timescale 1ns/1ps
51
+ module test_module(
52
+ );
53
+ endmodule
54
+ ```
55
+ ### 2. ports
56
+ ```ruby
57
+ TdlBuild.test_module(__dir__) do
58
+ input.clock - 'clock'
59
+ input.reset('low') - 'rst_n'
60
+ input - 'd0'
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+ input[32] - 'd32'
62
+ output[16] - 'o16'
63
+ output.logic[8] - 'o8'
64
+ output.logic - 'o1'
65
+ end
66
+ ```
67
+ ```systemverilog
68
+ module test_module (
69
+ input clock,
70
+ input rst_n,
71
+ input d0,
72
+ input [31:0] d32,
73
+ output [15:0] o16,
74
+ output logic[7:0] o8,
75
+ output logic o1
76
+ );
77
+ endmodule
78
+ ```
79
+
80
+ ## 3. interface
81
+ ```ruby
82
+ TdlBuild.test_interface(__dir__) do
83
+
84
+ input.clock - 'clock'
85
+ input.reset('low') - 'rst_n'
86
+ input - 'd0'
87
+ input[32] - 'd32'
88
+ output[16] - 'o16'
89
+ output.logic[8] - 'o8'
90
+ output.logic - 'o1'
91
+
92
+ port.axis.slaver - 'axis_in'
93
+ port.axis.master - 'axis_out'
94
+ port.axis.mirror - 'axis_mirror'
95
+
96
+ port.data_c.master - 'intf_data_inf'
97
+ port.axi4.slaver - 'taxi4_inf'
98
+
99
+ end
100
+ ```
101
+ ```systemverilog
102
+ module test_module (
103
+ input clock,
104
+ input rst_n,
105
+ input d0,
106
+ input [31:0] d32,
107
+ output [15:0] o16,
108
+ output logic[7:0] o8,
109
+ output logic o1,
110
+ axi_stream_inf.slaver axis_in,
111
+ axi_stream_inf.master axis_out,
112
+ axi_stream_inf.mirror axis_mirror,
113
+ data_inf_c.master intf_data_inf,
114
+ axi_inf.slaver taxi4_inf
115
+ );
116
+ end
117
+ ```
118
+ ## 4. always assign
119
+ ```ruby
120
+ TdlBuild.test_module(__dir__) do
121
+ input.clock - 'clock'
122
+ input.reset('low') - 'rst_n'
123
+ input - 'd0'
124
+ input[32] - 'd32'
125
+ output[16] - 'o16'
126
+ output.logic[8] - 'o8'
127
+ output.logic - 'o1'
128
+
129
+ port.axis.slaver - 'axis_in'
130
+ port.axis.master - 'axis_out'
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+ port.axis.mirror - 'axis_mirror'
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+
133
+ port.data_c.master - 'intf_data_inf'
134
+ port.axi4.slaver - 'taxi4_inf'
135
+
136
+
137
+ always_ff(posedge: clock,negedge: rst_n) do
138
+ IF ~rst_n do
139
+ o16 <= 0.A
140
+ end
141
+ ELSE do
142
+ IF d0 do
143
+ o16 <= 1.A
144
+ end
145
+ ELSE do
146
+ o16 <= o16 + 1.b1
147
+ end
148
+ end
149
+ end
150
+
151
+ always_comb do
152
+ o8 <= d32[7,0]
153
+ end
154
+
155
+ Assign do
156
+ o1 <= 1.b0
157
+ end
158
+ end
159
+ ```
160
+ ```systemverilog
161
+ module test_module (
162
+ input clock,
163
+ input rst_n,
164
+ input d0,
165
+ input [31:0] d32,
166
+ output [15:0] o16,
167
+ output logic[7:0] o8,
168
+ output logic o1,
169
+ axi_stream_inf.slaver axis_in,
170
+ axi_stream_inf.master axis_out,
171
+ axi_stream_inf.mirror axis_mirror,
172
+ data_inf_c.master intf_data_inf,
173
+ axi_inf.slaver taxi4_inf
174
+ );
175
+
176
+ always_ff@(posedge clock,negedge rst_n) begin
177
+ if(~rst_n)begin
178
+ o16 <= '0;
179
+ end
180
+ else begin
181
+ if(d0)begin
182
+ o16 <= '1;
183
+ end
184
+ else begin
185
+ o16 <= ( o16+1'b1);
186
+ end
187
+ end
188
+ end
189
+
190
+ always_comb begin
191
+ o8 = d32[7:0];
192
+ end
193
+
194
+ assign o1 = 1'b0;
195
+
196
+ endmodule
197
+ ```
198
+ ## 5. generate
199
+ ```ruby
200
+ TdlBuild.test_generate(__dir__) do
201
+ parameter.NUM 8
202
+ input[8] - 'ain'
203
+ output[8] - 'bout'
204
+
205
+ input[param.NUM,6] - 'cin'
206
+ output[6,param.NUM] - 'dout'
207
+
208
+ input[param.NUM] - 'ein'
209
+ output[param.NUM] - 'fout'
210
+
211
+ generate(8) do |kk|
212
+ Assign do
213
+ bout[kk] <= ain[7-kk]
214
+ end
215
+ end
216
+
217
+ generate(param.NUM) do |cc|
218
+ IF cc < 4 do
219
+ Assign do
220
+ dout[cc] <= cin[cc]
221
+ end
222
+ end
223
+ ELSE do
224
+ Assign do
225
+ dout[cc] <= cin[cc] + cc
226
+ end
227
+ end
228
+ end
229
+
230
+ generate(param.NUM,6) do |ii,gg|
231
+ Assign do
232
+ fout[ii][gg] <= ein[gg][ii]
233
+ end
234
+ end
235
+ end
236
+ ```
237
+ ```systemverilog
238
+ module test_generate #(
239
+ parameter NUM = 8
240
+ )(
241
+ input [7:0] ain,
242
+ output [7:0] bout,
243
+ input [5:0] cin [NUM-1:0],
244
+ output [ NUM-1:0] dout [6-1:0],
245
+ input [ NUM-1:0] ein,
246
+ output [ NUM-1:0] fout
247
+ );
248
+
249
+ generate
250
+ for(genvar KK0=0;KK0 < 8;KK0++)begin
251
+ assign bout[ KK0] = ain[ 7-( KK0)];
252
+ end
253
+ endgenerate
254
+
255
+ generate
256
+ for(genvar KK0=0;KK0 < NUM;KK0++)begin
257
+
258
+ if( KK0<4)begin
259
+ assign dout[ KK0] = cin[ KK0];
260
+ end
261
+ else begin
262
+ assign dout[ KK0] = ( cin[ KK0]+( KK0));
263
+ end
264
+ end
265
+ endgenerate
266
+
267
+ generate
268
+ for(genvar KK0=0;KK0 < NUM;KK0++)begin
269
+ for(genvar KK1=0;KK1 < 6;KK1++)begin
270
+ assign fout[ KK0][ KK1] = ein[ KK1][ KK0];
271
+ end
272
+ end
273
+ endgenerate
274
+
275
+ endmodule
276
+ ```
277
+
278
+ ## 6. combin logic
279
+ ```ruby
280
+ TdlBuild.test_logic_combin(__dir__) do
281
+ logic[7] - 'a0'
282
+ logic[5] - 'a1'
283
+ logic[9] - 'a2'
284
+ logic[9+5+7] - 'ca'
285
+
286
+ logic[2,8] - 'b0'
287
+ logic[16] - 'b1'
288
+ logic[32] - 'cb'
289
+
290
+ logic[1,8] - 'c0'
291
+ logic[3,8] - 'c1'
292
+ logic[2,16] - 'cc'
293
+
294
+ Assign do
295
+ ca <= logic_bind_(a0, a1, a2)
296
+ cb <= self.>>(b1, b0)
297
+ cc <= self.<<(c0, c1)
298
+ end
299
+ end
300
+ ```
301
+ ```systemverilog
302
+ module test_logic_combin ();
303
+
304
+ logic [7-1:0] a0 ;
305
+ logic [5-1:0] a1 ;
306
+ logic [9-1:0] a2 ;
307
+ logic [21-1:0] ca ;
308
+ logic [8-1:0] b0[2-1:0] ;
309
+ logic [16-1:0] b1 ;
310
+ logic [32-1:0] cb ;
311
+ logic [8-1:0] c0[1-1:0] ;
312
+ logic [8-1:0] c1[3-1:0] ;
313
+ logic [16-1:0] cc[2-1:0] ;
314
+
315
+ assign ca = {a0,a1,a2};
316
+ assign cb = {>>{b1,b0}};
317
+ assign cc = {<<{c0,c1}};
318
+
319
+ endmodule
320
+ ```
321
+
322
+
data/README.md CHANGED
@@ -1,52 +1,57 @@
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- # Axi
2
- &emsp;&emsp;It is a wonderful library of axi4, but it is not full axi4, It is designed by systemverilog. I compact axi4 and add something to it.
3
- &emsp;&emsp;axi hdl path
1
+ # AxiTdl
2
+ [![Gem Version](https://badge.fury.io/rb/axi_tdl.svg)](https://badge.fury.io/rb/axi_tdl)
3
+ [![Build Status](https://travis-ci.com/CookDarwin/axi_tdl.svg?branch=main)](https://travis-ci.com/CookDarwin/axi_tdl)
4
+
5
+ ## Axi
6
+ &emsp;&emsp;axi是一个 axi4 拓展库,它使用的是删减版的AXI4协议,使用systemverilog开发,除此外我还拓展了AXI4的一些信号。
7
+
8
+ &emsp;&emsp;axi hdl 所在路径可以如下Ruby 脚本获取
4
9
  ```ruby
5
10
  require 'axi_tdl'
6
11
  AxiTdl::AXI_PATH
7
12
  ```
8
- # Other
9
- &emsp;&emsp;It contain a simple interface that only define three signals, `valid`, `ready`, and `data`. I think it is useful for design.
13
+ ## 其他
14
+ &emsp;&emsp;此库还包含一个简单的接口定义, 接口信号只有 `valid`, `ready`, `data`. 对于一些轻量设计很有帮助。
10
15
 
11
- ## What is tdl?
12
- &emsp;&emsp;tdl is a hardware Construction language, it like chisel, but more intresting. It is a DSL and base on ruby. Finally, it convert to systemverilog. And it depend on the axi library of my other github respo.
16
+ ## tdl 是什么?
17
+ &emsp;&emsp;tdl 是一种硬件构造语言, chisel类似, 但是更加有趣, 他是一种基于Ruby的DSL. 最终它会编译输出systemverilog tdl也是基于axi库做的设计。这两部分都包含这此gem包中。
13
18
 
14
- ## What tdl can do?
15
- &emsp;&emsp;When you write RTL code by tdl, it look like systemverilog. And not only that, you can verify design by tdl. Even more, you can construct `Logic System`, I think it is main difference between tdl and other hardware Construction languages.
19
+ ## tdl 能做什么?
20
+ &emsp;&emsp;使用tdl做设计开发, 语法类似systemverilog,这样更亲切。不止于此, tdl加入了大量的验证语法。tdl创建的初衷就是为了快速构建`逻辑系统`, 这就是tdl和其他硬件构造语言最大的区别。
16
21
 
17
- ## Installation
22
+ ## 安装
18
23
 
19
- Add this line to your application's Gemfile:
24
+ Gemfile中添加:
20
25
 
21
26
  ```ruby
22
27
  gem 'axi_tdl'
23
28
  ```
24
29
 
25
- And then execute:
30
+ 然后执行:
26
31
 
27
32
  $ bundle
28
33
 
29
- Or install it yourself as:
34
+ 或则通过gem命令安装:
30
35
 
31
36
  $ gem install axi_tdl
32
37
 
33
- ## Code Example
38
+ ## 代码示例
34
39
 
35
- ### 1. define module
36
- It will create a module of systemverilog that name is `test_module` in current dir.
40
+ ### 1. 定义模块
41
+ 在当前tdl所在的路径创建一个systemverilog模块文件,模块名为 `test_module`.
37
42
  ```ruby
38
43
  TdlBuild.test_module(__dir__) do
39
44
  ## Other code
40
45
  end
41
46
  ```
42
- the sv file look like this
47
+ 输出的systemverilog 文件如下:
43
48
  ```systemverilog
44
49
  `timescale 1ns/1ps
45
50
  module test_module(
46
51
  );
47
52
  endmodule
48
53
  ```
49
- ### 2. ports
54
+ ### 2. 端口
50
55
  ```ruby
51
56
  TdlBuild.test_module(__dir__) do
52
57
  input.clock - 'clock'
@@ -71,7 +76,7 @@ module test_module (
71
76
  endmodule
72
77
  ```
73
78
 
74
- ## 3. interface
79
+ ## 3. 接口
75
80
  ```ruby
76
81
  TdlBuild.test_interface(__dir__) do
77
82
 
@@ -269,7 +274,7 @@ endgenerate
269
274
  endmodule
270
275
  ```
271
276
 
272
- ## 6. combin logic
277
+ ## 6. 合并 logic
273
278
  ```ruby
274
279
  TdlBuild.test_logic_combin(__dir__) do
275
280
  logic[7] - 'a0'