axi_tdl 0.0.8 → 0.0.15
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/.github/workflows/gem-push.yml +42 -0
- data/.github/workflows/ruby.yml +35 -0
- data/.gitignore +3 -1
- data/.travis.yml +9 -0
- data/Gemfile +4 -0
- data/README.EN.md +322 -0
- data/README.md +25 -20
- data/Rakefile +2 -6
- data/axi_tdl.gemspec +5 -5
- data/lib/axi/AXI4/axi4_dpram_cache.rb +1 -0
- data/lib/axi/AXI4/axi4_dpram_cache.sv +4 -4
- data/lib/axi/AXI4/axis_to_axi4_wr.rb +5 -0
- data/lib/axi/AXI4/axis_to_axi4_wr.sv +7 -7
- data/lib/axi/AXI4/packet_partition/axi4_partition_rd_verb.sv +1 -1
- data/lib/axi/AXI4/packet_partition/data_inf_partition.sv +2 -2
- data/lib/axi/AXI_stream/axi_stream_latency.sv +56 -0
- data/lib/axi/AXI_stream/axi_stream_split_channel.sv +20 -20
- data/lib/axi/AXI_stream/axis_head_cut_verc.rb +98 -42
- data/lib/axi/AXI_stream/axis_head_cut_verc.sv +36 -39
- data/lib/axi/AXI_stream/axis_insert_copy.sv +1 -1
- data/lib/axi/AXI_stream/axis_length_split_with_user.sv +87 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.rb +41 -0
- data/lib/axi/AXI_stream/axis_pipe_sync_seam.sv +48 -0
- data/lib/axi/AXI_stream/packet_fifo/axi_stream_packet_long_fifo.sv +37 -16
- data/lib/axi/AXI_stream/parse_big_field_table_A2.sv +3 -2
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_force_vld_bind_data.sv +1 -1
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync.sv +70 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.rb +49 -0
- data/lib/axi/data_interface/data_inf_c/data_c_pipe_sync_seam.sv +84 -0
- data/lib/axi_tdl.rb +12 -0
- data/lib/axi_tdl/version.rb +1 -1
- data/lib/tdl/SDL/axistream/axi_stream_packet_long_fifo_sdl.rb +1 -0
- data/lib/tdl/SDL/path_lib.rb +1 -1
- data/lib/tdl/SDL/vcs_axi4_comptable.rb +9 -0
- data/lib/tdl/SDL/vcs_axis_comptable.rb +17 -0
- data/lib/tdl/SDL/vcs_data_c_comptable.rb +9 -0
- data/lib/tdl/class_hdl/hdl_always_ff.rb +1 -1
- data/lib/tdl/class_hdl/hdl_redefine_opertor.rb +15 -3
- data/lib/tdl/examples/2_hdl_class/module_def.rb +2 -1
- data/lib/tdl/examples/2_hdl_class/test_inst_sugar.rb +3 -1
- data/lib/tdl/examples/2_hdl_class/tmp/always_ff_test.sv +1 -1
- data/lib/tdl/examples/2_hdl_class/tmp/test_function.sv +2 -2
- data/lib/tdl/sdlmodule/sdlmodule.rb +64 -0
- data/lib/tdl/sdlmodule/sdlmodule_draw.rb +2 -1
- data/lib/tdl/sdlmodule/top_module.rb +1 -0
- data/lib/tdl/tdl.rb +14 -2
- metadata +128 -28
- data/Gemfile.lock +0 -28
@@ -11,7 +11,8 @@ madified:
|
|
11
11
|
`timescale 1ns/1ps
|
12
12
|
|
13
13
|
module axis_head_cut_verc #(
|
14
|
-
parameter BYTE_BITS = 8
|
14
|
+
parameter BYTE_BITS = 8,
|
15
|
+
parameter DX = origin_inf.DSIZE/BYTE_BITS
|
15
16
|
)(
|
16
17
|
input [9:0] bytes,
|
17
18
|
axi_stream_inf.slaver origin_inf,
|
@@ -20,16 +21,19 @@ module axis_head_cut_verc #(
|
|
20
21
|
|
21
22
|
//==========================================================================
|
22
23
|
//-------- define ----------------------------------------------------------
|
23
|
-
localparam DX = origin_inf.DSIZE/BYTE_BITS;
|
24
24
|
logic clock;
|
25
25
|
logic rst_n;
|
26
|
+
logic [18-1:0] origin_sync_info[3-1:0] ;
|
27
|
+
logic [18-1:0] origin_sync_info_out[3-1:0] ;
|
28
|
+
logic [10-1:0] bytes_Q ;
|
29
|
+
logic [10-1:0] bytes_QQ ;
|
26
30
|
logic [4-1:0] bytes_x ;
|
27
31
|
logic [4-1:0] bytes_x_Q ;
|
28
32
|
logic [4-1:0] bytes_x_tmp ;
|
29
33
|
logic [4-1:0] bytes_x_sub_nDx ;
|
34
|
+
logic [4-1:0] bytes_x_sub_nDx_tmp ;
|
30
35
|
logic [2-1:0] route_addr ;
|
31
|
-
logic [
|
32
|
-
logic [10-1:0] tmp_loop ;
|
36
|
+
logic [2-1:0] route_addr_tmp ;
|
33
37
|
logic fifo_wr_en;
|
34
38
|
logic [4-1:0] int_cut_len ;
|
35
39
|
logic [4-1:0] shift_sel_pre ;
|
@@ -41,14 +45,17 @@ axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss (.aclk(origin
|
|
41
45
|
axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_cut_mix (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
|
42
46
|
axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss_E0 (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
|
43
47
|
axi_stream_inf #(.DSIZE(origin_inf.DSIZE),.USIZE(1)) origin_inf_ss_E0_CH (.aclk(origin_inf.aclk),.aresetn(origin_inf.aresetn),.aclken(1'b1)) ;
|
44
|
-
axi_stream_inf #(.DSIZE(out_inf.DSIZE),.USIZE(1))
|
48
|
+
axi_stream_inf #(.DSIZE(out_inf.DSIZE),.USIZE(1)) out_inf_branchR671 (.aclk(out_inf.aclk),.aresetn(out_inf.aresetn),.aclken(1'b1)) ;
|
45
49
|
//==========================================================================
|
46
50
|
//-------- instance --------------------------------------------------------
|
47
|
-
|
48
|
-
.
|
49
|
-
)
|
50
|
-
|
51
|
-
/*
|
51
|
+
axis_pipe_sync_seam #(
|
52
|
+
.LAT (3 ),
|
53
|
+
.DSIZE (18 )
|
54
|
+
)axis_pipe_sync_seam_inst(
|
55
|
+
/* input */.in_datas (origin_sync_info ),
|
56
|
+
/* output */.out_datas (origin_sync_info_out ),
|
57
|
+
/* axi_stream_inf.slaver */.in_inf (origin_inf ),
|
58
|
+
/* axi_stream_inf.master */.out_inf (origin_inf_post )
|
52
59
|
);
|
53
60
|
axi_stream_interconnect_S2M #(
|
54
61
|
.NUM (3 )
|
@@ -115,7 +122,7 @@ axis_connect_pipe_right_shift_verb #(
|
|
115
122
|
axis_head_cut_verb last_cut_inst(
|
116
123
|
/* input */.length (16'd1 ),
|
117
124
|
/* axi_stream_inf.slaver */.axis_in (origin_inf_ss_E0_CH ),
|
118
|
-
/* axi_stream_inf.master */.axis_out (
|
125
|
+
/* axi_stream_inf.master */.axis_out (out_inf_branchR671 )
|
119
126
|
);
|
120
127
|
//==========================================================================
|
121
128
|
//-------- expression ------------------------------------------------------
|
@@ -129,7 +136,7 @@ axis_direct axis_direct_out_inf_inst0 (
|
|
129
136
|
);
|
130
137
|
|
131
138
|
axis_direct axis_direct_out_inf_inst1 (
|
132
|
-
/* axi_stream_inf.slaver*/ .slaver (
|
139
|
+
/* axi_stream_inf.slaver*/ .slaver (out_inf_branchR671),
|
133
140
|
/* axi_stream_inf.master*/ .master (sub_out_inf[1])
|
134
141
|
);
|
135
142
|
|
@@ -160,41 +167,31 @@ always_comb begin
|
|
160
167
|
bytes_x_tmp = '0;
|
161
168
|
for(integer gvar_cc_1=0;gvar_cc_1<10;gvar_cc_1=gvar_cc_1+1)begin
|
162
169
|
if( bytes<DX*(10-gvar_cc_1))begin
|
163
|
-
bytes_x_tmp = ( 10-1-
|
170
|
+
bytes_x_tmp = ( ( 10-1)-gvar_cc_1);
|
164
171
|
end
|
165
172
|
end
|
166
173
|
end
|
167
174
|
|
168
|
-
|
169
|
-
|
170
|
-
|
171
|
-
|
172
|
-
|
175
|
+
assign origin_sync_info[0] = {bytes_x_tmp,bytes_x_tmp,bytes};
|
176
|
+
assign {bytes_x,bytes_Q} = {origin_sync_info_out[0][13:10],origin_sync_info_out[0][9:0]};
|
177
|
+
assign bytes_x_sub_nDx_tmp = ( bytes_Q-( bytes_x*DX));
|
178
|
+
assign origin_sync_info[1] = {bytes_x_sub_nDx_tmp,bytes_x,bytes_Q};
|
179
|
+
assign {bytes_x_sub_nDx,bytes_x_Q,bytes_QQ} = {origin_sync_info_out[1][17:14],origin_sync_info_out[1][13:10],origin_sync_info_out[1][9:0]};
|
180
|
+
assign origin_sync_info[2] = {10'd0,route_addr_tmp};
|
181
|
+
assign route_addr = origin_sync_info_out[2][1:0];
|
182
|
+
|
183
|
+
always_comb begin
|
184
|
+
if( bytes_QQ=='0)begin
|
185
|
+
route_addr_tmp = 2'd0;
|
173
186
|
end
|
174
|
-
else begin
|
175
|
-
|
176
|
-
bytes_x_Q <= bytes_x;
|
177
|
-
bytes_x_sub_nDx <= ( bytes-( bytes_x*DX));
|
187
|
+
else if( bytes_x_Q=='0)begin
|
188
|
+
route_addr_tmp = 2'd2;
|
178
189
|
end
|
179
|
-
|
180
|
-
|
181
|
-
always_ff@(posedge clock,negedge rst_n) begin
|
182
|
-
if(~rst_n)begin
|
183
|
-
route_addr <= '0;
|
190
|
+
else if( bytes_x_sub_nDx=='0)begin
|
191
|
+
route_addr_tmp = 2'd1;
|
184
192
|
end
|
185
193
|
else begin
|
186
|
-
|
187
|
-
route_addr <= 2'd0;
|
188
|
-
end
|
189
|
-
else if( bytes_x=='0)begin
|
190
|
-
route_addr <= 2'd2;
|
191
|
-
end
|
192
|
-
else if( bytes_x_sub_nDx=='0)begin
|
193
|
-
route_addr <= 2'd1;
|
194
|
-
end
|
195
|
-
else begin
|
196
|
-
route_addr <= 2'd1;
|
197
|
-
end
|
194
|
+
route_addr_tmp = 2'd1;
|
198
195
|
end
|
199
196
|
end
|
200
197
|
|
@@ -58,7 +58,7 @@ always_ff@(posedge clock,negedge rst_n) begin
|
|
58
58
|
end
|
59
59
|
end
|
60
60
|
else begin
|
61
|
-
insert_tri <= ( in_inf_valve.axis_tcnt>=( insert_seed-1'b1)&& in_inf_valve.axis_tvalid && in_inf_valve.axis_tready && ( in_inf_valve.axis_tcnt<( insert_seed+insert_len-
|
61
|
+
insert_tri <= ( in_inf_valve.axis_tcnt>=( insert_seed-1'b1)&& in_inf_valve.axis_tvalid && in_inf_valve.axis_tready && ( in_inf_valve.axis_tcnt<( ( insert_seed+insert_len)-1'b1))&& ~in_inf.axis_tlast);
|
62
62
|
end
|
63
63
|
end
|
64
64
|
end
|
@@ -0,0 +1,87 @@
|
|
1
|
+
/**********************************************
|
2
|
+
______________ ______________
|
3
|
+
______________ X ______________
|
4
|
+
______________ ______________
|
5
|
+
|
6
|
+
descript:
|
7
|
+
author : Cook.Darwin
|
8
|
+
Version: VERA.0.X 2018/1/25
|
9
|
+
use axis_user to detect last
|
10
|
+
creaded: 2017/5/19
|
11
|
+
madified:
|
12
|
+
***********************************************/
|
13
|
+
`timescale 1ns/1ps
|
14
|
+
(* axi_stream = "true" *)
|
15
|
+
module axis_length_split_with_user (
|
16
|
+
input [31:0] length, ////[0] mean 0 len
|
17
|
+
(* up_stream = "true" *)
|
18
|
+
axi_stream_inf.slaver axis_in,
|
19
|
+
(* down_stream = "true" *)
|
20
|
+
axi_stream_inf.master axis_out
|
21
|
+
);
|
22
|
+
|
23
|
+
wire clock,rst_n,clken;
|
24
|
+
|
25
|
+
assign clock = axis_in.aclk;
|
26
|
+
assign rst_n = axis_in.aresetn;
|
27
|
+
assign clken = axis_in.aclken;
|
28
|
+
|
29
|
+
axi_stream_inf #(.DSIZE(axis_in.DSIZE)) axis_pre (.aclk(clock),.aresetn(rst_n),.aclken(clken));
|
30
|
+
|
31
|
+
|
32
|
+
logic [31:0] cnt;
|
33
|
+
|
34
|
+
always@(posedge clock,negedge rst_n)
|
35
|
+
if(~rst_n) cnt <= '0;
|
36
|
+
else begin
|
37
|
+
if(axis_in.axis_tvalid && axis_in.axis_tready && axis_in.axis_tlast)
|
38
|
+
cnt <= '0;
|
39
|
+
else if(axis_in.axis_tvalid && axis_in.axis_tready && (cnt >= (length-1)))
|
40
|
+
cnt <= '0;
|
41
|
+
else if(axis_in.axis_tvalid && axis_in.axis_tready)
|
42
|
+
cnt <= cnt + 1'b1;
|
43
|
+
else cnt <= cnt;
|
44
|
+
end
|
45
|
+
|
46
|
+
logic new_last;
|
47
|
+
|
48
|
+
always@(posedge clock,negedge rst_n)
|
49
|
+
if(~rst_n) new_last <= 1'b0;
|
50
|
+
else begin
|
51
|
+
if(axis_in.axis_tvalid && axis_in.axis_tready && (new_last||axis_in.axis_tlast))
|
52
|
+
new_last <= 1'b0;
|
53
|
+
else if(axis_in.axis_tvalid && axis_in.axis_tready && cnt==(length-2))
|
54
|
+
new_last <= 1'b1;
|
55
|
+
else new_last <= new_last;
|
56
|
+
end
|
57
|
+
|
58
|
+
// logic mark_tail;
|
59
|
+
//
|
60
|
+
// always@(posedge clock,negedge rst_n)
|
61
|
+
// if(~rst_n) mark_tail <= 1'b0;
|
62
|
+
// else begin
|
63
|
+
// if(axis_in.axis_tvalid && axis_in.axis_tready && axis_in.axis_tlast)
|
64
|
+
// mark_tail <= 1'b0;
|
65
|
+
// else if(axis_in.axis_tvalid && axis_in.axis_tready && axis_in.axis_tcnt==(length-1))
|
66
|
+
// mark_tail <= 1'b1;
|
67
|
+
// else mark_tail <= mark_tail;
|
68
|
+
// end
|
69
|
+
|
70
|
+
assign axis_pre.axis_tvalid = axis_in.axis_tvalid;
|
71
|
+
assign axis_pre.axis_tdata = axis_in.axis_tdata;
|
72
|
+
assign axis_pre.axis_tlast = new_last || axis_in.axis_tlast;
|
73
|
+
assign axis_pre.axis_tkeep = axis_in.axis_tkeep;
|
74
|
+
// assign axis_pre.axis_tuser = axis_in.axis_tuser;
|
75
|
+
assign axis_pre.axis_tuser = axis_in.axis_tlast;
|
76
|
+
assign axis_in.axis_tready = axis_pre.axis_tready;
|
77
|
+
|
78
|
+
axis_connect_pipe axis_connect_pipe_inst(
|
79
|
+
/* axi_stream_inf.slaver */ .axis_in (axis_pre ),
|
80
|
+
/* axi_stream_inf.master */ .axis_out (axis_out )
|
81
|
+
);
|
82
|
+
|
83
|
+
int out_cnt;
|
84
|
+
|
85
|
+
assign out_cnt = axis_out.axis_tcnt;
|
86
|
+
|
87
|
+
endmodule
|
@@ -0,0 +1,41 @@
|
|
1
|
+
require_sdl 'data_c_pipe_sync_seam.rb'
|
2
|
+
|
3
|
+
TdlBuild.axis_pipe_sync_seam(__dir__) do
|
4
|
+
parameter.LAT 4
|
5
|
+
parameter.DSIZE 32
|
6
|
+
## as like: hdl```
|
7
|
+
## assign in_datas[0] = in_inf.axis_tdata + 1;
|
8
|
+
## assign in_datas[1] = out_datas[0]+1;```
|
9
|
+
input[param.LAT,param.DSIZE] - 'in_datas'
|
10
|
+
output[param.LAT,param.DSIZE] - 'out_datas'
|
11
|
+
port.axis.slaver - 'in_inf'
|
12
|
+
port.axis.master - 'out_inf'
|
13
|
+
|
14
|
+
data_inf_c(clock: in_inf.aclk, reset: in_inf.aresetn, dsize: "in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE".to_nq) - 'data_in_inf'
|
15
|
+
data_in_inf.copy(name: 'data_out_inf')
|
16
|
+
|
17
|
+
data_c_pipe_sync_seam.data_c_pipe_sync_seam_inst do |h|
|
18
|
+
h.parameter.LAT param.LAT
|
19
|
+
h.parameter.DSIZE param.DSIZE
|
20
|
+
## as like: hdl```
|
21
|
+
## assign in_datas[0] = in_inf.data + 1;
|
22
|
+
## assign in_datas[1] = out_datas[0]+1;```
|
23
|
+
h.input[h.param.LAT,h.param.DSIZE].in_datas in_datas
|
24
|
+
h.output[h.param.LAT,h.param.DSIZE].out_datas out_datas
|
25
|
+
h.port.data_inf_c.slaver.in_inf data_in_inf
|
26
|
+
h.port.data_inf_c.master.out_inf data_out_inf
|
27
|
+
end
|
28
|
+
|
29
|
+
Assign do
|
30
|
+
data_in_inf.data <= self.>>(in_inf.axis_tuser, in_inf.axis_tkeep, in_inf.axis_tlast, in_inf.axis_tdata)
|
31
|
+
data_in_inf.valid <= in_inf.axis_tvalid
|
32
|
+
in_inf.axis_tready <= data_in_inf.ready
|
33
|
+
|
34
|
+
|
35
|
+
logic_bind_(out_inf.axis_tuser, out_inf.axis_tkeep, out_inf.axis_tlast, out_inf.axis_tdata) <= data_out_inf.data
|
36
|
+
out_inf.axis_tvalid <= data_out_inf.valid
|
37
|
+
data_out_inf.ready <= out_inf.axis_tready
|
38
|
+
|
39
|
+
end
|
40
|
+
|
41
|
+
end
|
@@ -0,0 +1,48 @@
|
|
1
|
+
/**********************************************
|
2
|
+
_______________________________________
|
3
|
+
___________ Cook Darwin __________
|
4
|
+
_______________________________________
|
5
|
+
descript:
|
6
|
+
author : Cook.Darwin
|
7
|
+
Version: VERA.0.0
|
8
|
+
created: xxxx.xx.xx
|
9
|
+
madified:
|
10
|
+
***********************************************/
|
11
|
+
`timescale 1ns/1ps
|
12
|
+
|
13
|
+
module axis_pipe_sync_seam #(
|
14
|
+
parameter LAT = 4,
|
15
|
+
parameter DSIZE = 32
|
16
|
+
)(
|
17
|
+
input [ DSIZE-1:0] in_datas [LAT-1:0],
|
18
|
+
output [ DSIZE-1:0] out_datas [LAT-1:0],
|
19
|
+
axi_stream_inf.slaver in_inf,
|
20
|
+
axi_stream_inf.master out_inf
|
21
|
+
);
|
22
|
+
|
23
|
+
//==========================================================================
|
24
|
+
//-------- define ----------------------------------------------------------
|
25
|
+
|
26
|
+
data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE)) data_in_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
|
27
|
+
data_inf_c #(.DSIZE(in_inf.DSIZE+in_inf.KSIZE+1+in_inf.USIZE)) data_out_inf (.clock(in_inf.aclk),.rst_n(in_inf.aresetn)) ;
|
28
|
+
//==========================================================================
|
29
|
+
//-------- instance --------------------------------------------------------
|
30
|
+
data_c_pipe_sync_seam #(
|
31
|
+
.LAT (LAT ),
|
32
|
+
.DSIZE (DSIZE )
|
33
|
+
)data_c_pipe_sync_seam_inst(
|
34
|
+
/* input */.in_datas (in_datas ),
|
35
|
+
/* output */.out_datas (out_datas ),
|
36
|
+
/* data_inf_c.slaver */.in_inf (data_in_inf ),
|
37
|
+
/* data_inf_c.master */.out_inf (data_out_inf )
|
38
|
+
);
|
39
|
+
//==========================================================================
|
40
|
+
//-------- expression ------------------------------------------------------
|
41
|
+
assign data_in_inf.data = {>>{in_inf.axis_tuser,in_inf.axis_tkeep,in_inf.axis_tlast,in_inf.axis_tdata}};
|
42
|
+
assign data_in_inf.valid = in_inf.axis_tvalid;
|
43
|
+
assign in_inf.axis_tready = data_in_inf.ready;
|
44
|
+
assign {out_inf.axis_tuser,out_inf.axis_tkeep,out_inf.axis_tlast,out_inf.axis_tdata} = data_out_inf.data;
|
45
|
+
assign out_inf.axis_tvalid = data_out_inf.valid;
|
46
|
+
assign data_out_inf.ready = out_inf.axis_tready;
|
47
|
+
|
48
|
+
endmodule
|
@@ -12,7 +12,8 @@ madified:
|
|
12
12
|
(* axi_stream = "true" *)
|
13
13
|
module axi_stream_packet_long_fifo #(
|
14
14
|
parameter DEPTH = 2, //2-4
|
15
|
-
parameter BYTE_DEPTH = 8096
|
15
|
+
parameter BYTE_DEPTH = 8096,
|
16
|
+
parameter USE_KEEP = "OFF"
|
16
17
|
)(
|
17
18
|
(* up_stream = "true" *)
|
18
19
|
axi_stream_inf.slaver axis_in,
|
@@ -27,21 +28,41 @@ logic data_fifo_full;
|
|
27
28
|
logic data_fifo_empty;
|
28
29
|
logic [axis_in.DSIZE-1:0] stream_fifo_data;
|
29
30
|
|
30
|
-
|
31
|
-
|
32
|
-
|
33
|
-
)
|
34
|
-
|
35
|
-
|
36
|
-
/* input */ .
|
37
|
-
/* input */ .
|
38
|
-
/* input
|
39
|
-
/* input */ .
|
40
|
-
/* input
|
41
|
-
/*
|
42
|
-
/*
|
43
|
-
/* output
|
44
|
-
)
|
31
|
+
generate
|
32
|
+
if(USE_KEEP=="OFF" || USE_KEEP=="FALSE")begin
|
33
|
+
fifo_36kb_long #(
|
34
|
+
.DSIZE (axis_out.DSIZE ),
|
35
|
+
.DEPTH (BYTE_DEPTH )
|
36
|
+
)fifo_36kb_long_inst(
|
37
|
+
/* input */ .wr_clk (axis_in.aclk ),
|
38
|
+
/* input */ .wr_rst (~axis_in.aresetn ),
|
39
|
+
/* input */ .rd_clk (axis_out.aclk ),
|
40
|
+
/* input */ .rd_rst (~axis_out.aresetn ),
|
41
|
+
/* input [DSIZE-1:0] */ .din (axis_in.axis_tdata ),
|
42
|
+
/* input */ .wr_en ((axis_in.axis_tvalid && !data_fifo_full && axis_in.axis_tready) ),
|
43
|
+
/* input */ .rd_en ((axis_out.axis_tvalid && !data_fifo_empty && axis_out.axis_tready) ),
|
44
|
+
/* output [DSIZE-1:0] */ .dout (axis_out.axis_tdata ),
|
45
|
+
/* output */ .full (data_fifo_full ),
|
46
|
+
/* output */ .empty (data_fifo_empty )
|
47
|
+
);
|
48
|
+
end else begin
|
49
|
+
fifo_36kb_long #(
|
50
|
+
.DSIZE (axis_out.DSIZE+axis_out.KSIZE ),
|
51
|
+
.DEPTH (BYTE_DEPTH )
|
52
|
+
)fifo_36kb_long_inst(
|
53
|
+
/* input */ .wr_clk (axis_in.aclk ),
|
54
|
+
/* input */ .wr_rst (~axis_in.aresetn ),
|
55
|
+
/* input */ .rd_clk (axis_out.aclk ),
|
56
|
+
/* input */ .rd_rst (~axis_out.aresetn ),
|
57
|
+
/* input [DSIZE-1:0] */ .din ({axis_in.axis_tkeep, axis_in.axis_tdata} ),
|
58
|
+
/* input */ .wr_en ((axis_in.axis_tvalid && !data_fifo_full && axis_in.axis_tready) ),
|
59
|
+
/* input */ .rd_en ((axis_out.axis_tvalid && !data_fifo_empty && axis_out.axis_tready) ),
|
60
|
+
/* output [DSIZE-1:0] */ .dout ({axis_out.axis_tkeep, axis_out.axis_tdata} ),
|
61
|
+
/* output */ .full (data_fifo_full ),
|
62
|
+
/* output */ .empty (data_fifo_empty )
|
63
|
+
);
|
64
|
+
end
|
65
|
+
endgenerate
|
45
66
|
|
46
67
|
// assign axis_out.axis_tdata = axis_out.axis_tvalid? stream_fifo_data : '0;
|
47
68
|
//---<< NATIVE FIFO IP >>------------------------------
|
@@ -16,10 +16,11 @@ module parse_big_field_table_A2 #(
|
|
16
16
|
parameter DSIZE = 8,
|
17
17
|
parameter FIELD_LEN = 16*8, //MAX 16*8
|
18
18
|
parameter FIELD_NAME = "Big Filed",
|
19
|
-
parameter TRY_PARSE = "OFF"
|
19
|
+
parameter TRY_PARSE = "OFF",
|
20
|
+
parameter TMP_START = 0
|
20
21
|
)(
|
21
22
|
input enable,
|
22
|
-
output[
|
23
|
+
output[TMP_START:DSIZE*FIELD_LEN-1] value,
|
23
24
|
output logic out_valid,
|
24
25
|
axi_stream_inf.slaver cm_tb_s,
|
25
26
|
axi_stream_inf.master cm_tb_m,
|
@@ -15,7 +15,7 @@ module data_c_pipe_force_vld_bind_data #(
|
|
15
15
|
parameter HEAD_MODE = "ON", // data in master.head
|
16
16
|
parameter SYNC = "master"
|
17
17
|
)(
|
18
|
-
input [DSIZE-1:0] data, //sync master
|
18
|
+
input [DSIZE-1:0] data, //sync master, need bypass
|
19
19
|
data_inf_c.slaver slaver,
|
20
20
|
data_inf_c.master master
|
21
21
|
);
|
@@ -0,0 +1,70 @@
|
|
1
|
+
/**********************************************
|
2
|
+
_______________________________________
|
3
|
+
___________ Cook Darwin __________
|
4
|
+
_______________________________________
|
5
|
+
descript: covert A to B
|
6
|
+
author : Cook.Darwin
|
7
|
+
Version: VERA.0.0
|
8
|
+
creaded:
|
9
|
+
madified:
|
10
|
+
***********************************************/
|
11
|
+
`timescale 1ns/1ps
|
12
|
+
(* data_inf_c = "true" *)
|
13
|
+
module data_c_pipe_sync #(
|
14
|
+
parameter DSIZE = 32
|
15
|
+
|
16
|
+
)(
|
17
|
+
input [DSIZE-1:0] in_data, // as like: hdl``` assign in_data = in_inf.data + 1;
|
18
|
+
output logic [DSIZE-1:0] out_data,
|
19
|
+
data_inf_c.slaver in_inf,
|
20
|
+
data_inf_c.master out_inf
|
21
|
+
);
|
22
|
+
|
23
|
+
initial begin
|
24
|
+
assert(in_inf.DSIZE == out_inf.DSIZE)
|
25
|
+
else begin
|
26
|
+
$error("in_inf DSIZE<%0d> != out_inf DSIZE<%0d>",in_inf.DSIZE,out_inf.DSIZE);
|
27
|
+
$stop;
|
28
|
+
end
|
29
|
+
end
|
30
|
+
|
31
|
+
logic clock;
|
32
|
+
logic rst_n;
|
33
|
+
|
34
|
+
assign clock = in_inf.clock;
|
35
|
+
assign rst_n = in_inf.rst_n;
|
36
|
+
|
37
|
+
always@(posedge clock,negedge rst_n)
|
38
|
+
if(~rst_n) out_inf.valid <= 1'b0;
|
39
|
+
else begin
|
40
|
+
if(in_inf.valid && in_inf.ready)
|
41
|
+
out_inf.valid <= 1'b1;
|
42
|
+
else if(out_inf.valid && out_inf.ready)
|
43
|
+
out_inf.valid <= 1'b0;
|
44
|
+
else out_inf.valid <= out_inf.valid;
|
45
|
+
end
|
46
|
+
|
47
|
+
assign in_inf.ready = !out_inf.valid || out_inf.ready;
|
48
|
+
|
49
|
+
// logic[in_inf.DSIZE-1:0] master_origin_data;
|
50
|
+
|
51
|
+
|
52
|
+
always@(posedge clock,negedge rst_n)
|
53
|
+
if(~rst_n)begin
|
54
|
+
out_inf.data <= '0;
|
55
|
+
out_data <= '0;
|
56
|
+
end else begin
|
57
|
+
if(in_inf.valid && in_inf.ready)begin
|
58
|
+
out_data <= in_data;
|
59
|
+
out_inf.data <= in_inf.data;
|
60
|
+
end else if(out_inf.valid && out_inf.ready)begin
|
61
|
+
out_inf.data <= '0;
|
62
|
+
out_data <= '0;
|
63
|
+
end else begin
|
64
|
+
out_inf.data <= out_inf.data;
|
65
|
+
out_data <= out_data;
|
66
|
+
end
|
67
|
+
end
|
68
|
+
|
69
|
+
|
70
|
+
endmodule
|