avruby 0.5.1

data/lib/avr/opcode/data/stack.rb

@@ -0,0 +1,22 @@
+# typed: strict
+# frozen_string_literal: true
+
+module AVR
+  class Opcode
+    decode('1001 001r rrrr 1111', :push) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:push, operands.fetch(:Rr))
+    end
+
+    opcode(:push, %i[register]) do |cpu, _memory, args|
+      stack_push(cpu, args.fetch(0).value)
+    end
+
+    decode('1001 000d dddd 1111', :pop) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:pop, operands.fetch(:Rd))
+    end
+
+    opcode(:pop, %i[register]) do |cpu, _memory, args|
+      args.fetch(0).value = stack_pop(cpu)
+    end
+  end
+end

data/lib/avr/opcode/io/bit.rb

@@ -0,0 +1,22 @@
+# typed: strict
+# frozen_string_literal: true
+
+module AVR
+  class Opcode
+    decode('1001 1000 AAAA Abbb', :cbi) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:cbi, operands.fetch(:A), operands.fetch(:b))
+    end
+
+    opcode(:cbi, %i[lower_io_address bit_number]) do |cpu, _memory, args|
+      cpu.sram.memory.fetch(cpu.device.io_register_start + args.fetch(0).value).value &= ~(1 << args.fetch(1).value)
+    end
+
+    decode('1001 1010 AAAA Abbb', :sbi) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:sbi, operands.fetch(:A), operands.fetch(:b))
+    end
+
+    opcode(:sbi, %i[lower_io_address bit_number]) do |cpu, _memory, args|
+      cpu.sram.memory.fetch(cpu.device.io_register_start + args.fetch(0).value).value |= (1 << args.fetch(1).value)
+    end
+  end
+end

data/lib/avr/opcode/io/in_out.rb

@@ -0,0 +1,38 @@
+# typed: strict
+# frozen_string_literal: true
+
+module AVR
+  class Opcode
+    parse_operands('____ _AAd dddd AAAA') do |cpu, operands|
+      {
+        Rd: cpu.registers.fetch(operands.fetch(:d).value),
+        A: operands.fetch(:A),
+      }
+    end
+
+    decode('1011 0AAd dddd AAAA', :in) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:in, operands.fetch(:Rd), operands.fetch(:A))
+    end
+
+    opcode(:in, %i[register io_address]) do |cpu, _memory, args|
+      reg = cpu.device.io_registers.fetch(args.fetch(1).value)
+      args.fetch(0).value = cpu.send(T.must(reg)).value
+    end
+
+    parse_operands('____ _AAr rrrr AAAA') do |cpu, operands|
+      {
+        Rr: cpu.registers.fetch(operands.fetch(:r).value),
+        A: operands.fetch(:A),
+      }
+    end
+
+    decode('1011 1AAr rrrr AAAA', :out) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:out, operands.fetch(:A), operands.fetch(:Rr))
+    end
+
+    opcode(:out, %i[io_address register]) do |cpu, _memory, args|
+      reg = cpu.device.io_registers.fetch(args.fetch(0).value)
+      cpu.send(T.must(reg)).value = args.fetch(1).value
+    end
+  end
+end

data/lib/avr/opcode/math/addition.rb

@@ -0,0 +1,120 @@
+# typed: strict
+# frozen_string_literal: true
+
+module AVR
+  class Opcode
+    # rubocop:disable Naming/MethodParameterName
+    sig { params(cpu: CPU, r: Integer, rd: Integer).void }
+    def self.set_sreg_for_inc(cpu, r, rd)
+      n = (r & (1 << 7)) != 0
+      v = (rd == 0x7f)
+
+      cpu.sreg.from_h(
+        {
+          S: n ^ v,
+          V: v,
+          N: n,
+          Z: r.zero?,
+        }
+      )
+    end
+    # rubocop:enable Naming/MethodParameterName
+
+    decode('1001 101d dddd 0011', :inc) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:inc, operands.fetch(:Rd))
+    end
+
+    opcode(:inc, %i[register], %i[S V N Z]) do |cpu, _memory, args|
+      result = (args.fetch(0).value + 1) & 0xff
+      set_sreg_for_inc(cpu, result, args.fetch(0).value)
+      args.fetch(0).value = result
+    end
+
+    # rubocop:disable Naming/MethodParameterName
+    sig { params(cpu: CPU, r: Integer, rd: Integer, rr: Integer).void }
+    def self.set_sreg_for_add_adc(cpu, r, rd, rr)
+      b7  = (1 << 7)
+      r7  = (r  & b7) != 0
+      rd7 = (rd & b7) != 0
+      rr7 = (rr & b7) != 0
+      r3  = (r  & b7) != 0
+      rd3 = (rd & b7) != 0
+      rr3 = (rr & b7) != 0
+      n   = r7
+      v   = rd7 & rr7 & !r7 | !rd7 & !rr7 & r7
+      c   = rd7 & rr7 | rr7 & !r7 | !r7 & rd7
+      h   = rd3 & rr3 | rr3 & !r3 | !r3 & rd3
+
+      cpu.sreg.from_h(
+        {
+          H: h,
+          S: n ^ v,
+          V: v,
+          N: n,
+          Z: r.zero?,
+          C: c,
+        }
+      )
+    end
+    # rubocop:enable Naming/MethodParameterName
+
+    decode('0000 11rd dddd rrrr', :add) do |cpu, _opcode_definition, operands|
+      if operands.fetch(:Rd).value == operands.fetch(:Rr).value
+        cpu.instruction(:lsl, operands.fetch(:Rd))
+      else
+        cpu.instruction(:add, operands.fetch(:Rd), operands.fetch(:Rr))
+      end
+    end
+
+    opcode(:add, %i[register register], %i[H S V N Z C]) do |cpu, _memory, args|
+      result = (args.fetch(0).value + args.fetch(1).value) & 0xff
+      set_sreg_for_add_adc(cpu, result, args.fetch(0).value, args.fetch(1).value)
+      args.fetch(0).value = result
+    end
+
+    decode('0001 11rd dddd rrrr', :adc) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:adc, operands.fetch(:Rd), operands.fetch(:Rr))
+    end
+
+    opcode(:adc, %i[register register], %i[H S V N Z C]) do |cpu, _memory, args|
+      result = (args.fetch(0).value + args.fetch(1).value + (cpu.sreg.C ? 1 : 0)) & 0xff
+      set_sreg_for_add_adc(cpu, result, args.fetch(0).value, args.fetch(1).value)
+      args.fetch(0).value = result
+    end
+
+    # rubocop:disable Naming/MethodParameterName
+    # rubocop:disable Layout/SpaceAroundOperators
+    sig { params(cpu: CPU, r: Integer, rd: Integer).void }
+    def self.set_sreg_for_adiw(cpu, r, rd)
+      b15  = (1 << 15)
+      b7   = (1 << 7)
+      rdh7 = (rd & b7) != 0
+      r15  = (r & b15) != 0
+      v   = !rdh7 & r15
+      n   = r15
+      c   = !r15 & rdh7
+
+      cpu.sreg.from_h(
+        {
+          S: n ^ v,
+          V: v,
+          N: n,
+          Z: r.zero?,
+          C: c,
+        }
+      )
+    end
+    # rubocop:enable Layout/SpaceAroundOperators
+    # rubocop:enable Naming/MethodParameterName
+
+    decode('1001 0110 KKdd KKKK', :adiw) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:adiw, operands.fetch(:Rd), operands.fetch(:K))
+    end
+
+    opcode(:adiw, %i[word_register byte], %i[S V N Z C]) do |cpu, _memory, args|
+      result = (args.fetch(0).value + args.fetch(1).value) & 0xffff
+      set_sreg_for_adiw(cpu, result, args.fetch(0).value)
+      args.fetch(0).value = result
+    end
+  end
+end

data/lib/avr/opcode/math/bitwise.rb

@@ -0,0 +1,170 @@
+# typed: strict
+# frozen_string_literal: true
+
+module AVR
+  class Opcode
+    sig { params(cpu: CPU, value: Integer).void }
+    def self.set_sreg_for_and_or(cpu, value)
+      r7 = (value & (1 << 7)) != 0
+
+      cpu.sreg.from_h(
+        {
+          S: r7 ^ false,
+          V: false,
+          N: r7,
+          Z: value.zero?,
+        }
+      )
+    end
+
+    decode('0010 00rd dddd rrrr', :and) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:and, operands.fetch(:Rd), operands.fetch(:Rr))
+    end
+
+    opcode(:and, %i[register register], %i[S V N Z]) do |cpu, _memory, args|
+      result = (args.fetch(0).value & args.fetch(1).value)
+      set_sreg_for_and_or(cpu, result)
+      args.fetch(0).value = result
+    end
+
+    decode('0111 KKKK dddd KKKK', :andi) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:andi, operands.fetch(:Rd), operands.fetch(:K))
+    end
+
+    opcode(:andi, %i[register byte], %i[S V N Z]) do |cpu, _memory, args|
+      result = (args.fetch(0).value & args.fetch(1).value)
+      set_sreg_for_and_or(cpu, result)
+      args.fetch(0).value = result
+    end
+
+    decode('0010 01rd dddd rrrr', :eor) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:eor, operands.fetch(:Rd), operands.fetch(:Rr))
+    end
+
+    opcode(:eor, %i[register register], %i[S V N Z]) do |cpu, _memory, args|
+      result = (args.fetch(0).value ^ args.fetch(1).value)
+      set_sreg_for_and_or(cpu, result)
+      args.fetch(0).value = result
+    end
+
+    decode('0010 10rd dddd rrrr', :or) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:or, operands.fetch(:Rd), operands.fetch(:Rr))
+    end
+
+    opcode(:or, %i[register register], %i[S V N Z]) do |cpu, _memory, args|
+      result = (args.fetch(0).value | args.fetch(1).value)
+      set_sreg_for_and_or(cpu, result)
+      args.fetch(0).value = result
+    end
+
+    decode('0110 KKKK dddd KKKK', :ori) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:ori, operands.fetch(:Rd), operands.fetch(:K))
+    end
+
+    opcode(:ori, %i[register byte], %i[S V N Z]) do |cpu, _memory, args|
+      result = (args.fetch(0).value | args.fetch(1).value)
+      set_sreg_for_and_or(cpu, result)
+      args.fetch(0).value = result
+    end
+
+    decode('1001 010d dddd 0010', :swap) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:swap, operands.fetch(:Rd))
+    end
+
+    opcode(:swap, %i[register]) do |_cpu, _memory, args|
+      result = ((args.fetch(0).value & 0xf0) >> 4) | ((args.fetch(0).value & 0x0f) << 4)
+      args.fetch(0).value = result
+    end
+
+    decode('1001 010d dddd 0000', :com) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:com, operands.fetch(:Rd))
+    end
+
+    opcode(:com, %i[register], %i[S V N Z C]) do |cpu, _memory, args|
+      result = 0xff - args.fetch(0).value
+      cpu.sreg.from_h(
+        {
+          S: ((result & 0x80) != 0) ^ false,
+          V: false,
+          N: (result & 0x80) != 0,
+          Z: result.zero?,
+          C: true,
+        }
+      )
+      args.fetch(0).value = result
+    end
+
+    # There is no specific opcode for LSL Rd; it is encoded as ADD Rd, Rd.
+    # decode('0000 11dd dddd dddd', :lsl) ...
+
+    opcode(:lsl, %i[register], %i[H S V N Z C]) do |cpu, _memory, args|
+      result = (args.fetch(0).value << 1) & 0xff
+
+      h = (args.fetch(0).value & (1 << 3)) != 0
+      n = (result & (1 << 7)) != 0
+      c = (args.fetch(0).value & (1 << 7)) != 0
+      v = n ^ c
+      s = n ^ v
+      cpu.sreg.from_h(
+        {
+          H: h,
+          S: s,
+          V: v,
+          N: n,
+          Z: result.zero?,
+          C: c,
+        }
+      )
+
+      args.fetch(0).value = result
+    end
+
+    decode('1001 010d dddd 0110', :lsr) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:lsr, operands.fetch(:Rd))
+    end
+
+    opcode(:lsr, %i[register], %i[S V N Z C]) do |cpu, _memory, args|
+      result = args.fetch(0).value >> 1
+
+      n = false
+      c = (args.fetch(0).value & 1) != 0
+      v = n ^ c
+      s = n ^ v
+      cpu.sreg.from_h(
+        {
+          S: s,
+          V: v,
+          N: n,
+          Z: result.zero?,
+          C: c,
+        }
+      )
+
+      args.fetch(0).value = result
+    end
+
+    decode('1001 010d dddd 0101', :asr) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:asr, operands.fetch(:Rd))
+    end
+
+    opcode(:asr, %i[register], %i[S V N Z C]) do |cpu, _memory, args|
+      result = (args.fetch(0).value >> 1) | (args.fetch(0).value & 0x80)
+
+      n = (result & (1 << 7)) != 0
+      c = (args.fetch(0).value & 1) != 0
+      v = n ^ c
+      s = n ^ v
+      cpu.sreg.from_h(
+        {
+          S: s,
+          V: v,
+          N: n,
+          Z: result.zero?,
+          C: c,
+        }
+      )
+
+      args.fetch(0).value = result
+    end
+  end
+end

data/lib/avr/opcode/math/multiplication.rb

@@ -0,0 +1,23 @@
+# typed: strict
+# frozen_string_literal: true
+
+module AVR
+  class Opcode
+    decode('1001 11rd dddd rrrr', :mul) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:mul, operands.fetch(:Rd), operands.fetch(:Rr))
+    end
+
+    opcode(:mul, %i[register register], %i[Z C]) do |cpu, _memory, args|
+      result = (args.fetch(0).value * args.fetch(1).value)
+      set_sreg_for_inc(cpu, result, args.fetch(0).value)
+      cpu.sreg.from_h(
+        {
+          Z: result.zero?,
+          C: (result & 0x8000) != 0,
+        }
+      )
+      cpu.r0 = result & 0x00ff
+      cpu.r1 = (result & 0xff00) >> 8
+    end
+  end
+end

data/lib/avr/opcode/math/subtraction.rb

@@ -0,0 +1,137 @@
+# typed: strict
+# frozen_string_literal: true
+
+module AVR
+  class Opcode
+    # rubocop:disable Naming/MethodParameterName
+    sig { params(cpu: CPU, r: Integer, rd: Integer).void }
+    def self.set_sreg_for_dec(cpu, r, rd)
+      n = (r & (1 << 7)) != 0
+      v = (rd == 0x80)
+
+      cpu.sreg.from_h(
+        {
+          S: n ^ v,
+          V: v,
+          N: n,
+          Z: r.zero?,
+        }
+      )
+    end
+    # rubocop:enable Naming/MethodParameterName
+
+    decode('1001 010d dddd 1010', :dec) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:dec, operands.fetch(:Rd))
+    end
+
+    opcode(:dec, %i[register], %i[S V N Z]) do |cpu, _memory, args|
+      result = (args.fetch(0).value - 1) & 0xff
+      set_sreg_for_dec(cpu, result, args.fetch(0).value)
+      args.fetch(0).value = result
+    end
+
+    # rubocop:disable Naming/MethodParameterName
+    sig { params(cpu: CPU, r: Integer, rd: Integer, rr: Integer).void }
+    def self.set_sreg_for_sub_sbc(cpu, r, rd, rr)
+      b7  = (1 << 7)
+      r7  = (r  & b7) != 0
+      rd7 = (rd & b7) != 0
+      rr7 = (rr & b7) != 0
+      r3  = (r  & b7) != 0
+      rd3 = (rd & b7) != 0
+      rr3 = (rr & b7) != 0
+
+      n   = r7
+      v   = rd7 & rr7 & !r7 | !rd7 & rr7 & r7
+      c   = !rd7 & rr7 | rr7 & r7 | r7 & !rd7
+      h   = !rd3 & rr3 | rr3 & r3 | r3 & !rd3
+
+      cpu.sreg.from_h(
+        {
+          H: h,
+          S: n ^ v,
+          V: v,
+          N: n,
+          Z: r.zero?,
+          C: c,
+        }
+      )
+    end
+    # rubocop:enable Naming/MethodParameterName
+
+    decode('0001 10rd dddd rrrr', :sub) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:sub, operands.fetch(:Rd), operands.fetch(:Rr))
+    end
+
+    opcode(:sub, %i[register register], %i[H S V N Z C]) do |cpu, _memory, args|
+      result = (args.fetch(0).value - args.fetch(1).value) & 0xff
+      set_sreg_for_sub_sbc(cpu, result, args.fetch(0).value, args.fetch(1).value)
+      args.fetch(0).value = result
+    end
+
+    decode('0101 KKKK dddd KKKK', :subi) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:subi, operands.fetch(:Rd), operands.fetch(:K))
+    end
+
+    opcode(:subi, %i[register byte], %i[H S V N Z C]) do |cpu, _memory, args|
+      result = (args.fetch(0).value - args.fetch(1).value) & 0xff
+      set_sreg_for_sub_sbc(cpu, result, args.fetch(0).value, args.fetch(1).value)
+      args.fetch(0).value = result
+    end
+
+    decode('0000 10rd dddd rrrr', :sbc) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:sbc, operands.fetch(:Rd), operands.fetch(:Rr))
+    end
+
+    opcode(:sbc, %i[register register], %i[H S V N Z C]) do |cpu, _memory, args|
+      result = (args.fetch(0).value - args.fetch(1).value - (cpu.sreg.C ? 1 : 0)) & 0xff
+      set_sreg_for_sub_sbc(cpu, result, args.fetch(0).value, args.fetch(1).value)
+      args.fetch(0).value = result
+    end
+
+    decode('0100 KKKK dddd KKKK', :sbci) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:sbci, operands.fetch(:Rd), operands.fetch(:K))
+    end
+
+    opcode(:sbci, %i[register byte], %i[H S V N Z C]) do |cpu, _memory, args|
+      result = (args.fetch(0).value - args.fetch(1).value - (cpu.sreg.C ? 1 : 0)) & 0xff
+      set_sreg_for_sub_sbc(cpu, result, args.fetch(0).value, args.fetch(1).value)
+      args.fetch(0).value = result
+    end
+
+    # rubocop:disable Naming/MethodParameterName
+    # rubocop:disable Layout/SpaceAroundOperators
+    sig { params(cpu: CPU, r: Integer, rd: Integer).void }
+    def self.set_sreg_for_sbiw(cpu, r, rd)
+      b15  = (1 << 15)
+      b7   = (1 << 7)
+      rdh7 = (rd & b7) != 0
+      r15  = (r & b15) != 0
+      v   = r15 & !rdh7
+      n   = r15
+      c   = r15 & !rdh7
+
+      cpu.sreg.from_h(
+        {
+          S: n ^ v,
+          V: v,
+          N: n,
+          Z: r.zero?,
+          C: c,
+        }
+      )
+    end
+    # rubocop:enable Layout/SpaceAroundOperators
+    # rubocop:enable Naming/MethodParameterName
+
+    decode('1001 0111 KKdd KKKK', :sbiw) do |cpu, _opcode_definition, operands|
+      cpu.instruction(:sbiw, operands.fetch(:Rd), operands.fetch(:K))
+    end
+
+    opcode(:sbiw, %i[word_register byte], %i[S V N Z C]) do |cpu, _memory, args|
+      result = (args.fetch(0).value - args.fetch(1).value) & 0xffff
+      set_sreg_for_sbiw(cpu, result, args.fetch(0).value)
+      args.fetch(0).value = result
+    end
+  end
+end