avruby 0.5.1

data/lib/avr/device.rb

@@ -0,0 +1,249 @@
+# typed: strict
+# frozen_string_literal: true
+
+module AVR
+  class Device
+    extend T::Sig
+    extend T::Helpers
+    abstract!
+
+    sig { abstract.returns(Integer) }
+    def sram_size; end
+
+    sig { abstract.returns(Integer) }
+    def flash_size; end
+
+    sig { abstract.returns(Integer) }
+    def eeprom_size; end
+
+    sig { abstract.returns(T::Hash[Symbol, Integer]) }
+    def data_memory_map; end
+
+    sig { abstract.returns(Integer) }
+    def register_start; end
+
+    sig { abstract.returns(Integer) }
+    def register_count; end
+
+    sig { abstract.returns(T::Hash[Symbol, T::Array[T.nilable(Symbol)]]) }
+    def register_bit_names_map; end
+
+    sig { abstract.returns(T::Hash[Symbol, T::Hash[Symbol, Integer]]) }
+    def word_register_map; end
+
+    sig { abstract.returns(Integer) }
+    def io_register_start; end
+
+    sig { abstract.returns(Integer) }
+    def io_register_count; end
+
+    sig { abstract.returns(Integer) }
+    def ext_io_register_start; end
+
+    sig { abstract.returns(Integer) }
+    def ext_io_register_count; end
+
+    sig { abstract.returns(Integer) }
+    def ram_start; end
+
+    sig { abstract.returns(Integer) }
+    def ram_end; end
+
+    sig { abstract.returns(T::Hash[Symbol, Integer]) }
+    def interrupt_vector_map; end
+
+    sig { abstract.returns(T::Hash[Symbol, T::Hash[Symbol, Integer]]) }
+    def port_map; end
+
+    sig { returns(T::Hash[Integer, Symbol]) }
+    def data_memory_map_by_address
+      @data_memory_map_by_address ||= data_memory_map.each_with_object({}) do |(n, a), h|
+        h[a] = n unless n =~ /^_/
+      end
+    end
+
+    sig { returns(T::Array[T.nilable(Symbol)]) }
+    def io_registers
+      @io_registers ||= (0...io_register_count).map do |i|
+        data_memory_map_by_address[io_register_start + i]
+      end
+    end
+
+    sig { params(port: T.any(Symbol, String)).returns(T::Hash[Symbol, Integer]) }
+    def standard_port(port)
+      {
+        pin: data_memory_map["PIN#{port}".to_sym],
+        ddr: data_memory_map["DDR#{port}".to_sym],
+        port: data_memory_map["PORT#{port}".to_sym],
+      }
+    end
+
+    sig do
+      params(
+        ports: T::Array[T.any(Symbol, String)]
+      ).returns(T::Hash[Symbol, T::Hash[Symbol, Integer]])
+    end
+    def standard_ports(ports)
+      ports.each_with_object({}) { |m, h| h[m] = standard_port(m) }
+    end
+
+    sig { params(interrupts: T::Array[T.any(Symbol, String)]).returns(T::Hash[Symbol, Integer]) }
+    def sequential_interrupt_vectors(interrupts)
+      interrupts.each_with_index.each_with_object({}) { |(name, i), h| h[name.to_sym] = i * 2 }
+    end
+
+    sig { returns(CPU) }
+    attr_reader :cpu
+
+    sig { returns(Clock) }
+    attr_reader :system_clock
+
+    sig { returns(Oscillator) }
+    attr_reader :oscillator
+
+    sig { returns(Flash) }
+    attr_reader :flash
+
+    sig { returns(EEPROM) }
+    attr_reader :eeprom
+
+    sig { void }
+    def initialize
+      @cpu = T.let(CPU.new(self), CPU)
+      @flash = T.let(Flash.new(flash_size), Flash)
+      @eeprom = T.let(EEPROM.new(eeprom_size, cpu), EEPROM)
+
+      @system_clock = T.let(Clock.new('system'), Clock)
+      @system_clock.push_sink(cpu.clock)
+
+      @oscillator = T.let(Oscillator.new('oscillator'), Oscillator)
+      @oscillator.push_sink(system_clock)
+
+      @data_memory_map_by_address = T.let(nil, T.nilable(T::Hash[Integer, Symbol]))
+      @io_registers = T.let(nil, T.nilable(T::Array[T.nilable(Symbol)]))
+    end
+
+    sig { void }
+    def trace_cpu
+      cpu.trace do |instruction|
+        puts '*** %20s: %s' % [
+          'INSTRUCTION TRACE',
+          instruction,
+        ]
+      end
+    end
+
+    sig { void }
+    def trace_registers
+      register_addresses = {}
+      cpu.registers.registers.each do |_name, register|
+        case register
+        when MemoryByteRegister
+          register_addresses[register.memory_byte.address] ||= []
+          register_addresses[register.memory_byte.address] << register
+        when RegisterPair
+          register_addresses[register.l.memory_byte.address] ||= []
+          register_addresses[register.l.memory_byte.address] << register
+          register_addresses[register.h.memory_byte.address] ||= []
+          register_addresses[register.h.memory_byte.address] << register
+        end
+      end
+      cpu.sram.watch do |memory_byte, old_value, _new_value|
+        registers = register_addresses[memory_byte.address]
+        registers&.each do |register|
+          puts '*** %20s: %12s: %4s -> %4s' % [
+            'REGISTER TRACE',
+            register.name,
+            register.is_a?(MemoryByteRegister) ? register.format % old_value : '',
+            register.format % register.value,
+          ]
+        end
+      end
+    end
+
+    sig { void }
+    def trace_sreg
+      cpu.sram.watch do |memory_byte, old_value, new_value|
+        if memory_byte.address == cpu.sreg.memory_byte.address
+          puts '*** %20s: %s' % [
+            'SREG TRACE',
+            cpu.sreg.diff_values(old_value, new_value),
+          ]
+        end
+      end
+    end
+
+    sig { void }
+    def trace_sram
+      cpu.sram.watch do |memory_byte, old_value, new_value|
+        puts '*** %20s: %12s: %4s -> %4s' % [
+          'MEMORY TRACE',
+          '%s[%04x]' % [memory_byte.memory.name, memory_byte.address],
+          memory_byte.format % old_value,
+          memory_byte.format % new_value,
+        ]
+      end
+    end
+
+    sig { void }
+    def trace_flash
+      flash.watch do |memory_byte, old_value, new_value|
+        puts '*** %20s: %12s: %4s -> %4s' % [
+          'MEMORY TRACE',
+          '%s[%04x]' % [memory_byte.memory.name, memory_byte.address],
+          memory_byte.format % old_value,
+          memory_byte.format % new_value,
+        ]
+      end
+    end
+
+    sig { void }
+    def trace_eeprom
+      eeprom.watch do |memory_byte, old_value, new_value|
+        puts '*** %20s: %12s: %4s -> %4s' % [
+          'MEMORY TRACE',
+          '%s[%04x]' % [memory_byte.memory.name, memory_byte.address],
+          memory_byte.format % old_value,
+          memory_byte.format % new_value,
+        ]
+      end
+    end
+
+    sig { void }
+    def trace_status_pre_tick
+      oscillator.unshift_sink(
+        Clock::Sink.new('pre-execution status') do
+          puts
+          puts
+          puts 'PRE-EXECUTION STATUS'
+          puts '********************'
+          cpu.print_status
+        end
+      )
+    end
+
+    sig { void }
+    def trace_status_post_tick
+      oscillator.push_sink(
+        Clock::Sink.new('post-execution status') do
+          puts
+          puts 'POST-EXECUTION STATUS'
+          puts '*********************'
+          cpu.print_status
+        end
+      )
+    end
+
+    sig { void }
+    def trace_all
+      trace_cpu
+      trace_sram
+      trace_flash
+      trace_eeprom
+      trace_sreg
+      trace_registers
+      trace_status_pre_tick
+      trace_status_post_tick
+    end
+  end
+end

data/lib/avr/device/atmel_atmega328p.rb

@@ -0,0 +1,181 @@
+# typed: strict
+# frozen_string_literal: true
+
+module AVR
+  class Device
+    class Atmel_ATmega328p < Device # rubocop:disable Naming/ClassAndModuleCamelCase
+      extend T::Sig
+
+      sig { void }
+      def initialize
+        super
+
+        # Type annotations for variables used in memoization.
+        @register_bit_names_map = T.let(nil, T.nilable(T::Hash[Symbol, T::Array[T.nilable(Symbol)]]))
+        @word_register_map = T.let(nil, T.nilable(T::Hash[Symbol, T::Hash[Symbol, Integer]]))
+        @data_memory_map = T.let(nil, T.nilable(T::Hash[Symbol, Integer]))
+        @interrupt_vector_map = T.let(nil, T.nilable(T::Hash[Symbol, Integer]))
+        @port_map = T.let(nil, T.nilable(T::Hash[Symbol, T::Hash[Symbol, Integer]]))
+      end
+
+      sig { override.returns(Integer) }
+      def sram_size
+        2048
+      end
+
+      sig { override.returns(Integer) }
+      def flash_size
+        32_768
+      end
+
+      sig { override.returns(Integer) }
+      def eeprom_size
+        512
+      end
+
+      sig { override.returns(T::Hash[Symbol, T::Hash[Symbol, Integer]]) }
+      def word_register_map
+        @word_register_map ||= {
+          X: { l: 26, h: 27 },
+          Y: { l: 28, h: 29 },
+          Z: { l: 30, h: 31 },
+        }
+      end
+
+      sig { override.returns(T::Hash[Symbol, Integer]) }
+      def data_memory_map
+        # rubocop:disable Layout/HashAlignment
+        @data_memory_map ||= {
+          # 32 registers, r0-r31
+          PINB:               0x0023,
+          DDRB:               0x0024,
+          PORTB:              0x0025,
+          PINC:               0x0026,
+          DDRC:               0x0027,
+          PORTC:              0x0028,
+          PIND:               0x0029,
+          DDRD:               0x002a,
+          PORTD:              0x002b,
+          TIFR0:              0x0035,
+          TIFR1:              0x0035,
+          TIFR2:              0x0035,
+          PCIFR:              0x003b,
+          EIFR:               0x003c,
+          EIMSK:              0x003d,
+          GPIOR0:             0x003e,
+          EECR:               0x003f,
+          EEDR:               0x0040,
+          EEARL:              0x0041,
+          EEARH:              0x0042,
+          GTCCR:              0x0043,
+          TCCR0A:             0x0044,
+          TCCR0B:             0x0045,
+          TCNT0:              0x0046,
+          OCR0A:              0x0047,
+          OCR0B:              0x0048,
+          GPIOR1:             0x004a,
+          GPIOR2:             0x004b,
+          SPCR:               0x004c,
+          SPSR:               0x004d,
+          SPDR:               0x004e,
+          ACSR:               0x0050,
+          SMCR:               0x0053,
+          MCUSR:              0x0054,
+          MCUCR:              0x0055,
+          SPMCSR:             0x0057,
+          SPL:                0x005d,
+          SPH:                0x005e,
+          SREG:               0x005f,
+          EICRA:              0x0069,
+        }.freeze
+        # rubocop:enable Layout/HashAlignment
+      end
+
+      sig { override.returns(T::Hash[Symbol, T::Array[T.nilable(Symbol)]]) }
+      def register_bit_names_map
+        @register_bit_names_map ||= {
+          EECR: [:EERE, :EEPE, :EEMPE, :EERIE, :EEPM0, :EEPM1, nil, nil],
+        }
+      end
+
+      sig { override.returns(Integer) }
+      def register_start
+        0x0000
+      end
+
+      sig { override.returns(Integer) }
+      def register_count
+        32
+      end
+
+      sig { override.returns(Integer) }
+      def io_register_start
+        0x0020
+      end
+
+      sig { override.returns(Integer) }
+      def io_register_count
+        64
+      end
+
+      sig { override.returns(Integer) }
+      def ext_io_register_start
+        0x0060
+      end
+
+      sig { override.returns(Integer) }
+      def ext_io_register_count
+        160
+      end
+
+      sig { override.returns(Integer) }
+      def ram_start
+        0x0100
+      end
+
+      sig { override.returns(Integer) }
+      def ram_end
+        ram_start + sram_size - 1
+      end
+
+      sig { override.returns(T::Hash[Symbol, Integer]) }
+      def interrupt_vector_map
+        @interrupt_vector_map ||= sequential_interrupt_vectors(
+          %i[
+            RESET
+            INT0
+            INT1
+            PCINT0
+            PCINT1
+            PCINT2
+            WDT
+            TIMER2_COMPA
+            TIMER2_COMPB
+            TIMER2_OVF
+            TIMER1_CAPT
+            TIMER1_COMPA
+            TIMER1_COMPB
+            TIMER1_OVF
+            TIMER0_COMPA
+            TIMER0_COMPB
+            TIMER0_OVF
+            SPI_STC
+            USART_RX
+            USART_UDRE
+            USART_TX
+            ADC
+            EE_READY
+            ANALOG_COMP
+            TWI
+            SPM_READY
+          ]
+        )
+      end
+
+      sig { override.returns(T::Hash[Symbol, T::Hash[Symbol, Integer]]) }
+      def port_map
+        @port_map ||= standard_ports(%i[B C D])
+      end
+    end
+  end
+end

data/lib/avr/instruction.rb

@@ -0,0 +1,72 @@
+# typed: strict
+# frozen_string_literal: true
+
+module AVR
+  class Instruction
+    extend T::Sig
+
+    sig { returns(CPU) }
+    attr_reader :cpu
+
+    sig { returns(Symbol) }
+    attr_reader :mnemonic
+
+    sig { returns(Argument::ArrayType) }
+    attr_reader :args
+
+    sig { returns(Opcode) }
+    attr_reader :opcode
+
+    sig { params(cpu: CPU, mnemonic: Symbol, args: Argument::ArrayType).void }
+    def initialize(cpu, mnemonic, args)
+      raise "Unknown opcode #{mnemonic}" unless Opcode.opcodes.include?(mnemonic)
+
+      @cpu = cpu
+      @mnemonic = mnemonic
+      @args = args
+      @opcode = T.let(Opcode.opcodes.fetch(mnemonic), Opcode)
+    end
+
+    sig { returns(T::Boolean) }
+    def validate
+      opcode.validate(args)
+    end
+
+    sig { returns(T::Boolean) }
+    def valid?
+      validate
+      true
+    end
+
+    sig { returns(T.nilable(String)) }
+    def args_to_s
+      #return args.join(', ') unless opcode
+      return nil if opcode.arg_types.empty?
+
+      opcode.format_args(args).join(', ')
+    end
+
+    sig { returns(String) }
+    def to_s
+      return mnemonic.to_s if args.empty?
+
+      "#{mnemonic} #{args_to_s}"
+    end
+
+    sig { returns(String) }
+    def inspect
+      "#<#{self.class.name} {#{self}}>"
+    end
+
+    sig { void }
+    def execute
+      raise 'Invalid instruction' unless valid?
+
+      cpu.next_pc = cpu.pc + 1
+      opcode.execute(cpu, nil, args)
+      cpu.pc = cpu.next_pc
+
+      nil
+    end
+  end
+end