art-decomp 0.3.0 → 0.4.0

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
@@ -0,0 +1,86 @@
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+ ---
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+ :-:
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+ 0----:
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+ :next_state: :state1
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+ :output: -11---1-00------
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+ :state1:
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+ 1----:
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+ :next_state: :state3
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+ :output: -11---1-00------
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+ :state2:
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+ 1----:
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+ :next_state: :state0
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+ :output: -11---1-00------
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+ :state3:
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+ 1----:
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+ :next_state: :state4
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+ :output: 101---1-01------
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+ :state4:
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+ 1-111:
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+ :next_state: :state13
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+ :output: -11---1-00------
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+ 1-110:
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+ :next_state: :state10
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+ :output: -11---1-00------
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+ 1-10-:
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+ :next_state: :state9
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+ :output: -11---1-00------
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+ 1-011:
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+ :next_state: :state8
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+ :output: -11---1-00------
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+ 1-010:
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+ :next_state: :state7
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+ :output: -11---1-00------
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+ 1-001:
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+ :next_state: :state6
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+ :output: -11---1-00------
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+ 1-000:
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+ :next_state: :state5
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+ :output: -11---1-00------
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+ :state5:
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+ 1----:
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+ :next_state: :state14
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+ :output: 0011--1-00------
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+ :state6:
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+ 1----:
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+ :next_state: :state14
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+ :output: 00100-0-00000011
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+ :state7:
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+ 1----:
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+ :next_state: :state14
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+ :output: 001---1100------
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+ :state8:
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+ 1----:
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+ :next_state: :state14
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+ :output: 010---1-00------
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+ :state9:
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+ 1----:
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+ :next_state: :state14
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+ :output: 001---1010000101
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+ :state10:
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+ 1----:
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+ :next_state: :state11
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+ :output: -11---1-00100000
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+ :state11:
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+ 10---:
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+ :next_state: :state13
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+ :output: -11---1-00------
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+ 11---:
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+ :next_state: :state12
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+ :output: -11---1-00------
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+ :state12:
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+ 1----:
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+ :next_state: :state13
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+ :output: -110110-00------
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+ :state13:
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+ 1----:
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+ :next_state: :state14
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+ :output: -11---1-00------
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+ :state14:
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+ 1----:
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+ :next_state: :state3
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+ :output: -110110-00------
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+ :state0:
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+ 0----:
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+ :next_state: :state1
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+ :output: -11---1-00------
@@ -0,0 +1,94 @@
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+ library ieee;
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+ use ieee.numeric_std.all;
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+ use ieee.std_logic_1164.all;
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+ entity mark1_hot is
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+ port(
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+ clock: in std_logic;
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+ input: in std_logic_vector(4 downto 0);
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+ output: out std_logic_vector(15 downto 0)
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+ );
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+ end mark1_hot;
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+ architecture behaviour of mark1_hot is
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+ constant state1: std_logic_vector(14 downto 0) := "100000000000000";
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+ constant state3: std_logic_vector(14 downto 0) := "010000000000000";
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+ constant state2: std_logic_vector(14 downto 0) := "001000000000000";
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+ constant state0: std_logic_vector(14 downto 0) := "000100000000000";
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+ constant state4: std_logic_vector(14 downto 0) := "000010000000000";
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+ constant state13: std_logic_vector(14 downto 0) := "000001000000000";
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+ constant state10: std_logic_vector(14 downto 0) := "000000100000000";
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+ constant state9: std_logic_vector(14 downto 0) := "000000010000000";
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+ constant state8: std_logic_vector(14 downto 0) := "000000001000000";
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+ constant state7: std_logic_vector(14 downto 0) := "000000000100000";
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+ constant state6: std_logic_vector(14 downto 0) := "000000000010000";
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+ constant state5: std_logic_vector(14 downto 0) := "000000000001000";
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+ constant state14: std_logic_vector(14 downto 0) := "000000000000100";
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+ constant state11: std_logic_vector(14 downto 0) := "000000000000010";
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+ constant state12: std_logic_vector(14 downto 0) := "000000000000001";
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+ signal current_state, next_state: std_logic_vector(14 downto 0);
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+ begin
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+ process(clock) begin
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+ if rising_edge(clock) then current_state <= next_state;
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+ end if;
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+ end process;
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+ process(input, current_state) begin
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+ next_state <= "---------------"; output <= "----------------";
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+ if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
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+ else
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+ case current_state is
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+ when state1 =>
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+ if std_match(input, "1----") then next_state <= state3; output <= "-11---1-00------";
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+ end if;
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+ when state2 =>
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+ if std_match(input, "1----") then next_state <= state0; output <= "-11---1-00------";
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+ end if;
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+ when state3 =>
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+ if std_match(input, "1----") then next_state <= state4; output <= "101---1-01------";
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+ end if;
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+ when state4 =>
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+ if std_match(input, "1-111") then next_state <= state13; output <= "-11---1-00------";
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+ elsif std_match(input, "1-110") then next_state <= state10; output <= "-11---1-00------";
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+ elsif std_match(input, "1-10-") then next_state <= state9; output <= "-11---1-00------";
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+ elsif std_match(input, "1-011") then next_state <= state8; output <= "-11---1-00------";
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+ elsif std_match(input, "1-010") then next_state <= state7; output <= "-11---1-00------";
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+ elsif std_match(input, "1-001") then next_state <= state6; output <= "-11---1-00------";
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+ elsif std_match(input, "1-000") then next_state <= state5; output <= "-11---1-00------";
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+ end if;
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+ when state5 =>
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+ if std_match(input, "1----") then next_state <= state14; output <= "0011--1-00------";
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+ end if;
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+ when state6 =>
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+ if std_match(input, "1----") then next_state <= state14; output <= "00100-0-00000011";
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+ end if;
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+ when state7 =>
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+ if std_match(input, "1----") then next_state <= state14; output <= "001---1100------";
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+ end if;
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+ when state8 =>
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+ if std_match(input, "1----") then next_state <= state14; output <= "010---1-00------";
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+ end if;
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+ when state9 =>
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+ if std_match(input, "1----") then next_state <= state14; output <= "001---1010000101";
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+ end if;
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+ when state10 =>
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+ if std_match(input, "1----") then next_state <= state11; output <= "-11---1-00100000";
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+ end if;
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+ when state11 =>
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+ if std_match(input, "10---") then next_state <= state13; output <= "-11---1-00------";
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+ elsif std_match(input, "11---") then next_state <= state12; output <= "-11---1-00------";
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+ end if;
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+ when state12 =>
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+ if std_match(input, "1----") then next_state <= state13; output <= "-110110-00------";
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+ end if;
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+ when state13 =>
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+ if std_match(input, "1----") then next_state <= state14; output <= "-11---1-00------";
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+ end if;
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+ when state14 =>
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+ if std_match(input, "1----") then next_state <= state3; output <= "-110110-00------";
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+ end if;
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+ when state0 =>
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+ if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
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+ end if;
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+ when others => next_state <= "---------------"; output <= "----------------";
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+ end case;
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+ end if;
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+ end process;
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+ end behaviour;
@@ -0,0 +1,94 @@
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+ library ieee;
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+ use ieee.numeric_std.all;
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+ use ieee.std_logic_1164.all;
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+ entity mark1_jed is
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+ port(
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+ clock: in std_logic;
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+ input: in std_logic_vector(4 downto 0);
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+ output: out std_logic_vector(15 downto 0)
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+ );
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+ end mark1_jed;
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+ architecture behaviour of mark1_jed is
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+ constant state1: std_logic_vector(3 downto 0) := "0001";
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+ constant state3: std_logic_vector(3 downto 0) := "1111";
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+ constant state2: std_logic_vector(3 downto 0) := "0011";
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+ constant state0: std_logic_vector(3 downto 0) := "1101";
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+ constant state4: std_logic_vector(3 downto 0) := "1001";
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+ constant state13: std_logic_vector(3 downto 0) := "1010";
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+ constant state10: std_logic_vector(3 downto 0) := "1000";
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+ constant state9: std_logic_vector(3 downto 0) := "1100";
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+ constant state8: std_logic_vector(3 downto 0) := "0010";
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+ constant state7: std_logic_vector(3 downto 0) := "0000";
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+ constant state6: std_logic_vector(3 downto 0) := "0110";
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+ constant state5: std_logic_vector(3 downto 0) := "0100";
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+ constant state14: std_logic_vector(3 downto 0) := "1110";
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+ constant state11: std_logic_vector(3 downto 0) := "0111";
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+ constant state12: std_logic_vector(3 downto 0) := "1011";
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+ signal current_state, next_state: std_logic_vector(3 downto 0);
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+ begin
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+ process(clock) begin
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+ if rising_edge(clock) then current_state <= next_state;
31
+ end if;
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+ end process;
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+ process(input, current_state) begin
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+ next_state <= "----"; output <= "----------------";
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+ if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
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+ else
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+ case current_state is
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+ when state1 =>
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+ if std_match(input, "1----") then next_state <= state3; output <= "-11---1-00------";
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+ end if;
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+ when state2 =>
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+ if std_match(input, "1----") then next_state <= state0; output <= "-11---1-00------";
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+ end if;
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+ when state3 =>
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+ if std_match(input, "1----") then next_state <= state4; output <= "101---1-01------";
46
+ end if;
47
+ when state4 =>
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+ if std_match(input, "1-111") then next_state <= state13; output <= "-11---1-00------";
49
+ elsif std_match(input, "1-110") then next_state <= state10; output <= "-11---1-00------";
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+ elsif std_match(input, "1-10-") then next_state <= state9; output <= "-11---1-00------";
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+ elsif std_match(input, "1-011") then next_state <= state8; output <= "-11---1-00------";
52
+ elsif std_match(input, "1-010") then next_state <= state7; output <= "-11---1-00------";
53
+ elsif std_match(input, "1-001") then next_state <= state6; output <= "-11---1-00------";
54
+ elsif std_match(input, "1-000") then next_state <= state5; output <= "-11---1-00------";
55
+ end if;
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+ when state5 =>
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+ if std_match(input, "1----") then next_state <= state14; output <= "0011--1-00------";
58
+ end if;
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+ when state6 =>
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+ if std_match(input, "1----") then next_state <= state14; output <= "00100-0-00000011";
61
+ end if;
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+ when state7 =>
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+ if std_match(input, "1----") then next_state <= state14; output <= "001---1100------";
64
+ end if;
65
+ when state8 =>
66
+ if std_match(input, "1----") then next_state <= state14; output <= "010---1-00------";
67
+ end if;
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+ when state9 =>
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+ if std_match(input, "1----") then next_state <= state14; output <= "001---1010000101";
70
+ end if;
71
+ when state10 =>
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+ if std_match(input, "1----") then next_state <= state11; output <= "-11---1-00100000";
73
+ end if;
74
+ when state11 =>
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+ if std_match(input, "10---") then next_state <= state13; output <= "-11---1-00------";
76
+ elsif std_match(input, "11---") then next_state <= state12; output <= "-11---1-00------";
77
+ end if;
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+ when state12 =>
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+ if std_match(input, "1----") then next_state <= state13; output <= "-110110-00------";
80
+ end if;
81
+ when state13 =>
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+ if std_match(input, "1----") then next_state <= state14; output <= "-11---1-00------";
83
+ end if;
84
+ when state14 =>
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+ if std_match(input, "1----") then next_state <= state3; output <= "-110110-00------";
86
+ end if;
87
+ when state0 =>
88
+ if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
89
+ end if;
90
+ when others => next_state <= "----"; output <= "----------------";
91
+ end case;
92
+ end if;
93
+ end process;
94
+ end behaviour;
@@ -0,0 +1,94 @@
1
+ library ieee;
2
+ use ieee.numeric_std.all;
3
+ use ieee.std_logic_1164.all;
4
+ entity mark1_nov is
5
+ port(
6
+ clock: in std_logic;
7
+ input: in std_logic_vector(4 downto 0);
8
+ output: out std_logic_vector(15 downto 0)
9
+ );
10
+ end mark1_nov;
11
+ architecture behaviour of mark1_nov is
12
+ constant state1: std_logic_vector(3 downto 0) := "0100";
13
+ constant state2: std_logic_vector(3 downto 0) := "1000";
14
+ constant state3: std_logic_vector(3 downto 0) := "1011";
15
+ constant state4: std_logic_vector(3 downto 0) := "1100";
16
+ constant state5: std_logic_vector(3 downto 0) := "0001";
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+ constant state6: std_logic_vector(3 downto 0) := "0011";
18
+ constant state7: std_logic_vector(3 downto 0) := "0000";
19
+ constant state8: std_logic_vector(3 downto 0) := "0010";
20
+ constant state9: std_logic_vector(3 downto 0) := "1101";
21
+ constant state10: std_logic_vector(3 downto 0) := "1010";
22
+ constant state11: std_logic_vector(3 downto 0) := "0111";
23
+ constant state12: std_logic_vector(3 downto 0) := "1001";
24
+ constant state13: std_logic_vector(3 downto 0) := "0101";
25
+ constant state14: std_logic_vector(3 downto 0) := "0110";
26
+ constant state0: std_logic_vector(3 downto 0) := "1110";
27
+ signal current_state, next_state: std_logic_vector(3 downto 0);
28
+ begin
29
+ process(clock) begin
30
+ if rising_edge(clock) then current_state <= next_state;
31
+ end if;
32
+ end process;
33
+ process(input, current_state) begin
34
+ next_state <= "----"; output <= "----------------";
35
+ if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
36
+ else
37
+ case current_state is
38
+ when state1 =>
39
+ if std_match(input, "1----") then next_state <= state3; output <= "-11---1-00------";
40
+ end if;
41
+ when state2 =>
42
+ if std_match(input, "1----") then next_state <= state0; output <= "-11---1-00------";
43
+ end if;
44
+ when state3 =>
45
+ if std_match(input, "1----") then next_state <= state4; output <= "101---1-01------";
46
+ end if;
47
+ when state4 =>
48
+ if std_match(input, "1-111") then next_state <= state13; output <= "-11---1-00------";
49
+ elsif std_match(input, "1-110") then next_state <= state10; output <= "-11---1-00------";
50
+ elsif std_match(input, "1-10-") then next_state <= state9; output <= "-11---1-00------";
51
+ elsif std_match(input, "1-011") then next_state <= state8; output <= "-11---1-00------";
52
+ elsif std_match(input, "1-010") then next_state <= state7; output <= "-11---1-00------";
53
+ elsif std_match(input, "1-001") then next_state <= state6; output <= "-11---1-00------";
54
+ elsif std_match(input, "1-000") then next_state <= state5; output <= "-11---1-00------";
55
+ end if;
56
+ when state5 =>
57
+ if std_match(input, "1----") then next_state <= state14; output <= "0011--1-00------";
58
+ end if;
59
+ when state6 =>
60
+ if std_match(input, "1----") then next_state <= state14; output <= "00100-0-00000011";
61
+ end if;
62
+ when state7 =>
63
+ if std_match(input, "1----") then next_state <= state14; output <= "001---1100------";
64
+ end if;
65
+ when state8 =>
66
+ if std_match(input, "1----") then next_state <= state14; output <= "010---1-00------";
67
+ end if;
68
+ when state9 =>
69
+ if std_match(input, "1----") then next_state <= state14; output <= "001---1010000101";
70
+ end if;
71
+ when state10 =>
72
+ if std_match(input, "1----") then next_state <= state11; output <= "-11---1-00100000";
73
+ end if;
74
+ when state11 =>
75
+ if std_match(input, "10---") then next_state <= state13; output <= "-11---1-00------";
76
+ elsif std_match(input, "11---") then next_state <= state12; output <= "-11---1-00------";
77
+ end if;
78
+ when state12 =>
79
+ if std_match(input, "1----") then next_state <= state13; output <= "-110110-00------";
80
+ end if;
81
+ when state13 =>
82
+ if std_match(input, "1----") then next_state <= state14; output <= "-11---1-00------";
83
+ end if;
84
+ when state14 =>
85
+ if std_match(input, "1----") then next_state <= state3; output <= "-110110-00------";
86
+ end if;
87
+ when state0 =>
88
+ if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
89
+ end if;
90
+ when others => next_state <= "----"; output <= "----------------";
91
+ end case;
92
+ end if;
93
+ end process;
94
+ end behaviour;
metadata CHANGED
@@ -1,7 +1,12 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: art-decomp
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.3.0
4
+ prerelease: false
5
+ segments:
6
+ - 0
7
+ - 4
8
+ - 0
9
+ version: 0.4.0
5
10
  platform: ruby
6
11
  authors:
7
12
  - Piotr Szotkowski
@@ -9,74 +14,87 @@ autorequire:
9
14
  bindir: bin
10
15
  cert_chain: []
11
16
 
12
- date: 2010-01-10 00:00:00 +01:00
17
+ date: 2010-03-13 00:00:00 +01:00
13
18
  default_executable:
14
19
  dependencies:
15
20
  - !ruby/object:Gem::Dependency
16
- name: teejayvanslyke-gazer
17
- type: :runtime
18
- version_requirement:
19
- version_requirements: !ruby/object:Gem::Requirement
21
+ name: rcapture
22
+ prerelease: false
23
+ requirement: &id001 !ruby/object:Gem::Requirement
20
24
  requirements:
21
25
  - - ">="
22
26
  - !ruby/object:Gem::Version
27
+ segments:
28
+ - 0
23
29
  version: "0"
24
- version:
30
+ type: :runtime
31
+ version_requirements: *id001
25
32
  - !ruby/object:Gem::Dependency
26
33
  name: trollop
27
- type: :runtime
28
- version_requirement:
29
- version_requirements: !ruby/object:Gem::Requirement
34
+ prerelease: false
35
+ requirement: &id002 !ruby/object:Gem::Requirement
30
36
  requirements:
31
37
  - - ">="
32
38
  - !ruby/object:Gem::Version
39
+ segments:
40
+ - 0
33
41
  version: "0"
34
- version:
42
+ type: :runtime
43
+ version_requirements: *id002
35
44
  - !ruby/object:Gem::Dependency
36
45
  name: diff-lcs
37
- type: :development
38
- version_requirement:
39
- version_requirements: !ruby/object:Gem::Requirement
46
+ prerelease: false
47
+ requirement: &id003 !ruby/object:Gem::Requirement
40
48
  requirements:
41
49
  - - ">="
42
50
  - !ruby/object:Gem::Version
51
+ segments:
52
+ - 0
43
53
  version: "0"
44
- version:
54
+ type: :development
55
+ version_requirements: *id003
45
56
  - !ruby/object:Gem::Dependency
46
57
  name: jeweler
47
- type: :development
48
- version_requirement:
49
- version_requirements: !ruby/object:Gem::Requirement
58
+ prerelease: false
59
+ requirement: &id004 !ruby/object:Gem::Requirement
50
60
  requirements:
51
61
  - - ">="
52
62
  - !ruby/object:Gem::Version
63
+ segments:
64
+ - 0
53
65
  version: "0"
54
- version:
66
+ type: :development
67
+ version_requirements: *id004
55
68
  - !ruby/object:Gem::Dependency
56
69
  name: rcov
57
- type: :development
58
- version_requirement:
59
- version_requirements: !ruby/object:Gem::Requirement
70
+ prerelease: false
71
+ requirement: &id005 !ruby/object:Gem::Requirement
60
72
  requirements:
61
73
  - - ">="
62
74
  - !ruby/object:Gem::Version
75
+ segments:
76
+ - 0
63
77
  version: "0"
64
- version:
78
+ type: :development
79
+ version_requirements: *id005
65
80
  - !ruby/object:Gem::Dependency
66
81
  name: rspec
67
- type: :development
68
- version_requirement:
69
- version_requirements: !ruby/object:Gem::Requirement
82
+ prerelease: false
83
+ requirement: &id006 !ruby/object:Gem::Requirement
70
84
  requirements:
71
85
  - - ">="
72
86
  - !ruby/object:Gem::Version
87
+ segments:
88
+ - 0
73
89
  version: "0"
74
- version:
90
+ type: :development
91
+ version_requirements: *id006
75
92
  description:
76
93
  email: p.szotkowski@tele.pw.edu.pl
77
94
  executables:
78
95
  - ad-validate
79
96
  - ad-console
97
+ - ad-kiss2vhdl
80
98
  - ad-fsm-info
81
99
  - art-decomp
82
100
  extensions: []
@@ -91,6 +109,7 @@ files:
91
109
  - VERSION
92
110
  - bin/ad-console
93
111
  - bin/ad-fsm-info
112
+ - bin/ad-kiss2vhdl
94
113
  - bin/ad-validate
95
114
  - bin/art-decomp
96
115
  - lib/art-decomp.rb
@@ -116,6 +135,7 @@ files:
116
135
  - lib/art-decomp/uv_generator/general_relevance.rb
117
136
  - lib/art-decomp/uv_generator/unique_relevance.rb
118
137
  - lib/art-decomp/uv_relevance_generator.rb
138
+ - lib/art-decomp/vhdl.rb
119
139
  - lib/core/enumerable.rb
120
140
  - lib/core/file.rb
121
141
  - lib/core/integer.rb
@@ -142,12 +162,15 @@ files:
142
162
  - spec/art-decomp/uv_generator/general_relevance_spec.rb
143
163
  - spec/art-decomp/uv_generator/unique_relevance_spec.rb
144
164
  - spec/art-decomp/uv_relevance_generator_spec.rb
165
+ - spec/art-decomp/vhdl_spec.rb
145
166
  - spec/core/enumerable_spec.rb
146
167
  - spec/core/file_spec.rb
147
168
  - spec/core/integer_spec.rb
148
169
  - spec/core/set_spec.rb
149
170
  - spec/core/string_spec.rb
150
171
  - spec/fixtures/ex4
172
+ - spec/fixtures/ex4.hot
173
+ - spec/fixtures/ex4_hot.vhd
151
174
  - spec/fixtures/ex5
152
175
  - spec/fixtures/fsm
153
176
  - spec/fixtures/fsm.exp
@@ -156,11 +179,21 @@ files:
156
179
  - spec/fixtures/fsm.h
157
180
  - spec/fixtures/fsm.partially-exp
158
181
  - spec/fixtures/fsm.q
182
+ - spec/fixtures/fsm.vhd
183
+ - spec/fixtures/kirkman
159
184
  - spec/fixtures/lion
160
185
  - spec/fixtures/lion.exp
161
186
  - spec/fixtures/lion.h
162
187
  - spec/fixtures/lion.to_kiss
163
188
  - spec/fixtures/mark1
189
+ - spec/fixtures/mark1.hot
190
+ - spec/fixtures/mark1.jed
191
+ - spec/fixtures/mark1.nov
192
+ - spec/fixtures/mark1.vhd
193
+ - spec/fixtures/mark1.yml
194
+ - spec/fixtures/mark1_hot.vhd
195
+ - spec/fixtures/mark1_jed.vhd
196
+ - spec/fixtures/mark1_nov.vhd
164
197
  - spec/fixtures/mc
165
198
  - spec/fixtures/mc.to_kiss
166
199
  - spec/fixtures/opus
@@ -184,18 +217,20 @@ required_ruby_version: !ruby/object:Gem::Requirement
184
217
  requirements:
185
218
  - - ">="
186
219
  - !ruby/object:Gem::Version
220
+ segments:
221
+ - 0
187
222
  version: "0"
188
- version:
189
223
  required_rubygems_version: !ruby/object:Gem::Requirement
190
224
  requirements:
191
225
  - - ">="
192
226
  - !ruby/object:Gem::Version
227
+ segments:
228
+ - 0
193
229
  version: "0"
194
- version:
195
230
  requirements: []
196
231
 
197
232
  rubyforge_project:
198
- rubygems_version: 1.3.5
233
+ rubygems_version: 1.3.6
199
234
  signing_key:
200
235
  specification_version: 3
201
236
  summary: "art d\xC3\xA9comp: an FSM \xE2\x86\x92 FPGA decomposer"
@@ -219,6 +254,7 @@ test_files:
219
254
  - spec/art-decomp/qv_generator/graph_merging_spec.rb
220
255
  - spec/art-decomp/executable_spec.rb
221
256
  - spec/art-decomp/decomposer_spec.rb
257
+ - spec/art-decomp/vhdl_spec.rb
222
258
  - spec/art-decomp/qu_generator/edge_labels_spec.rb
223
259
  - spec/art-decomp/qu_generator/block_table_spec.rb
224
260
  - spec/art-decomp/uv_generator/general_relevance_spec.rb