art-decomp 0.3.0 → 0.4.0

data/spec/fixtures/mark1.yml

@@ -0,0 +1,86 @@
+--- 
+:-: 
+  0----: 
+    :next_state: :state1
+    :output: -11---1-00------
+:state1: 
+  1----: 
+    :next_state: :state3
+    :output: -11---1-00------
+:state2: 
+  1----: 
+    :next_state: :state0
+    :output: -11---1-00------
+:state3: 
+  1----: 
+    :next_state: :state4
+    :output: 101---1-01------
+:state4: 
+  1-111: 
+    :next_state: :state13
+    :output: -11---1-00------
+  1-110: 
+    :next_state: :state10
+    :output: -11---1-00------
+  1-10-: 
+    :next_state: :state9
+    :output: -11---1-00------
+  1-011: 
+    :next_state: :state8
+    :output: -11---1-00------
+  1-010: 
+    :next_state: :state7
+    :output: -11---1-00------
+  1-001: 
+    :next_state: :state6
+    :output: -11---1-00------
+  1-000: 
+    :next_state: :state5
+    :output: -11---1-00------
+:state5: 
+  1----: 
+    :next_state: :state14
+    :output: 0011--1-00------
+:state6: 
+  1----: 
+    :next_state: :state14
+    :output: 00100-0-00000011
+:state7: 
+  1----: 
+    :next_state: :state14
+    :output: 001---1100------
+:state8: 
+  1----: 
+    :next_state: :state14
+    :output: 010---1-00------
+:state9: 
+  1----: 
+    :next_state: :state14
+    :output: 001---1010000101
+:state10: 
+  1----: 
+    :next_state: :state11
+    :output: -11---1-00100000
+:state11: 
+  10---: 
+    :next_state: :state13
+    :output: -11---1-00------
+  11---: 
+    :next_state: :state12
+    :output: -11---1-00------
+:state12: 
+  1----: 
+    :next_state: :state13
+    :output: -110110-00------
+:state13: 
+  1----: 
+    :next_state: :state14
+    :output: -11---1-00------
+:state14: 
+  1----: 
+    :next_state: :state3
+    :output: -110110-00------
+:state0: 
+  0----: 
+    :next_state: :state1
+    :output: -11---1-00------

data/spec/fixtures/mark1_hot.vhd

@@ -0,0 +1,94 @@
+library ieee;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+entity mark1_hot is
+  port(
+    clock:  in  std_logic;
+    input:  in  std_logic_vector(4 downto 0);
+    output: out std_logic_vector(15 downto 0)
+  );
+end mark1_hot;
+architecture behaviour of mark1_hot is
+  constant state1: std_logic_vector(14 downto 0) := "100000000000000";
+  constant state3: std_logic_vector(14 downto 0) := "010000000000000";
+  constant state2: std_logic_vector(14 downto 0) := "001000000000000";
+  constant state0: std_logic_vector(14 downto 0) := "000100000000000";
+  constant state4: std_logic_vector(14 downto 0) := "000010000000000";
+  constant state13: std_logic_vector(14 downto 0) := "000001000000000";
+  constant state10: std_logic_vector(14 downto 0) := "000000100000000";
+  constant state9: std_logic_vector(14 downto 0) := "000000010000000";
+  constant state8: std_logic_vector(14 downto 0) := "000000001000000";
+  constant state7: std_logic_vector(14 downto 0) := "000000000100000";
+  constant state6: std_logic_vector(14 downto 0) := "000000000010000";
+  constant state5: std_logic_vector(14 downto 0) := "000000000001000";
+  constant state14: std_logic_vector(14 downto 0) := "000000000000100";
+  constant state11: std_logic_vector(14 downto 0) := "000000000000010";
+  constant state12: std_logic_vector(14 downto 0) := "000000000000001";
+  signal current_state, next_state: std_logic_vector(14 downto 0);
+begin
+  process(clock) begin
+    if rising_edge(clock) then current_state <= next_state;
+    end if;
+  end process;
+  process(input, current_state) begin
+    next_state <= "---------------"; output <= "----------------";
+    if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
+    else
+    case current_state is
+      when state1 =>
+        if std_match(input, "1----") then next_state <= state3; output <= "-11---1-00------";
+        end if;
+      when state2 =>
+        if std_match(input, "1----") then next_state <= state0; output <= "-11---1-00------";
+        end if;
+      when state3 =>
+        if std_match(input, "1----") then next_state <= state4; output <= "101---1-01------";
+        end if;
+      when state4 =>
+        if std_match(input, "1-111") then next_state <= state13; output <= "-11---1-00------";
+        elsif std_match(input, "1-110") then next_state <= state10; output <= "-11---1-00------";
+        elsif std_match(input, "1-10-") then next_state <= state9; output <= "-11---1-00------";
+        elsif std_match(input, "1-011") then next_state <= state8; output <= "-11---1-00------";
+        elsif std_match(input, "1-010") then next_state <= state7; output <= "-11---1-00------";
+        elsif std_match(input, "1-001") then next_state <= state6; output <= "-11---1-00------";
+        elsif std_match(input, "1-000") then next_state <= state5; output <= "-11---1-00------";
+        end if;
+      when state5 =>
+        if std_match(input, "1----") then next_state <= state14; output <= "0011--1-00------";
+        end if;
+      when state6 =>
+        if std_match(input, "1----") then next_state <= state14; output <= "00100-0-00000011";
+        end if;
+      when state7 =>
+        if std_match(input, "1----") then next_state <= state14; output <= "001---1100------";
+        end if;
+      when state8 =>
+        if std_match(input, "1----") then next_state <= state14; output <= "010---1-00------";
+        end if;
+      when state9 =>
+        if std_match(input, "1----") then next_state <= state14; output <= "001---1010000101";
+        end if;
+      when state10 =>
+        if std_match(input, "1----") then next_state <= state11; output <= "-11---1-00100000";
+        end if;
+      when state11 =>
+        if std_match(input, "10---") then next_state <= state13; output <= "-11---1-00------";
+        elsif std_match(input, "11---") then next_state <= state12; output <= "-11---1-00------";
+        end if;
+      when state12 =>
+        if std_match(input, "1----") then next_state <= state13; output <= "-110110-00------";
+        end if;
+      when state13 =>
+        if std_match(input, "1----") then next_state <= state14; output <= "-11---1-00------";
+        end if;
+      when state14 =>
+        if std_match(input, "1----") then next_state <= state3; output <= "-110110-00------";
+        end if;
+      when state0 =>
+        if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
+        end if;
+      when others => next_state <= "---------------"; output <= "----------------";
+    end case;
+    end if;
+  end process;
+end behaviour;

data/spec/fixtures/mark1_jed.vhd

@@ -0,0 +1,94 @@
+library ieee;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+entity mark1_jed is
+  port(
+    clock:  in  std_logic;
+    input:  in  std_logic_vector(4 downto 0);
+    output: out std_logic_vector(15 downto 0)
+  );
+end mark1_jed;
+architecture behaviour of mark1_jed is
+  constant state1: std_logic_vector(3 downto 0) := "0001";
+  constant state3: std_logic_vector(3 downto 0) := "1111";
+  constant state2: std_logic_vector(3 downto 0) := "0011";
+  constant state0: std_logic_vector(3 downto 0) := "1101";
+  constant state4: std_logic_vector(3 downto 0) := "1001";
+  constant state13: std_logic_vector(3 downto 0) := "1010";
+  constant state10: std_logic_vector(3 downto 0) := "1000";
+  constant state9: std_logic_vector(3 downto 0) := "1100";
+  constant state8: std_logic_vector(3 downto 0) := "0010";
+  constant state7: std_logic_vector(3 downto 0) := "0000";
+  constant state6: std_logic_vector(3 downto 0) := "0110";
+  constant state5: std_logic_vector(3 downto 0) := "0100";
+  constant state14: std_logic_vector(3 downto 0) := "1110";
+  constant state11: std_logic_vector(3 downto 0) := "0111";
+  constant state12: std_logic_vector(3 downto 0) := "1011";
+  signal current_state, next_state: std_logic_vector(3 downto 0);
+begin
+  process(clock) begin
+    if rising_edge(clock) then current_state <= next_state;
+    end if;
+  end process;
+  process(input, current_state) begin
+    next_state <= "----"; output <= "----------------";
+    if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
+    else
+    case current_state is
+      when state1 =>
+        if std_match(input, "1----") then next_state <= state3; output <= "-11---1-00------";
+        end if;
+      when state2 =>
+        if std_match(input, "1----") then next_state <= state0; output <= "-11---1-00------";
+        end if;
+      when state3 =>
+        if std_match(input, "1----") then next_state <= state4; output <= "101---1-01------";
+        end if;
+      when state4 =>
+        if std_match(input, "1-111") then next_state <= state13; output <= "-11---1-00------";
+        elsif std_match(input, "1-110") then next_state <= state10; output <= "-11---1-00------";
+        elsif std_match(input, "1-10-") then next_state <= state9; output <= "-11---1-00------";
+        elsif std_match(input, "1-011") then next_state <= state8; output <= "-11---1-00------";
+        elsif std_match(input, "1-010") then next_state <= state7; output <= "-11---1-00------";
+        elsif std_match(input, "1-001") then next_state <= state6; output <= "-11---1-00------";
+        elsif std_match(input, "1-000") then next_state <= state5; output <= "-11---1-00------";
+        end if;
+      when state5 =>
+        if std_match(input, "1----") then next_state <= state14; output <= "0011--1-00------";
+        end if;
+      when state6 =>
+        if std_match(input, "1----") then next_state <= state14; output <= "00100-0-00000011";
+        end if;
+      when state7 =>
+        if std_match(input, "1----") then next_state <= state14; output <= "001---1100------";
+        end if;
+      when state8 =>
+        if std_match(input, "1----") then next_state <= state14; output <= "010---1-00------";
+        end if;
+      when state9 =>
+        if std_match(input, "1----") then next_state <= state14; output <= "001---1010000101";
+        end if;
+      when state10 =>
+        if std_match(input, "1----") then next_state <= state11; output <= "-11---1-00100000";
+        end if;
+      when state11 =>
+        if std_match(input, "10---") then next_state <= state13; output <= "-11---1-00------";
+        elsif std_match(input, "11---") then next_state <= state12; output <= "-11---1-00------";
+        end if;
+      when state12 =>
+        if std_match(input, "1----") then next_state <= state13; output <= "-110110-00------";
+        end if;
+      when state13 =>
+        if std_match(input, "1----") then next_state <= state14; output <= "-11---1-00------";
+        end if;
+      when state14 =>
+        if std_match(input, "1----") then next_state <= state3; output <= "-110110-00------";
+        end if;
+      when state0 =>
+        if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
+        end if;
+      when others => next_state <= "----"; output <= "----------------";
+    end case;
+    end if;
+  end process;
+end behaviour;

data/spec/fixtures/mark1_nov.vhd

@@ -0,0 +1,94 @@
+library ieee;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+entity mark1_nov is
+  port(
+    clock:  in  std_logic;
+    input:  in  std_logic_vector(4 downto 0);
+    output: out std_logic_vector(15 downto 0)
+  );
+end mark1_nov;
+architecture behaviour of mark1_nov is
+  constant state1: std_logic_vector(3 downto 0) := "0100";
+  constant state2: std_logic_vector(3 downto 0) := "1000";
+  constant state3: std_logic_vector(3 downto 0) := "1011";
+  constant state4: std_logic_vector(3 downto 0) := "1100";
+  constant state5: std_logic_vector(3 downto 0) := "0001";
+  constant state6: std_logic_vector(3 downto 0) := "0011";
+  constant state7: std_logic_vector(3 downto 0) := "0000";
+  constant state8: std_logic_vector(3 downto 0) := "0010";
+  constant state9: std_logic_vector(3 downto 0) := "1101";
+  constant state10: std_logic_vector(3 downto 0) := "1010";
+  constant state11: std_logic_vector(3 downto 0) := "0111";
+  constant state12: std_logic_vector(3 downto 0) := "1001";
+  constant state13: std_logic_vector(3 downto 0) := "0101";
+  constant state14: std_logic_vector(3 downto 0) := "0110";
+  constant state0: std_logic_vector(3 downto 0) := "1110";
+  signal current_state, next_state: std_logic_vector(3 downto 0);
+begin
+  process(clock) begin
+    if rising_edge(clock) then current_state <= next_state;
+    end if;
+  end process;
+  process(input, current_state) begin
+    next_state <= "----"; output <= "----------------";
+    if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
+    else
+    case current_state is
+      when state1 =>
+        if std_match(input, "1----") then next_state <= state3; output <= "-11---1-00------";
+        end if;
+      when state2 =>
+        if std_match(input, "1----") then next_state <= state0; output <= "-11---1-00------";
+        end if;
+      when state3 =>
+        if std_match(input, "1----") then next_state <= state4; output <= "101---1-01------";
+        end if;
+      when state4 =>
+        if std_match(input, "1-111") then next_state <= state13; output <= "-11---1-00------";
+        elsif std_match(input, "1-110") then next_state <= state10; output <= "-11---1-00------";
+        elsif std_match(input, "1-10-") then next_state <= state9; output <= "-11---1-00------";
+        elsif std_match(input, "1-011") then next_state <= state8; output <= "-11---1-00------";
+        elsif std_match(input, "1-010") then next_state <= state7; output <= "-11---1-00------";
+        elsif std_match(input, "1-001") then next_state <= state6; output <= "-11---1-00------";
+        elsif std_match(input, "1-000") then next_state <= state5; output <= "-11---1-00------";
+        end if;
+      when state5 =>
+        if std_match(input, "1----") then next_state <= state14; output <= "0011--1-00------";
+        end if;
+      when state6 =>
+        if std_match(input, "1----") then next_state <= state14; output <= "00100-0-00000011";
+        end if;
+      when state7 =>
+        if std_match(input, "1----") then next_state <= state14; output <= "001---1100------";
+        end if;
+      when state8 =>
+        if std_match(input, "1----") then next_state <= state14; output <= "010---1-00------";
+        end if;
+      when state9 =>
+        if std_match(input, "1----") then next_state <= state14; output <= "001---1010000101";
+        end if;
+      when state10 =>
+        if std_match(input, "1----") then next_state <= state11; output <= "-11---1-00100000";
+        end if;
+      when state11 =>
+        if std_match(input, "10---") then next_state <= state13; output <= "-11---1-00------";
+        elsif std_match(input, "11---") then next_state <= state12; output <= "-11---1-00------";
+        end if;
+      when state12 =>
+        if std_match(input, "1----") then next_state <= state13; output <= "-110110-00------";
+        end if;
+      when state13 =>
+        if std_match(input, "1----") then next_state <= state14; output <= "-11---1-00------";
+        end if;
+      when state14 =>
+        if std_match(input, "1----") then next_state <= state3; output <= "-110110-00------";
+        end if;
+      when state0 =>
+        if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
+        end if;
+      when others => next_state <= "----"; output <= "----------------";
+    end case;
+    end if;
+  end process;
+end behaviour;

metadata

@@ -1,7 +1,12 @@
 --- !ruby/object:Gem::Specification 
 name: art-decomp
 version: !ruby/object:Gem::Version 
-  version: 0.3.0
+  prerelease: false
+  segments: 
+  - 0
+  - 4
+  - 0
+  version: 0.4.0
 platform: ruby
 authors: 
 - Piotr Szotkowski
@@ -9,74 +14,87 @@ autorequire:
 bindir: bin
 cert_chain: []
 
-date: 2010-01-10 00:00:00 +01:00
+date: 2010-03-13 00:00:00 +01:00
 default_executable: 
 dependencies: 
 - !ruby/object:Gem::Dependency 
-  name: teejayvanslyke-gazer
-  type: :runtime
-  version_requirement: 
-  version_requirements: !ruby/object:Gem::Requirement 
+  name: rcapture
+  prerelease: false
+  requirement: &id001 !ruby/object:Gem::Requirement 
     requirements: 
     - - ">="
       - !ruby/object:Gem::Version 
+        segments: 
+        - 0
         version: "0"
-    version: 
+  type: :runtime
+  version_requirements: *id001
 - !ruby/object:Gem::Dependency 
   name: trollop
-  type: :runtime
-  version_requirement: 
-  version_requirements: !ruby/object:Gem::Requirement 
+  prerelease: false
+  requirement: &id002 !ruby/object:Gem::Requirement 
     requirements: 
     - - ">="
       - !ruby/object:Gem::Version 
+        segments: 
+        - 0
         version: "0"
-    version: 
+  type: :runtime
+  version_requirements: *id002
 - !ruby/object:Gem::Dependency 
   name: diff-lcs
-  type: :development
-  version_requirement: 
-  version_requirements: !ruby/object:Gem::Requirement 
+  prerelease: false
+  requirement: &id003 !ruby/object:Gem::Requirement 
     requirements: 
     - - ">="
       - !ruby/object:Gem::Version 
+        segments: 
+        - 0
         version: "0"
-    version: 
+  type: :development
+  version_requirements: *id003
 - !ruby/object:Gem::Dependency 
   name: jeweler
-  type: :development
-  version_requirement: 
-  version_requirements: !ruby/object:Gem::Requirement 
+  prerelease: false
+  requirement: &id004 !ruby/object:Gem::Requirement 
     requirements: 
     - - ">="
       - !ruby/object:Gem::Version 
+        segments: 
+        - 0
         version: "0"
-    version: 
+  type: :development
+  version_requirements: *id004
 - !ruby/object:Gem::Dependency 
   name: rcov
-  type: :development
-  version_requirement: 
-  version_requirements: !ruby/object:Gem::Requirement 
+  prerelease: false
+  requirement: &id005 !ruby/object:Gem::Requirement 
     requirements: 
     - - ">="
       - !ruby/object:Gem::Version 
+        segments: 
+        - 0
         version: "0"
-    version: 
+  type: :development
+  version_requirements: *id005
 - !ruby/object:Gem::Dependency 
   name: rspec
-  type: :development
-  version_requirement: 
-  version_requirements: !ruby/object:Gem::Requirement 
+  prerelease: false
+  requirement: &id006 !ruby/object:Gem::Requirement 
     requirements: 
     - - ">="
       - !ruby/object:Gem::Version 
+        segments: 
+        - 0
         version: "0"
-    version: 
+  type: :development
+  version_requirements: *id006
 description: 
 email: p.szotkowski@tele.pw.edu.pl
 executables: 
 - ad-validate
 - ad-console
+- ad-kiss2vhdl
 - ad-fsm-info
 - art-decomp
 extensions: []
@@ -91,6 +109,7 @@ files:
 - VERSION
 - bin/ad-console
 - bin/ad-fsm-info
+- bin/ad-kiss2vhdl
 - bin/ad-validate
 - bin/art-decomp
 - lib/art-decomp.rb
@@ -116,6 +135,7 @@ files:
 - lib/art-decomp/uv_generator/general_relevance.rb
 - lib/art-decomp/uv_generator/unique_relevance.rb
 - lib/art-decomp/uv_relevance_generator.rb
+- lib/art-decomp/vhdl.rb
 - lib/core/enumerable.rb
 - lib/core/file.rb
 - lib/core/integer.rb
@@ -142,12 +162,15 @@ files:
 - spec/art-decomp/uv_generator/general_relevance_spec.rb
 - spec/art-decomp/uv_generator/unique_relevance_spec.rb
 - spec/art-decomp/uv_relevance_generator_spec.rb
+- spec/art-decomp/vhdl_spec.rb
 - spec/core/enumerable_spec.rb
 - spec/core/file_spec.rb
 - spec/core/integer_spec.rb
 - spec/core/set_spec.rb
 - spec/core/string_spec.rb
 - spec/fixtures/ex4
+- spec/fixtures/ex4.hot
+- spec/fixtures/ex4_hot.vhd
 - spec/fixtures/ex5
 - spec/fixtures/fsm
 - spec/fixtures/fsm.exp
@@ -156,11 +179,21 @@ files:
 - spec/fixtures/fsm.h
 - spec/fixtures/fsm.partially-exp
 - spec/fixtures/fsm.q
+- spec/fixtures/fsm.vhd
+- spec/fixtures/kirkman
 - spec/fixtures/lion
 - spec/fixtures/lion.exp
 - spec/fixtures/lion.h
 - spec/fixtures/lion.to_kiss
 - spec/fixtures/mark1
+- spec/fixtures/mark1.hot
+- spec/fixtures/mark1.jed
+- spec/fixtures/mark1.nov
+- spec/fixtures/mark1.vhd
+- spec/fixtures/mark1.yml
+- spec/fixtures/mark1_hot.vhd
+- spec/fixtures/mark1_jed.vhd
+- spec/fixtures/mark1_nov.vhd
 - spec/fixtures/mc
 - spec/fixtures/mc.to_kiss
 - spec/fixtures/opus
@@ -184,18 +217,20 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements: 
   - - ">="
     - !ruby/object:Gem::Version 
+      segments: 
+      - 0
       version: "0"
-  version: 
 required_rubygems_version: !ruby/object:Gem::Requirement 
   requirements: 
   - - ">="
     - !ruby/object:Gem::Version 
+      segments: 
+      - 0
       version: "0"
-  version: 
 requirements: []
 
 rubyforge_project: 
-rubygems_version: 1.3.5
+rubygems_version: 1.3.6
 signing_key: 
 specification_version: 3
 summary: "art d\xC3\xA9comp: an FSM \xE2\x86\x92 FPGA decomposer"
@@ -219,6 +254,7 @@ test_files:
 - spec/art-decomp/qv_generator/graph_merging_spec.rb
 - spec/art-decomp/executable_spec.rb
 - spec/art-decomp/decomposer_spec.rb
+- spec/art-decomp/vhdl_spec.rb
 - spec/art-decomp/qu_generator/edge_labels_spec.rb
 - spec/art-decomp/qu_generator/block_table_spec.rb
 - spec/art-decomp/uv_generator/general_relevance_spec.rb