art-decomp 0.3.0 → 0.4.0
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- data/Rakefile +1 -1
- data/VERSION +1 -1
- data/bin/ad-kiss2vhdl +8 -0
- data/lib/art-decomp.rb +2 -0
- data/lib/art-decomp/bipainter.rb +36 -36
- data/lib/art-decomp/executable.rb +3 -3
- data/lib/art-decomp/fsm.rb +28 -3
- data/lib/art-decomp/graph.rb +19 -19
- data/lib/art-decomp/logging.rb +51 -34
- data/lib/art-decomp/uv_generator/braindead.rb +1 -2
- data/lib/art-decomp/vhdl.rb +72 -0
- data/spec/art-decomp/executable_spec.rb +2 -2
- data/spec/art-decomp/fsm_spec.rb +41 -0
- data/spec/art-decomp/logging_spec.rb +10 -24
- data/spec/art-decomp/vhdl_spec.rb +22 -0
- data/spec/fixtures/ex4.hot +44 -0
- data/spec/fixtures/ex4_hot.vhd +87 -0
- data/spec/fixtures/fsm.vhd +64 -0
- data/spec/fixtures/kirkman +374 -0
- data/spec/fixtures/mark1.hot +46 -0
- data/spec/fixtures/mark1.jed +48 -0
- data/spec/fixtures/mark1.nov +340 -0
- data/spec/fixtures/mark1.vhd +79 -0
- data/spec/fixtures/mark1.yml +86 -0
- data/spec/fixtures/mark1_hot.vhd +94 -0
- data/spec/fixtures/mark1_jed.vhd +94 -0
- data/spec/fixtures/mark1_nov.vhd +94 -0
- metadata +66 -30
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.model jedi_output
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2
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.start_kiss
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3
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.i 5
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4
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.o 16
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5
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.s 15
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6
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.p 22
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7
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.r state1
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0---- * state1 -11---1-00------
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9
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1---- state1 state3 -11---1-00------
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10
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1---- state2 state0 -11---1-00------
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11
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1---- state3 state4 101---1-01------
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12
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1-111 state4 state13 -11---1-00------
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13
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1-110 state4 state10 -11---1-00------
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14
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1-10- state4 state9 -11---1-00------
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1-011 state4 state8 -11---1-00------
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1-010 state4 state7 -11---1-00------
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1-001 state4 state6 -11---1-00------
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1-000 state4 state5 -11---1-00------
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1---- state5 state14 0011--1-00------
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1---- state6 state14 00100-0-00000011
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1---- state7 state14 001---1100------
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1---- state8 state14 010---1-00------
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1---- state9 state14 001---1010000101
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1---- state10 state11 -11---1-00100000
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10--- state11 state13 -11---1-00------
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11--- state11 state12 -11---1-00------
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1---- state12 state13 -110110-00------
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1---- state13 state14 -11---1-00------
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1---- state14 state3 -110110-00------
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.end_kiss
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.code state1 100000000000000
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.code state3 010000000000000
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.code state2 001000000000000
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.code state0 000100000000000
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.code state4 000010000000000
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.code state13 000001000000000
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.code state10 000000100000000
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.code state9 000000010000000
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.code state8 000000001000000
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.code state7 000000000100000
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.code state6 000000000010000
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.code state5 000000000001000
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.code state14 000000000000100
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.code state11 000000000000010
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.code state12 000000000000001
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.end
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#
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# JEDI, official release 1.2
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#
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# States.state1 0001
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# States.state3 1111
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# States.state2 0011
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# States.state0 1101
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# States.state4 1001
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# States.state13 1010
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# States.state10 1000
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11
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# States.state9 1100
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12
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# States.state8 0010
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13
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# States.state7 0000
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14
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# States.state6 0110
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15
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# States.state5 0100
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16
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# States.state14 1110
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# States.state11 0111
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# States.state12 1011
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#
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.type fr
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.i 9
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.o 20
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.ilb v.0 v.1 v.2 v.3 v.4 v.5.0 v.5.1 v.5.2 v.5.3
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.ob v.6.0 v.6.1 v.6.2 v.6.3 v.7 v.8 v.9 v.10 v.11 v.12 v.13 v.14 v.15 v.16 v.17 v.18 v.19 v.20 v.21 v.22
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0-------- 0001-11---1-00------
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1----0001 1111-11---1-00------
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1----0011 1101-11---1-00------
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1----1111 1001101---1-01------
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1-1111001 1010-11---1-00------
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1-1101001 1000-11---1-00------
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1-10-1001 1100-11---1-00------
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1-0111001 0010-11---1-00------
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1-0101001 0000-11---1-00------
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1-0011001 0110-11---1-00------
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1-0001001 0100-11---1-00------
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1----0100 11100011--1-00------
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1----0110 111000100-0-00000011
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1----0000 1110001---1100------
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1----0010 1110010---1-00------
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1----1100 1110001---1010000101
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1----1000 0111-11---1-00100000
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10---0111 1010-11---1-00------
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1----1011 1010-110110-00------
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1----1010 1110-11---1-00------
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1----1110 1111-110110-00------
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-----0101 --------------------
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.e
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# c:/users/mariusz/sis/bin/nova.exe -t 1MARK1
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.model 1MARK1.esp
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.start_kiss
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.i 5
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.o 16
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.p 22
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.s 15
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0---- * state1 -11---1-00------
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1---- state1 state3 -11---1-00------
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1---- state2 state0 -11---1-00------
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1---- state3 state4 101---1-01------
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1-111 state4 state13 -11---1-00------
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1-110 state4 state10 -11---1-00------
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1-10- state4 state9 -11---1-00------
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1-011 state4 state8 -11---1-00------
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1-010 state4 state7 -11---1-00------
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1-001 state4 state6 -11---1-00------
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1-000 state4 state5 -11---1-00------
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1---- state5 state14 0011--1-00------
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1---- state6 state14 00100-0-00000011
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1---- state7 state14 001---1100------
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1---- state8 state14 010---1-00------
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1---- state9 state14 001---1010000101
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1---- state10 state11 -11---1-00100000
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10--- state11 state13 -11---1-00------
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11--- state11 state12 -11---1-00------
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1---- state12 state13 -110110-00------
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1---- state13 state14 -11---1-00------
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1---- state14 state3 -110110-00------
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.end_kiss
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#
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# Prod.-terms of minimized MV cover = 19
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# Prod.-terms of encoded cover = 20
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# Pla area = 760
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#
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# .start_codes
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.code * 1111
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.code state1 0100
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.code state2 1000
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.code state3 1011
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.code state4 1100
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.code state5 0001
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.code state6 0011
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.code state7 0000
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.code state8 0010
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.code state9 1101
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.code state10 1010
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.code state11 0111
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.code state12 1001
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.code state13 0101
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.code state14 0110
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.code state0 1110
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# .end_codes
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#
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# .start_network
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.inputs v0 v1 v2 v3 v4
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.outputs v9.4 v9.5 v9.6 v9.7 v9.8 v9.9 v9.10 v9.11 v9.12 \
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v9.13 v9.14 v9.15 v9.16 v9.17 v9.18 v9.19
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.latch v9.0 v5 1
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.latch v9.1 v6 1
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.latch v9.2 v7 1
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.latch v9.3 v8 1
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.latch_order v5 v6 v7 v8
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.names v1 v2 v3 v4 v5 v6 v7 v8 v9.0
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----01-0 1
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----1011 1
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----1000 1
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1---0111 1
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-110-1-0 1
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-10-11-0 1
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.names v1 v2 v3 v4 v5 v6 v7 v8 v9.1
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----00-- 1
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----111- 1
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----1-10 1
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----1011 1
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----1101 1
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----0101 1
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----1001 1
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----1000 1
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-1-111-0 1
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.names v2 v3 v4 v5 v6 v7 v8 v9.2
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---00-- 1
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---0-0- 1
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.names v1 v2 v3 v4 v5 v6 v7 v8 v9.3
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--0--1-0 1
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----01-0 1
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.names v5 v6 v7 v8 v9.4
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1011 1
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.names v1 v5 v6 v7 v8 v9.5
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-111- 1
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--100 1
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-0101 1
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-1001 1
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-1000 1
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10111 1
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00111 1
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.names v5 v6 v7 v8 v9.6
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---1 1
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.names v5 v7 v9.7
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.names v5 v6 v7 v8 v9.8
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1001 1
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.names v5 v6 v7 v8 v9.9
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01-0 1
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1001 1
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.names v1 v5 v6 v7 v8 v9.10
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--010 1
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--100 1
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-1101 1
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-1000 1
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10111 1
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00111 1
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.names v5 v7 v9.11
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.names v5 v6 v7 v8 v9.12
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1101 1
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.names v5 v6 v7 v8 v9.13
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1011 1
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.names v5 v7 v8 v9.14
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110 1
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.names v9.15
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.names v9.16
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.names v5 v6 v7 v8 v9.17
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1101 1
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.names v5 v6 v9.18
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00 1
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.names v8 v9.19
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1 1
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.exdc
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.inputs v0 v1 v2 v3 v4 v5 v6 v7 v8
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.outputs v9.0 v9.1 v9.2 v9.3 v9.4 v9.5 v9.6 v9.7 v9.8 v9.9 v9.10 v9.11 v9.12 \
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v9.13 v9.14 v9.15 v9.16 v9.17 v9.18 v9.19
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.names v0 v5 v6 v7 v8 v9.0
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.names v0 v5 v6 v7 v8 v9.1
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.names v0 v5 v6 v7 v8 v9.2
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.names v0 v5 v6 v7 v8 v9.3
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.names v0 v5 v6 v7 v8 v9.4
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.names v0 v5 v6 v7 v8 v9.5
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.names v0 v5 v6 v7 v8 v9.6
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.names v0 v5 v6 v7 v8 v9.7
|
|
207
|
+
0---- 1
|
|
208
|
+
-1-1- 1
|
|
209
|
+
--10- 1
|
|
210
|
+
--1-1 1
|
|
211
|
+
--0-0 1
|
|
212
|
+
---00 1
|
|
213
|
+
.names v0 v5 v6 v7 v8 v9.8
|
|
214
|
+
0---- 1
|
|
215
|
+
-1-1- 1
|
|
216
|
+
-0-0- 1
|
|
217
|
+
--10- 1
|
|
218
|
+
--1-1 1
|
|
219
|
+
--0-0 1
|
|
220
|
+
---00 1
|
|
221
|
+
.names v0 v5 v6 v7 v8 v9.9
|
|
222
|
+
0---- 1
|
|
223
|
+
-1-1- 1
|
|
224
|
+
--01- 1
|
|
225
|
+
-0-0- 1
|
|
226
|
+
--10- 1
|
|
227
|
+
--1-1 1
|
|
228
|
+
--0-0 1
|
|
229
|
+
---00 1
|
|
230
|
+
.names v0 v5 v6 v7 v8 v9.10
|
|
231
|
+
00--- 1
|
|
232
|
+
0-0-- 1
|
|
233
|
+
0--0- 1
|
|
234
|
+
0---0 1
|
|
235
|
+
1111- 1
|
|
236
|
+
-1110 1
|
|
237
|
+
.names v0 v5 v6 v7 v8 v9.11
|
|
238
|
+
0---- 1
|
|
239
|
+
-01-- 1
|
|
240
|
+
-10-- 1
|
|
241
|
+
-0-1- 1
|
|
242
|
+
-0--1 1
|
|
243
|
+
-1--0 1
|
|
244
|
+
1111- 1
|
|
245
|
+
.names v0 v5 v6 v7 v8 v9.12
|
|
246
|
+
00--- 1
|
|
247
|
+
0-0-- 1
|
|
248
|
+
0--0- 1
|
|
249
|
+
0---0 1
|
|
250
|
+
1111- 1
|
|
251
|
+
-1110 1
|
|
252
|
+
.names v0 v5 v6 v7 v8 v9.13
|
|
253
|
+
00--- 1
|
|
254
|
+
0-0-- 1
|
|
255
|
+
0--0- 1
|
|
256
|
+
0---0 1
|
|
257
|
+
1111- 1
|
|
258
|
+
-1110 1
|
|
259
|
+
.names v0 v5 v6 v7 v8 v9.14
|
|
260
|
+
0---- 1
|
|
261
|
+
-01-- 1
|
|
262
|
+
-0-0- 1
|
|
263
|
+
--00- 1
|
|
264
|
+
-0--0 1
|
|
265
|
+
--1-0 1
|
|
266
|
+
-10-1 1
|
|
267
|
+
1111- 1
|
|
268
|
+
.names v0 v5 v6 v7 v8 v9.15
|
|
269
|
+
0---- 1
|
|
270
|
+
-01-- 1
|
|
271
|
+
--11- 1
|
|
272
|
+
-0-0- 1
|
|
273
|
+
--00- 1
|
|
274
|
+
-0--0 1
|
|
275
|
+
--1-0 1
|
|
276
|
+
-10-1 1
|
|
277
|
+
.names v0 v5 v6 v7 v8 v9.16
|
|
278
|
+
0---- 1
|
|
279
|
+
-01-- 1
|
|
280
|
+
--11- 1
|
|
281
|
+
-0-0- 1
|
|
282
|
+
--00- 1
|
|
283
|
+
-0--0 1
|
|
284
|
+
--1-0 1
|
|
285
|
+
-10-1 1
|
|
286
|
+
.names v0 v5 v6 v7 v8 v9.17
|
|
287
|
+
0---- 1
|
|
288
|
+
-01-- 1
|
|
289
|
+
--11- 1
|
|
290
|
+
-0-0- 1
|
|
291
|
+
--00- 1
|
|
292
|
+
-0--0 1
|
|
293
|
+
--1-0 1
|
|
294
|
+
-10-1 1
|
|
295
|
+
.names v0 v5 v6 v7 v8 v9.18
|
|
296
|
+
0---- 1
|
|
297
|
+
-01-- 1
|
|
298
|
+
--11- 1
|
|
299
|
+
-0-0- 1
|
|
300
|
+
--00- 1
|
|
301
|
+
-0--0 1
|
|
302
|
+
--1-0 1
|
|
303
|
+
-10-1 1
|
|
304
|
+
.names v0 v5 v6 v7 v8 v9.19
|
|
305
|
+
0---- 1
|
|
306
|
+
-01-- 1
|
|
307
|
+
--11- 1
|
|
308
|
+
-0-0- 1
|
|
309
|
+
--00- 1
|
|
310
|
+
-0--0 1
|
|
311
|
+
--1-0 1
|
|
312
|
+
-10-1 1
|
|
313
|
+
.end
|
|
314
|
+
# .end_network
|
|
315
|
+
.i 9
|
|
316
|
+
.o 20
|
|
317
|
+
.p 20
|
|
318
|
+
--110-1-0 10100000000000000000
|
|
319
|
+
--10-11-0 11000000000000000000
|
|
320
|
+
--1-111-0 01010000000000000000
|
|
321
|
+
--0-1---0 00100000000000000000
|
|
322
|
+
-1---0111 10010100001000000000
|
|
323
|
+
-0---0111 01010100001000000000
|
|
324
|
+
---0--1-0 00010000000000000000
|
|
325
|
+
-----0101 01000100000000000000
|
|
326
|
+
-----1011 11001000001001000000
|
|
327
|
+
-----1001 01010100110000000000
|
|
328
|
+
------010 00000100001000000000
|
|
329
|
+
-----1101 01100000001010000100
|
|
330
|
+
------100 00000110001000000000
|
|
331
|
+
-----00-- 01100000000000000010
|
|
332
|
+
-----111- 01000100001000000000
|
|
333
|
+
--------1 00000010000000000001
|
|
334
|
+
-----0-0- 00100011001100000000
|
|
335
|
+
-----1-10 01110010000000100000
|
|
336
|
+
-----1000 11100110001000000000
|
|
337
|
+
-----01-0 10110110110000000000
|
|
338
|
+
.e
|
|
339
|
+
#
|
|
340
|
+
# CPU time = 0.0 seconds
|
|
@@ -0,0 +1,79 @@
|
|
|
1
|
+
library ieee;
|
|
2
|
+
use ieee.numeric_std.all;
|
|
3
|
+
use ieee.std_logic_1164.all;
|
|
4
|
+
entity mark1 is
|
|
5
|
+
port(
|
|
6
|
+
clock: in std_logic;
|
|
7
|
+
input: in std_logic_vector(4 downto 0);
|
|
8
|
+
output: out std_logic_vector(15 downto 0)
|
|
9
|
+
);
|
|
10
|
+
end mark1;
|
|
11
|
+
architecture behaviour of mark1 is
|
|
12
|
+
type state is (state1, state2, state3, state4, state5, state6, state7, state8, state9, state10, state11, state12, state13, state14, state0);
|
|
13
|
+
signal current_state, next_state: state;
|
|
14
|
+
begin
|
|
15
|
+
process(clock) begin
|
|
16
|
+
if rising_edge(clock) then current_state <= next_state;
|
|
17
|
+
end if;
|
|
18
|
+
end process;
|
|
19
|
+
process(input, current_state) begin
|
|
20
|
+
next_state <= state1; output <= "----------------";
|
|
21
|
+
if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
|
|
22
|
+
else
|
|
23
|
+
case current_state is
|
|
24
|
+
when state1 =>
|
|
25
|
+
if std_match(input, "1----") then next_state <= state3; output <= "-11---1-00------";
|
|
26
|
+
end if;
|
|
27
|
+
when state2 =>
|
|
28
|
+
if std_match(input, "1----") then next_state <= state0; output <= "-11---1-00------";
|
|
29
|
+
end if;
|
|
30
|
+
when state3 =>
|
|
31
|
+
if std_match(input, "1----") then next_state <= state4; output <= "101---1-01------";
|
|
32
|
+
end if;
|
|
33
|
+
when state4 =>
|
|
34
|
+
if std_match(input, "1-111") then next_state <= state13; output <= "-11---1-00------";
|
|
35
|
+
elsif std_match(input, "1-110") then next_state <= state10; output <= "-11---1-00------";
|
|
36
|
+
elsif std_match(input, "1-10-") then next_state <= state9; output <= "-11---1-00------";
|
|
37
|
+
elsif std_match(input, "1-011") then next_state <= state8; output <= "-11---1-00------";
|
|
38
|
+
elsif std_match(input, "1-010") then next_state <= state7; output <= "-11---1-00------";
|
|
39
|
+
elsif std_match(input, "1-001") then next_state <= state6; output <= "-11---1-00------";
|
|
40
|
+
elsif std_match(input, "1-000") then next_state <= state5; output <= "-11---1-00------";
|
|
41
|
+
end if;
|
|
42
|
+
when state5 =>
|
|
43
|
+
if std_match(input, "1----") then next_state <= state14; output <= "0011--1-00------";
|
|
44
|
+
end if;
|
|
45
|
+
when state6 =>
|
|
46
|
+
if std_match(input, "1----") then next_state <= state14; output <= "00100-0-00000011";
|
|
47
|
+
end if;
|
|
48
|
+
when state7 =>
|
|
49
|
+
if std_match(input, "1----") then next_state <= state14; output <= "001---1100------";
|
|
50
|
+
end if;
|
|
51
|
+
when state8 =>
|
|
52
|
+
if std_match(input, "1----") then next_state <= state14; output <= "010---1-00------";
|
|
53
|
+
end if;
|
|
54
|
+
when state9 =>
|
|
55
|
+
if std_match(input, "1----") then next_state <= state14; output <= "001---1010000101";
|
|
56
|
+
end if;
|
|
57
|
+
when state10 =>
|
|
58
|
+
if std_match(input, "1----") then next_state <= state11; output <= "-11---1-00100000";
|
|
59
|
+
end if;
|
|
60
|
+
when state11 =>
|
|
61
|
+
if std_match(input, "10---") then next_state <= state13; output <= "-11---1-00------";
|
|
62
|
+
elsif std_match(input, "11---") then next_state <= state12; output <= "-11---1-00------";
|
|
63
|
+
end if;
|
|
64
|
+
when state12 =>
|
|
65
|
+
if std_match(input, "1----") then next_state <= state13; output <= "-110110-00------";
|
|
66
|
+
end if;
|
|
67
|
+
when state13 =>
|
|
68
|
+
if std_match(input, "1----") then next_state <= state14; output <= "-11---1-00------";
|
|
69
|
+
end if;
|
|
70
|
+
when state14 =>
|
|
71
|
+
if std_match(input, "1----") then next_state <= state3; output <= "-110110-00------";
|
|
72
|
+
end if;
|
|
73
|
+
when state0 =>
|
|
74
|
+
if std_match(input, "0----") then next_state <= state1; output <= "-11---1-00------";
|
|
75
|
+
end if;
|
|
76
|
+
end case;
|
|
77
|
+
end if;
|
|
78
|
+
end process;
|
|
79
|
+
end behaviour;
|