art-decomp 0.3.0 → 0.4.0

data/spec/art-decomp/executable_spec.rb

@@ -145,14 +145,14 @@ module ArtDecomp describe Executable do
     Executable.new(['--archs', '5/1', '4/2', '--debug', '--log', log.path, '--outdir', @dir, @fsm]).run
     Logging.level.should == Logger::DEBUG
     Logging.off
-    File.read(log.path).should =~ rex('FSM 4/2+10s → 5/1+4/2')
+    File.read(log.path).should =~ rex('4/2+10s')
   end
 
   it 'should handle the s8 edge case with grace' do
     log = Tempfile.new rand
     Executable.new(['--archs', '2/1', '--log', log.path, '--outdir', @dir, 'spec/fixtures/s8']).run
     Logging.off
-    File.read(log.path).should =~ rex('final best decomposition: 0 cells')
+    File.read(log.path).should =~ rex(' 0c')
   end
 
   # FIXME: add specs for --binary, --non-disjoint and --deep-ndj

data/spec/art-decomp/fsm_spec.rb

@@ -23,6 +23,10 @@ module ArtDecomp describe FSM do
       lambda { FSM.from_kiss 'spec/fixtures/ex5' }.should_not raise_error
     end
 
+    it 'should ignore KISS lines with don’t-care next states and outputs' do
+      FSM.from_kiss('spec/fixtures/kirkman').beta_q.ints.map(&:bits).flatten.max.should == 366
+    end
+
     it 'should handle truth table files by faking a don’t-care state column' do
       @tt.input_count.should  == 4
       @tt.output_count.should == 2
@@ -178,6 +182,43 @@ module ArtDecomp describe FSM do
       @fsm.should_not be_truth_table
     end
 
+    it 'should properly generate its structure' do
+      @mark1.structure.to_yaml.should == File.read('spec/fixtures/mark1.yml')
+    end
+
+    it 'should properly generate its VHDL representation' do
+      @fsm.to_vhdl('fsm').should     == File.read('spec/fixtures/fsm.vhd')
+      @mark1.to_vhdl('mark1').should == File.read('spec/fixtures/mark1.vhd')
+    end
+
+  end
+
+  context 'parsed from an encoded KISS file' do
+
+    before do
+      @one_hot = FSM.from_kiss 'spec/fixtures/mark1.hot'
+      @nova    = FSM.from_kiss 'spec/fixtures/mark1.nov'
+      @jedi    = FSM.from_kiss 'spec/fixtures/mark1.jed'
+    end
+
+    it 'should properly create the FSM' do
+      @one_hot.should == FSM.from_kiss('spec/fixtures/mark1')
+      @nova.should    == FSM.from_kiss('spec/fixtures/mark1')
+      @jedi.should    == FSM.from_kiss('spec/fixtures/mark1')
+    end
+
+    it 'should properly find codes in an one-hot file' do
+      @one_hot.codes.should == {:state1 => :'100000000000000', :state3 => :'010000000000000', :state2 => :'001000000000000', :state0 => :'000100000000000', :state4 => :'000010000000000', :state13 => :'000001000000000', :state10 => :'000000100000000', :state9 => :'000000010000000', :state8 => :'000000001000000', :state7 => :'000000000100000', :state6 => :'000000000010000', :state5 => :'000000000001000', :state14 => :'000000000000100', :state11 => :'000000000000010', :state12 => :'000000000000001'}
+      @nova.codes.should    == {:state1 => :'0100', :state2 => :'1000', :state3 => :'1011', :state4 => :'1100', :state5 => :'0001', :state6 => :'0011', :state7 => :'0000', :state8 => :'0010', :state9 => :'1101', :state10 => :'1010', :state11 => :'0111', :state12 => :'1001', :state13 => :'0101', :state14 => :'0110', :state0 => :'1110'}
+      @jedi.codes.should    == {:state1 => :'0001', :state3 => :'1111', :state2 => :'0011', :state0 => :'1101', :state4 => :'1001', :state13 => :'1010', :state10 => :'1000', :state9 => :'1100', :state8 => :'0010', :state7 => :'0000', :state6 => :'0110', :state5 => :'0100', :state14 => :'1110', :state11 => :'0111', :state12 => :'1011'}
+    end
+
+    it 'should properly generate the (encoded) VHDL' do
+      @one_hot.to_vhdl('mark1_hot').should == File.read('spec/fixtures/mark1_hot.vhd')
+      @nova.to_vhdl('mark1_nov').should    == File.read('spec/fixtures/mark1_nov.vhd')
+      @jedi.to_vhdl('mark1_jed').should    == File.read('spec/fixtures/mark1_jed.vhd')
+    end
+
   end
 
 end end

data/spec/art-decomp/logging_spec.rb

@@ -9,6 +9,7 @@ module ArtDecomp describe Logging do
     @fsm = mock FSM, :beta_f => Blanket[], :beta_q => Blanket[], :beta_x => Blanket[]
     @log = StringIO.new
     Logging.log = @log
+    Logging.level = Logger::INFO
   end
 
   after do
@@ -24,7 +25,7 @@ module ArtDecomp describe Logging do
   it 'should log Executable’s decompositions calls on simple cases' do
     args = ['-a', '5/1', '4/2', '-o', @dir, 'spec/fixtures/lion']
     Executable.new(args).run
-    log.should =~ rex('final best decomposition: 2 cells; done in 0s (0h 0m 0s)')
+    log.should =~ rex('took 1s')
   end
 
   it 'should log Executable’s decompositions calls on typical cases' do
@@ -33,41 +34,26 @@ module ArtDecomp describe Logging do
     ex = Executable.new(args)
     ex.stub!(:best).and_return 69
     ex.run
-    log.should =~ rex('FSM 4/2+10s → 5/1+4/2 () with UniqueRelevance, EdgeLabels, GraphColouring – best so far: 69 cells')
-    log.should =~ rex('final best decomposition: 69 cells; done in 0s (0h 0m 0s)')
+    log.should =~ rex('4/2+10s with UniqueRelevance, EdgeLabels, GraphColouring')
+    log.should =~ rex('took 1s')
   end
 
   it 'should log Executable’s decompositions calls on problematic cases' do
     Decomposer.should_receive(:new).and_return mock(Decomposer, :decompositions => [].each)
     args = ['-a', '5/1', '4/2', '-o', @dir, 'spec/fixtures/fsm']
     Executable.new(args).run
-    log.should =~ rex('FSM 4/2+10s → 5/1+4/2 () with UniqueRelevance, EdgeLabels, GraphColouring – no decomposition so far')
-    log.should =~ rex('no final decomposition; done in 0s (0h 0m 0s)')
+    log.should =~ rex('4/2+10s with UniqueRelevance, EdgeLabels, GraphColouring')
+    log.should =~ rex('took 1s')
   end
 
-  it 'should log UVGenerators’ uv_pairs calls' do
-    uv = UVGenerator::Braindead.new
-    uv.uv_pairs mock(FSM, :input_count => 2), Set[Arch[5,1]]
-    log.should =~ rex('UV with Braindead')
-  end
-
-  it 'should log QuGenerators’ blankets calls' do
+  it 'should log QuGenerators’ blankets calls (if debug-level logging enabled)' do
+    Logging.level = Logger::DEBUG
     qu = QuGenerator::BlockTable.new
     [[Set[0], Set[1]], [Set[1], Set[0]]].each do |u, v|
       qu.blankets @fsm, u, v
     end
-    log.should =~ rex('U = [0], V = [1], Qu with BlockTable')
-    log.should =~ rex('U = [1], V = [0], Qu with BlockTable')
-  end
-
-  it 'should log QvGenerators’ blankets calls (on the DEBUG level)' do
-    Logging.level = Logger::DEBUG
-    qv = QvGenerator::GraphColouring.new
-    [mock(Blanket, :size => 8), mock(Blanket, :size => 4)].each do |qu|
-      qv.blankets @fsm, Set[0], Set[1], qu
-    end
-    log.should =~ rex('|Qu| = 8, Qv+G with GraphColouring')
-    log.should =~ rex('|Qu| = 4, Qv+G with GraphColouring')
+    log.should =~ rex('0          1          via  with BlockTable')
+    log.should =~ rex('1          0          via  with BlockTable')
   end
 
 end end

data/spec/art-decomp/vhdl_spec.rb

@@ -0,0 +1,22 @@
+# encoding: UTF-8
+
+module ArtDecomp describe VHDL do
+
+  context 'generated from an FSM' do
+
+    it 'should properly generates the VHDL representation' do
+      VHDL.new(FSM.from_kiss 'spec/fixtures/fsm').vhdl('fsm').should     == File.read('spec/fixtures/fsm.vhd')
+      VHDL.new(FSM.from_kiss 'spec/fixtures/mark1').vhdl('mark1').should == File.read('spec/fixtures/mark1.vhd')
+    end
+
+    it 'should generate encoded VHDL if the FSM is encoded' do
+      VHDL.new(FSM.from_kiss 'spec/fixtures/mark1.hot').vhdl('mark1_hot').should == File.read('spec/fixtures/mark1_hot.vhd')
+    end
+
+    it 'should rename digit-only states' do
+      VHDL.new(FSM.from_kiss 'spec/fixtures/ex4.hot').vhdl('ex4_hot').should == File.read('spec/fixtures/ex4_hot.vhd')
+    end
+
+  end
+
+end end

data/spec/fixtures/ex4.hot

@@ -0,0 +1,44 @@
+.model jedi_output
+.start_kiss
+.i 6
+.o 9
+.s 14
+.p 21
+.r 1
+1----- 1 3 110000000
+1----- 3 2 000000000
+1----- 2 5 001000000
+1----- 5 7 000000000
+10---- 7 7 000000000
+11---- 7 11 100110000
+1----- 11 12 100100000
+1-1--- 12 8 000001100
+1-0--- 12 8 000000100
+1-0--- 8 3 110000000
+1-10-- 8 3 110000000
+1-11-- 8 4 110000000
+1---1- 4 13 000000010
+1---0- 4 13 000000000
+1----- 13 14 001000010
+1----- 14 6 000000000
+10---- 6 6 000000000
+11---- 6 9 100110000
+1----- 9 10 100100000
+1----1 10 3 110000101
+1----0 10 4 110000100
+.end_kiss
+.code 1 10000000000000
+.code 3 01000000000000
+.code 2 00100000000000
+.code 5 00010000000000
+.code 7 00001000000000
+.code 11 00000100000000
+.code 12 00000010000000
+.code 8 00000001000000
+.code 4 00000000100000
+.code 13 00000000010000
+.code 14 00000000001000
+.code 6 00000000000100
+.code 9 00000000000010
+.code 10 00000000000001
+.end

data/spec/fixtures/ex4_hot.vhd

@@ -0,0 +1,87 @@
+library ieee;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+entity ex4_hot is
+  port(
+    clock:  in  std_logic;
+    input:  in  std_logic_vector(5 downto 0);
+    output: out std_logic_vector(8 downto 0)
+  );
+end ex4_hot;
+architecture behaviour of ex4_hot is
+  constant s1: std_logic_vector(13 downto 0) := "10000000000000";
+  constant s3: std_logic_vector(13 downto 0) := "01000000000000";
+  constant s2: std_logic_vector(13 downto 0) := "00100000000000";
+  constant s5: std_logic_vector(13 downto 0) := "00010000000000";
+  constant s7: std_logic_vector(13 downto 0) := "00001000000000";
+  constant s11: std_logic_vector(13 downto 0) := "00000100000000";
+  constant s12: std_logic_vector(13 downto 0) := "00000010000000";
+  constant s8: std_logic_vector(13 downto 0) := "00000001000000";
+  constant s4: std_logic_vector(13 downto 0) := "00000000100000";
+  constant s13: std_logic_vector(13 downto 0) := "00000000010000";
+  constant s14: std_logic_vector(13 downto 0) := "00000000001000";
+  constant s6: std_logic_vector(13 downto 0) := "00000000000100";
+  constant s9: std_logic_vector(13 downto 0) := "00000000000010";
+  constant s10: std_logic_vector(13 downto 0) := "00000000000001";
+  signal current_state, next_state: std_logic_vector(13 downto 0);
+begin
+  process(clock) begin
+    if rising_edge(clock) then current_state <= next_state;
+    end if;
+  end process;
+  process(input, current_state) begin
+    next_state <= "--------------"; output <= "---------";
+    case current_state is
+      when s1 =>
+        if std_match(input, "1-----") then next_state <= s3; output <= "110000000";
+        end if;
+      when s3 =>
+        if std_match(input, "1-----") then next_state <= s2; output <= "000000000";
+        end if;
+      when s2 =>
+        if std_match(input, "1-----") then next_state <= s5; output <= "001000000";
+        end if;
+      when s5 =>
+        if std_match(input, "1-----") then next_state <= s7; output <= "000000000";
+        end if;
+      when s7 =>
+        if std_match(input, "10----") then next_state <= s7; output <= "000000000";
+        elsif std_match(input, "11----") then next_state <= s11; output <= "100110000";
+        end if;
+      when s11 =>
+        if std_match(input, "1-----") then next_state <= s12; output <= "100100000";
+        end if;
+      when s12 =>
+        if std_match(input, "1-1---") then next_state <= s8; output <= "000001100";
+        elsif std_match(input, "1-0---") then next_state <= s8; output <= "000000100";
+        end if;
+      when s8 =>
+        if std_match(input, "1-0---") then next_state <= s3; output <= "110000000";
+        elsif std_match(input, "1-10--") then next_state <= s3; output <= "110000000";
+        elsif std_match(input, "1-11--") then next_state <= s4; output <= "110000000";
+        end if;
+      when s4 =>
+        if std_match(input, "1---1-") then next_state <= s13; output <= "000000010";
+        elsif std_match(input, "1---0-") then next_state <= s13; output <= "000000000";
+        end if;
+      when s13 =>
+        if std_match(input, "1-----") then next_state <= s14; output <= "001000010";
+        end if;
+      when s14 =>
+        if std_match(input, "1-----") then next_state <= s6; output <= "000000000";
+        end if;
+      when s6 =>
+        if std_match(input, "10----") then next_state <= s6; output <= "000000000";
+        elsif std_match(input, "11----") then next_state <= s9; output <= "100110000";
+        end if;
+      when s9 =>
+        if std_match(input, "1-----") then next_state <= s10; output <= "100100000";
+        end if;
+      when s10 =>
+        if std_match(input, "1----1") then next_state <= s3; output <= "110000101";
+        elsif std_match(input, "1----0") then next_state <= s4; output <= "110000100";
+        end if;
+      when others => next_state <= "--------------"; output <= "---------";
+    end case;
+  end process;
+end behaviour;

data/spec/fixtures/fsm.vhd

@@ -0,0 +1,64 @@
+library ieee;
+use ieee.numeric_std.all;
+use ieee.std_logic_1164.all;
+entity fsm is
+  port(
+    clock:  in  std_logic;
+    input:  in  std_logic_vector(3 downto 0);
+    output: out std_logic_vector(1 downto 0)
+  );
+end fsm;
+architecture behaviour of fsm is
+  type state is (init0, init1, init2, init4, IOwait, RMACK, WMACK, read0, read1, write0);
+  signal current_state, next_state: state;
+begin
+  process(clock) begin
+    if rising_edge(clock) then current_state <= next_state;
+    end if;
+  end process;
+  process(input, current_state) begin
+    next_state <= init0; output <= "--";
+    case current_state is
+      when init0 =>
+        if std_match(input, "--00") then next_state <= init1; output <= "00";
+        end if;
+      when init1 =>
+        if std_match(input, "0100") then next_state <= init1; output <= "00";
+        elsif std_match(input, "--1-") then next_state <= init2; output <= "10";
+        end if;
+      when init2 =>
+        if std_match(input, "1-10") then next_state <= init4; output <= "10";
+        end if;
+      when init4 =>
+        if std_match(input, "-111") then next_state <= init4; output <= "10";
+        elsif std_match(input, "--01") then next_state <= IOwait; output <= "01";
+        end if;
+      when IOwait =>
+        if std_match(input, "000-") then next_state <= IOwait; output <= "01";
+        elsif std_match(input, "100-") then next_state <= init1; output <= "01";
+        elsif std_match(input, "0110") then next_state <= read0; output <= "00";
+        elsif std_match(input, "1100") then next_state <= write0; output <= "11";
+        elsif std_match(input, "0111") then next_state <= RMACK; output <= "11";
+        elsif std_match(input, "1101") then next_state <= WMACK; output <= "00";
+        elsif std_match(input, "-01-") then next_state <= init2; output <= "01";
+        end if;
+      when RMACK =>
+        if std_match(input, "0010") then next_state <= RMACK; output <= "11";
+        elsif std_match(input, "0111") then next_state <= read0; output <= "00";
+        end if;
+      when WMACK =>
+        if std_match(input, "1100") then next_state <= WMACK; output <= "00";
+        elsif std_match(input, "1001") then next_state <= write0; output <= "01";
+        end if;
+      when read0 =>
+        if std_match(input, "0001") then next_state <= read1; output <= "11";
+        end if;
+      when read1 =>
+        if std_match(input, "0010") then next_state <= IOwait; output <= "01";
+        end if;
+      when write0 =>
+        if std_match(input, "0100") then next_state <= IOwait; output <= "01";
+        end if;
+    end case;
+  end process;
+end behaviour;

data/spec/fixtures/kirkman

@@ -0,0 +1,374 @@
+.i 12
+.o 6
+.p 370
+.s 16
+--------1--- * rst0 1-----
+--------0000 rst0 rst0 0----0
+--------0001 rst0 bit1 0---00
+--------0001 bit1 bit2 0---10
+--------0001 bit2 bit3 0---00
+0-------0001 bit3 bit4 1---00
+1-------0001 bit3 bit4 1---10
+0-------0001 bit4 bit5 1---00
+1-------0001 bit4 bit5 1---10
+0-------0001 bit5 bit6 1---00
+1-------0001 bit5 bit6 1---10
+0-------0001 bit6 bit7 1---00
+1-------0001 bit6 bit7 1---10
+0-------0001 bit7 bit8 1---00
+1-------0001 bit7 bit8 1---10
+0-------0001 bit8 bit9 1---00
+1-------0001 bit8 bit9 1---10
+0-------0001 bit9 bitA 1---00
+1-------0001 bit9 bitA 1---10
+0-------0001 bitA bitB 1---00
+1-------0001 bitA bitB 1---10
+--------0001 bitB bitC 0---00
+--------0001 bitC bitD 0---00
+--------0001 bitD bitE 0---00
+--------0001 bitE bitF 0---01
+--------0001 bitF rst0 0---00
+-----0--0111 rst0 bit1 0--010
+-----0--0111 bit1 bit2 0--010
+-----0--0111 bit2 bit3 0--000
+-00--00-0111 bit3 bit4 100000
+-01--00-0111 bit3 bit4 100010
+-10--00-0111 bit3 bit4 100010
+-11--00-0111 bit3 bit4 110000
+-00--01-0111 bit3 bit4 101000
+-01--01-0111 bit3 bit4 100010
+-10--01-0111 bit3 bit4 100010
+-11--01-0111 bit3 bit4 111000
+-000000-0111 bit4 bit5 100000
+-001000-0111 bit4 bit5 100010
+-010000-0111 bit4 bit5 100010
+-011000-0111 bit4 bit5 110000
+-100000-0111 bit4 bit5 100010
+-101000-0111 bit4 bit5 110000
+-110000-0111 bit4 bit5 110000
+-111000-0111 bit4 bit5 110010
+-000100-0111 bit4 bit5 101000
+-001100-0111 bit4 bit5 100010
+-010100-0111 bit4 bit5 100010
+-011100-0111 bit4 bit5 111000
+-100100-0111 bit4 bit5 100010
+-101100-0111 bit4 bit5 111000
+-110100-0111 bit4 bit5 111000
+-111100-0111 bit4 bit5 110010
+-000001-0111 bit4 bit5 101000
+-001001-0111 bit4 bit5 100010
+-010001-0111 bit4 bit5 100010
+-011001-0111 bit4 bit5 111000
+-100001-0111 bit4 bit5 100010
+-101001-0111 bit4 bit5 111000
+-110001-0111 bit4 bit5 111000
+-111001-0111 bit4 bit5 111010
+-000101-0111 bit4 bit5 101000
+-001101-0111 bit4 bit5 101010
+-010101-0111 bit4 bit5 101010
+-011101-0111 bit4 bit5 111000
+-100101-0111 bit4 bit5 101010
+-101101-0111 bit4 bit5 111000
+-110101-0111 bit4 bit5 111000
+-111101-0111 bit4 bit5 111010
+-000000-0111 bit5 bit6 100000
+-001000-0111 bit5 bit6 100010
+-010000-0111 bit5 bit6 100010
+-011000-0111 bit5 bit6 110000
+-100000-0111 bit5 bit6 100010
+-101000-0111 bit5 bit6 110000
+-110000-0111 bit5 bit6 110000
+-111000-0111 bit5 bit6 110010
+-000100-0111 bit5 bit6 101000
+-001100-0111 bit5 bit6 100010
+-010100-0111 bit5 bit6 100010
+-011100-0111 bit5 bit6 111000
+-100100-0111 bit5 bit6 100010
+-101100-0111 bit5 bit6 111000
+-110100-0111 bit5 bit6 111000
+-111100-0111 bit5 bit6 110010
+-000001-0111 bit5 bit6 101000
+-001001-0111 bit5 bit6 100010
+-010001-0111 bit5 bit6 100010
+-011001-0111 bit5 bit6 111000
+-100001-0111 bit5 bit6 100010
+-101001-0111 bit5 bit6 111000
+-110001-0111 bit5 bit6 111000
+-111001-0111 bit5 bit6 111010
+-000101-0111 bit5 bit6 101000
+-001101-0111 bit5 bit6 101010
+-010101-0111 bit5 bit6 101010
+-011101-0111 bit5 bit6 111000
+-100101-0111 bit5 bit6 101010
+-101101-0111 bit5 bit6 111000
+-110101-0111 bit5 bit6 111000
+-111101-0111 bit5 bit6 111010
+-000000-0111 bit6 bit7 100000
+-001000-0111 bit6 bit7 100010
+-010000-0111 bit6 bit7 100010
+-011000-0111 bit6 bit7 110000
+-100000-0111 bit6 bit7 100010
+-101000-0111 bit6 bit7 110000
+-110000-0111 bit6 bit7 110000
+-111000-0111 bit6 bit7 110010
+-000100-0111 bit6 bit7 101000
+-001100-0111 bit6 bit7 100010
+-010100-0111 bit6 bit7 100010
+-011100-0111 bit6 bit7 111000
+-100100-0111 bit6 bit7 100010
+-101100-0111 bit6 bit7 111000
+-110100-0111 bit6 bit7 111000
+-111100-0111 bit6 bit7 110010
+-000001-0111 bit6 bit7 101000
+-001001-0111 bit6 bit7 100010
+-010001-0111 bit6 bit7 100010
+-011001-0111 bit6 bit7 111000
+-100001-0111 bit6 bit7 100010
+-101001-0111 bit6 bit7 111000
+-110001-0111 bit6 bit7 111000
+-111001-0111 bit6 bit7 111010
+-000101-0111 bit6 bit7 101000
+-001101-0111 bit6 bit7 101010
+-010101-0111 bit6 bit7 101010
+-011101-0111 bit6 bit7 111000
+-100101-0111 bit6 bit7 101010
+-101101-0111 bit6 bit7 111000
+-110101-0111 bit6 bit7 111000
+-111101-0111 bit6 bit7 111010
+-000000-0111 bit7 bit8 100000
+-001000-0111 bit7 bit8 100010
+-010000-0111 bit7 bit8 100010
+-011000-0111 bit7 bit8 110000
+-100000-0111 bit7 bit8 100010
+-101000-0111 bit7 bit8 110000
+-110000-0111 bit7 bit8 110000
+-111000-0111 bit7 bit8 110010
+-000100-0111 bit7 bit8 101000
+-001100-0111 bit7 bit8 100010
+-010100-0111 bit7 bit8 100010
+-011100-0111 bit7 bit8 111000
+-100100-0111 bit7 bit8 100010
+-101100-0111 bit7 bit8 111000
+-110100-0111 bit7 bit8 111000
+-111100-0111 bit7 bit8 110010
+-000001-0111 bit7 bit8 101000
+-001001-0111 bit7 bit8 100010
+-010001-0111 bit7 bit8 100010
+-011001-0111 bit7 bit8 111000
+-100001-0111 bit7 bit8 100010
+-101001-0111 bit7 bit8 111000
+-110001-0111 bit7 bit8 111000
+-111001-0111 bit7 bit8 111010
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