art-decomp 0.3.0 → 0.4.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- data/Rakefile +1 -1
- data/VERSION +1 -1
- data/bin/ad-kiss2vhdl +8 -0
- data/lib/art-decomp.rb +2 -0
- data/lib/art-decomp/bipainter.rb +36 -36
- data/lib/art-decomp/executable.rb +3 -3
- data/lib/art-decomp/fsm.rb +28 -3
- data/lib/art-decomp/graph.rb +19 -19
- data/lib/art-decomp/logging.rb +51 -34
- data/lib/art-decomp/uv_generator/braindead.rb +1 -2
- data/lib/art-decomp/vhdl.rb +72 -0
- data/spec/art-decomp/executable_spec.rb +2 -2
- data/spec/art-decomp/fsm_spec.rb +41 -0
- data/spec/art-decomp/logging_spec.rb +10 -24
- data/spec/art-decomp/vhdl_spec.rb +22 -0
- data/spec/fixtures/ex4.hot +44 -0
- data/spec/fixtures/ex4_hot.vhd +87 -0
- data/spec/fixtures/fsm.vhd +64 -0
- data/spec/fixtures/kirkman +374 -0
- data/spec/fixtures/mark1.hot +46 -0
- data/spec/fixtures/mark1.jed +48 -0
- data/spec/fixtures/mark1.nov +340 -0
- data/spec/fixtures/mark1.vhd +79 -0
- data/spec/fixtures/mark1.yml +86 -0
- data/spec/fixtures/mark1_hot.vhd +94 -0
- data/spec/fixtures/mark1_jed.vhd +94 -0
- data/spec/fixtures/mark1_nov.vhd +94 -0
- metadata +66 -30
@@ -145,14 +145,14 @@ module ArtDecomp describe Executable do
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Executable.new(['--archs', '5/1', '4/2', '--debug', '--log', log.path, '--outdir', @dir, @fsm]).run
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Logging.level.should == Logger::DEBUG
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Logging.off
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-
File.read(log.path).should =~ rex('
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File.read(log.path).should =~ rex('4/2+10s')
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end
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it 'should handle the s8 edge case with grace' do
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log = Tempfile.new rand
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Executable.new(['--archs', '2/1', '--log', log.path, '--outdir', @dir, 'spec/fixtures/s8']).run
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Logging.off
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File.read(log.path).should =~ rex('
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File.read(log.path).should =~ rex(' 0c')
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end
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# FIXME: add specs for --binary, --non-disjoint and --deep-ndj
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data/spec/art-decomp/fsm_spec.rb
CHANGED
@@ -23,6 +23,10 @@ module ArtDecomp describe FSM do
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lambda { FSM.from_kiss 'spec/fixtures/ex5' }.should_not raise_error
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end
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it 'should ignore KISS lines with don’t-care next states and outputs' do
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FSM.from_kiss('spec/fixtures/kirkman').beta_q.ints.map(&:bits).flatten.max.should == 366
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end
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it 'should handle truth table files by faking a don’t-care state column' do
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@tt.input_count.should == 4
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@tt.output_count.should == 2
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@@ -178,6 +182,43 @@ module ArtDecomp describe FSM do
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@fsm.should_not be_truth_table
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end
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it 'should properly generate its structure' do
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@mark1.structure.to_yaml.should == File.read('spec/fixtures/mark1.yml')
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end
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it 'should properly generate its VHDL representation' do
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@fsm.to_vhdl('fsm').should == File.read('spec/fixtures/fsm.vhd')
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@mark1.to_vhdl('mark1').should == File.read('spec/fixtures/mark1.vhd')
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end
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end
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context 'parsed from an encoded KISS file' do
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before do
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@one_hot = FSM.from_kiss 'spec/fixtures/mark1.hot'
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@nova = FSM.from_kiss 'spec/fixtures/mark1.nov'
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@jedi = FSM.from_kiss 'spec/fixtures/mark1.jed'
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end
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it 'should properly create the FSM' do
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@one_hot.should == FSM.from_kiss('spec/fixtures/mark1')
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@nova.should == FSM.from_kiss('spec/fixtures/mark1')
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@jedi.should == FSM.from_kiss('spec/fixtures/mark1')
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end
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it 'should properly find codes in an one-hot file' do
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@one_hot.codes.should == {:state1 => :'100000000000000', :state3 => :'010000000000000', :state2 => :'001000000000000', :state0 => :'000100000000000', :state4 => :'000010000000000', :state13 => :'000001000000000', :state10 => :'000000100000000', :state9 => :'000000010000000', :state8 => :'000000001000000', :state7 => :'000000000100000', :state6 => :'000000000010000', :state5 => :'000000000001000', :state14 => :'000000000000100', :state11 => :'000000000000010', :state12 => :'000000000000001'}
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@nova.codes.should == {:state1 => :'0100', :state2 => :'1000', :state3 => :'1011', :state4 => :'1100', :state5 => :'0001', :state6 => :'0011', :state7 => :'0000', :state8 => :'0010', :state9 => :'1101', :state10 => :'1010', :state11 => :'0111', :state12 => :'1001', :state13 => :'0101', :state14 => :'0110', :state0 => :'1110'}
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@jedi.codes.should == {:state1 => :'0001', :state3 => :'1111', :state2 => :'0011', :state0 => :'1101', :state4 => :'1001', :state13 => :'1010', :state10 => :'1000', :state9 => :'1100', :state8 => :'0010', :state7 => :'0000', :state6 => :'0110', :state5 => :'0100', :state14 => :'1110', :state11 => :'0111', :state12 => :'1011'}
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end
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it 'should properly generate the (encoded) VHDL' do
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@one_hot.to_vhdl('mark1_hot').should == File.read('spec/fixtures/mark1_hot.vhd')
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@nova.to_vhdl('mark1_nov').should == File.read('spec/fixtures/mark1_nov.vhd')
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@jedi.to_vhdl('mark1_jed').should == File.read('spec/fixtures/mark1_jed.vhd')
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end
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end
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end end
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@@ -9,6 +9,7 @@ module ArtDecomp describe Logging do
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@fsm = mock FSM, :beta_f => Blanket[], :beta_q => Blanket[], :beta_x => Blanket[]
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@log = StringIO.new
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Logging.log = @log
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Logging.level = Logger::INFO
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end
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after do
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@@ -24,7 +25,7 @@ module ArtDecomp describe Logging do
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it 'should log Executable’s decompositions calls on simple cases' do
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args = ['-a', '5/1', '4/2', '-o', @dir, 'spec/fixtures/lion']
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Executable.new(args).run
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log.should =~ rex('
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log.should =~ rex('took 1s')
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end
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it 'should log Executable’s decompositions calls on typical cases' do
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@@ -33,41 +34,26 @@ module ArtDecomp describe Logging do
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ex = Executable.new(args)
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ex.stub!(:best).and_return 69
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ex.run
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log.should =~ rex('
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log.should =~ rex('
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log.should =~ rex('4/2+10s with UniqueRelevance, EdgeLabels, GraphColouring')
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log.should =~ rex('took 1s')
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end
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it 'should log Executable’s decompositions calls on problematic cases' do
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Decomposer.should_receive(:new).and_return mock(Decomposer, :decompositions => [].each)
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args = ['-a', '5/1', '4/2', '-o', @dir, 'spec/fixtures/fsm']
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Executable.new(args).run
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log.should =~ rex('
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log.should =~ rex('
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log.should =~ rex('4/2+10s with UniqueRelevance, EdgeLabels, GraphColouring')
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log.should =~ rex('took 1s')
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end
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it 'should log
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uv.uv_pairs mock(FSM, :input_count => 2), Set[Arch[5,1]]
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log.should =~ rex('UV with Braindead')
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end
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-
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it 'should log QuGenerators’ blankets calls' do
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it 'should log QuGenerators’ blankets calls (if debug-level logging enabled)' do
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Logging.level = Logger::DEBUG
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qu = QuGenerator::BlockTable.new
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[[Set[0], Set[1]], [Set[1], Set[0]]].each do |u, v|
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qu.blankets @fsm, u, v
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end
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log.should =~ rex('
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log.should =~ rex('
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end
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it 'should log QvGenerators’ blankets calls (on the DEBUG level)' do
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Logging.level = Logger::DEBUG
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qv = QvGenerator::GraphColouring.new
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[mock(Blanket, :size => 8), mock(Blanket, :size => 4)].each do |qu|
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qv.blankets @fsm, Set[0], Set[1], qu
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end
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log.should =~ rex('|Qu| = 8, Qv+G with GraphColouring')
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log.should =~ rex('|Qu| = 4, Qv+G with GraphColouring')
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log.should =~ rex('0 1 via with BlockTable')
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log.should =~ rex('1 0 via with BlockTable')
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end
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end end
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@@ -0,0 +1,22 @@
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# encoding: UTF-8
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module ArtDecomp describe VHDL do
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context 'generated from an FSM' do
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it 'should properly generates the VHDL representation' do
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VHDL.new(FSM.from_kiss 'spec/fixtures/fsm').vhdl('fsm').should == File.read('spec/fixtures/fsm.vhd')
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VHDL.new(FSM.from_kiss 'spec/fixtures/mark1').vhdl('mark1').should == File.read('spec/fixtures/mark1.vhd')
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end
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it 'should generate encoded VHDL if the FSM is encoded' do
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VHDL.new(FSM.from_kiss 'spec/fixtures/mark1.hot').vhdl('mark1_hot').should == File.read('spec/fixtures/mark1_hot.vhd')
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end
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it 'should rename digit-only states' do
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VHDL.new(FSM.from_kiss 'spec/fixtures/ex4.hot').vhdl('ex4_hot').should == File.read('spec/fixtures/ex4_hot.vhd')
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end
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end
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end end
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@@ -0,0 +1,44 @@
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.model jedi_output
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.start_kiss
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.i 6
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.o 9
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.s 14
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.p 21
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.r 1
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1----- 1 3 110000000
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1----- 3 2 000000000
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1----- 2 5 001000000
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1----- 5 7 000000000
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10---- 7 7 000000000
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11---- 7 11 100110000
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1----- 11 12 100100000
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1-1--- 12 8 000001100
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1-0--- 12 8 000000100
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1-0--- 8 3 110000000
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1-10-- 8 3 110000000
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1-11-- 8 4 110000000
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1---1- 4 13 000000010
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1---0- 4 13 000000000
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1----- 13 14 001000010
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1----- 14 6 000000000
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10---- 6 6 000000000
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11---- 6 9 100110000
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1----- 9 10 100100000
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1----1 10 3 110000101
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1----0 10 4 110000100
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.end_kiss
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.code 1 10000000000000
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.code 3 01000000000000
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.code 2 00100000000000
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.code 5 00010000000000
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.code 7 00001000000000
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.code 11 00000100000000
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.code 12 00000010000000
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.code 8 00000001000000
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.code 4 00000000100000
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.code 13 00000000010000
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.code 14 00000000001000
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.code 6 00000000000100
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.code 9 00000000000010
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.code 10 00000000000001
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.end
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@@ -0,0 +1,87 @@
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library ieee;
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use ieee.numeric_std.all;
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use ieee.std_logic_1164.all;
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entity ex4_hot is
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port(
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clock: in std_logic;
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input: in std_logic_vector(5 downto 0);
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output: out std_logic_vector(8 downto 0)
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);
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end ex4_hot;
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architecture behaviour of ex4_hot is
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constant s1: std_logic_vector(13 downto 0) := "10000000000000";
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constant s3: std_logic_vector(13 downto 0) := "01000000000000";
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constant s2: std_logic_vector(13 downto 0) := "00100000000000";
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constant s5: std_logic_vector(13 downto 0) := "00010000000000";
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constant s7: std_logic_vector(13 downto 0) := "00001000000000";
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constant s11: std_logic_vector(13 downto 0) := "00000100000000";
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constant s12: std_logic_vector(13 downto 0) := "00000010000000";
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constant s8: std_logic_vector(13 downto 0) := "00000001000000";
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constant s4: std_logic_vector(13 downto 0) := "00000000100000";
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constant s13: std_logic_vector(13 downto 0) := "00000000010000";
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constant s14: std_logic_vector(13 downto 0) := "00000000001000";
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constant s6: std_logic_vector(13 downto 0) := "00000000000100";
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constant s9: std_logic_vector(13 downto 0) := "00000000000010";
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constant s10: std_logic_vector(13 downto 0) := "00000000000001";
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signal current_state, next_state: std_logic_vector(13 downto 0);
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begin
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process(clock) begin
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if rising_edge(clock) then current_state <= next_state;
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end if;
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end process;
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process(input, current_state) begin
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next_state <= "--------------"; output <= "---------";
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case current_state is
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when s1 =>
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if std_match(input, "1-----") then next_state <= s3; output <= "110000000";
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end if;
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when s3 =>
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if std_match(input, "1-----") then next_state <= s2; output <= "000000000";
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end if;
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when s2 =>
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if std_match(input, "1-----") then next_state <= s5; output <= "001000000";
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end if;
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when s5 =>
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if std_match(input, "1-----") then next_state <= s7; output <= "000000000";
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end if;
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when s7 =>
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if std_match(input, "10----") then next_state <= s7; output <= "000000000";
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elsif std_match(input, "11----") then next_state <= s11; output <= "100110000";
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end if;
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when s11 =>
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if std_match(input, "1-----") then next_state <= s12; output <= "100100000";
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end if;
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when s12 =>
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if std_match(input, "1-1---") then next_state <= s8; output <= "000001100";
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elsif std_match(input, "1-0---") then next_state <= s8; output <= "000000100";
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end if;
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when s8 =>
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if std_match(input, "1-0---") then next_state <= s3; output <= "110000000";
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elsif std_match(input, "1-10--") then next_state <= s3; output <= "110000000";
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elsif std_match(input, "1-11--") then next_state <= s4; output <= "110000000";
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end if;
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when s4 =>
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if std_match(input, "1---1-") then next_state <= s13; output <= "000000010";
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elsif std_match(input, "1---0-") then next_state <= s13; output <= "000000000";
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end if;
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when s13 =>
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if std_match(input, "1-----") then next_state <= s14; output <= "001000010";
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end if;
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when s14 =>
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if std_match(input, "1-----") then next_state <= s6; output <= "000000000";
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end if;
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when s6 =>
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if std_match(input, "10----") then next_state <= s6; output <= "000000000";
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elsif std_match(input, "11----") then next_state <= s9; output <= "100110000";
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end if;
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when s9 =>
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if std_match(input, "1-----") then next_state <= s10; output <= "100100000";
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end if;
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when s10 =>
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if std_match(input, "1----1") then next_state <= s3; output <= "110000101";
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elsif std_match(input, "1----0") then next_state <= s4; output <= "110000100";
|
83
|
+
end if;
|
84
|
+
when others => next_state <= "--------------"; output <= "---------";
|
85
|
+
end case;
|
86
|
+
end process;
|
87
|
+
end behaviour;
|
@@ -0,0 +1,64 @@
|
|
1
|
+
library ieee;
|
2
|
+
use ieee.numeric_std.all;
|
3
|
+
use ieee.std_logic_1164.all;
|
4
|
+
entity fsm is
|
5
|
+
port(
|
6
|
+
clock: in std_logic;
|
7
|
+
input: in std_logic_vector(3 downto 0);
|
8
|
+
output: out std_logic_vector(1 downto 0)
|
9
|
+
);
|
10
|
+
end fsm;
|
11
|
+
architecture behaviour of fsm is
|
12
|
+
type state is (init0, init1, init2, init4, IOwait, RMACK, WMACK, read0, read1, write0);
|
13
|
+
signal current_state, next_state: state;
|
14
|
+
begin
|
15
|
+
process(clock) begin
|
16
|
+
if rising_edge(clock) then current_state <= next_state;
|
17
|
+
end if;
|
18
|
+
end process;
|
19
|
+
process(input, current_state) begin
|
20
|
+
next_state <= init0; output <= "--";
|
21
|
+
case current_state is
|
22
|
+
when init0 =>
|
23
|
+
if std_match(input, "--00") then next_state <= init1; output <= "00";
|
24
|
+
end if;
|
25
|
+
when init1 =>
|
26
|
+
if std_match(input, "0100") then next_state <= init1; output <= "00";
|
27
|
+
elsif std_match(input, "--1-") then next_state <= init2; output <= "10";
|
28
|
+
end if;
|
29
|
+
when init2 =>
|
30
|
+
if std_match(input, "1-10") then next_state <= init4; output <= "10";
|
31
|
+
end if;
|
32
|
+
when init4 =>
|
33
|
+
if std_match(input, "-111") then next_state <= init4; output <= "10";
|
34
|
+
elsif std_match(input, "--01") then next_state <= IOwait; output <= "01";
|
35
|
+
end if;
|
36
|
+
when IOwait =>
|
37
|
+
if std_match(input, "000-") then next_state <= IOwait; output <= "01";
|
38
|
+
elsif std_match(input, "100-") then next_state <= init1; output <= "01";
|
39
|
+
elsif std_match(input, "0110") then next_state <= read0; output <= "00";
|
40
|
+
elsif std_match(input, "1100") then next_state <= write0; output <= "11";
|
41
|
+
elsif std_match(input, "0111") then next_state <= RMACK; output <= "11";
|
42
|
+
elsif std_match(input, "1101") then next_state <= WMACK; output <= "00";
|
43
|
+
elsif std_match(input, "-01-") then next_state <= init2; output <= "01";
|
44
|
+
end if;
|
45
|
+
when RMACK =>
|
46
|
+
if std_match(input, "0010") then next_state <= RMACK; output <= "11";
|
47
|
+
elsif std_match(input, "0111") then next_state <= read0; output <= "00";
|
48
|
+
end if;
|
49
|
+
when WMACK =>
|
50
|
+
if std_match(input, "1100") then next_state <= WMACK; output <= "00";
|
51
|
+
elsif std_match(input, "1001") then next_state <= write0; output <= "01";
|
52
|
+
end if;
|
53
|
+
when read0 =>
|
54
|
+
if std_match(input, "0001") then next_state <= read1; output <= "11";
|
55
|
+
end if;
|
56
|
+
when read1 =>
|
57
|
+
if std_match(input, "0010") then next_state <= IOwait; output <= "01";
|
58
|
+
end if;
|
59
|
+
when write0 =>
|
60
|
+
if std_match(input, "0100") then next_state <= IOwait; output <= "01";
|
61
|
+
end if;
|
62
|
+
end case;
|
63
|
+
end process;
|
64
|
+
end behaviour;
|
@@ -0,0 +1,374 @@
|
|
1
|
+
.i 12
|
2
|
+
.o 6
|
3
|
+
.p 370
|
4
|
+
.s 16
|
5
|
+
--------1--- * rst0 1-----
|
6
|
+
--------0000 rst0 rst0 0----0
|
7
|
+
--------0001 rst0 bit1 0---00
|
8
|
+
--------0001 bit1 bit2 0---10
|
9
|
+
--------0001 bit2 bit3 0---00
|
10
|
+
0-------0001 bit3 bit4 1---00
|
11
|
+
1-------0001 bit3 bit4 1---10
|
12
|
+
0-------0001 bit4 bit5 1---00
|
13
|
+
1-------0001 bit4 bit5 1---10
|
14
|
+
0-------0001 bit5 bit6 1---00
|
15
|
+
1-------0001 bit5 bit6 1---10
|
16
|
+
0-------0001 bit6 bit7 1---00
|
17
|
+
1-------0001 bit6 bit7 1---10
|
18
|
+
0-------0001 bit7 bit8 1---00
|
19
|
+
1-------0001 bit7 bit8 1---10
|
20
|
+
0-------0001 bit8 bit9 1---00
|
21
|
+
1-------0001 bit8 bit9 1---10
|
22
|
+
0-------0001 bit9 bitA 1---00
|
23
|
+
1-------0001 bit9 bitA 1---10
|
24
|
+
0-------0001 bitA bitB 1---00
|
25
|
+
1-------0001 bitA bitB 1---10
|
26
|
+
--------0001 bitB bitC 0---00
|
27
|
+
--------0001 bitC bitD 0---00
|
28
|
+
--------0001 bitD bitE 0---00
|
29
|
+
--------0001 bitE bitF 0---01
|
30
|
+
--------0001 bitF rst0 0---00
|
31
|
+
-----0--0111 rst0 bit1 0--010
|
32
|
+
-----0--0111 bit1 bit2 0--010
|
33
|
+
-----0--0111 bit2 bit3 0--000
|
34
|
+
-00--00-0111 bit3 bit4 100000
|
35
|
+
-01--00-0111 bit3 bit4 100010
|
36
|
+
-10--00-0111 bit3 bit4 100010
|
37
|
+
-11--00-0111 bit3 bit4 110000
|
38
|
+
-00--01-0111 bit3 bit4 101000
|
39
|
+
-01--01-0111 bit3 bit4 100010
|
40
|
+
-10--01-0111 bit3 bit4 100010
|
41
|
+
-11--01-0111 bit3 bit4 111000
|
42
|
+
-000000-0111 bit4 bit5 100000
|
43
|
+
-001000-0111 bit4 bit5 100010
|
44
|
+
-010000-0111 bit4 bit5 100010
|
45
|
+
-011000-0111 bit4 bit5 110000
|
46
|
+
-100000-0111 bit4 bit5 100010
|
47
|
+
-101000-0111 bit4 bit5 110000
|
48
|
+
-110000-0111 bit4 bit5 110000
|
49
|
+
-111000-0111 bit4 bit5 110010
|
50
|
+
-000100-0111 bit4 bit5 101000
|
51
|
+
-001100-0111 bit4 bit5 100010
|
52
|
+
-010100-0111 bit4 bit5 100010
|
53
|
+
-011100-0111 bit4 bit5 111000
|
54
|
+
-100100-0111 bit4 bit5 100010
|
55
|
+
-101100-0111 bit4 bit5 111000
|
56
|
+
-110100-0111 bit4 bit5 111000
|
57
|
+
-111100-0111 bit4 bit5 110010
|
58
|
+
-000001-0111 bit4 bit5 101000
|
59
|
+
-001001-0111 bit4 bit5 100010
|
60
|
+
-010001-0111 bit4 bit5 100010
|
61
|
+
-011001-0111 bit4 bit5 111000
|
62
|
+
-100001-0111 bit4 bit5 100010
|
63
|
+
-101001-0111 bit4 bit5 111000
|
64
|
+
-110001-0111 bit4 bit5 111000
|
65
|
+
-111001-0111 bit4 bit5 111010
|
66
|
+
-000101-0111 bit4 bit5 101000
|
67
|
+
-001101-0111 bit4 bit5 101010
|
68
|
+
-010101-0111 bit4 bit5 101010
|
69
|
+
-011101-0111 bit4 bit5 111000
|
70
|
+
-100101-0111 bit4 bit5 101010
|
71
|
+
-101101-0111 bit4 bit5 111000
|
72
|
+
-110101-0111 bit4 bit5 111000
|
73
|
+
-111101-0111 bit4 bit5 111010
|
74
|
+
-000000-0111 bit5 bit6 100000
|
75
|
+
-001000-0111 bit5 bit6 100010
|
76
|
+
-010000-0111 bit5 bit6 100010
|
77
|
+
-011000-0111 bit5 bit6 110000
|
78
|
+
-100000-0111 bit5 bit6 100010
|
79
|
+
-101000-0111 bit5 bit6 110000
|
80
|
+
-110000-0111 bit5 bit6 110000
|
81
|
+
-111000-0111 bit5 bit6 110010
|
82
|
+
-000100-0111 bit5 bit6 101000
|
83
|
+
-001100-0111 bit5 bit6 100010
|
84
|
+
-010100-0111 bit5 bit6 100010
|
85
|
+
-011100-0111 bit5 bit6 111000
|
86
|
+
-100100-0111 bit5 bit6 100010
|
87
|
+
-101100-0111 bit5 bit6 111000
|
88
|
+
-110100-0111 bit5 bit6 111000
|
89
|
+
-111100-0111 bit5 bit6 110010
|
90
|
+
-000001-0111 bit5 bit6 101000
|
91
|
+
-001001-0111 bit5 bit6 100010
|
92
|
+
-010001-0111 bit5 bit6 100010
|
93
|
+
-011001-0111 bit5 bit6 111000
|
94
|
+
-100001-0111 bit5 bit6 100010
|
95
|
+
-101001-0111 bit5 bit6 111000
|
96
|
+
-110001-0111 bit5 bit6 111000
|
97
|
+
-111001-0111 bit5 bit6 111010
|
98
|
+
-000101-0111 bit5 bit6 101000
|
99
|
+
-001101-0111 bit5 bit6 101010
|
100
|
+
-010101-0111 bit5 bit6 101010
|
101
|
+
-011101-0111 bit5 bit6 111000
|
102
|
+
-100101-0111 bit5 bit6 101010
|
103
|
+
-101101-0111 bit5 bit6 111000
|
104
|
+
-110101-0111 bit5 bit6 111000
|
105
|
+
-111101-0111 bit5 bit6 111010
|
106
|
+
-000000-0111 bit6 bit7 100000
|
107
|
+
-001000-0111 bit6 bit7 100010
|
108
|
+
-010000-0111 bit6 bit7 100010
|
109
|
+
-011000-0111 bit6 bit7 110000
|
110
|
+
-100000-0111 bit6 bit7 100010
|
111
|
+
-101000-0111 bit6 bit7 110000
|
112
|
+
-110000-0111 bit6 bit7 110000
|
113
|
+
-111000-0111 bit6 bit7 110010
|
114
|
+
-000100-0111 bit6 bit7 101000
|
115
|
+
-001100-0111 bit6 bit7 100010
|
116
|
+
-010100-0111 bit6 bit7 100010
|
117
|
+
-011100-0111 bit6 bit7 111000
|
118
|
+
-100100-0111 bit6 bit7 100010
|
119
|
+
-101100-0111 bit6 bit7 111000
|
120
|
+
-110100-0111 bit6 bit7 111000
|
121
|
+
-111100-0111 bit6 bit7 110010
|
122
|
+
-000001-0111 bit6 bit7 101000
|
123
|
+
-001001-0111 bit6 bit7 100010
|
124
|
+
-010001-0111 bit6 bit7 100010
|
125
|
+
-011001-0111 bit6 bit7 111000
|
126
|
+
-100001-0111 bit6 bit7 100010
|
127
|
+
-101001-0111 bit6 bit7 111000
|
128
|
+
-110001-0111 bit6 bit7 111000
|
129
|
+
-111001-0111 bit6 bit7 111010
|
130
|
+
-000101-0111 bit6 bit7 101000
|
131
|
+
-001101-0111 bit6 bit7 101010
|
132
|
+
-010101-0111 bit6 bit7 101010
|
133
|
+
-011101-0111 bit6 bit7 111000
|
134
|
+
-100101-0111 bit6 bit7 101010
|
135
|
+
-101101-0111 bit6 bit7 111000
|
136
|
+
-110101-0111 bit6 bit7 111000
|
137
|
+
-111101-0111 bit6 bit7 111010
|
138
|
+
-000000-0111 bit7 bit8 100000
|
139
|
+
-001000-0111 bit7 bit8 100010
|
140
|
+
-010000-0111 bit7 bit8 100010
|
141
|
+
-011000-0111 bit7 bit8 110000
|
142
|
+
-100000-0111 bit7 bit8 100010
|
143
|
+
-101000-0111 bit7 bit8 110000
|
144
|
+
-110000-0111 bit7 bit8 110000
|
145
|
+
-111000-0111 bit7 bit8 110010
|
146
|
+
-000100-0111 bit7 bit8 101000
|
147
|
+
-001100-0111 bit7 bit8 100010
|
148
|
+
-010100-0111 bit7 bit8 100010
|
149
|
+
-011100-0111 bit7 bit8 111000
|
150
|
+
-100100-0111 bit7 bit8 100010
|
151
|
+
-101100-0111 bit7 bit8 111000
|
152
|
+
-110100-0111 bit7 bit8 111000
|
153
|
+
-111100-0111 bit7 bit8 110010
|
154
|
+
-000001-0111 bit7 bit8 101000
|
155
|
+
-001001-0111 bit7 bit8 100010
|
156
|
+
-010001-0111 bit7 bit8 100010
|
157
|
+
-011001-0111 bit7 bit8 111000
|
158
|
+
-100001-0111 bit7 bit8 100010
|
159
|
+
-101001-0111 bit7 bit8 111000
|
160
|
+
-110001-0111 bit7 bit8 111000
|
161
|
+
-111001-0111 bit7 bit8 111010
|
162
|
+
-000101-0111 bit7 bit8 101000
|
163
|
+
-001101-0111 bit7 bit8 101010
|
164
|
+
-010101-0111 bit7 bit8 101010
|
165
|
+
-011101-0111 bit7 bit8 111000
|
166
|
+
-100101-0111 bit7 bit8 101010
|
167
|
+
-101101-0111 bit7 bit8 111000
|
168
|
+
-110101-0111 bit7 bit8 111000
|
169
|
+
-111101-0111 bit7 bit8 111010
|
170
|
+
-000000-0111 bit8 bit9 100000
|
171
|
+
-001000-0111 bit8 bit9 100010
|
172
|
+
-010000-0111 bit8 bit9 100010
|
173
|
+
-011000-0111 bit8 bit9 110000
|
174
|
+
-100000-0111 bit8 bit9 100010
|
175
|
+
-101000-0111 bit8 bit9 110000
|
176
|
+
-110000-0111 bit8 bit9 110000
|
177
|
+
-111000-0111 bit8 bit9 110010
|
178
|
+
-000100-0111 bit8 bit9 101000
|
179
|
+
-001100-0111 bit8 bit9 100010
|
180
|
+
-010100-0111 bit8 bit9 100010
|
181
|
+
-011100-0111 bit8 bit9 111000
|
182
|
+
-100100-0111 bit8 bit9 100010
|
183
|
+
-101100-0111 bit8 bit9 111000
|
184
|
+
-110100-0111 bit8 bit9 111000
|
185
|
+
-111100-0111 bit8 bit9 110010
|
186
|
+
-000001-0111 bit8 bit9 101000
|
187
|
+
-001001-0111 bit8 bit9 100010
|
188
|
+
-010001-0111 bit8 bit9 100010
|
189
|
+
-011001-0111 bit8 bit9 111000
|
190
|
+
-100001-0111 bit8 bit9 100010
|
191
|
+
-101001-0111 bit8 bit9 111000
|
192
|
+
-110001-0111 bit8 bit9 111000
|
193
|
+
-111001-0111 bit8 bit9 111010
|
194
|
+
-000101-0111 bit8 bit9 101000
|
195
|
+
-001101-0111 bit8 bit9 101010
|
196
|
+
-010101-0111 bit8 bit9 101010
|
197
|
+
-011101-0111 bit8 bit9 111000
|
198
|
+
-100101-0111 bit8 bit9 101010
|
199
|
+
-101101-0111 bit8 bit9 111000
|
200
|
+
-110101-0111 bit8 bit9 111000
|
201
|
+
-111101-0111 bit8 bit9 111010
|
202
|
+
-000000-0111 bit9 bitA 100000
|
203
|
+
-001000-0111 bit9 bitA 100010
|
204
|
+
-010000-0111 bit9 bitA 100010
|
205
|
+
-011000-0111 bit9 bitA 110000
|
206
|
+
-100000-0111 bit9 bitA 100010
|
207
|
+
-101000-0111 bit9 bitA 110000
|
208
|
+
-110000-0111 bit9 bitA 110000
|
209
|
+
-111000-0111 bit9 bitA 110010
|
210
|
+
-000100-0111 bit9 bitA 101000
|
211
|
+
-001100-0111 bit9 bitA 100010
|
212
|
+
-010100-0111 bit9 bitA 100010
|
213
|
+
-011100-0111 bit9 bitA 111000
|
214
|
+
-100100-0111 bit9 bitA 100010
|
215
|
+
-101100-0111 bit9 bitA 111000
|
216
|
+
-110100-0111 bit9 bitA 111000
|
217
|
+
-111100-0111 bit9 bitA 110010
|
218
|
+
-000001-0111 bit9 bitA 101000
|
219
|
+
-001001-0111 bit9 bitA 100010
|
220
|
+
-010001-0111 bit9 bitA 100010
|
221
|
+
-011001-0111 bit9 bitA 111000
|
222
|
+
-100001-0111 bit9 bitA 100010
|
223
|
+
-101001-0111 bit9 bitA 111000
|
224
|
+
-110001-0111 bit9 bitA 111000
|
225
|
+
-111001-0111 bit9 bitA 111010
|
226
|
+
-000101-0111 bit9 bitA 101000
|
227
|
+
-001101-0111 bit9 bitA 101010
|
228
|
+
-010101-0111 bit9 bitA 101010
|
229
|
+
-011101-0111 bit9 bitA 111000
|
230
|
+
-100101-0111 bit9 bitA 101010
|
231
|
+
-101101-0111 bit9 bitA 111000
|
232
|
+
-110101-0111 bit9 bitA 111000
|
233
|
+
-111101-0111 bit9 bitA 111010
|
234
|
+
-000000-0111 bitA bitB 100000
|
235
|
+
-001000-0111 bitA bitB 100010
|
236
|
+
-010000-0111 bitA bitB 100010
|
237
|
+
-011000-0111 bitA bitB 110000
|
238
|
+
-100000-0111 bitA bitB 100010
|
239
|
+
-101000-0111 bitA bitB 110000
|
240
|
+
-110000-0111 bitA bitB 110000
|
241
|
+
-111000-0111 bitA bitB 110010
|
242
|
+
-000100-0111 bitA bitB 101000
|
243
|
+
-001100-0111 bitA bitB 100010
|
244
|
+
-010100-0111 bitA bitB 100010
|
245
|
+
-011100-0111 bitA bitB 111000
|
246
|
+
-100100-0111 bitA bitB 100010
|
247
|
+
-101100-0111 bitA bitB 111000
|
248
|
+
-110100-0111 bitA bitB 111000
|
249
|
+
-111100-0111 bitA bitB 110010
|
250
|
+
-000001-0111 bitA bitB 101000
|
251
|
+
-001001-0111 bitA bitB 100010
|
252
|
+
-010001-0111 bitA bitB 100010
|
253
|
+
-011001-0111 bitA bitB 111000
|
254
|
+
-100001-0111 bitA bitB 100010
|
255
|
+
-101001-0111 bitA bitB 111000
|
256
|
+
-110001-0111 bitA bitB 111000
|
257
|
+
-111001-0111 bitA bitB 111010
|
258
|
+
-000101-0111 bitA bitB 101000
|
259
|
+
-001101-0111 bitA bitB 101010
|
260
|
+
-010101-0111 bitA bitB 101010
|
261
|
+
-011101-0111 bitA bitB 111000
|
262
|
+
-100101-0111 bitA bitB 101010
|
263
|
+
-101101-0111 bitA bitB 111000
|
264
|
+
-110101-0111 bitA bitB 111000
|
265
|
+
-111101-0111 bitA bitB 111010
|
266
|
+
--0000--0111 bitB bitC 000000
|
267
|
+
--0100--0111 bitB bitC 000010
|
268
|
+
--1000--0111 bitB bitC 000010
|
269
|
+
--1100--0111 bitB bitC 010000
|
270
|
+
--0010--0111 bitB bitC 001000
|
271
|
+
--0110--0111 bitB bitC 000010
|
272
|
+
--1010--0111 bitB bitC 000010
|
273
|
+
--1110--0111 bitB bitC 011000
|
274
|
+
--0000--0111 bitC bitD 000000
|
275
|
+
--0100--0111 bitC bitD 000010
|
276
|
+
--1000--0111 bitC bitD 000010
|
277
|
+
--1100--0111 bitC bitD 010000
|
278
|
+
--0010--0111 bitC bitD 001000
|
279
|
+
--0110--0111 bitC bitD 000010
|
280
|
+
--1010--0111 bitC bitD 000010
|
281
|
+
--1110--0111 bitC bitD 011000
|
282
|
+
--0000--0111 bitD bitE 000000
|
283
|
+
--0100--0111 bitD bitE 000010
|
284
|
+
--1000--0111 bitD bitE 000010
|
285
|
+
--1100--0111 bitD bitE 010000
|
286
|
+
--0010--0111 bitD bitE 001000
|
287
|
+
--0110--0111 bitD bitE 000010
|
288
|
+
--1010--0111 bitD bitE 000010
|
289
|
+
--1110--0111 bitD bitE 011000
|
290
|
+
--0000--0111 bitE bitF 000001
|
291
|
+
--0100--0111 bitE bitF 000011
|
292
|
+
--1000--0111 bitE bitF 000011
|
293
|
+
--1100--0111 bitE bitF 010001
|
294
|
+
--0010--0111 bitE bitF 001100
|
295
|
+
--0110--0111 bitE bitF 000011
|
296
|
+
--1010--0111 bitE bitF 000011
|
297
|
+
--1110--0111 bitE bitF 011001
|
298
|
+
---0-0--0111 bitF rst0 0--000
|
299
|
+
---1-0--0111 bitF rst0 0--010
|
300
|
+
-----1--0111 bitF rst0 0--100
|
301
|
+
-----1--0111 rst0 bit1 0--110
|
302
|
+
-----1--0111 bit1 bit2 0--110
|
303
|
+
-----1--0111 bit2 bit3 0--100
|
304
|
+
-----10-0111 bit3 bit4 1--100
|
305
|
+
-----11-0111 bit3 bit4 1--110
|
306
|
+
-----10-0111 bit4 bit5 1--100
|
307
|
+
-----11-0111 bit4 bit5 1--110
|
308
|
+
-----10-0111 bit5 bit6 1--100
|
309
|
+
-----11-0111 bit5 bit6 1--110
|
310
|
+
-----10-0111 bit6 bit7 1--100
|
311
|
+
-----11-0111 bit6 bit7 1--110
|
312
|
+
-----10-0111 bit7 bit8 1--100
|
313
|
+
-----11-0111 bit7 bit8 1--110
|
314
|
+
-----10-0111 bit8 bit9 1--100
|
315
|
+
-----11-0111 bit8 bit9 1--110
|
316
|
+
-----10-0111 bit9 bitA 1--100
|
317
|
+
-----11-0111 bit9 bitA 1--110
|
318
|
+
-----10-0111 bitA bitB 1--100
|
319
|
+
-----11-0111 bitA bitB 1--110
|
320
|
+
-----1--0111 bitB bitC 0--100
|
321
|
+
-----1--0111 bitC bitD 0--100
|
322
|
+
-----1--0111 bitD bitE 0--100
|
323
|
+
-----1--0111 bitE bitF 0--001
|
324
|
+
--------0010 rst0 bit1 0---00
|
325
|
+
--------0010 bit1 bit2 0---00
|
326
|
+
--------0010 bit2 bit3 0---10
|
327
|
+
-------00010 bit3 bit4 1---00
|
328
|
+
-------10010 bit3 bit4 1---10
|
329
|
+
-------00010 bit4 bit5 1---00
|
330
|
+
-------10010 bit4 bit5 1---10
|
331
|
+
-------00010 bit5 bit6 1---00
|
332
|
+
-------10010 bit5 bit6 1---10
|
333
|
+
-------00010 bit6 bit7 1---00
|
334
|
+
-------10010 bit6 bit7 1---10
|
335
|
+
-------00010 bit7 bit8 1---00
|
336
|
+
-------10010 bit7 bit8 1---10
|
337
|
+
-------00010 bit8 bit9 1---00
|
338
|
+
-------10010 bit8 bit9 1---10
|
339
|
+
-------00010 bit9 bitA 1---00
|
340
|
+
-------10010 bit9 bitA 1---10
|
341
|
+
-------00010 bitA bitB 1---00
|
342
|
+
-------10010 bitA bitB 1---10
|
343
|
+
--------0010 bitB bitC 0---00
|
344
|
+
--------0010 bitC bitD 0---00
|
345
|
+
--------0010 bitD bitE 0---00
|
346
|
+
--------0010 bitE bitF 0---01
|
347
|
+
--------0010 bitF rst0 0---00
|
348
|
+
--------0100 rst0 bit1 0---00
|
349
|
+
--------0100 bit1 bit2 0---00
|
350
|
+
--------0100 bit2 bit3 0---10
|
351
|
+
------0-0100 bit3 bit4 1---00
|
352
|
+
------1-0100 bit3 bit4 1---10
|
353
|
+
------0-0100 bit4 bit5 1---00
|
354
|
+
------1-0100 bit4 bit5 1---10
|
355
|
+
------0-0100 bit5 bit6 1---00
|
356
|
+
------1-0100 bit5 bit6 1---10
|
357
|
+
------0-0100 bit6 bit7 1---00
|
358
|
+
------1-0100 bit6 bit7 1---10
|
359
|
+
------0-0100 bit7 bit8 1---00
|
360
|
+
------1-0100 bit7 bit8 1---10
|
361
|
+
------0-0100 bit8 bit9 1---00
|
362
|
+
------1-0100 bit8 bit9 1---10
|
363
|
+
------0-0100 bit9 bitA 1---00
|
364
|
+
------1-0100 bit9 bitA 1---10
|
365
|
+
------0-0100 bitA bitB 1---00
|
366
|
+
------1-0100 bitA bitB 1---10
|
367
|
+
--------0100 bitB bitC 0---00
|
368
|
+
--------0100 bitC bitD 0---00
|
369
|
+
--------0100 bitD bitE 0---00
|
370
|
+
--------0100 bitE bitF 0---01
|
371
|
+
--------0100 bitF rst0 0---00
|
372
|
+
--------0110 * * ------
|
373
|
+
--------0101 * * ------
|
374
|
+
--------0011 * * ------
|