art-decomp 0.3.0 → 0.4.0

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@@ -145,14 +145,14 @@ module ArtDecomp describe Executable do
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  Executable.new(['--archs', '5/1', '4/2', '--debug', '--log', log.path, '--outdir', @dir, @fsm]).run
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  Logging.level.should == Logger::DEBUG
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  Logging.off
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- File.read(log.path).should =~ rex('FSM 4/2+10s → 5/1+4/2')
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+ File.read(log.path).should =~ rex('4/2+10s')
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  end
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  it 'should handle the s8 edge case with grace' do
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  log = Tempfile.new rand
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  Executable.new(['--archs', '2/1', '--log', log.path, '--outdir', @dir, 'spec/fixtures/s8']).run
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  Logging.off
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- File.read(log.path).should =~ rex('final best decomposition: 0 cells')
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+ File.read(log.path).should =~ rex(' 0c')
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  end
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  # FIXME: add specs for --binary, --non-disjoint and --deep-ndj
@@ -23,6 +23,10 @@ module ArtDecomp describe FSM do
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  lambda { FSM.from_kiss 'spec/fixtures/ex5' }.should_not raise_error
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  end
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+ it 'should ignore KISS lines with don’t-care next states and outputs' do
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+ FSM.from_kiss('spec/fixtures/kirkman').beta_q.ints.map(&:bits).flatten.max.should == 366
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+ end
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+
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  it 'should handle truth table files by faking a don’t-care state column' do
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  @tt.input_count.should == 4
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  @tt.output_count.should == 2
@@ -178,6 +182,43 @@ module ArtDecomp describe FSM do
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  @fsm.should_not be_truth_table
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  end
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+ it 'should properly generate its structure' do
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+ @mark1.structure.to_yaml.should == File.read('spec/fixtures/mark1.yml')
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+ end
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+
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+ it 'should properly generate its VHDL representation' do
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+ @fsm.to_vhdl('fsm').should == File.read('spec/fixtures/fsm.vhd')
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+ @mark1.to_vhdl('mark1').should == File.read('spec/fixtures/mark1.vhd')
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+ end
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+
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+ end
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+
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+ context 'parsed from an encoded KISS file' do
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+
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+ before do
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+ @one_hot = FSM.from_kiss 'spec/fixtures/mark1.hot'
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+ @nova = FSM.from_kiss 'spec/fixtures/mark1.nov'
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+ @jedi = FSM.from_kiss 'spec/fixtures/mark1.jed'
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+ end
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+
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+ it 'should properly create the FSM' do
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+ @one_hot.should == FSM.from_kiss('spec/fixtures/mark1')
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+ @nova.should == FSM.from_kiss('spec/fixtures/mark1')
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+ @jedi.should == FSM.from_kiss('spec/fixtures/mark1')
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+ end
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+
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+ it 'should properly find codes in an one-hot file' do
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+ @one_hot.codes.should == {:state1 => :'100000000000000', :state3 => :'010000000000000', :state2 => :'001000000000000', :state0 => :'000100000000000', :state4 => :'000010000000000', :state13 => :'000001000000000', :state10 => :'000000100000000', :state9 => :'000000010000000', :state8 => :'000000001000000', :state7 => :'000000000100000', :state6 => :'000000000010000', :state5 => :'000000000001000', :state14 => :'000000000000100', :state11 => :'000000000000010', :state12 => :'000000000000001'}
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+ @nova.codes.should == {:state1 => :'0100', :state2 => :'1000', :state3 => :'1011', :state4 => :'1100', :state5 => :'0001', :state6 => :'0011', :state7 => :'0000', :state8 => :'0010', :state9 => :'1101', :state10 => :'1010', :state11 => :'0111', :state12 => :'1001', :state13 => :'0101', :state14 => :'0110', :state0 => :'1110'}
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+ @jedi.codes.should == {:state1 => :'0001', :state3 => :'1111', :state2 => :'0011', :state0 => :'1101', :state4 => :'1001', :state13 => :'1010', :state10 => :'1000', :state9 => :'1100', :state8 => :'0010', :state7 => :'0000', :state6 => :'0110', :state5 => :'0100', :state14 => :'1110', :state11 => :'0111', :state12 => :'1011'}
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+ end
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+
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+ it 'should properly generate the (encoded) VHDL' do
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+ @one_hot.to_vhdl('mark1_hot').should == File.read('spec/fixtures/mark1_hot.vhd')
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+ @nova.to_vhdl('mark1_nov').should == File.read('spec/fixtures/mark1_nov.vhd')
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+ @jedi.to_vhdl('mark1_jed').should == File.read('spec/fixtures/mark1_jed.vhd')
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+ end
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+
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  end
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  end end
@@ -9,6 +9,7 @@ module ArtDecomp describe Logging do
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  @fsm = mock FSM, :beta_f => Blanket[], :beta_q => Blanket[], :beta_x => Blanket[]
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  @log = StringIO.new
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  Logging.log = @log
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+ Logging.level = Logger::INFO
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  end
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  after do
@@ -24,7 +25,7 @@ module ArtDecomp describe Logging do
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  it 'should log Executable’s decompositions calls on simple cases' do
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  args = ['-a', '5/1', '4/2', '-o', @dir, 'spec/fixtures/lion']
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  Executable.new(args).run
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- log.should =~ rex('final best decomposition: 2 cells; done in 0s (0h 0m 0s)')
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+ log.should =~ rex('took 1s')
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  end
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  it 'should log Executable’s decompositions calls on typical cases' do
@@ -33,41 +34,26 @@ module ArtDecomp describe Logging do
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  ex = Executable.new(args)
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  ex.stub!(:best).and_return 69
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  ex.run
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- log.should =~ rex('FSM 4/2+10s → 5/1+4/2 () with UniqueRelevance, EdgeLabels, GraphColouring – best so far: 69 cells')
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- log.should =~ rex('final best decomposition: 69 cells; done in 0s (0h 0m 0s)')
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+ log.should =~ rex('4/2+10s with UniqueRelevance, EdgeLabels, GraphColouring')
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+ log.should =~ rex('took 1s')
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  end
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  it 'should log Executable’s decompositions calls on problematic cases' do
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  Decomposer.should_receive(:new).and_return mock(Decomposer, :decompositions => [].each)
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  args = ['-a', '5/1', '4/2', '-o', @dir, 'spec/fixtures/fsm']
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  Executable.new(args).run
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- log.should =~ rex('FSM 4/2+10s → 5/1+4/2 () with UniqueRelevance, EdgeLabels, GraphColouring – no decomposition so far')
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- log.should =~ rex('no final decomposition; done in 0s (0h 0m 0s)')
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+ log.should =~ rex('4/2+10s with UniqueRelevance, EdgeLabels, GraphColouring')
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+ log.should =~ rex('took 1s')
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  end
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- it 'should log UVGeneratorsuv_pairs calls' do
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- uv = UVGenerator::Braindead.new
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- uv.uv_pairs mock(FSM, :input_count => 2), Set[Arch[5,1]]
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- log.should =~ rex('UV with Braindead')
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- end
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-
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- it 'should log QuGenerators’ blankets calls' do
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+ it 'should log QuGeneratorsblankets calls (if debug-level logging enabled)' do
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+ Logging.level = Logger::DEBUG
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  qu = QuGenerator::BlockTable.new
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  [[Set[0], Set[1]], [Set[1], Set[0]]].each do |u, v|
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  qu.blankets @fsm, u, v
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  end
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- log.should =~ rex('U = [0], V = [1], Qu with BlockTable')
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- log.should =~ rex('U = [1], V = [0], Qu with BlockTable')
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- end
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-
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- it 'should log QvGenerators’ blankets calls (on the DEBUG level)' do
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- Logging.level = Logger::DEBUG
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- qv = QvGenerator::GraphColouring.new
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- [mock(Blanket, :size => 8), mock(Blanket, :size => 4)].each do |qu|
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- qv.blankets @fsm, Set[0], Set[1], qu
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- end
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- log.should =~ rex('|Qu| = 8, Qv+G with GraphColouring')
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- log.should =~ rex('|Qu| = 4, Qv+G with GraphColouring')
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+ log.should =~ rex('0 1 via with BlockTable')
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+ log.should =~ rex('1 0 via with BlockTable')
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  end
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  end end
@@ -0,0 +1,22 @@
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+ # encoding: UTF-8
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+
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+ module ArtDecomp describe VHDL do
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+
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+ context 'generated from an FSM' do
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+
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+ it 'should properly generates the VHDL representation' do
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+ VHDL.new(FSM.from_kiss 'spec/fixtures/fsm').vhdl('fsm').should == File.read('spec/fixtures/fsm.vhd')
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+ VHDL.new(FSM.from_kiss 'spec/fixtures/mark1').vhdl('mark1').should == File.read('spec/fixtures/mark1.vhd')
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+ end
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+
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+ it 'should generate encoded VHDL if the FSM is encoded' do
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+ VHDL.new(FSM.from_kiss 'spec/fixtures/mark1.hot').vhdl('mark1_hot').should == File.read('spec/fixtures/mark1_hot.vhd')
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+ end
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+
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+ it 'should rename digit-only states' do
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+ VHDL.new(FSM.from_kiss 'spec/fixtures/ex4.hot').vhdl('ex4_hot').should == File.read('spec/fixtures/ex4_hot.vhd')
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+ end
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+
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+ end
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+
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+ end end
@@ -0,0 +1,44 @@
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+ .model jedi_output
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+ .start_kiss
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+ .i 6
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+ .o 9
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+ .s 14
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+ .p 21
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+ .r 1
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+ 1----- 1 3 110000000
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+ 1----- 3 2 000000000
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+ 1----- 2 5 001000000
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+ 1----- 5 7 000000000
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+ 10---- 7 7 000000000
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+ 11---- 7 11 100110000
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+ 1----- 11 12 100100000
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+ 1-1--- 12 8 000001100
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+ 1-0--- 12 8 000000100
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+ 1-0--- 8 3 110000000
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+ 1-10-- 8 3 110000000
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+ 1-11-- 8 4 110000000
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+ 1---1- 4 13 000000010
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+ 1---0- 4 13 000000000
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+ 1----- 13 14 001000010
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+ 1----- 14 6 000000000
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+ 10---- 6 6 000000000
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+ 11---- 6 9 100110000
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+ 1----- 9 10 100100000
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+ 1----1 10 3 110000101
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+ 1----0 10 4 110000100
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+ .end_kiss
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+ .code 1 10000000000000
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+ .code 3 01000000000000
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+ .code 2 00100000000000
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+ .code 5 00010000000000
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+ .code 7 00001000000000
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+ .code 11 00000100000000
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+ .code 12 00000010000000
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+ .code 8 00000001000000
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+ .code 4 00000000100000
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+ .code 13 00000000010000
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+ .code 14 00000000001000
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+ .code 6 00000000000100
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+ .code 9 00000000000010
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+ .code 10 00000000000001
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+ .end
@@ -0,0 +1,87 @@
1
+ library ieee;
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+ use ieee.numeric_std.all;
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+ use ieee.std_logic_1164.all;
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+ entity ex4_hot is
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+ port(
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+ clock: in std_logic;
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+ input: in std_logic_vector(5 downto 0);
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+ output: out std_logic_vector(8 downto 0)
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+ );
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+ end ex4_hot;
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+ architecture behaviour of ex4_hot is
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+ constant s1: std_logic_vector(13 downto 0) := "10000000000000";
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+ constant s3: std_logic_vector(13 downto 0) := "01000000000000";
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+ constant s2: std_logic_vector(13 downto 0) := "00100000000000";
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+ constant s5: std_logic_vector(13 downto 0) := "00010000000000";
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+ constant s7: std_logic_vector(13 downto 0) := "00001000000000";
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+ constant s11: std_logic_vector(13 downto 0) := "00000100000000";
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+ constant s12: std_logic_vector(13 downto 0) := "00000010000000";
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+ constant s8: std_logic_vector(13 downto 0) := "00000001000000";
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+ constant s4: std_logic_vector(13 downto 0) := "00000000100000";
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+ constant s13: std_logic_vector(13 downto 0) := "00000000010000";
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+ constant s14: std_logic_vector(13 downto 0) := "00000000001000";
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+ constant s6: std_logic_vector(13 downto 0) := "00000000000100";
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+ constant s9: std_logic_vector(13 downto 0) := "00000000000010";
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+ constant s10: std_logic_vector(13 downto 0) := "00000000000001";
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+ signal current_state, next_state: std_logic_vector(13 downto 0);
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+ begin
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+ process(clock) begin
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+ if rising_edge(clock) then current_state <= next_state;
30
+ end if;
31
+ end process;
32
+ process(input, current_state) begin
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+ next_state <= "--------------"; output <= "---------";
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+ case current_state is
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+ when s1 =>
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+ if std_match(input, "1-----") then next_state <= s3; output <= "110000000";
37
+ end if;
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+ when s3 =>
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+ if std_match(input, "1-----") then next_state <= s2; output <= "000000000";
40
+ end if;
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+ when s2 =>
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+ if std_match(input, "1-----") then next_state <= s5; output <= "001000000";
43
+ end if;
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+ when s5 =>
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+ if std_match(input, "1-----") then next_state <= s7; output <= "000000000";
46
+ end if;
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+ when s7 =>
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+ if std_match(input, "10----") then next_state <= s7; output <= "000000000";
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+ elsif std_match(input, "11----") then next_state <= s11; output <= "100110000";
50
+ end if;
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+ when s11 =>
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+ if std_match(input, "1-----") then next_state <= s12; output <= "100100000";
53
+ end if;
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+ when s12 =>
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+ if std_match(input, "1-1---") then next_state <= s8; output <= "000001100";
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+ elsif std_match(input, "1-0---") then next_state <= s8; output <= "000000100";
57
+ end if;
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+ when s8 =>
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+ if std_match(input, "1-0---") then next_state <= s3; output <= "110000000";
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+ elsif std_match(input, "1-10--") then next_state <= s3; output <= "110000000";
61
+ elsif std_match(input, "1-11--") then next_state <= s4; output <= "110000000";
62
+ end if;
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+ when s4 =>
64
+ if std_match(input, "1---1-") then next_state <= s13; output <= "000000010";
65
+ elsif std_match(input, "1---0-") then next_state <= s13; output <= "000000000";
66
+ end if;
67
+ when s13 =>
68
+ if std_match(input, "1-----") then next_state <= s14; output <= "001000010";
69
+ end if;
70
+ when s14 =>
71
+ if std_match(input, "1-----") then next_state <= s6; output <= "000000000";
72
+ end if;
73
+ when s6 =>
74
+ if std_match(input, "10----") then next_state <= s6; output <= "000000000";
75
+ elsif std_match(input, "11----") then next_state <= s9; output <= "100110000";
76
+ end if;
77
+ when s9 =>
78
+ if std_match(input, "1-----") then next_state <= s10; output <= "100100000";
79
+ end if;
80
+ when s10 =>
81
+ if std_match(input, "1----1") then next_state <= s3; output <= "110000101";
82
+ elsif std_match(input, "1----0") then next_state <= s4; output <= "110000100";
83
+ end if;
84
+ when others => next_state <= "--------------"; output <= "---------";
85
+ end case;
86
+ end process;
87
+ end behaviour;
@@ -0,0 +1,64 @@
1
+ library ieee;
2
+ use ieee.numeric_std.all;
3
+ use ieee.std_logic_1164.all;
4
+ entity fsm is
5
+ port(
6
+ clock: in std_logic;
7
+ input: in std_logic_vector(3 downto 0);
8
+ output: out std_logic_vector(1 downto 0)
9
+ );
10
+ end fsm;
11
+ architecture behaviour of fsm is
12
+ type state is (init0, init1, init2, init4, IOwait, RMACK, WMACK, read0, read1, write0);
13
+ signal current_state, next_state: state;
14
+ begin
15
+ process(clock) begin
16
+ if rising_edge(clock) then current_state <= next_state;
17
+ end if;
18
+ end process;
19
+ process(input, current_state) begin
20
+ next_state <= init0; output <= "--";
21
+ case current_state is
22
+ when init0 =>
23
+ if std_match(input, "--00") then next_state <= init1; output <= "00";
24
+ end if;
25
+ when init1 =>
26
+ if std_match(input, "0100") then next_state <= init1; output <= "00";
27
+ elsif std_match(input, "--1-") then next_state <= init2; output <= "10";
28
+ end if;
29
+ when init2 =>
30
+ if std_match(input, "1-10") then next_state <= init4; output <= "10";
31
+ end if;
32
+ when init4 =>
33
+ if std_match(input, "-111") then next_state <= init4; output <= "10";
34
+ elsif std_match(input, "--01") then next_state <= IOwait; output <= "01";
35
+ end if;
36
+ when IOwait =>
37
+ if std_match(input, "000-") then next_state <= IOwait; output <= "01";
38
+ elsif std_match(input, "100-") then next_state <= init1; output <= "01";
39
+ elsif std_match(input, "0110") then next_state <= read0; output <= "00";
40
+ elsif std_match(input, "1100") then next_state <= write0; output <= "11";
41
+ elsif std_match(input, "0111") then next_state <= RMACK; output <= "11";
42
+ elsif std_match(input, "1101") then next_state <= WMACK; output <= "00";
43
+ elsif std_match(input, "-01-") then next_state <= init2; output <= "01";
44
+ end if;
45
+ when RMACK =>
46
+ if std_match(input, "0010") then next_state <= RMACK; output <= "11";
47
+ elsif std_match(input, "0111") then next_state <= read0; output <= "00";
48
+ end if;
49
+ when WMACK =>
50
+ if std_match(input, "1100") then next_state <= WMACK; output <= "00";
51
+ elsif std_match(input, "1001") then next_state <= write0; output <= "01";
52
+ end if;
53
+ when read0 =>
54
+ if std_match(input, "0001") then next_state <= read1; output <= "11";
55
+ end if;
56
+ when read1 =>
57
+ if std_match(input, "0010") then next_state <= IOwait; output <= "01";
58
+ end if;
59
+ when write0 =>
60
+ if std_match(input, "0100") then next_state <= IOwait; output <= "01";
61
+ end if;
62
+ end case;
63
+ end process;
64
+ end behaviour;
@@ -0,0 +1,374 @@
1
+ .i 12
2
+ .o 6
3
+ .p 370
4
+ .s 16
5
+ --------1--- * rst0 1-----
6
+ --------0000 rst0 rst0 0----0
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+ --------0001 rst0 bit1 0---00
8
+ --------0001 bit1 bit2 0---10
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+ --------0001 bit2 bit3 0---00
10
+ 0-------0001 bit3 bit4 1---00
11
+ 1-------0001 bit3 bit4 1---10
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+ 0-------0001 bit4 bit5 1---00
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+ 1-------0001 bit4 bit5 1---10
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+ 0-------0001 bit5 bit6 1---00
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+ 1-------0001 bit5 bit6 1---10
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+ 0-------0001 bit6 bit7 1---00
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+ 1-------0001 bit6 bit7 1---10
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+ 0-------0001 bit7 bit8 1---00
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+ 1-------0001 bit7 bit8 1---10
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+ 0-------0001 bit8 bit9 1---00
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+ 1-------0001 bit8 bit9 1---10
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+ 0-------0001 bit9 bitA 1---00
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+ 1-------0001 bit9 bitA 1---10
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+ 0-------0001 bitA bitB 1---00
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+ 1-------0001 bitA bitB 1---10
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+ --------0001 bitB bitC 0---00
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+ --------0001 bitC bitD 0---00
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+ --------0001 bitD bitE 0---00
29
+ --------0001 bitE bitF 0---01
30
+ --------0001 bitF rst0 0---00
31
+ -----0--0111 rst0 bit1 0--010
32
+ -----0--0111 bit1 bit2 0--010
33
+ -----0--0111 bit2 bit3 0--000
34
+ -00--00-0111 bit3 bit4 100000
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+ -01--00-0111 bit3 bit4 100010
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+ -10--00-0111 bit3 bit4 100010
37
+ -11--00-0111 bit3 bit4 110000
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+ -00--01-0111 bit3 bit4 101000
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+ -01--01-0111 bit3 bit4 100010
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+ -10--01-0111 bit3 bit4 100010
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+ -11--01-0111 bit3 bit4 111000
42
+ -000000-0111 bit4 bit5 100000
43
+ -001000-0111 bit4 bit5 100010
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+ -010000-0111 bit4 bit5 100010
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+ -011000-0111 bit4 bit5 110000
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+ -100000-0111 bit4 bit5 100010
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+ -101000-0111 bit4 bit5 110000
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+ -110000-0111 bit4 bit5 110000
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+ -111000-0111 bit4 bit5 110010
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+ -000100-0111 bit4 bit5 101000
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+ -001100-0111 bit4 bit5 100010
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+ -010100-0111 bit4 bit5 100010
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+ -011100-0111 bit4 bit5 111000
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+ -100100-0111 bit4 bit5 100010
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+ -101100-0111 bit4 bit5 111000
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+ -110100-0111 bit4 bit5 111000
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+ -111100-0111 bit4 bit5 110010
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+ -000001-0111 bit4 bit5 101000
59
+ -001001-0111 bit4 bit5 100010
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+ -010001-0111 bit4 bit5 100010
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+ -011001-0111 bit4 bit5 111000
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+ -100001-0111 bit4 bit5 100010
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+ -101001-0111 bit4 bit5 111000
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+ -110001-0111 bit4 bit5 111000
65
+ -111001-0111 bit4 bit5 111010
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+ -000101-0111 bit4 bit5 101000
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+ -001101-0111 bit4 bit5 101010
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+ -010101-0111 bit4 bit5 101010
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+ -011101-0111 bit4 bit5 111000
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+ -100101-0111 bit4 bit5 101010
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+ -101101-0111 bit4 bit5 111000
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+ -110101-0111 bit4 bit5 111000
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+ -111101-0111 bit4 bit5 111010
74
+ -000000-0111 bit5 bit6 100000
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