HDLRuby 2.10.5 → 2.11.0

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Files changed (38) hide show
  1. checksums.yaml +4 -4
  2. data/HDLRuby.gemspec +1 -0
  3. data/README.md +8 -4
  4. data/Rakefile +8 -0
  5. data/{lib/HDLRuby/sim/Makefile → ext/hruby_sim/Makefile_csim} +0 -0
  6. data/ext/hruby_sim/extconf.rb +13 -0
  7. data/ext/hruby_sim/hruby_rcsim_build.c +1188 -0
  8. data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim.h +255 -16
  9. data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_calc.c +310 -181
  10. data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_core.c +34 -17
  11. data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_list.c +0 -0
  12. data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_stack_calc.c +4 -1
  13. data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_stack_calc.c.sav +0 -0
  14. data/ext/hruby_sim/hruby_sim_tree_calc.c +375 -0
  15. data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_vcd.c +5 -5
  16. data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_vizualize.c +2 -2
  17. data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_value_pool.c +4 -1
  18. data/lib/HDLRuby/hdr_samples/bstr_bench.rb +2 -0
  19. data/lib/HDLRuby/hdr_samples/case_bench.rb +2 -2
  20. data/lib/HDLRuby/hdr_samples/counter_bench.rb +0 -1
  21. data/lib/HDLRuby/hdr_samples/counter_dff_bench.rb +46 -0
  22. data/lib/HDLRuby/hdr_samples/dff_bench.rb +1 -1
  23. data/lib/HDLRuby/hdr_samples/print_bench.rb +62 -0
  24. data/lib/HDLRuby/hdr_samples/rom.rb +5 -3
  25. data/lib/HDLRuby/hdr_samples/simple_counter_bench.rb +43 -0
  26. data/lib/HDLRuby/hdrcc.rb +54 -8
  27. data/lib/HDLRuby/hruby_bstr.rb +1175 -917
  28. data/lib/HDLRuby/hruby_high.rb +200 -90
  29. data/lib/HDLRuby/hruby_high_fullname.rb +82 -0
  30. data/lib/HDLRuby/hruby_low.rb +41 -23
  31. data/lib/HDLRuby/hruby_low2c.rb +7 -0
  32. data/lib/HDLRuby/hruby_rcsim.rb +978 -0
  33. data/lib/HDLRuby/hruby_rsim.rb +1134 -0
  34. data/lib/HDLRuby/hruby_rsim_vcd.rb +322 -0
  35. data/lib/HDLRuby/hruby_values.rb +362 -18
  36. data/lib/HDLRuby/hruby_verilog.rb +21 -3
  37. data/lib/HDLRuby/version.rb +1 -1
  38. metadata +24 -13
checksums.yaml CHANGED
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data/HDLRuby.gemspec CHANGED
@@ -26,6 +26,7 @@ Gem::Specification.new do |spec|
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  spec.executables = spec.files.grep(%r{^exe/}) { |f| File.basename(f) }
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  # spec.require_paths = ["lib"]
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  spec.require_paths = ["lib","lib/HDLRuby"]
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+ spec.extensions = %w[ext/hruby_sim/extconf.rb]
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  spec.required_ruby_version = '>= 2.0'
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  # spec.add_development_dependency "bundler", "~> 2.0.1"
data/README.md CHANGED
@@ -49,8 +49,11 @@ Where:
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  | `-v, --verilog` | Output in Verilog HDL format |
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  | `-V, --vhdl` | Output in VHDL format |
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  | `-s, --syntax` | Output the Ruby syntax tree |
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- | `-C, --clang` | Output the C code of the simulator |
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- | `-S, --sim` | Output the executable simulator and execute it |
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+ | `-C, --clang` | Output the C code of the standalone simulator. |
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+ | `-S, --sim` | Perform the simulation with the default engine. |
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+ | `--csim` | Perform the simulation with the standalone engine. |
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+ | `--rsim` | Perform the simulation with the Ruby engine. |
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+ | `--rcsim` | Perform the simulation with the Hybris engine. |
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  | `--vcd` | Make the simulator generate a VCD file |
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  | `-d, --directory` | Specify the base directory for loading the HDLRuby files |
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  | `-D, --debug` | Set the HDLRuby debug mode |
@@ -91,13 +94,14 @@ hdrcc -V -t adder --param 16 adder_gen.rb adder
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  hdrcc -y -t multer -p 16,16,32 multer_gen.rb multer
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  ```
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- * Simulate the circuit described in file `counter_bench.rb` using directory `counter` for
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- storing the simulator's files:
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+ * Simulate the circuit described in file `counter_bench.rb` using the default simluation engine and putting the simulator's files in directory `counter`:
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  ```
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  hdrcc -S counter_bench.rb counter
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  ```
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+ As a policy, the default simulation enigne is set to the fastest one (cuttently it is the hybrid engine).
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+
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  * Run in interactive mode.
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  ```
data/Rakefile CHANGED
@@ -1,5 +1,11 @@
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  require "bundler/gem_tasks"
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  require "rake/testtask"
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+ require "rake/extensiontask"
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+
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+ Rake::ExtensionTask.new "hruby_sim" do |ext|
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+ ext.lib_dir = "lib/hruby_sim"
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+ end
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+
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  Rake::TestTask.new(:test) do |t|
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  t.libs << "test"
@@ -7,4 +13,6 @@ Rake::TestTask.new(:test) do |t|
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  t.test_files = FileList['test/**/*_test.rb']
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  end
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+
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+
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  task :default => :test
@@ -0,0 +1,13 @@
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+ require 'mkmf'
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+
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+ append_cppflags(["-DRCSIM"])
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+ # For debugging RCSIM
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+ append_cflags(["-g"])
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+ # append_cflags(["-fsanitize=address"])
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+ # append_ldflags(["-fsanitize=address"])
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+
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+ abort "missing malloc()" unless have_func "malloc"
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+ abort "missing free()" unless have_func "free"
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+
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+ create_header
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+ create_makefile 'hruby_sim/hruby_sim'