HDLRuby 2.10.5 → 2.11.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/HDLRuby.gemspec +1 -0
- data/README.md +8 -4
- data/Rakefile +8 -0
- data/{lib/HDLRuby/sim/Makefile → ext/hruby_sim/Makefile_csim} +0 -0
- data/ext/hruby_sim/extconf.rb +13 -0
- data/ext/hruby_sim/hruby_rcsim_build.c +1188 -0
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim.h +255 -16
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_calc.c +310 -181
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_core.c +34 -17
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_list.c +0 -0
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_stack_calc.c +4 -1
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_stack_calc.c.sav +0 -0
- data/ext/hruby_sim/hruby_sim_tree_calc.c +375 -0
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_vcd.c +5 -5
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_vizualize.c +2 -2
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_value_pool.c +4 -1
- data/lib/HDLRuby/hdr_samples/bstr_bench.rb +2 -0
- data/lib/HDLRuby/hdr_samples/case_bench.rb +2 -2
- data/lib/HDLRuby/hdr_samples/counter_bench.rb +0 -1
- data/lib/HDLRuby/hdr_samples/counter_dff_bench.rb +46 -0
- data/lib/HDLRuby/hdr_samples/dff_bench.rb +1 -1
- data/lib/HDLRuby/hdr_samples/print_bench.rb +62 -0
- data/lib/HDLRuby/hdr_samples/rom.rb +5 -3
- data/lib/HDLRuby/hdr_samples/simple_counter_bench.rb +43 -0
- data/lib/HDLRuby/hdrcc.rb +54 -8
- data/lib/HDLRuby/hruby_bstr.rb +1175 -917
- data/lib/HDLRuby/hruby_high.rb +200 -90
- data/lib/HDLRuby/hruby_high_fullname.rb +82 -0
- data/lib/HDLRuby/hruby_low.rb +41 -23
- data/lib/HDLRuby/hruby_low2c.rb +7 -0
- data/lib/HDLRuby/hruby_rcsim.rb +978 -0
- data/lib/HDLRuby/hruby_rsim.rb +1134 -0
- data/lib/HDLRuby/hruby_rsim_vcd.rb +322 -0
- data/lib/HDLRuby/hruby_values.rb +362 -18
- data/lib/HDLRuby/hruby_verilog.rb +21 -3
- data/lib/HDLRuby/version.rb +1 -1
- metadata +24 -13
data/lib/HDLRuby/hruby_values.rb
CHANGED
@@ -1,52 +1,339 @@
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module HDLRuby
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##
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# Library for implementing the value processing.
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#
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########################################################################
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##
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# Library for implementing the value processing.
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#
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########################################################################
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# To include to classes for value processing support.
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module Vprocess
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# TRUNC_P_T = 65536.times.map { |i| 2**i - 1 }
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# TRUNC_N_T = 65536.times.map { |i| (-1 * 2**i) }
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# Truncs integer +val+ to +width+
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def trunc(val,width)
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if val.bit_length > width then
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if val >= 0 then
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# return val & (2**width-1)
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return val % (2**width)
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# return val & TRUNC_P_T[width]
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else
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# return val | (-1 * 2**width)
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return val % -(2**width)
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# return val | TRUNC_N_T[width]
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end
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else
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return val
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end
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end
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# Redefinition of the arithmetic and logic operations binary operators
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[ :+, :-, :*, :/, :%, :&, :|, :**,
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[ :+, :-, :*, :/, :%, :&, :|, :^, :**,
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:<<, :>>,
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:==, :<, :>, :<=, :>=, :<=> ].
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define_method(op) do |
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# puts "value=#{value}"
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# Ensures
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unless
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:==, :!=, :<, :>, :<=, :>=, :<=> ].
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each do |op|
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define_method(op) do |val|
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# puts "op=#{op} value=#{value}"
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# Ensures val is computable.
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unless val.to_value? then
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# Not computable, use the former method that generates
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# HDLRuby code.
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return self.send(orig_operator(op),value)
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end
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# Handle Numeric op BitString case.
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if self.content.is_a?(Numeric) && val.content.is_a?(BitString)
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if val.content.specified? then
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res_content = self.content.send(op,val.content.to_i)
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else
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res_content =
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BitString.new(self.content).send(op,val.content)
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end
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else
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# Generate the resulting content.
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res_content = self.content.send(op,val.content)
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# puts "op=#{op} self.content=#{self.content} (#{self.content.class}) val.content=#{val.content} (#{val.content.class}) res_content=#{res_content} (#{res_content.class})"
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end
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res_type = self.type.resolve(val.type)
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# # Adjust the result content size.
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# res_width = res_type.width
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# if res_content.is_a?(BitString) then
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# res_content.trunc!(res_width)
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# else
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# res_content = self.trunc(res_content,res_width)
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# end
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# Return the resulting value.
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return self.class.new(res_type,res_content)
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end
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end
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+
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# Redefinition of the access operators.
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define_method(:[]) do |val|
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if val.is_a?(Range) then
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# Range case.
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# Ensures value is really a range of values.
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left = val.first
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right = val.last
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unless left.to_value? && right.to_value? then
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# Not a value, use the former method.
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# Assumed
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return self.send(orig_operator(op),
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return self.send(orig_operator(op),val)
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end
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# Process left.
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# unless left.is_a?(Numeric) || left.is_a?(BitString) then
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# left = left.to_value.content
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# end
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left = left.content
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if left.is_a?(BitString) && !left.specified? then
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return self.class.new(self.type.base,
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BitString::UNKNOWN.clone)
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end
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-
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# left = left.to_i
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left = self.trunc(left.to_i,val.first.type.width)
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# Process right.
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# unless right.is_a?(Numeric) || right.is_a?(BitString) then
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# right = right.to_value.content
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# end
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right = right.content
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if right.is_a?(BitString) && !right.specified? then
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return self.class.new(self.type.base,
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BitString::UNKNOWN.clone)
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end
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# right = right.to_i
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right = self.trunc(right.to_i,val.last.type.width)
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# Generate the resulting type.
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res_type = self.type.
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# Generate the resulting
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# puts "
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res_type = self.type.base[(left-right+1).abs]
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# Generate the resulting value.
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width = res_type.base.width
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# puts "width=#{width}, left=#{left} right=#{right}"
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if self.content.is_a?(BitString) then
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res_content = self.content[right*width..(left+1)*width-1]
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else
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sh = right*width
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mask = (-1 << sh) & ~(-1 << (left+1)*width)
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res_content = (self.content & mask) >> sh
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end
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# Return the resulting value.
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return self.class.new(res_type,res_content)
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else
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# Index case.
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# Ensures val is really a value.
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unless val.to_value? then
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# Not a value, use the former method.
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# Assumed
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return self.send(orig_operator(op),val)
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end
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# Process val.
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index = val.content
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if index.is_a?(BitString) && !index.specified? then
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return self.class.new(self.type.base,
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BitString::UNKNOWN.clone)
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end
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index = self.trunc(index.to_i,val.type.width)
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# index = index.to_i
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# if index >= self.type.size then
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# # puts "index=#{index}"
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# index %= self.type.size
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# # puts "now index=#{index}"
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# end
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# Generate the resulting type.
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res_type = self.type.base
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# Generate the resulting value.
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width = res_type.width
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# puts "type width=#{self.type.width}, element width=#{width}, index=#{index}"
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if self.content.is_a?(BitString) then
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res_content = self.content[index*width..(index+1)*width-1]
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else
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sh = index*width
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mask = (-1 << sh) & ~(-1 << (index+1)*width)
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res_content = (self.content & mask) >> sh
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end
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# Return the resulting value.
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return self.class.new(res_type,res_content)
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end
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end
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define_method(:[]=) do |index,val|
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if index.is_a?(Range) then
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# Range case.
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# Ensures indexes and val are really values.
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left = index.first
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right = index.last
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unless val.to_value? &&
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left.to_value? && right.to_value? then
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# Not a value, use the former method.
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# Assumed
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return self.send(orig_operator(op),index,value)
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end
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# Process val.
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val = val.content if val.is_a?(Value)
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# Process left.
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left = left.content if left.is_a?(Value)
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if left.is_a?(BitString) && !left.specified? then
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return self.class.new(self.type.base,
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BitString::UNKNOWN.clone)
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end
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left = left.to_i
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# Process right.
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right = right.content if right.is_a?(Value)
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if right.is_a?(BitString) && !right.specified? then
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return self.class.new(self.type.base,
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BitString::UNKNOWN.clone)
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end
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right = right.to_i
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# Compute the width of one element.
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width = self.type.base.width
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# Write the value at the right position.
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# puts "width=#{width}, left=#{left}, right=#{right}"
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if @content.is_a?(BitString) then
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@content[right*width..(left+1)*width-1] = val
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else
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sh = right*width
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val = self.trunc(val,((left-right).abs+1)*width) << sh
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mask = ~(-1 << sh) | (-1 << (left+1)*width)
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@content =((@content & mask) | val)
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end
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else
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# Index case.
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# Ensures index and val are really values.
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unless val.to_value? && index.to_value? then
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# Not a value, use the former method.
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# Assumed
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return self.send(orig_operator(op),index,value)
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end
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# Process val.
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val = val.content if val.is_a?(Value)
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# puts "val=#{val} (#{val.class})"
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# Process index.
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index = index.content if index.is_a?(Value)
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# puts "index=#{index} (#{index.class})"
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if index.is_a?(BitString) && !index.specified? then
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return self.class.new(self.type.base,
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BitString::UNKNOWN.clone)
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end
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index = index.to_i
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# Compute the width of one element.
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width = self.type.base.width
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# Write the value at the right position.
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# puts "width=#{width}, index=#{index}, val=#{val}"
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# puts "first @content=#{@content}, index*width=#{index*width} next=#{(index+1)*width-1}"
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if @content.is_a?(BitString) then
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@content[index*width..(index+1)*width-1] = val
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else
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sh = index*width
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val = self.trunc(val,width) << sh
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mask = ~(-1 << sh) | (-1 << (index+1)*width)
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@content = ((@content & mask) | val)
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end
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# puts "now @content=#{@content}"
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end
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end
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# Redefinition of the arithmetic and logic operations unary operators
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[ :-@, :+@, :~, :abs ].each do |op|
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# Actual redefinition.
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define_method(op) do
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# Generate the resulting type.
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res_type = self.type
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res_type = self.type
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# Generate the resulting content.
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# puts "op=#{op} content=#{content.to_s}"
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res_content = self.content.send(op)
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# puts "res_content=#{res_content}"
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# Return the resulting value.
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return self.class.new(res_type,res_content)
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end
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end
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# Cast to +type+.
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# NOTE: nodir tells if the direction is to be ignored.
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def cast(type,nodir = false)
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# Handle the direction.
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if !nodir && type.direction != self.type.direction then
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if self.content.is_a?(Numeric) then
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tmp = 0
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res_content = self.content
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self.type.width.times do |i|
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tmp = tmp*2 | (res_content & 1)
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res_content /= 2
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end
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res_content = tmp
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elsif self.content.is_a?(BitString) then
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res_content = self.content.clone.reverse!(self.type.width)
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else
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res_content = self.content.reverse
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end
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else
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res_content = self.content.clone
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end
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# Handle the sign.
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if type.unsigned? && !self.content.positive? then
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# Ensure the content is a positive value to match unsigned type.
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if res_content.is_a?(Numeric) then
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res_content &= ~(-1 << type.width) if res_content < 0
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# res_content &= ~(-1 * 2**type.width) if res_content < 0
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else
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res_content.positive!
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end
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end
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# # truncs to the right size if necessary.
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# if res_content.is_a?(BitString) then
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# res_content.trunc!(type.width)
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# else
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# res_content = self.trunc(res_content,type.width)
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# end
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# Generate the resulting value.
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return self.class.new(type,res_content)
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end
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# Concat the content of +vals+.
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def self.concat(*vals)
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# Compute the resulting type.
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types = vals.map {|v| v.type }
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if types.uniq.count <= 1 then
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res_type = types[0][types.size]
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else
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res_type = vals.map {|v| v.type }.to_type
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end
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# Concat the contents.
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+
res_content = []
|
299
|
+
content = width = 0
|
300
|
+
vals.each_with_index do |val,i|
|
301
|
+
content = val.content
|
302
|
+
width = types[i].width
|
303
|
+
if content.is_a?(BitString) then
|
304
|
+
count = 0
|
305
|
+
content.raw_content.each do |b|
|
306
|
+
res_content << b
|
307
|
+
count += 1
|
308
|
+
break if count == width
|
309
|
+
end
|
310
|
+
if count < width then
|
311
|
+
res_content.concat(res_content[-1] * (width-count))
|
312
|
+
end
|
313
|
+
else
|
314
|
+
width.times do |p|
|
315
|
+
res_content << content[p]
|
316
|
+
end
|
317
|
+
end
|
318
|
+
end
|
319
|
+
# Make a bit string from res_content.
|
320
|
+
res_content = BitString.new(res_content,:raw)
|
321
|
+
# Return the resulting value.
|
322
|
+
return vals[0].class.new(res_type,res_content)
|
323
|
+
end
|
324
|
+
|
325
|
+
|
48
326
|
# Conversion to an integer if possible.
|
49
327
|
def to_i
|
328
|
+
# if self.content.is_a?(BitString) then
|
329
|
+
# if self.type.signed? then
|
330
|
+
# return self.content.to_numeric_signed
|
331
|
+
# else
|
332
|
+
# return self.content.to_numeric
|
333
|
+
# end
|
334
|
+
# else
|
335
|
+
# return self.content.to_i
|
336
|
+
# end
|
50
337
|
return self.content.to_i
|
51
338
|
end
|
52
339
|
|
@@ -55,10 +342,67 @@ module HDLRuby
|
|
55
342
|
return self.content.to_f
|
56
343
|
end
|
57
344
|
|
345
|
+
# # Conversion to a BitString of the right size.
|
346
|
+
# def to_bstr
|
347
|
+
# # Ensure the content is a bit string.
|
348
|
+
# bstr = self.content
|
349
|
+
# if bstr.is_a?(Numeric) then
|
350
|
+
# # Handle negative values.
|
351
|
+
# bstr = 2**self.type.width + bstr if bstr < 0
|
352
|
+
# end
|
353
|
+
# bstr = BitString.new(bstr) unless bstr.is_a?(BitString)
|
354
|
+
# # Resize it if necessary.
|
355
|
+
# cwidth = self.content.width
|
356
|
+
# twidth = self.type.width
|
357
|
+
# if cwidth < twidth then
|
358
|
+
# # Its lenght must be extended.
|
359
|
+
# if self.type.signed? then
|
360
|
+
# return bstr.sext(twidth)
|
361
|
+
# else
|
362
|
+
# return bstr.zext(twidth)
|
363
|
+
# end
|
364
|
+
# elsif cwidth > twidth then
|
365
|
+
# # Its lenght must be reduced.
|
366
|
+
# return bstr.trunc(twidth)
|
367
|
+
# else
|
368
|
+
# return bstr.clone
|
369
|
+
# end
|
370
|
+
# end
|
371
|
+
|
58
372
|
# Coercion when operation from Ruby values.
|
59
373
|
def coerce(other)
|
60
374
|
return other,self.content
|
61
375
|
end
|
376
|
+
|
377
|
+
# Tell if the value is zero.
|
378
|
+
def zero?
|
379
|
+
return false unless @content
|
380
|
+
if content.is_a?(Numeric) then
|
381
|
+
return @content & (2**self.type.width-1) == 0
|
382
|
+
else
|
383
|
+
return !@content.raw_content[0..self.type.width-1].any?{|b| b!=0}
|
384
|
+
end
|
385
|
+
end
|
386
|
+
|
387
|
+
## Converts the value to a string of the right size.
|
388
|
+
def to_vstr
|
389
|
+
if self.content.is_a?(Numeric) then
|
390
|
+
if self.content >= 0 then
|
391
|
+
str = "0" + self.content.to_s(2)
|
392
|
+
else
|
393
|
+
str = (2**((-self.content).width+1) + self.content).to_s(2)
|
394
|
+
end
|
395
|
+
else
|
396
|
+
str = self.content.to_s
|
397
|
+
end
|
398
|
+
width = self.type.width
|
399
|
+
if str.size >= width then
|
400
|
+
return str[-width..-1]
|
401
|
+
else
|
402
|
+
return str[0] * (width-str.size) + str
|
403
|
+
end
|
404
|
+
end
|
405
|
+
|
62
406
|
end
|
63
407
|
|
64
408
|
end
|
@@ -194,7 +194,8 @@ module HDLRuby::Low
|
|
194
194
|
|
195
195
|
# Converts the system to Verilog code adding 'spc' spaces at the begining
|
196
196
|
# of each line.
|
197
|
-
|
197
|
+
# NOTE: if +vcdmodule+ is not nil add code for generating vcd file when simulating
|
198
|
+
def to_verilog(spc = 3, vcdmodule = nil)
|
198
199
|
code = "begin"
|
199
200
|
if self.name && !self.name.empty? then
|
200
201
|
vname = name_to_verilog(self.name)
|
@@ -229,6 +230,12 @@ module HDLRuby::Low
|
|
229
230
|
code << ";\n"
|
230
231
|
end
|
231
232
|
|
233
|
+
# Make the generation of vcd file if required.
|
234
|
+
if vcdmodule then
|
235
|
+
code << "\n#{" " * (spc+3)}$dumpfile(\"verilog_simulator.vcd\");"
|
236
|
+
code << "\n#{" " * (spc+3)}$dumpvars(0,#{vcdmodule});\n"
|
237
|
+
end
|
238
|
+
|
232
239
|
# Translate the block that finished scheduling.
|
233
240
|
block.each_statement do |statement|
|
234
241
|
# puts "#{statement.to_verilog(spc+3)}"
|
@@ -1864,7 +1871,9 @@ module HDLRuby::Low
|
|
1864
1871
|
|
1865
1872
|
|
1866
1873
|
# Converts the system to Verilog code.
|
1867
|
-
|
1874
|
+
# NOTE: if +vcd+ is true, generate verilog code whose simulation
|
1875
|
+
# produces a vcd file.
|
1876
|
+
def to_verilog(vcd = false)
|
1868
1877
|
# Detect the registers
|
1869
1878
|
HDLRuby::Low::VERILOG_REGS.clear
|
1870
1879
|
# The left values.
|
@@ -2122,8 +2131,12 @@ module HDLRuby::Low
|
|
2122
2131
|
end
|
2123
2132
|
|
2124
2133
|
# Translation of behavior part (always).
|
2134
|
+
$timebeh_shown = false
|
2125
2135
|
self.each_behavior do |behavior|
|
2136
|
+
timebeh = false
|
2126
2137
|
if behavior.block.is_a?(TimeBlock) then
|
2138
|
+
# Tell it is a time behavior for further processing.
|
2139
|
+
timebeh = true
|
2127
2140
|
# Extract and translate the TimeRepeat separately.
|
2128
2141
|
behavior.each_block_deep do |blk|
|
2129
2142
|
codeC << blk.repeat_to_verilog!
|
@@ -2157,7 +2170,12 @@ module HDLRuby::Low
|
|
2157
2170
|
codeC << " ) "
|
2158
2171
|
end
|
2159
2172
|
|
2160
|
-
|
2173
|
+
if vcd && timebeh && !$timebeh_shown then
|
2174
|
+
codeC << behavior.block.to_verilog(3,name_to_verilog(self.name))
|
2175
|
+
$timebeh_shown = true
|
2176
|
+
else
|
2177
|
+
codeC << behavior.block.to_verilog
|
2178
|
+
end
|
2161
2179
|
|
2162
2180
|
end
|
2163
2181
|
|
data/lib/HDLRuby/version.rb
CHANGED
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: HDLRuby
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 2.
|
4
|
+
version: 2.11.0
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Lovic Gauthier
|
8
8
|
autorequire:
|
9
9
|
bindir: exe
|
10
10
|
cert_chain: []
|
11
|
-
date: 2022-
|
11
|
+
date: 2022-09-23 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: bundler
|
@@ -46,7 +46,8 @@ email:
|
|
46
46
|
- lovic@ariake-nct.ac.jp
|
47
47
|
executables:
|
48
48
|
- hdrcc
|
49
|
-
extensions:
|
49
|
+
extensions:
|
50
|
+
- ext/hruby_sim/extconf.rb
|
50
51
|
extra_rdoc_files:
|
51
52
|
- README.md
|
52
53
|
files:
|
@@ -62,6 +63,19 @@ files:
|
|
62
63
|
- bin/console
|
63
64
|
- bin/setup
|
64
65
|
- exe/hdrcc
|
66
|
+
- ext/hruby_sim/Makefile_csim
|
67
|
+
- ext/hruby_sim/extconf.rb
|
68
|
+
- ext/hruby_sim/hruby_rcsim_build.c
|
69
|
+
- ext/hruby_sim/hruby_sim.h
|
70
|
+
- ext/hruby_sim/hruby_sim_calc.c
|
71
|
+
- ext/hruby_sim/hruby_sim_core.c
|
72
|
+
- ext/hruby_sim/hruby_sim_list.c
|
73
|
+
- ext/hruby_sim/hruby_sim_stack_calc.c
|
74
|
+
- ext/hruby_sim/hruby_sim_stack_calc.c.sav
|
75
|
+
- ext/hruby_sim/hruby_sim_tree_calc.c
|
76
|
+
- ext/hruby_sim/hruby_sim_vcd.c
|
77
|
+
- ext/hruby_sim/hruby_sim_vizualize.c
|
78
|
+
- ext/hruby_sim/hruby_value_pool.c
|
65
79
|
- lib/HDLRuby.rb
|
66
80
|
- lib/HDLRuby/alcc.rb
|
67
81
|
- lib/HDLRuby/backend/hruby_allocator.rb
|
@@ -88,6 +102,7 @@ files:
|
|
88
102
|
- lib/HDLRuby/hdr_samples/comparison_bench.rb
|
89
103
|
- lib/HDLRuby/hdr_samples/constant_in_function.rb
|
90
104
|
- lib/HDLRuby/hdr_samples/counter_bench.rb
|
105
|
+
- lib/HDLRuby/hdr_samples/counter_dff_bench.rb
|
91
106
|
- lib/HDLRuby/hdr_samples/dff.rb
|
92
107
|
- lib/HDLRuby/hdr_samples/dff_bench.rb
|
93
108
|
- lib/HDLRuby/hdr_samples/dff_counter.rb
|
@@ -128,6 +143,7 @@ files:
|
|
128
143
|
- lib/HDLRuby/hdr_samples/neural/sigmoid.rb
|
129
144
|
- lib/HDLRuby/hdr_samples/neural/z.rb
|
130
145
|
- lib/HDLRuby/hdr_samples/parseq_bench.rb
|
146
|
+
- lib/HDLRuby/hdr_samples/print_bench.rb
|
131
147
|
- lib/HDLRuby/hdr_samples/prog.obj
|
132
148
|
- lib/HDLRuby/hdr_samples/ram.rb
|
133
149
|
- lib/HDLRuby/hdr_samples/range_bench.rb
|
@@ -136,6 +152,7 @@ files:
|
|
136
152
|
- lib/HDLRuby/hdr_samples/rom_nest.rb
|
137
153
|
- lib/HDLRuby/hdr_samples/ruby_fir_hw.rb
|
138
154
|
- lib/HDLRuby/hdr_samples/seqpar_bench.rb
|
155
|
+
- lib/HDLRuby/hdr_samples/simple_counter_bench.rb
|
139
156
|
- lib/HDLRuby/hdr_samples/struct.rb
|
140
157
|
- lib/HDLRuby/hdr_samples/sumprod.rb
|
141
158
|
- lib/HDLRuby/hdr_samples/sw_encrypt_bench.rb
|
@@ -241,6 +258,7 @@ files:
|
|
241
258
|
- lib/HDLRuby/hruby_decorator.rb
|
242
259
|
- lib/HDLRuby/hruby_error.rb
|
243
260
|
- lib/HDLRuby/hruby_high.rb
|
261
|
+
- lib/HDLRuby/hruby_high_fullname.rb
|
244
262
|
- lib/HDLRuby/hruby_low.rb
|
245
263
|
- lib/HDLRuby/hruby_low2c.rb
|
246
264
|
- lib/HDLRuby/hruby_low2hdr.rb
|
@@ -265,6 +283,9 @@ files:
|
|
265
283
|
- lib/HDLRuby/hruby_low_without_outread.rb
|
266
284
|
- lib/HDLRuby/hruby_low_without_parinseq.rb
|
267
285
|
- lib/HDLRuby/hruby_low_without_select.rb
|
286
|
+
- lib/HDLRuby/hruby_rcsim.rb
|
287
|
+
- lib/HDLRuby/hruby_rsim.rb
|
288
|
+
- lib/HDLRuby/hruby_rsim_vcd.rb
|
268
289
|
- lib/HDLRuby/hruby_serializer.rb
|
269
290
|
- lib/HDLRuby/hruby_tools.rb
|
270
291
|
- lib/HDLRuby/hruby_types.rb
|
@@ -313,16 +334,6 @@ files:
|
|
313
334
|
- lib/HDLRuby/low_samples/with_seq.yaml
|
314
335
|
- lib/HDLRuby/low_samples/yaml2hdr.rb
|
315
336
|
- lib/HDLRuby/low_samples/yaml2vhd.rb
|
316
|
-
- lib/HDLRuby/sim/Makefile
|
317
|
-
- lib/HDLRuby/sim/hruby_sim.h
|
318
|
-
- lib/HDLRuby/sim/hruby_sim_calc.c
|
319
|
-
- lib/HDLRuby/sim/hruby_sim_core.c
|
320
|
-
- lib/HDLRuby/sim/hruby_sim_list.c
|
321
|
-
- lib/HDLRuby/sim/hruby_sim_stack_calc.c
|
322
|
-
- lib/HDLRuby/sim/hruby_sim_stack_calc.c.sav
|
323
|
-
- lib/HDLRuby/sim/hruby_sim_vcd.c
|
324
|
-
- lib/HDLRuby/sim/hruby_sim_vizualize.c
|
325
|
-
- lib/HDLRuby/sim/hruby_value_pool.c
|
326
337
|
- lib/HDLRuby/std/channel.rb
|
327
338
|
- lib/HDLRuby/std/clocks.rb
|
328
339
|
- lib/HDLRuby/std/connector.rb
|