HDLRuby 2.10.5 → 2.11.0

data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_value_pool.c

@@ -44,7 +44,9 @@ Value get_value() {
         }
     }
     /* Readjust the position in the pool and return the value. */
-    return pool_values[pool_pos++];
+    // return pool_values[pool_pos++];
+    Value res = pool_values[pool_pos++];
+    return res;
 }
 
 /** Get the current top value. */
@@ -59,6 +61,7 @@ Value get_top_value() {
 
 /** Frees the last value of the pool. */
 void free_value() {
+    if (pool_pos <= 0) { printf("Pool error!\n");exit(1);}
     if (pool_pos > 0) pool_pos--;
 }
 

data/lib/HDLRuby/hdr_samples/bstr_bench.rb

@@ -10,5 +10,7 @@ system :bstr_bench do
         !10.ns
         val <= -25
         !10.ns
+        val <= -32
+        !10.ns
     end
 end

data/lib/HDLRuby/hdr_samples/case_bench.rb

@@ -1,7 +1,7 @@
 # Test the comparison operators.
 
-# A benchmark for the if statement.
-system :if_bench do
+# A benchmark for the case statement.
+system :case_bench do
     [8].inner :x, :z
 
     par do

data/lib/HDLRuby/hdr_samples/counter_bench.rb

@@ -17,7 +17,6 @@ system :counter do
 
 
     par do
-        add.(q,0)
         hif(rst) { [cc,qq] <= 0 }
         helse do
             add.(q,1,[cc,qq])

data/lib/HDLRuby/hdr_samples/counter_dff_bench.rb

@@ -0,0 +1,46 @@
+# A simple D-FF
+system :dff do
+    input  :clk, :d
+    output q: 0
+
+    (q <= d).at(clk.posedge)
+end
+
+# A benchmark for the dff.
+system :dff_bench do
+    inner :clk
+    inner :d0, :q0, :d1, :q1
+
+    dff(:my_dff0).(clk,d0,q0)
+    dff(:my_dff1).(d0,d1,q1)
+
+    d0 <= ~q0
+    d1 <= ~q1
+
+    timed do
+        clk <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/dff_bench.rb

@@ -14,7 +14,7 @@ system :dff_bench do
     # dff(:my_dff).(d,clk,rst,q)
     dff(:my_dff).(d,clk)
     q <= my_dff.q
-    my_dff.clk <= clk
+    my_dff.rst <= rst
 
     timed do
         clk <= 0

data/lib/HDLRuby/hdr_samples/print_bench.rb

@@ -0,0 +1,62 @@
+##
+# A simple system for testing hw print and strings.
+######################################################
+
+system :with_print do
+    input  :clk, :rst
+    [4].output :counter
+
+    seq(clk.posedge) do
+        hif(rst) do
+            counter <= 0
+        end
+        helse do
+            counter <= counter + 1
+            hprint("In '#{__FILE__}' line #{__LINE__}: ")
+            hprint("Counter=", counter, "\n")
+        end
+    end
+end
+
+# A benchmark for the dff.
+system :with_print_bench do
+    inner :clk, :rst
+    [4].inner :counter
+
+    with_print(:my_print).(clk,rst,counter)
+
+    timed do
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        rst <= 0
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        rst <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+    end
+
+
+    # cur_system.properties[:pre_driver] = "drivers/hw_print.rb", :hw_print_generator
+end

data/lib/HDLRuby/hdr_samples/rom.rb

@@ -6,9 +6,11 @@ system :rom4_8 do
     [2..0].input :addr
     [7..0].output :data0,:data1,:data2
 
-    bit[7..0][0..7].constant content0: [0,1,2,3,4,5,6,7]
-    signed[7..0][-8].constant content1: [0,1,2,3,4,5,6,7]
-    typ[-8].constant content2: (8).times.to_a
+    bit[7..0][0..7].constant content0: [_00000000,_00000001,_00000010,_00000011,
+                                        _00000100,_00000101,_00000110,_00000111]
+    signed[7..0][-8].constant content1: [_sh00,_sh01,_sh02,_sh03,
+                                         _sh04,_sh05,_sh06,_sh07]
+    typ[-8].constant content2: (8).times.map {|i| i.to_expr.as(typ) }.reverse
 
     data0 <= content0[addr]
     data1 <= content1[addr]

data/lib/HDLRuby/hdr_samples/simple_counter_bench.rb

@@ -0,0 +1,43 @@
+# A benchmark for very simple counters.
+# Also test the use of ~ on the clock.
+system :counter_bench do
+    inner :clk, :rst
+    [3].inner :counter
+    [4].inner :counter2
+
+    par(clk.posedge) do
+        hif(rst) { counter <= 0 }
+        helse    { counter <= counter + 1 }
+    end
+
+    par(clk.posedge) do
+        hif(rst) { counter2 <= 0 }
+        helse    { counter2 <= counter2 + 1 }
+    end
+
+
+    timed do
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        rst <= 0
+        !10.ns
+        clk <= ~clk
+        rst <= 1
+        !10.ns
+        clk <= ~clk
+        !10.ns
+        clk <= ~clk
+        rst <= 0
+        !10.ns
+        clk <= ~clk
+        !10.ns
+        10.times do
+            clk <= ~clk
+            !10.ns
+            clk <= ~clk
+            !10.ns
+        end
+    end
+end

data/lib/HDLRuby/hdrcc.rb

@@ -363,10 +363,22 @@ $optparse = OptionParser.new do |opts|
     opts.on("--allocate=LOW,HIGH,WORD","Allocate signals to addresses") do |v|
         $options[:allocate] = v
     end
-    opts.on("-S", "--sim","Output in C format (simulator)") do |v|
+    opts.on("-S","--sim","Default simulator (hybrid C-Ruby)") do |v|
+        $options[:rcsim] = v
+        $options[:multiple] = v
+    end
+    opts.on("--csim","Standalone C-based simulator") do |v|
         $options[:clang] = v
         $options[:multiple] = v
-        $options[:sim] = v
+        $options[:csim] = v
+    end
+    opts.on("--rsim","Ruby-based simulator") do |v|
+        $options[:rsim] = v
+        $options[:multiple] = v
+    end
+    opts.on("--rcsim","Hybrid C-Ruby-based simulator") do |v|
+        $options[:rcsim] = v
+        $options[:multiple] = v
     end
     opts.on("--vcd", "The simulator will generate a vcd file") do |v|
         $options[:vcd] = v
@@ -556,12 +568,12 @@ end
 # Generate the result.
 # Get the top systemT.
 HDLRuby.show "#{Time.now}#{show_mem}"
-$top_system = $top_instance.to_low.systemT
+# Ruby simulation uses the HDLRuby::High tree, other the HDLRuby::Lowais used 
+$top_system = ($options[:rsim] || $options[:rcsim]) ? $top_instance.systemT : $top_instance.to_low.systemT
 $top_intance = nil # Free as much memory as possible.
 HDLRuby.show "##### Top system built #####"
 HDLRuby.show "#{Time.now}#{show_mem}"
 
-
 # # Apply the pre drivers if any.
 # Hdecorator.each_with_property(:pre_driver) do |obj, value|
 #     unless value.is_a?(Array) && value.size == 2 then
@@ -746,11 +758,12 @@ elsif $options[:clang] then
         $output << HDLRuby::Low::Low2C.main(top_system,
                                             *top_system.each_systemT_deep.to_a)
     end
-    if $options[:sim] then
+    if $options[:csim] then
         # Simulation mode, compile and exectute.
         # Path of the simulator core files.
-        # simdir = File.dirname(__FILE__) + "/sim/"
-        $simdir = $hdr_dir + "/sim/"
+        # $simdir = $hdr_dir + "sim/"
+        # puts "$hdr_dir=#{$hdr_dir}"
+        $simdir = $hdr_dir + "/../../ext/hruby_sim/"
         # Generate and execute the simulation commands.
         # Kernel.system("cp -n #{simdir}* #{$output}/; cd #{$output}/ ; make -s ; ./hruby_simulator")
         Dir.entries($simdir).each do |filename| 
@@ -826,7 +839,8 @@ elsif $options[:verilog] then
             # Open the file for current systemT
             outfile = File.open($name,"w")
             # Generate the Verilog code in to.
-            outfile << systemT.to_verilog
+            # outfile << systemT.to_verilog
+            outfile << systemT.to_verilog($options[:vcd])
             # Close the file.
             outfile.close
             # Clears the name.
@@ -838,6 +852,38 @@ elsif $options[:verilog] then
             $output << systemT.to_verilog
         end
     end
+elsif $options[:rsim] then
+    HDLRuby.show "Loading Ruby-level simulator..."
+    HDLRuby.show "#{Time.now}#{show_mem}"
+    # Ruby-level simulation.
+    require 'HDLRuby/hruby_rsim.rb'
+    # Is VCD output is required.
+    if $options[:vcd] then
+        # Yes
+        require "HDLRuby/hruby_rsim_vcd.rb"
+        vcdout = File.open($output+"/hruby_simulator.vcd","w")
+        $top_system.sim(vcdout)
+        vcdout.close
+    else
+        # No
+        $top_system.sim($stdout)
+    end
+    HDLRuby.show "End of Ruby-level simulation..."
+    HDLRuby.show "#{Time.now}#{show_mem}"
+elsif $options[:rcsim] then
+    HDLRuby.show "Building the hybrid C-Ruby-level simulator..."
+    HDLRuby.show "#{Time.now}#{show_mem}"
+    # C-Ruby-level simulation.
+    require 'HDLRuby/hruby_rcsim.rb'
+    # Merge the included from the top system.
+    $top_system.merge_included!
+    # Generate the C data structures.
+    $top_system.to_rcsim
+    HDLRuby.show "Executing the hybrid C-Ruby-level simulator..."
+    HDLRuby.show "#{Time.now}#{show_mem}"
+    HDLRuby::High.rcsim($top_system,"hruby_simulator",$output,$options[:vcd] && true)
+    HDLRuby.show "End of hybrid C-Ruby-level simulation..."
+    HDLRuby.show "#{Time.now}#{show_mem}"
 elsif $options[:vhdl] then
     # top_system = $top_instance.to_low.systemT
     # top_system = $top_system