HDLRuby 2.10.5 → 2.11.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/HDLRuby.gemspec +1 -0
- data/README.md +8 -4
- data/Rakefile +8 -0
- data/{lib/HDLRuby/sim/Makefile → ext/hruby_sim/Makefile_csim} +0 -0
- data/ext/hruby_sim/extconf.rb +13 -0
- data/ext/hruby_sim/hruby_rcsim_build.c +1188 -0
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim.h +255 -16
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_calc.c +310 -181
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_core.c +34 -17
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_list.c +0 -0
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_stack_calc.c +4 -1
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_stack_calc.c.sav +0 -0
- data/ext/hruby_sim/hruby_sim_tree_calc.c +375 -0
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_vcd.c +5 -5
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_sim_vizualize.c +2 -2
- data/{lib/HDLRuby/sim → ext/hruby_sim}/hruby_value_pool.c +4 -1
- data/lib/HDLRuby/hdr_samples/bstr_bench.rb +2 -0
- data/lib/HDLRuby/hdr_samples/case_bench.rb +2 -2
- data/lib/HDLRuby/hdr_samples/counter_bench.rb +0 -1
- data/lib/HDLRuby/hdr_samples/counter_dff_bench.rb +46 -0
- data/lib/HDLRuby/hdr_samples/dff_bench.rb +1 -1
- data/lib/HDLRuby/hdr_samples/print_bench.rb +62 -0
- data/lib/HDLRuby/hdr_samples/rom.rb +5 -3
- data/lib/HDLRuby/hdr_samples/simple_counter_bench.rb +43 -0
- data/lib/HDLRuby/hdrcc.rb +54 -8
- data/lib/HDLRuby/hruby_bstr.rb +1175 -917
- data/lib/HDLRuby/hruby_high.rb +200 -90
- data/lib/HDLRuby/hruby_high_fullname.rb +82 -0
- data/lib/HDLRuby/hruby_low.rb +41 -23
- data/lib/HDLRuby/hruby_low2c.rb +7 -0
- data/lib/HDLRuby/hruby_rcsim.rb +978 -0
- data/lib/HDLRuby/hruby_rsim.rb +1134 -0
- data/lib/HDLRuby/hruby_rsim_vcd.rb +322 -0
- data/lib/HDLRuby/hruby_values.rb +362 -18
- data/lib/HDLRuby/hruby_verilog.rb +21 -3
- data/lib/HDLRuby/version.rb +1 -1
- metadata +24 -13
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require "HDLRuby/hruby_rsim"
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##
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# Library for enhancing the Ruby simulator with VCD support
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#
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########################################################################
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module HDLRuby::High
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## Converts a HDLRuby name to a VCD name.
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def self.vcd_name(name)
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return name.to_s.gsub(/[^a-zA-Z0-9_$]/,"$")
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end
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##
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# Enhance the system type class with VCD support.
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class SystemT
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## Initializes the displayer for generating a vcd on +vcdout+
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def show_init(vcdout)
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# puts "show_init"
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@vcdout = vcdout
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# Show the date.
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@vcdout << "$date\n"
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@vcdout << " #{Time.now}\n"
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@vcdout << "$end\n"
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# Show the version.
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@vcdout << "$version\n"
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@vcdout << " #{VERSION}\n"
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@vcdout << "$end\n"
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# Show the comment section.
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@vcdout << "$comment\n"
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@vcdout << " Generated from HDLRuby Ruby simulator\n"
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@vcdout << "$end\n"
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# Show the time scale.
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@vcdout << "$timescale\n"
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@vcdout << " 1ps\n"
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@vcdout << "$end\n"
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# Displays the hierarchy of the variables.
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self.show_hierarchy(@vcdout)
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# Closes the header.
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@vcdout << "$enddefinitions $end\n"
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# Initializes the variables with their name.
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@vars_with_fullname = self.get_vars_with_fullname
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@vcdout << "$dumpvars\n"
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@vars_with_fullname.each_pair do |sig,fullname|
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if sig.f_value then
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@vcdout << " b#{sig.f_value.to_vstr} #{fullname}\n"
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else
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# @vcdout << " b#{"x"*sig.type.width} #{fullname}\n"
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@vcdout << " b#{"x"} #{fullname}\n"
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end
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end
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@vcdout << "$end\n"
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end
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## Gets the VCD variables with their long name.
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def get_vars_with_fullname(vars_with_fullname = {})
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# Adds the signals of the interface of the system.
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self.each_signal do |sig|
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vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
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end
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# Recurse on the scope.
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return self.scope.get_vars_with_fullname(vars_with_fullname)
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end
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## Shows the hierarchy of the variables.
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def show_hierarchy(vcdout)
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# puts "show_hierarchy for module #{self} (#{self.name})"
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# Shows the current level of hierarchy.
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vcdout << "$scope module #{HDLRuby::High.vcd_name(self.name)} $end\n"
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# Shows the interface signals.
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self.each_signal do |sig|
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# puts "showing signal #{HDLRuby::High.vcd_name(sig.fullname)}"
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vcdout << "$var wire #{sig.type.width} "
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vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
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vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
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end
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# Recurse on the scope.
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self.scope.show_hierarchy(vcdout)
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# Close the current level of hierarchy.
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vcdout << "$upscope $end\n"
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end
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## Displays the time.
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def show_time
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@vcdout << "##{@time}\n"
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end
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## Displays the value of signal +sig+.
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def show_signal(sig)
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@vcdout << "b#{sig.f_value.to_vstr} "
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@vcdout << "#{@vars_with_fullname[sig]}\n"
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end
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## Displays value +val+.
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# NOTE: for now displays on the standard output and NOT the vcd.
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def show_value(val)
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$stdout << val.to_vstr
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end
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## Displays string +str+.
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def show_string(str)
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$stdout << str.to_s
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end
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end
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##
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# Enhance the scope class with VCD support.
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class Scope
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## Shows the hierarchy of the variables.
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def show_hierarchy(vcdout)
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# puts "show_hierarchy for scope=#{self}"
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# Shows the current level of hierarchy if there is a name.
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ismodule = false
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if !self.name.empty? && !self.parent.is_a?(SystemT) then
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vcdout << "$scope module #{HDLRuby::High.vcd_name(self.fullname)} $end\n"
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ismodule = true
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end
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# Shows the inner signals.
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self.each_inner do |sig|
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# puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
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vcdout << "$var wire #{sig.type.width} "
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vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
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vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
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end
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# Recurse on the behaviors' blocks
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self.each_behavior do |beh|
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beh.block.show_hierarchy(vcdout)
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end
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# Recurse on the systemI's Eigen system.
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self.each_systemI do |sys|
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sys.systemT.show_hierarchy(vcdout)
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end
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# Recurse on the subscopes.
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self.each_scope do |scope|
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scope.show_hierarchy(vcdout)
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end
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# Close the current level of hierarchy if there is a name.
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if ismodule then
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vcdout << "$upscope $end\n"
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end
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end
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## Gets the VCD variables with their long name.
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def get_vars_with_fullname(vars_with_fullname = {})
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# Adds the inner signals.
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self.each_inner do |sig|
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vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
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end
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# Recurse on the behaviors' blocks
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self.each_behavior do |beh|
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beh.block.get_vars_with_fullname(vars_with_fullname)
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end
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# Recurse on the systemI's Eigen system.
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self.each_systemI do |sys|
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sys.systemT.get_vars_with_fullname(vars_with_fullname)
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end
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# Recurse on the subscopes.
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self.each_scope do |scope|
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scope.get_vars_with_fullname(vars_with_fullname)
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end
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return vars_with_fullname
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end
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end
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##
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# Enhance the Transmit class with VCD support.
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class Transmit
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## Shows the hierarchy of the variables.
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def show_hierarchy(vcdout)
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# By default: nothing to do.
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end
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## Gets the VCD variables with their long name.
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def get_vars_with_fullname(vars_with_fullname = {})
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# By default: nothing to do
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end
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end
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##
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# Enhance the TimeWait class with VCD support.
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class TimeWait
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## Shows the hierarchy of the variables.
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def show_hierarchy(vcdout)
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# By default: nothing to do.
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end
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## Gets the VCD variables with their long name.
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def get_vars_with_fullname(vars_with_fullname = {})
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# By default: nothing to do
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end
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end
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##
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# Enhance the Print class with VCD support.
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class Print
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## Shows the hierarchy of the variables.
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def show_hierarchy(vcdout)
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# By default: nothing to do.
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end
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## Gets the VCD variables with their long name.
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def get_vars_with_fullname(vars_with_fullname = {})
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# By default: nothing to do
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end
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end
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## Module adding show_hierarchyto block objects.
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module BlockHierarchy
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## Shows the hierarchy of the variables.
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def show_hierarchy(vcdout)
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# puts "show_hierarchy for block=#{self}"
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# Shows the current level of hierarchy if there is a name.
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ismodule = false
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unless self.name.empty?
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vcdout << "$scope module #{HDLRuby::High.vcd_name(self.name)} $end\n"
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ismodule = true
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end
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# Shows the inner signals.
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self.each_inner do |sig|
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# puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
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vcdout << "$var wire #{sig.type.width} "
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vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
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vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
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end
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# Recurse on the statements
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self.each_statement do |stmnt|
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stmnt.show_hierarchy(vcdout)
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end
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# Close the current level of hierarchy if there is a name.
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if ismodule then
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vcdout << "$upscope $end\n"
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end
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end
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## Gets the VCD variables with their long name.
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def get_vars_with_fullname(vars_with_fullname = {})
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# Adds the inner signals.
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self.each_inner do |sig|
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vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
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end
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# Recurse on the statements.
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self.each_statement do |stmnt|
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stmnt.get_vars_with_fullname(vars_with_fullname)
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end
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return vars_with_fullname
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end
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end
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##
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# Enhance the block class with VCD support.
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class Block
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include HDLRuby::High::BlockHierarchy
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end
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##
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# Enhance the block class with VCD support.
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class TimeBlock
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include HDLRuby::High::BlockHierarchy
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end
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##
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# Enhance the if class with VCD support.
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class If
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## Shows the hierarchy of the variables.
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def show_hierarchy(vcdout)
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# Recurse on the yes.
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self.yes.show_hierarchy(vcdout)
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# Recurse on the noifs.
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self.each_noif do |cond,stmnt|
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stmnt.show_hierarchy(vcdout)
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end
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# Recure on the no if any.
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self.no.show_hierarchy(vcdout) if self.no
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end
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## Gets the VCD variables with their long name.
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def get_vars_with_fullname(vars_with_fullname = {})
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# Recurse on the yes.
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self.yes.get_vars_with_fullname(vars_with_fullname)
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# Recurse on the noifs.
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self.each_noif do |cond,stmnt|
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stmnt.get_vars_with_fullname(vars_with_fullname)
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end
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# Recure on the no if any.
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self.no.get_vars_with_fullname(vars_with_fullname) if self.no
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return vars_with_fullname
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end
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end
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##
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# Enhance the Case class with VCD support.
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class Case
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## Shows the hierarchy of the variables.
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def show_hierarchy(vcdout)
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# Recurse on each when.
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self.each_when do |w|
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w.statement.show_hierarchy(vcdout)
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end
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# Recurse on the default if any.
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self.default.show_hierarchy(vcdout)
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end
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## Gets the VCD variables with their long name.
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def get_vars_with_fullname(vars_with_fullname = {})
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# Recurse on each when.
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self.each_when do |w|
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w.statement.get_vars_with_fullname(vars_with_fullname)
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end
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# Recurse on the default if any.
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self.default.get_vars_with_fullname(vars_with_fullname)
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return vars_with_fullname
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end
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end
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end
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