HDLRuby 3.9.0 → 3.9.3

data/lib/HDLRuby/std/hruby_enum.rb

@@ -557,7 +557,7 @@ module HDLRuby::High::Std
       if !ruby_block then
         return HEnumeratorWrapper.new(self,:hreverse_each,*args)
       end
-      return self.to_a.reverse_each(&ruby_block)
+      return self.hto_a.reverse_each(&ruby_block)
     end
 
     # HW implementation of the Ruby slice_after.
@@ -786,7 +786,7 @@ module HDLRuby::High::Std
       if !ruby_block then
         return HEnumeratorWrapper.new(self,:heach_range)
       end
-      return self.to_a.each_range(rng,&ruby_block)
+      return self.hto_a.each_range(rng,&ruby_block)
     end
 
     # Iterates with an index.
@@ -839,18 +839,26 @@ module HDLRuby::High::Std
       return self unless ruby_block
       # Create a namespace.
       base_block = ruby_block
+      caught = false
       ruby_block = proc do |*args| 
         HDLRuby::High.top_user.sub do
-          base_block.call(*args)
+          caught = true
+          catch(:HDLRubyThrow) do
+            base_block.call(*args)
+            caught = false
+          end
         end
+        throw(:HDLRubyThrow) if caught
       end
       # Iterate.
-      if self.respond_to?(:[]) then
-        return self.size.times do |i|
-          ruby_block.call(self[i])
+      catch(:HDLRubyThrow) do
+        if self.respond_to?(:[]) then
+          return self.size.htimes do |i|
+            ruby_block.call(self[i])
+          end
+        else
+          return self.hto_a.each(&ruby_block)
         end
-      else
-        return self.hto_a.each(&ruby_block)
       end
     end
 
@@ -995,10 +1003,16 @@ module HDLRuby::High::Std
       # A block? Apply it on each element.
       # Create a namespace.
       base_block = ruby_block
+      caught = false
       ruby_block = proc do |*args|
         HDLRuby::High.top_user.sub do
-          base_block.call(*args)
+          caught = true
+          catch(:HDLRubyThrow) do
+            base_block.call(*args)
+            caught = false
+          end
         end
+        throw(:HDLRubyThrow) if caught
       end
       # Iterate.
       self.type.range.heach do |i|
@@ -1101,10 +1115,18 @@ module HDLRuby::High::Std
         return HEnumeratorWrapper.new(self)
       end
       # self.each { |e| HDLRuby::High.top_user.sub { ruby_block.call(e) } }
-      self.each do |e|
-        HDLRuby::High.top_user.sub do
-          # HDLRuby::High.top_user.instance_exec(e,&ruby_block)
-          ruby_block.call(e)
+      catch(:HDLRubyThrow) do
+        caught = false
+        self.each do |e|
+          HDLRuby::High.top_user.sub do
+            caught = true
+            catch(:HDLRubyThrow) do
+              # HDLRuby::High.top_user.instance_exec(e,&ruby_block)
+              ruby_block.call(e)
+              caught = false
+            end
+          end
+          throw(:HDLRubyThrow) if caught
         end
       end
     end
@@ -1134,10 +1156,16 @@ module HDLRuby::High::Std
         # A block is given, iterate on each element of the range
         # Create a namespace.
         base_block = ruby_block
+        caught = false
         ruby_block = proc do |*args|
           HDLRuby::High.top_user.sub do
-            base_block.call(*args)
+            caught = true
+            catch(:HDLRubyThrow) do
+              base_block.call(*args)
+              caught = false
+            end
           end
+          throw(:HDLRubyThrow) if caught
         end
         # converted to values of the right type.
         if first.is_a?(Value) then
@@ -1147,21 +1175,25 @@ module HDLRuby::High::Std
         end
         first = self.first.to_i
         last = self.last.to_i
-        if first <= last then
-          (first..last).each do |i|
-            ruby_block.call(i.as(typ))
-          end
-        else
-          (last..first).reverse_each do |i|
-            ruby_block.call(i.as(typ))
+        catch(:HDLRubyThrow) do
+          if first <= last then
+            (first..last).each do |i|
+              ruby_block.call(i.as(typ))
+            end
+          else
+            (last..first).reverse_each do |i|
+              ruby_block.call(i.as(typ))
+            end
           end
         end
       else
         # Other range cases.
-        if self.first <= self.last then
-          return self.each(&ruby_block)
-        else
-          return (self.last..self.first).reverse_each(&ruby_block)
+        catch(:HDLRubyThrow) do
+          if self.first <= self.last then
+            return self.each(&ruby_block)
+          else
+            return (self.last..self.first).reverse_each(&ruby_block)
+          end
         end
       end
     end
@@ -1176,13 +1208,57 @@ module HDLRuby::High::Std
     # Enhance the Integer class with sequencer iterations.
 
     # HW times iteration.
-    alias_method :htimes, :times
+    # alias_method :htimes, :times
+    def htimes(&ruby_block)
+      return HEnumeratorWrapper.new(self,:htimes) unless ruby_block
+      self.times do |i|
+        ruby_block.call(i)
+      end
+    end
 
     # HW upto iteration.
-    alias_method :hupto, :upto
+    # alias_method :hupto, :upto
+    def hupto(val,&ruby_block)
+      return HEnumeratorWrapper.new(self,:hupto) unless ruby_block
+      self.upto(val) do |i|
+        ruby_block.call(i)
+      end
+    end
 
     # HW downto iteration.
-    alias_method :hdownto, :downto
+    # alias_method :hdownto, :downto
+    def hdownto(val,&ruby_block)
+      return HEnumeratorWrapper.new(self,:hdownto) unless ruby_block
+      self.downto(val) do |i|
+        ruby_block.call(i)
+      end
+    end
+  end
+
+
+  # Handle the enumeration exits.
+  module HEnumeratorExit
+    # Parallel break.
+    def hbreak
+      throw(:"HDLRubyThrow")
+    end
+
+    # Parallel continue.
+    def hcontinue
+      raise("hcontinue not implemented yet.")
+    end
+  end
+
+
+  class HDLRuby::High::Scope
+    include HEnumeratorExit
+  end
+
+  module HDLRuby::High::HBlock
+    # Also adds the methods of HEnumerable.
+    HEnumeratorExit.instance_methods.each do |meth|
+      define_method(meth,HEnumeratorExit.instance_method(meth))
+    end
   end
 
 end

data/lib/HDLRuby/std/sequencer.rb

@@ -355,10 +355,24 @@ module HDLRuby::High::Std
         def make_inners(typ,*names)
             res = nil
             if SequencerT.current then
-                unames = names.map {|name| HDLRuby.uniq_name(name) }
-                res = HDLRuby::High.cur_scope.make_inners(typ, *unames)
-                names.zip(unames).each do |name,uname|
+                # unames = names.map {|name| HDLRuby.uniq_name(name) }
+                # res = HDLRuby::High.cur_scope.make_inners(typ, *unames)
+                # names.zip(unames).each do |name,uname|
+                #     HDLRuby::High.space_reg(name) { send(uname) }
+                # end
+                names.each do |name|
+                  if name.respond_to?(:to_sym) then
+                    uname = HDLRuby.uniq_name(name)
+                    res = HDLRuby::High.cur_scope.make_inners(typ, uname)
                     HDLRuby::High.space_reg(name) { send(uname) }
+                  elsif name.is_a?(Hash) then
+                    name.each do |key,value|
+                      uname = HDLRuby.uniq_name(key)
+                      res = HDLRuby::High.cur_scope.make_inners(typ,
+                                              uname => value)
+                      HDLRuby::High.space_reg(key) { send(uname) }
+                    end
+                  end
                 end
             else
                 # self.old_make_inners(typ,*names)

data/lib/HDLRuby/verilog_hruby.rb

@@ -5,6 +5,14 @@ require "HDLRuby/verilog_parser"
 
 module VerilogTools
 
+  # Table for fixing the reserved names in HDLRuby.
+  RESERVED_FIX = {
+    "load" => "_load",
+    "select" => "_select",
+    "in"   => "_in",
+    "sub"   => "_sub"
+  }
+
   # The possible levels in HDLRuby generation.
   HDLRubyLevels  = [ :top, :system, :hdef, :<=, :seq, :par, :timed, :expr ]
   NoEventLevels  = [ :hdef, :<=, :seq, :par, :timed ]
@@ -111,7 +119,10 @@ module VerilogTools
       # HDLRuby names cannot start with a $ or a capital letter.
       # To fix that add an "_", but then to avoid confusion, also
       # convert starting "_" to "__" if any.
+      name = "_Z" if name == "Z" # _Z mean something in HDLRuby
       return "_" + name
+    elsif RESERVED_FIX.key?(name) then
+      return RESERVED_FIX[name]
     else
       return name
     end
@@ -432,17 +443,49 @@ module VerilogTools
 
 
     TO_HDLRuby[:output_declaration] = lambda do |ast,state|
-      # Ignore the OUTPUTTYPE not used in HDLRuby
+      # # Ignore the OUTPUTTYPE not used in HDLRuby
+      # # Get the sign if any.
+      # sign = ast[1]
+      # sign = "" unless sign
+      # # Get the range.
+      # range = ast[2]
+      # range = range ? range.to_HDLRuby(state) + "." : ""
+      # # Get the names.
+      # names = ast[3].to_HDLRuby(state)
+      # # Genereate the resulting declaration.
+      # return state.indent + sign + range +"output " + names + "\n"
+
       # Get the sign if any.
       sign = ast[1]
       sign = "" unless sign
       # Get the range.
       range = ast[2]
       range = range ? range.to_HDLRuby(state) + "." : ""
-      # Get the names.
-      names = ast[3].to_HDLRuby(state)
-      # Genereate the resulting declaration.
-      return state.indent + sign + range +"output " + names + "\n"
+      res_txt = ""
+      ast[3][0].each do |reg|
+        if reg[0].type == :name_of_memory then
+          # It is a memory, it must be declared.
+          sign = "bit" if sign.empty?
+          res_txt += state.indent + sign + range[0..-2] + 
+            "[" + reg[1].to_HDLRuby(state) + ".." + 
+            reg[2].to_HDLRuby(state)  + "].output :" +
+            reg[0].to_HDLRuby(state) + "\n"
+        else
+          # It is a standard register, it may override a previous
+          # declaration and in such case can be omitted in HDLRuby.
+          n = reg[0].to_HDLRuby(state)
+          v = reg[1]
+          v = v.to_HDLRuby(state) if v
+          unless state.port_names.include?(n) then
+            if v then
+              res_txt += state.indent + sign + range + "output " + n + ": #{v}\n"
+            else
+              res_txt += state.indent + sign + range + "output :" + n + "\n"
+            end
+          end
+        end
+      end
+      return res_txt
     end
 
 
@@ -492,15 +535,6 @@ module VerilogTools
       # Get the range.
       range = ast[1]
       range = range ? range.to_HDLRuby(state) + "." : ""
-      # # Get the name.
-      # names = ast[2].to_HDLRuby(state)
-      # if names.empty? then
-      #   # There is actually no new inner.
-      #   return ""
-      # end
-      # Registers can also be memory, so treat each name independantly.
-      # # Genereate the resulting declaration.
-      # return state.indent + sign + range +"inner " + names + "\n"
       res_txt = ""
       ast[2][0].each do |reg|
         if reg[0].type == :name_of_memory then
@@ -514,12 +548,18 @@ module VerilogTools
           # It is a standard register, it may override a previous
           # declaration and in such case can be omitted in HDLRuby.
           n = reg[0].to_HDLRuby(state)
+          v = reg[1]
+          v = v.to_HDLRuby(state) if v
           unless state.port_names.include?(n) then
-            res_txt += state.indent + sign + range + "inner :" + n + "\n"
+            if v then
+              res_txt += state.indent + sign + range + "inner " + n + ": #{v}\n"
+            else
+              res_txt += state.indent + sign + range + "inner :" + n + "\n"
+            end
           end
         end
       end
-        return res_txt
+      return res_txt
     end
 
 
@@ -771,7 +811,7 @@ module VerilogTools
             if !content_txt.empty? then
               # There is a content, add it to the list.
               seq_par_txt[-1][1] = content_txt
-              content_txt == ""
+              content_txt = ""
             end
             # Add a new block.
             seq_par_txt << [seq_par, ""]
@@ -831,7 +871,7 @@ module VerilogTools
         # Generate the case items.
         case_txt += ast[2].map do |item|
           res_txt = ""
-          if item[0] then
+          if item[0] != "default" then
             # hwhen case.
             res_txt += indent + "hwhen(" 
             res_txt += item[0].map {|e| e.to_HDLRuby(state) }.join(",")
@@ -868,8 +908,8 @@ module VerilogTools
 
 
     TO_HDLRuby[:assignment] = lambda do |ast,state|
-      return state.indent + ast[0].to_HDLRuby(state) + " <= " +
-        ast[1].to_HDLRuby(state) + "\n"
+      return state.indent + ast[0].to_HDLRuby(state) + " <= (" +
+        ast[1].to_HDLRuby(state) + ")\n"
     end
 
 
@@ -880,8 +920,8 @@ module VerilogTools
       if ast[1] then
         raise "Internal error: unsupported delay or event in assingment yet."
       end
-      return state.indent + ast[0].to_HDLRuby(state)  + " <= " +
-        ast[2].to_HDLRuby(state)  + "\n"
+      return state.indent + ast[0].to_HDLRuby(state)  + " <= (" +
+        ast[2].to_HDLRuby(state)  + ")\n"
     end
 
     TO_HDLRuby[:non_blocking_assignment] = TO_HDLRuby[:blocking_assignment]
@@ -1001,10 +1041,12 @@ module VerilogTools
           return VerilogTools.operator_to_HDLRuby(op) + primary_txt
         when "&", "|", "^", "^|"
           return primary_txt + 
-            ".each.reduce(:" + VerilogTools.operator_to_HDLRuby(op) + ")"
+            # ".heach.reduce(:" + VerilogTools.operator_to_HDLRuby(op) + ")"
+            "." + VerilogTools.operator_to_HDLRuby(op) + "()"
         when "~&", "~|", "~^"
           return "~" + primary_txt + 
-            ".each.reduce(:" + VerilogTools.operator_to_HDLRuby(op[1]) +")"
+            # ".heach.reduce(:" + VerilogTools.operator_to_HDLRuby(op[1]) +")"
+            "." + VerilogTools.operator_to_HDLRuby(op) + "()"
         else
           raise "Internal error: unknown unary operator #{op}"
         end
@@ -1056,16 +1098,16 @@ module VerilogTools
       case base
       when "'b"
         # Binary encoding.
-        return "_#{number0}b#{number1}"
+        return "_u#{number0}b#{number1}"
       when "'o"
         # Octal encoding.
-        return "_#{number0}o#{number1}"
+        return "_u#{number0}o#{number1}"
       when "'d"
         # Decimal encoding.
-        return "_#{number0}d#{number1}"
+        return "_s#{number0}d#{number1}"
       when "'h"
         # Hexadecimal encoding.
-        return "_#{number0}h#{number1}"
+        return "_u#{number0}h#{number1}"
       when ""
         # Simple number.
         return number0

data/lib/HDLRuby/verilog_parser.rb

@@ -739,6 +739,7 @@ module VerilogTools
     EVENT_TOK      = "event"
     DEFPARAM_TOK   = "defparam"
     PARAMETER_TOK  = "parameter"
+    LOCALPARAM_TOK = "localparam"
     SCALARED_TOK   = "scalared"
     VECTORED_TOK   = "vectored"
 
@@ -979,7 +980,7 @@ module VerilogTools
     REAL_REX       = /\G#{S}(real)/
     EVENT_REX      = /\G#{S}(event)/
     DEFPARAM_REX   = /\G#{S}(defparam)/
-    PARAMETER_REX  = /\G#{S}(parameter)/
+    PARAMETER_REX  = /\G#{S}(parameter|localparam)/
     SCALARED_REX   = /\G#{S}(scalared)/
     VECTORED_REX   = /\G#{S}(vectored)/
 
@@ -1272,8 +1273,8 @@ module VerilogTools
                           EQUAL_EQUAL_EQUAL_TOK, NOT_EQUAL_EQUAL_TOK ]
     EQUAL_OPERATOR_REX = /\G#{S}(#{EQUAL_OPERATOR_TOKS.join("|")})/
 
-    COMPARISON_OPERATOR_TOKS = [ INFERIOR_TOK, SUPERIOR_TOK,
-                                 INFERIOR_EQUAL_TOK, SUPERIOR_EQUAL_TOK ]
+    COMPARISON_OPERATOR_TOKS = [ INFERIOR_EQUAL_TOK, SUPERIOR_EQUAL_TOK,
+                                 INFERIOR_TOK, SUPERIOR_TOK ]
     COMPARISON_OPERATOR_REX = /\G#{S}(#{COMPARISON_OPERATOR_TOKS.join("|")})/
 
     SHIFT_OPERATOR_TOKS = [ LEFT_SHIFT_TOK,  RIGHT_SHIFT_TOK, 
@@ -1515,7 +1516,7 @@ ___
       self.parse_error("opening parenthesis expected") unless self.get_token(OPEN_PAR_REX)
       self.parse_error("parameter expected") unless self.get_token(PARAMETER_REX)
       list_of_param_assignments = self.list_of_param_assignments_parse
-      self.parse_error("paramter assignment expected") unless list_of_param_assignments
+      self.parse_error("parameter assignment expected") unless list_of_param_assignments
       self.parse_error("closing parenthesis expected") unless self.get_token(CLOSE_PAR_REX)
       return pre_parameter_declaration_hook(list_of_param_assignments)
     end
@@ -1766,7 +1767,7 @@ ___
       name = self.name_of_variable_parse
       const0, const1 = nil, nil
       if self.get_token(OPEN_BRA_REX) then
-        const0 = self.constant_expression_prase
+        const0 = self.constant_expression_parse
         self.parse_error("constant expression expected") unless const0
         if self.get_token(COLON_REX) then
           const1 = self.constant_expression_parse
@@ -2622,10 +2623,10 @@ ___
     # Auth: Verilog HDL also supports output wire, reg and so on as well
     # as signed, so modified the rule as follows:
     # <output_declaration>
-    # ::= output OUTPUTTYPE? SIGNED? <range>? <list_of_variables> ;
+    # ::= output OUTPUTTYPE? SIGNED? <range>? <list_of_register_variables> ;
     RULES[:output_declaration] = <<-___
 <output_declaration>
-	::= output OUTPUTTYPE? SIGNED? <range>? <list_of_variables> ;
+	::= output OUTPUTTYPE? SIGNED? <range>? <list_of_register_variables> ;
 ___
 
     ORIGIN_RULES[:output_declaration] = <<-___
@@ -2641,7 +2642,7 @@ ___
       type = self.get_token(OUTPUTTYPE_REX)
       sign = self.get_token(SIGNED_REX)
       range = self.range_parse
-      list_of_variables = self.list_of_variables_parse
+      list_of_variables = self.list_of_register_variables_parse
       # list_of_variables = self.list_of_output_variables_parse
       # # Auth: semicolon included in list_of_output_variables!
       self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX)
@@ -2711,7 +2712,7 @@ ___
           expandrange = self.expandrange_parse
           delay = self.delay_parse
           list_of_variables = self.list_of_variables_parse
-          self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX)
+          self.parse_error("semicolon expected HERE #1") unless self.get_token(SEMICOLON_REX)
           return net_declaration_hook(nettype,sign,expandrange,delay,
                                       list_of_variables)
         else
@@ -2719,7 +2720,7 @@ ___
           expandrange = self.expandrange_parse
           delay = self.delay_parse
           list_of_assignments = self.list_of_assignments_parse
-          self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX)
+          self.parse_error("semicolon expected HERE #2") unless self.get_token(SEMICOLON_REX)
           return net_declaration_hook(nettype,sign,expandrange,delay,
                                       list_of_assignments)
         end
@@ -2732,7 +2733,7 @@ ___
         expandrange = self.expandrange_parse
         delay = self.delay_parse
         list_of_variables = self.list_of_variables_parse
-        self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX)
+        self.parse_error("semicolon expected HERE #3") unless self.get_token(SEMICOLON_REX)
         return net_declaration_hook(charge_strength,sign,expandrange,delay,
                                     list_of_variables)
       end
@@ -2828,7 +2829,7 @@ ___
     # ::= reg SIGNED? <range>? <list_of_register_variables> ;
     RULES[:reg_declaration] = <<-___
 <reg_declaration>
-	::= reg SIGNED? <range>? <list_of_register_variables> ;
+	::= reg SIGNED? <range>? <list_of_register_variables>;
 ___
 
     ORIGIN_RULES[:reg_declaration] = <<-___
@@ -2844,7 +2845,7 @@ ___
       sign = self.get_token(SIGNED_REX)
       range = self.range_parse
       list_of_register_variables = self.list_of_register_variables_parse
-      self.parse_error("semicolon exptected") unless self.get_token(SEMICOLON_REX)
+      self.parse_error("semicolon exptected HERE #4") unless self.get_token(SEMICOLON_REX)
       return reg_declaration_hook(sign,range,list_of_register_variables)
     end
 
@@ -2860,11 +2861,16 @@ ___
 
     def time_declaration_parse
       # puts "time_declaration_parse"
+      parse_state = self.state
       unless self.get_token(TIME_REX) then
         return nil
       end
       list_of_register_variables = self.list_of_register_variables_parse
-      self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX)
+      # self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX)
+      unless self.get_token(SEMICOLON_REX) then
+        self.state = parse_state
+        return nil
+      end
       return time_declaration_hook(list_of_register_variables)
     end
 
@@ -2952,7 +2958,7 @@ ___
         drive_strength = self.drive_strength_parse
         delay = self.delay_parse
         list_of_assignments = self.list_of_assignments_parse
-        self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX)
+        self.parse_error("semicolon expected HERE #5") unless self.get_token(SEMICOLON_REX)
         return continuous_assignment_hook(ASSIGN_TOK,
                                           drive_strength,nil,
                                           delay,list_of_assignments)
@@ -2963,7 +2969,7 @@ ___
         expandrange = self.expandrange_parse
         delay = self.delay_parse
         list_of_assignments = self.list_of_assignments_parse
-        self.parse_error("semicolon expected") unless self.get_token(SEMICOLON_REX)
+        self.parse_error("semicolon expected HERE #6") unless self.get_token(SEMICOLON_REX)
         return continuous_assignment_hook(nettype,
                                           drive_strength,expandrange,
                                           delay,list_of_assignments)
@@ -3059,7 +3065,14 @@ ___
     end
 
 
+    # Auth: there seems ot be a mistake in this rule: 
+    # initial assignments are also possible.
     RULES[:register_variable] = <<-___
+<register_variable>
+	::= <name_of_register> [ = <expression> ]
+	||= <name_of_memory> [ <constant_expression> : <constant_expression> ]
+___
+    ORIGIN_RULES[:register_variable] = <<-___
 <register_variable>
 	::= <name_of_register>
 	||= <name_of_memory> [ <constant_expression> : <constant_expression> ]
@@ -3081,7 +3094,14 @@ ___
       else
         self.state = parse_state
         name_of_register = self.name_of_register_parse
-        return register_variable_hook(name_of_register,nil,nil)
+        # Handle the initialization if any.
+        if self.get_token(EQUAL_REX) then
+          expression = self.expression_parse
+          self.parse_error("expression expected") unless expression
+        else
+          expression = nil
+        end
+        return register_variable_hook(name_of_register,expression,nil)
       end
     end
 
@@ -4371,7 +4391,7 @@ ___
     # <task_enable>
     # ::= <name_of_task> ;
     # ||= <name_of_task ( <expression <,<expression>>* ) ;
-    ORIGIN_RULES[:task_enable] = <<-___
+    RULES[:task_enable] = <<-___
 <task_enable>
 	::= <name_of_task> ;
 	||= <name_of_task> ( <expression> <,<expression>>* ) ;

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "3.9.0"
+  VERSION = "3.9.3"
 end

metadata

@@ -1,7 +1,7 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 3.9.0
+  version: 3.9.3
 platform: ruby
 authors:
 - Lovic Gauthier
@@ -255,6 +255,8 @@ files:
 - lib/HDLRuby/hdr_samples/with_terminate.rb
 - lib/HDLRuby/hdr_samples/with_to_a.rb
 - lib/HDLRuby/hdr_samples/with_to_array.rb
+- lib/HDLRuby/hdr_samples/with_to_svg.rb
+- lib/HDLRuby/hdr_samples/with_unary_reduction.rb
 - lib/HDLRuby/hdr_samples/with_val_control.rb
 - lib/HDLRuby/hdr_samples/with_values.rb
 - lib/HDLRuby/hdr_samples/with_verilog.rb
@@ -340,6 +342,7 @@ files:
 - lib/HDLRuby/hruby_low_mutable.rb
 - lib/HDLRuby/hruby_low_resolve.rb
 - lib/HDLRuby/hruby_low_skeleton.rb
+- lib/HDLRuby/hruby_low_split_signals.rb
 - lib/HDLRuby/hruby_low_with_bool.rb
 - lib/HDLRuby/hruby_low_with_port.rb
 - lib/HDLRuby/hruby_low_with_var.rb
@@ -499,7 +502,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.6.9
+rubygems_version: 3.7.2
 specification_version: 4
 summary: HDLRuby is a library for describing and simulating digital electronic systems.
 test_files: []