HDLRuby 3.9.0 → 3.9.3

data/lib/HDLRuby/hruby_viz.rb

@@ -1,4 +1,4 @@
-# An IC netlist mrdel and SVG-based vizualizer for HDLRuby 
+# An IC netlist model and SVG-based vizualizer for HDLRuby 
 
 # require 'stackprof'
 
@@ -12,6 +12,21 @@ module HDLRuby::Viz
   DOWN    = 8
   BLOCKED = 16
 
+  # Get the base name of the port.
+  def self.port_base_name(name)
+    return name.sub(/\[.*\]\z/,"")
+  end
+
+  # Get the bit part of the port name if any.
+  def self.port_bit_name(name)
+    return name.match(/\[.*\]\z/)[0]
+  end
+
+  # Tell if a port name is for a sub port.
+  def self.port_bit_name?(name)
+    return name =~ /\[.*\]\z/
+  end
+
 
   # An IC Port
   class Port
@@ -110,6 +125,9 @@ module HDLRuby::Viz
 
     # Give the size of the IC in number of statements.
     def number_statements
+      if self.type == :instance then
+        return self.system.number_statements
+      end
       # Get the number from the branches.
       snum = @branches.reduce(0) do |sum,branch|
         sum + branch.number_statements
@@ -118,6 +136,7 @@ module HDLRuby::Viz
       snum += @children.reduce(0) do |sum,child|
         sum + child.number_statements
       end
+      return snum
     end
 
 
@@ -269,43 +288,54 @@ module HDLRuby::Viz
       @uports.clear
       @rports.clear
       @dports.clear
+      # Ports sides by direction and base name.
+      @port_base_dir = {}
+      # Process the ports.
       @ports.each do |port|
-        if port.targets.empty? then
-          puts "Dangling port: #{port.name} (of #{port.ic.name})"
-          # Not connected port, put it on the side with the less ports.
-          if port.direction == :input then
-            if lports.size <= uports.size then
-              port.side = LEFT
-            else
-              port.side = UP
-            end
-          else
-            if rports.size <= dports.size then
-              port.side = RIGHT
-            else
-              port.side = DOWN
-            end
-          end
+        # Maybe there is a port with the same direction.
+        side = @port_base_dir[[HDLRuby::Viz.port_base_name(port.name),
+                               port.direction]]
+        if side then
+          port.side = side
         else
-          # The port is connected.
-          if port.direction == :input then
-            # For now, use the first target only for deciding.
-            d_left  = port.targets[0].ic.xpos - @box[0]
-            d_up    = @box[3] - 
-              port.targets[0].ic.ypos + port.targets[0].ic.height
-            if d_left <= d_up then
-              port.side = LEFT
+          # No, process to port.
+          if port.targets.empty? then
+            puts "Dangling port: #{port.name} (of #{port.ic.name})"
+            # Not connected port, put it on the side with the less ports.
+            if port.direction == :input then
+              if lports.size <= uports.size then
+                port.side = LEFT
+              else
+                port.side = UP
+              end
             else
-              port.side = UP
+              if rports.size <= dports.size then
+                port.side = RIGHT
+              else
+                port.side = DOWN
+              end
             end
           else
-            d_right = @box[2] - 
-              port.targets[0].ic.xpos + port.targets[0].ic.width
-            d_down  = port.targets[0].ic.ypos - @box[1]
-            if d_right <= d_down then
-              port.side = RIGHT
+            # The port is connected.
+            if port.direction == :input then
+              # For now, use the first target only for deciding.
+              d_left  = port.targets[0].ic.xpos - @box[0]
+              d_up    = @box[3] - 
+                port.targets[0].ic.ypos + port.targets[0].ic.height
+              if d_left <= d_up then
+                port.side = LEFT
+              else
+                port.side = UP
+              end
             else
-              port.side = DOWN
+              d_right = @box[2] - 
+                port.targets[0].ic.xpos + port.targets[0].ic.width
+              d_down  = port.targets[0].ic.ypos - @box[1]
+              if d_right <= d_down then
+                port.side = RIGHT
+              else
+                port.side = DOWN
+              end
             end
           end
         end
@@ -321,6 +351,9 @@ module HDLRuby::Viz
         when DOWN
           @dports << port
         end
+        # Also for the handling of bits.
+        @port_base_dir[[HDLRuby::Viz.port_base_name(port.name),
+                        port.direction]] = port.side
       end
     end
 
@@ -675,6 +708,7 @@ module HDLRuby::Viz
         nd = child.dports.size * @port_width
         child.height = nl > nr ? nl : nr
         child.width  = nu > nd ? nu : nd
+        puts "For assign" if child.type == :assign
         puts "First width=#{child.width} height=#{child.height} [#{child.lports.size},#{child.uports.size},#{child.rports.size},#{child.dports.size}]"
         # Ensure IC have some thickness.
         if child.type != :register then
@@ -684,15 +718,17 @@ module HDLRuby::Viz
           child.width = @port_width if child.width < @port_width
           # But enlarge if more than one port horizontally or
           # vertically for easier routing and readability.
-          if child.lports.size + child.rports.size > 1 and
-              child.height == @port_width and
-              child.width == @port_width then
-            child.width *= 2
-          end
-          if child.uports.size + child.dports.size > 1 and 
-              child.width == @port_width and
-              child.height == @port_width then
-            child.height *= 2
+          if child.type != :assign then # However assign are treated appart
+            if child.lports.size + child.rports.size > 1 and
+                child.height == @port_width and
+                child.width == @port_width then
+              child.width *= 2
+            end
+            if child.uports.size + child.dports.size > 1 and 
+                child.width == @port_width and
+                child.height == @port_width then
+              child.height *= 2
+            end
           end
           # Also ensure the chip is wide enough.
           if child.type == :assign then
@@ -728,8 +764,9 @@ module HDLRuby::Viz
             child.height = 3 if child.height < @port_width
             child.width = 3 if child.width < @port_width
           end
-          puts "for register: #{child.name} ports.size=#{child.ports.size}, width=#{child.width} height=#{child.height}"
+          # puts "for register: #{child.name} ports.size=#{child.ports.size}, width=#{child.width} height=#{child.height}"
         end
+        puts "Then width=#{child.width} height=#{child.height} [#{child.lports.size},#{child.uports.size},#{child.rports.size},#{child.dports.size}]"
 
       end
     end
@@ -759,6 +796,7 @@ module HDLRuby::Viz
         puts "With number of statements: #{num} are base area=#{area}"
         # First compute the target area, and width and height of each type.
         ics.each do |ic|
+          puts "For ic=#{ic.name}"
           # Update the target area.
           n_area = ic.width * ic.height
           area = n_area if n_area > area
@@ -782,11 +820,13 @@ module HDLRuby::Viz
             pH = ic.height if ic.height > pH
             # Ensure the target area is reached.
             if ic.branches[0].type == :par then
-              # For par processes, increase squarely.
-              if pW <= pH then
-                pW += 1
-              else
-                pH += 1
+              while pW*pW < area do
+                # For par processes, increase squarely.
+                if pW <= pH then
+                  pW += 1
+                else
+                  pH += 1
+                end
               end
             else
               # For non par processes, increase vertically.
@@ -804,7 +844,7 @@ module HDLRuby::Viz
           if ic.type == :instance then
             ic.width = iW
             ic.height = iH
-          else
+          elsif [:process, :clocked_process, :timed_process]. include?(ic.type) then
             puts "For process #{ic.name} setting size from #{ic.width},#{ic.height} to #{pW},#{pH}"
             ic.width = pW
             ic.height = pH
@@ -1278,6 +1318,7 @@ module HDLRuby::Viz
       # Also place the ports of the current IC.
       poses = []
       @lports.each do |lport|
+        next unless lport.targets[0] # Skip dangling port.
         lport.ypos = lport.targets[0].ypos
         lport.ypos += 1 if lport.targets[0].side == UP
         lport.ypos -= 1 if lport.targets[0].side == DOWN
@@ -1290,10 +1331,10 @@ module HDLRuby::Viz
       end
       poses = []
       @uports.each do |uport|
+        next unless uport.targets[0] # Skip dangling port.
         uport.xpos = uport.targets[0].xpos
         uport.xpos -= 1 if uport.targets[0].side == LEFT
         uport.xpos += 1 if uport.targets[0].side == RIGHT
-        puts "Now uport.xpos=#{uport.xpos}"
         # Ensure ports do not overlap.
         while poses[uport.xpos] do
           uport.xpos += 1
@@ -1303,6 +1344,7 @@ module HDLRuby::Viz
       end
       poses = []
       @rports.each do |rport|
+        next unless rport.targets[0] # Skip dangling port.
         rport.ypos = rport.targets[0].ypos
         rport.ypos += 1 if rport.targets[0].side == UP
         rport.ypos -= 1 if rport.targets[0].side == DOWN
@@ -1315,6 +1357,7 @@ module HDLRuby::Viz
       end
       poses = []
       @dports.each do |dport|
+        next unless dport.targets[0] # Skip dangling port.
         dport.xpos = dport.targets[0].xpos
         dport.xpos -= 1 if dport.targets[0].side == LEFT
         dport.xpos += 1 if dport.targets[0].side == RIGHT
@@ -1531,41 +1574,127 @@ module HDLRuby::Viz
     end
 
     # Get the neighbor free positions for port.
-    # def free_neighbors(port,cpos)
     def free_neighbors(port0,port1,cpos)
       res = []
-      # Left neighbor.
-      lpos = [cpos[0]-1,cpos[1]]
-      if lpos[0] >= 0 then
-        elem = @route_matrix[lpos[1]][lpos[0]]
-        # res << lpos if elem.free_from_right?(port)
-        res << lpos if elem.free_from_right?(port0,port1) and
-          !ic_port_conflict(port0,port1,[lpos[0]-1,lpos[1]],RIGHT)
-      end
-      # Up neighbor.
-      upos = [cpos[0],cpos[1]+1]
-      if upos[1] < @route_height then
-        elem = @route_matrix[upos[1]][upos[0]]
-        # res << upos if elem.free_from_down?(port)
-        res << upos if elem.free_from_down?(port0,port1) and
-          !ic_port_conflict(port0,port1,[upos[0],upos[1]+1],DOWN)
-      end
-      # Right neighbor.
-      rpos = [cpos[0]+1,cpos[1]]
-      if rpos[0] < @route_width then
-        elem = @route_matrix[rpos[1]][rpos[0]]
-        # res << rpos if elem.free_from_left?(port)
-        res << rpos if elem.free_from_left?(port0,port1) and
-          !ic_port_conflict(port0,port1,[rpos[0]+1,rpos[1]],LEFT)
-      end
-      # Down neighbor.
-      dpos = [cpos[0],cpos[1]-1]
-      if dpos[1] >= 0 then
-        elem = @route_matrix[dpos[1]][dpos[0]]
-        # res << dpos if elem.free_from_up?(port)
-        res << dpos if elem.free_from_up?(port0,port1) and
-          !ic_port_conflict(port0,port1,[dpos[0],dpos[1]-1],UP)
-      end
+      # For cosmetic reasons of the wires, the order of processing depends
+      # on the relative position of the ports.
+      if port0.xpos < port1.xpos and port0.ypos < port1.ypos then
+        # Left neighbor.
+        lpos = [cpos[0]-1,cpos[1]]
+        if lpos[0] >= 0 then
+          elem = @route_matrix[lpos[1]][lpos[0]]
+          res << lpos if elem.free_from_right?(port0,port1) and
+            !ic_port_conflict(port0,port1,[lpos[0]-1,lpos[1]],RIGHT)
+        end
+        # Up neighbor.
+        upos = [cpos[0],cpos[1]+1]
+        if upos[1] < @route_height then
+          elem = @route_matrix[upos[1]][upos[0]]
+          res << upos if elem.free_from_down?(port0,port1) and
+            !ic_port_conflict(port0,port1,[upos[0],upos[1]+1],DOWN)
+        end
+        # Right neighbor.
+        rpos = [cpos[0]+1,cpos[1]]
+        if rpos[0] < @route_width then
+          elem = @route_matrix[rpos[1]][rpos[0]]
+          res << rpos if elem.free_from_left?(port0,port1) and
+            !ic_port_conflict(port0,port1,[rpos[0]+1,rpos[1]],LEFT)
+        end
+        # Down neighbor.
+        dpos = [cpos[0],cpos[1]-1]
+        if dpos[1] >= 0 then
+          elem = @route_matrix[dpos[1]][dpos[0]]
+          res << dpos if elem.free_from_up?(port0,port1) and
+            !ic_port_conflict(port0,port1,[dpos[0],dpos[1]-1],UP)
+        end
+      elsif port0.xpos < port1.xpos and port0.ypos > port1.ypos then
+        # Left neighbor.
+        lpos = [cpos[0]-1,cpos[1]]
+        if lpos[0] >= 0 then
+          elem = @route_matrix[lpos[1]][lpos[0]]
+          res << lpos if elem.free_from_right?(port0,port1) and
+            !ic_port_conflict(port0,port1,[lpos[0]-1,lpos[1]],RIGHT)
+        end
+        # Down neighbor.
+        dpos = [cpos[0],cpos[1]-1]
+        if dpos[1] >= 0 then
+          elem = @route_matrix[dpos[1]][dpos[0]]
+          res << dpos if elem.free_from_up?(port0,port1) and
+            !ic_port_conflict(port0,port1,[dpos[0],dpos[1]-1],UP)
+        end
+        # Right neighbor.
+        rpos = [cpos[0]+1,cpos[1]]
+        if rpos[0] < @route_width then
+          elem = @route_matrix[rpos[1]][rpos[0]]
+          res << rpos if elem.free_from_left?(port0,port1) and
+            !ic_port_conflict(port0,port1,[rpos[0]+1,rpos[1]],LEFT)
+        end
+        # Up neighbor.
+        upos = [cpos[0],cpos[1]+1]
+        if upos[1] < @route_height then
+          elem = @route_matrix[upos[1]][upos[0]]
+          res << upos if elem.free_from_down?(port0,port1) and
+            !ic_port_conflict(port0,port1,[upos[0],upos[1]+1],DOWN)
+        end
+      elsif port0.xpos > port1.xpos and port0.ypos > port1.ypos then
+        # Right neighbor.
+        rpos = [cpos[0]+1,cpos[1]]
+        if rpos[0] < @route_width then
+          elem = @route_matrix[rpos[1]][rpos[0]]
+          res << rpos if elem.free_from_left?(port0,port1) and
+            !ic_port_conflict(port0,port1,[rpos[0]+1,rpos[1]],LEFT)
+        end
+        # Down neighbor.
+        dpos = [cpos[0],cpos[1]-1]
+        if dpos[1] >= 0 then
+          elem = @route_matrix[dpos[1]][dpos[0]]
+          res << dpos if elem.free_from_up?(port0,port1) and
+            !ic_port_conflict(port0,port1,[dpos[0],dpos[1]-1],UP)
+        end
+        # Left neighbor.
+        lpos = [cpos[0]-1,cpos[1]]
+        if lpos[0] >= 0 then
+          elem = @route_matrix[lpos[1]][lpos[0]]
+          res << lpos if elem.free_from_right?(port0,port1) and
+            !ic_port_conflict(port0,port1,[lpos[0]-1,lpos[1]],RIGHT)
+        end
+        # Up neighbor.
+        upos = [cpos[0],cpos[1]+1]
+        if upos[1] < @route_height then
+          elem = @route_matrix[upos[1]][upos[0]]
+          res << upos if elem.free_from_down?(port0,port1) and
+            !ic_port_conflict(port0,port1,[upos[0],upos[1]+1],DOWN)
+        end
+      else 
+        # Right neighbor.
+        rpos = [cpos[0]+1,cpos[1]]
+        if rpos[0] < @route_width then
+          elem = @route_matrix[rpos[1]][rpos[0]]
+          res << rpos if elem.free_from_left?(port0,port1) and
+            !ic_port_conflict(port0,port1,[rpos[0]+1,rpos[1]],LEFT)
+        end
+        # Up neighbor.
+        upos = [cpos[0],cpos[1]+1]
+        if upos[1] < @route_height then
+          elem = @route_matrix[upos[1]][upos[0]]
+          res << upos if elem.free_from_down?(port0,port1) and
+            !ic_port_conflict(port0,port1,[upos[0],upos[1]+1],DOWN)
+        end
+        # Left neighbor.
+        lpos = [cpos[0]-1,cpos[1]]
+        if lpos[0] >= 0 then
+          elem = @route_matrix[lpos[1]][lpos[0]]
+          res << lpos if elem.free_from_right?(port0,port1) and
+            !ic_port_conflict(port0,port1,[lpos[0]-1,lpos[1]],RIGHT)
+        end
+        # Down neighbor.
+        dpos = [cpos[0],cpos[1]-1]
+        if dpos[1] >= 0 then
+          elem = @route_matrix[dpos[1]][dpos[0]]
+          res << dpos if elem.free_from_up?(port0,port1) and
+            !ic_port_conflict(port0,port1,[dpos[0],dpos[1]-1],UP)
+        end
+      end 
       # Return the free neigbor positions.
       return res
     end
@@ -1651,29 +1780,16 @@ module HDLRuby::Viz
       pos0 = [port0.xpos,port0.ypos]
       pos1 = [port1.xpos,port1.ypos]
       oset = [pos0]
-      # oset = Set.new
       oset << pos0
       from = { }
-      # gscore = Hash.new(1/0.0)
-      # gscore[pos0] = 0
       gscore = Array.new(@route_matrix.size) { Array.new(@route_matrix[0].size) { 1/0.0 } }
       gscore[pos0[1]][pos0[0]] = 0
-      # fscore = Hash.new(1/0.0)
-      # fscore[pos0] = taxi_distance(pos0,pos1)
       fscore = Array.new(@route_matrix.size) { [] }
       fscore[pos0[1]][pos0[0]] = taxi_distance(pos0,pos1)
       while oset.any? do
         # Pick the position from oset with the minimum fscore.
         cpos = nil          # Current position
         mscore = 1/0.0      # Minimum score
-        # oset.each do |pos|
-        #   # score = fscore[pos]
-        #   score = fscore[pos[1]][pos[0]]
-        #   if score < mscore then
-        #     mscore = score
-        #     cpos = pos
-        #   end
-        # end
         # The best score is necessily at the end of oset.
         cpos = oset.pop
         # puts "cpos=#{cpos}"
@@ -1682,23 +1798,16 @@ module HDLRuby::Viz
           from[pos1] = cpos
           return reconstruct_path(port0,port1,from,pos1)
         end
-        # oset.delete(cpos) # No need anymore since pop
         # Get the neighbor positions for port.
-        # poses = free_neighbors(port0,cpos)
         poses = free_neighbors(port0,port1,cpos)
         poses.each do |pos|
           # Try it.
-          # tscore = gscore[cpos] + cost_position(port0,pos)
           tscore = gscore[cpos[1]][cpos[0]] + cost_position(port0,pos)
-          # if tscore < gscore[pos] then
           if tscore < gscore[pos[1]][pos[0]] then
             # This path to neigbor is better than any previous one, keep it.
             from[pos]   = cpos
-            # gscore[pos] = tscore
             gscore[pos[1]][pos[0]] = tscore
-            # fscore[pos] = tscore + taxi_distance(pos,pos1)
             fscore[pos[1]][pos[0]] = tscore + taxi_distance(pos,pos1)
-            # oset << pos unless oset.include?(pos)
             idx = oset.bsearch_index {|p| fscore[p[1]][p[0]] <= fscore[pos[1]][pos[0]] }
             if idx then
               oset.insert(idx,pos)
@@ -2377,14 +2486,26 @@ module HDLRuby::Viz
       id = Viz.to_svg_id(ic.name)
       # Determine the side of the inputs (and consequently of the outputs),
       # and the number of inputs.
-      iside = LEFT # Default side: left
+      iside = nil 
       inum = 0
       ic.ports.each do |port|
         if port.direction == :input then
           iside = port.side
           inum += 1
+        elsif port.direction == :output then
+          case port.side
+          when LEFT
+            iside = RIGHT
+          when RIGHT 
+            iside = LEFT
+          when UP
+            iside = DOWN
+          when DOWN
+            iside = UP
+          end
         end
       end
+      raise "Connection with no port for #{ic.name}" unless iside
       # NOTE: inum is zero in case of a constant, force at least 1.
       inum = 1 if inum < 1
       # The length of a leg
@@ -2498,6 +2619,8 @@ module HDLRuby::Viz
         res = "<rect fill=\"#88f\" stroke=\"#000\" " 
       when :negedge
         res = "<rect fill=\"#f88\" stroke=\"#000\" " 
+      when :anyedge
+        res = "<rect fill=\"#888\" stroke=\"#000\" " 
       else
         res = "<rect fill=\"#ff0\" stroke=\"#000\" " 
       end
@@ -2517,6 +2640,8 @@ module HDLRuby::Viz
         res = "<rect fill=\"#88f\" stroke=\"#000\" " 
       when :negedge
         res = "<rect fill=\"#f88\" stroke=\"#000\" " 
+      when :anyedge
+        res = "<rect fill=\"#888\" stroke=\"#000\" " 
       else
         res = "<rect fill=\"#ff0\" stroke=\"#000\" " 
       end
@@ -2551,6 +2676,8 @@ module HDLRuby::Viz
         res = "<rect fill=\"#88f\" stroke=\"#000\" " 
       when :negedge
         res = "<rect fill=\"#f88\" stroke=\"#000\" " 
+      when :anyedge
+        res = "<rect fill=\"#888\" stroke=\"#000\" " 
       else
         res = "<rect fill=\"#ff0\" stroke=\"#000\" " 
       end
@@ -2570,6 +2697,8 @@ module HDLRuby::Viz
         res = "<rect fill=\"#88f\" stroke=\"#000\" " 
       when :negedge
         res = "<rect fill=\"#f88\" stroke=\"#000\" " 
+      when :anyedge
+        res = "<rect fill=\"#888\" stroke=\"#000\" " 
       else
         res = "<rect fill=\"#ff0\" stroke=\"#000\" " 
       end
@@ -2605,15 +2734,22 @@ module HDLRuby::Viz
     # Generate the string representing a port for display in the SVG
     def port_str(port)
       # Generate the port name (strip everything before the last ".")
-      name = port.name.sub(/^.*\./,"")
+      # name = port.name.sub(/^.*\./,"")
+      name = port.name.split(/(?<!\.)\.(?!\.)/).last
       # Strip the suffix $I and $O
       name = name.sub(/\$(I|O)$/,"")
+      # For registers' bit ports, only keep the bit number.
+      if port.ic.type==:register and HDLRuby::Viz.port_bit_name?(name) then
+        name = HDLRuby::Viz.port_bit_name(name)
+      end
       # Add a suffix for edge properties.
       case port.type
       when :posedge
         return name + " \u2197"
       when :negedge
         return name + " \u2198"
+      when :anyedge
+        return name + " \u2195"
       else
         return name
       end
@@ -2660,7 +2796,10 @@ module HDLRuby::Viz
       # Sets the styles.
       res += "<style>\n"
       # Fonts
-      res += ".small#{self.idC}  { font: #{sF}px sans-serif; }\n"
+      res += ".small#{self.idC}  { font: #{sF}px sans-serif; " # }\n" # +
+      res += "stroke=\"yellow\"; stroke-width=\"6\"; paint-order=\"stroke fill;\" }\n"
+        # "border: 2px solid black; padding: 10px; display: inline-block; " +
+        # " background-color: rgba(0, 128, 255, 0.2); }\n"
       res += ".medium#{self.idC} { font: #{mF}px sans-serif; }\n"
       res += ".large#{self.idC}  { font: #{lF}px sans-serif; }\n"
       res += "</style>\n"
@@ -2818,11 +2957,19 @@ module HDLRuby::Viz
             if child == self then
               res += "<text class=\"small#{self.idC}\" style=\"text-anchor: end\" " +
                 "x=\"#{(port.xpos)*@scale-pT}\" "+
-                "y=\"#{(port.ypos+0.5)*@scale+sF/2.5}\">" + # port.name +
+                "y=\"#{(port.ypos+0.5)*@scale+sF/2.5}\">" + 
+                self.port_str(port) + "</text>\n"
+            elsif (child.type == :assign and port.direction == :input and
+                   child.ports.size.even? and child.ports.index(port) == child.ports.size/2) then
+              # Middle input of an alu, slide it bellow to avoid collision
+              # with the output port.
+              res += "<text class=\"small#{self.idC}\" x=\"#{(port.xpos)*@scale+pT}\" "+
+                "y=\"#{(port.ypos+0.8)*@scale+sF/2.5}\">" +
                 self.port_str(port) + "</text>\n"
             else
+              # General case.
               res += "<text class=\"small#{self.idC}\" x=\"#{(port.xpos)*@scale+pT}\" "+
-                "y=\"#{(port.ypos+0.5)*@scale+sF/2.5}\">" + # port.name + 
+                "y=\"#{(port.ypos+0.45)*@scale+sF/2.5}\">" + 
                 self.port_str(port) + "</text>\n"
             end
           end
@@ -2886,10 +3033,18 @@ module HDLRuby::Viz
                 "x=\"#{(port.xpos+1)*@scale+pT}\" " +
                 "y=\"#{(port.ypos+0.5)*@scale+sF/2.5}\">" + # port.name +
                 self.port_str(port) + "</text>\n"
+            elsif (child.type == :assign and port.direction == :input and
+                   child.ports.size.even? and child.ports.index(port) == child.ports.size/2) then
+              # Middle input of an alu, slide it bellow to avoid collision
+              # with the output port.
+              res += "<text class=\"small#{self.idC}\" style=\"text-anchor: end\" " +
+                "x=\"#{(port.xpos+1)*@scale-pT}\" "+
+                "y=\"#{(port.ypos+0.8)*@scale+sF/2.5}\">" + # port.name + 
+                self.port_str(port) + "</text>\n"
             else
               res += "<text class=\"small#{self.idC}\" style=\"text-anchor: end\" " +
                 "x=\"#{(port.xpos+1)*@scale-pT}\" "+
-                "y=\"#{(port.ypos+0.5)*@scale+sF/2.5}\">" + # port.name + 
+                "y=\"#{(port.ypos+0.45)*@scale+sF/2.5}\">" + # port.name + 
                 self.port_str(port) + "</text>\n"
             end
           end
@@ -2973,14 +3128,15 @@ module HDLRuby::Viz
             cty += 1
           end
         end
-        # Leave a space for left or right ports if any.
-        sl = child.ports.any? {|p| p.side == LEFT } ? 1.0 : 0.0
-        sr = child.ports.any? {|p| p.side == RIGHT } ? 1.0 : 0.0
+        # # Leave a space for left or right ports if any.
+        # sl = (child.ports.any? {|p| p.side == LEFT }) ? 1.0 : 0.0
+        # sr = (child.ports.any? {|p| p.side == RIGHT }) ? 1.0 : 0.0
         # Recompute the scale.
         fit = [
-          (target.width+sl+sr+(bT/@scale)) / (cwidth),
-          (target.height+(bT/@scale)) / (cheight),
-          3.0
+          # (target.width+sl+sr+(bT/@scale/2.0)) / (cwidth),
+          (target.width+(bT/@scale/2.0)) / (cwidth),
+          (target.height+(bT/@scale/2.0)) / (cheight),
+          1.0# 3.0
         ].max
         target.scale = @scale / fit
         puts "fit=#{fit} target.scale=#{target.scale}"
@@ -4382,7 +4538,7 @@ class HDLRuby::Low::SystemT
     # ports.each_value do |subs|
     ports.each do |name,subs|
       # Skip connection to registers, they are processed later.
-      next if regs[name]
+      next if regs[HDLRuby::Viz.port_base_name(name)]
       # Not a register, can go on.
       subs.each do |p0|
         subs.each do |p1|
@@ -4400,15 +4556,17 @@ class HDLRuby::Low::SystemT
       # Check if there is a register corresponding to the port
       # (full port or sub port of the register).
       next if name.include?("$") # Skip register ports which are targets.
-      rname = name
+      # rname = name
+      rname = HDLRuby::Viz.port_base_name(name)
       while !regs.key?(rname) do
         break unless rname.include?(".")
         rname = rname.gsub(/\.[^.]*$/,"")
       end
       reg = regs[rname]
       next unless reg
-      # Connect the register, once per ic and direction.
-      subs.uniq {|p| [p.ic,p.direction] }.each do |p|
+      # # Connect the register, once per ic and direction.
+      # Connect the register, once per ic, direction and type.
+      subs.uniq {|p| [p.ic,p.direction,p.type] }.each do |p|
         # puts "Connect to register port name #{name} in ic=#{world.name} with port=#{p.name}"
         if p.direction == :output then
           world.connect(p,ports[HDLRuby::Viz.reg2input_name(name)][0])
@@ -4444,16 +4602,48 @@ class HDLRuby::Low::SystemT
       # NOTE: p0 or p1 may be empty if outside current module.
       world.connect(p0,p1) unless (!p0 or !p1 or p0.targets.include?(p1))
     end
-    # Remove the dangling input ports in registers (they are ROMS).
+    # # Remove the dangling input ports in registers (they are ROMS).
+    # regs.each_value do |reg|
+    #   to_remove_input = reg.ports.select {|p| p.direction==:input }.all? do
+    #     |p|
+    #     p.targets.none?
+    #   end
+    #   if to_remove_input then
+    #     reg.ports.delete_if {|p| p.direction == :input }
+    #   end
+    # end
+    # Remove the dangling ports in registers (they are ROMS).
     regs.each_value do |reg|
-      to_remove_input = reg.ports.select {|p| p.direction==:input }.all? do
-        |p|
-        p.targets.none?
+      reg.ports.delete_if {|p| p.targets.none? }
+    end
+
+    # Gather the bit ports by owner port.
+    port2bits = {}
+    ports.each do |name,subs|
+      subs.each do |port|
+        port2bits[port.name] = []
       end
-      if to_remove_input then
-        reg.ports.delete_if {|p| p.direction == :input }
+    end
+    ports.each do |name,subs|
+      subs.each do |port|
+        if HDLRuby::Viz.port_bit_name?(port.name) then
+          port2bits[HDLRuby::Viz.port_base_name(port.name)] << port
+        end
       end
     end
+    # Remove the dangling ports that are accessed by sub ports.
+    ports.each do |name,subs|
+      subs.each do |port|
+        if port.targets.none? then
+          # This is a dangling port, is it connected by bits.
+          if port2bits[port.name].any? then
+            # Yes, remove it.
+            port.ic.ports.delete(port)
+          end
+        end
+      end
+    end
+
     # Return the resulting visualization.
     return world
   end
@@ -4482,18 +4672,23 @@ class HDLRuby::Low::Scope
       # name = sname + inner.name.to_s
       # name = inner.name.to_s
       name = sname + inner.name.to_s
-      # Create the viz for the "register"
-      if typ.is_a?(HDLRuby::Low::TypeVector) and
-          typ.base.width > 1 then
-        puts "Adding scope register #{name} to #{world.name}"
-        # This is in fact a memory matrix.
-        reg = HDLRuby::Viz::IC.new(name,:memory,world)
-      else
-        puts "Adding plain register #{name} to #{world.name}"
-        # This is a plain register.
-        reg = HDLRuby::Viz::IC.new(name,:register,world)
+      # But first cut of the index if any for the register.
+      rname = HDLRuby::Viz.port_base_name(name)
+      reg = regs[rname]
+      unless reg then
+        # Create the viz for the "register"
+        if typ.is_a?(HDLRuby::Low::TypeVector) and
+            typ.base.width > 1 then
+          puts "Adding scope register #{rname} to #{world.name}"
+          # This is in fact a memory matrix.
+          reg = HDLRuby::Viz::IC.new(rname,:memory,world)
+        else
+          puts "Adding plain register #{rname} to #{world.name}"
+          # This is a plain register.
+          reg = HDLRuby::Viz::IC.new(rname,:register,world)
+        end
+        regs[reg.name] = reg
       end
-      regs[reg.name] = reg
       # Create the corresponding input and output ports.
       iname = HDLRuby::Viz.reg2input_name(name)
       puts "Adding input port #{iname} to reg #{reg.name}"
@@ -4546,21 +4741,11 @@ class HDLRuby::Low::Scope
         # Explicit port connect case.
         links << [ connection.left.to_viz_names[0],
                    connection.right.to_viz_names[0] ]
-        # # Get the right refered name.
-        # rname = connection.right.to_viz_names[0]
-        # # If it is a register make the name its output.
-        # rname = HDLRuby::Viz.reg2output_name(rname) if regs[rname]
-        # # Get the left refered name.
-        # lname = connection.left.to_viz_names[0]
-        # # If it is a register make the name its input.
-        # lname = HDLRuby::Viz.reg2input_name(lname) if regs[lname]
-        # # Make the explicit port connect.
-        # links << [ lname, rname ]
         # Add the explicit port connection.
         puts "added link between #{links[-1][0]} and #{links[-1][1]}"
         next
       end
-      ic = HDLRuby::Viz::IC.new(HDLRuby.uniq_name("cxn"),:assign,world)
+      ic = HDLRuby::Viz::IC.new(HDLRuby.uniq_name("cnx"),:assign,world)
       # Add its ports.
       # Output.
       name = connection.left.to_viz_names[0]
@@ -4595,14 +4780,15 @@ class HDLRuby::Low::Scope
       behavior.each_event do |ev|
         name = ev.ref.to_viz_names[0]
         next if ic.port?(name) # The port has already been added.
-        # Is it a clocked event?
-        if ev.on_edge? then
-          # Yes.
-          ports[name] << ic.add_port(name, :input, ev.type)
-        else
-          # No, use a standard port.
-          ports[name] << ic.add_port(name, :input)
-        end
+        # # Is it a clocked event?
+        # if ev.on_edge? then
+        #   # Yes.
+        #   ports[name] << ic.add_port(name, :input, ev.type)
+        # else
+        #   # No, use a standard port.
+        #   ports[name] << ic.add_port(name, :input)
+        # end
+        ports[name] << ic.add_port(name, :input, ev.type)
       end
       # Recurse on its blocks.
       # behavior.block.to_viz(world,ic,ports)
@@ -4691,14 +4877,19 @@ class HDLRuby::Low::Block
     self.each_inner do |inner|
       name = bname + inner.name.to_s
       puts "Adding block register #{name} to #{world.name}"
-      # Create the viz for the "register"
-      if inner.type.base.width > 1 then
-        # This is in fact a memory matrix.
-        reg = HDLRuby::Viz::IC.new(name,:memory,world)
-      else
-        reg = HDLRuby::Viz::IC.new(name,:register,world)
+      # But first cut of the index if any for the register.
+      rname = HDLRuby::Viz.port_base_name(name)
+      reg = regs[rname]
+      unless reg then
+        # Create the viz for the "register"
+        if inner.type.base.width > 1 then
+          # This is in fact a memory matrix.
+          reg = HDLRuby::Viz::IC.new(rname,:memory,world)
+        else
+          reg = HDLRuby::Viz::IC.new(rname,:register,world)
+        end
+        regs[reg.name] = reg
       end
-      regs[reg.name] = reg
       # Create the corresponding input and output ports.
       iname = HDLRuby::Viz.reg2input_name(name)
       puts "Adding input port #{iname} to #{world.name}"
@@ -4767,20 +4958,22 @@ class HDLRuby::Low::Block
       end
 
       next unless stmnt.is_a?(HDLRuby::Low::Transmit)
-      name = stmnt.left.to_viz_names[0]
+      lnames = stmnt.left.to_viz_names
+      name = lnames[0]
       if iports.key?(name) then
         # Change to inout port.
         iports[name].direction = :inout
-        next
-      end
+        # next
+      # end
       # Add one port by output name.
-      unless oports.key?(name) then
+      # unless oports.key?(name) then
+      elsif !oports.key?(name) then
         puts "Adding output port #{name} to #{ic.name}"
         port = ic.add_port(name, :output)
         ports[name] << port
         oports[name] = port
       end
-      stmnt.right.to_viz_names.each do |name|
+      (stmnt.right.to_viz_names+lnames[1..-1]).each do |name|
         if oports.key?(name) then
           # Change to inout port.
           oports[name].direction = :inout