HDLRuby 3.2.0 → 3.3.0
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- checksums.yaml +4 -4
- data/README.html +2330 -2670
- data/README.md +391 -101
- data/ext/hruby_sim/hruby_rcsim_build.c +400 -3
- data/ext/hruby_sim/hruby_sim.h +2 -1
- data/ext/hruby_sim/hruby_sim_calc.c +1 -1
- data/ext/hruby_sim/hruby_sim_core.c +15 -5
- data/ext/hruby_sim/hruby_sim_tree_calc.c +1 -1
- data/lib/HDLRuby/hdr_samples/c_program/echo.c +33 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/echo.rb +9 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/stdrw.rb +6 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/sw_cpu_terminal.rb +614 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/sw_inc_mem.rb +32 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/sw_log.rb +33 -0
- data/lib/HDLRuby/hdr_samples/with_board.rb +63 -0
- data/lib/HDLRuby/hdr_samples/with_clocks.rb +42 -0
- data/lib/HDLRuby/hdr_samples/with_of.rb +1 -1
- data/lib/HDLRuby/hdr_samples/with_program_c.rb +28 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby.rb +28 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_cpu.rb +234 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_io.rb +23 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_mem.rb +58 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_threads.rb +56 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_func.rb +2 -4
- data/lib/HDLRuby/hdrcc.rb +60 -21
- data/lib/HDLRuby/hruby_error.rb +13 -0
- data/lib/HDLRuby/hruby_high.rb +50 -7
- data/lib/HDLRuby/hruby_low.rb +74 -30
- data/lib/HDLRuby/hruby_rcsim.rb +89 -5
- data/lib/HDLRuby/std/clocks.rb +118 -50
- data/lib/HDLRuby/std/std.rb +5 -0
- data/lib/HDLRuby/ui/hruby_board.rb +1079 -0
- data/lib/HDLRuby/version.rb +1 -1
- data/lib/c/Rakefile +8 -0
- data/lib/c/cHDL.h +12 -0
- data/lib/c/extconf.rb +7 -0
- data/lib/rubyHDL.rb +33 -0
- data/tuto/gui_accum.png +0 -0
- data/tuto/gui_board.png +0 -0
- data/tuto/tutorial_sw.html +2263 -1890
- data/tuto/tutorial_sw.md +957 -62
- metadata +24 -5
- data/README.pdf +0 -0
- data/tuto/tutorial_sw.pdf +0 -0
data/lib/HDLRuby/hruby_error.rb
CHANGED
@@ -5,6 +5,10 @@ module HDLRuby
|
|
5
5
|
class AnyError < ::StandardError
|
6
6
|
end
|
7
7
|
|
8
|
+
## The HDLRuby UI error class.
|
9
|
+
class UIError < ::StandardError
|
10
|
+
end
|
11
|
+
|
8
12
|
module High
|
9
13
|
## The HDLRuby::High error class.
|
10
14
|
class AnyError < HDLRuby::AnyError
|
@@ -13,12 +17,21 @@ module HDLRuby
|
|
13
17
|
## The HDLRuby error class replacing the standard Ruby NoMethodError
|
14
18
|
class NotDefinedError < AnyError
|
15
19
|
end
|
20
|
+
|
21
|
+
## The HDLRuby::High UI error class.
|
22
|
+
class UIError < HDLRuby::UIError
|
23
|
+
end
|
16
24
|
end
|
17
25
|
|
26
|
+
|
18
27
|
module Low
|
19
28
|
## The HDLRuby::Low error class.
|
20
29
|
class AnyError < HDLRuby::AnyError
|
21
30
|
end
|
31
|
+
|
32
|
+
## The HDLRuby::Low UI error class.
|
33
|
+
class UIError < HDLRuby::UIError
|
34
|
+
end
|
22
35
|
end
|
23
36
|
|
24
37
|
## Execution context for processing error messages in +code+.
|
data/lib/HDLRuby/hruby_high.rb
CHANGED
@@ -1171,10 +1171,10 @@ module HDLRuby::High
|
|
1171
1171
|
end
|
1172
1172
|
|
1173
1173
|
# Declares a program in language +lang+ with start function named +func+
|
1174
|
-
# and
|
1175
|
-
def program(lang, func,
|
1174
|
+
# and built through +ruby_block+.
|
1175
|
+
def program(lang, func, &ruby_block)
|
1176
1176
|
# Create the program.
|
1177
|
-
prog = Program.new(lang, func,
|
1177
|
+
prog = Program.new(lang, func, &ruby_block)
|
1178
1178
|
# Adds the resulting program to the current scope.
|
1179
1179
|
HDLRuby::High.top_user.add_program(prog)
|
1180
1180
|
# Return the resulting program
|
@@ -2502,16 +2502,59 @@ module HDLRuby::High
|
|
2502
2502
|
##
|
2503
2503
|
# Describes a program.
|
2504
2504
|
class Program < HDLRuby::Low::Program
|
2505
|
+
|
2506
|
+
include Hmissing
|
2507
|
+
|
2508
|
+
attr_reader :namespace
|
2509
|
+
|
2510
|
+
# Create a program in language +lang+ with start function named +func+
|
2511
|
+
# and built through +ruby_block+.
|
2512
|
+
def initialize(lang, func, &ruby_block)
|
2513
|
+
# Create the program.
|
2514
|
+
super(lang,func)
|
2515
|
+
# Create the namespace for the program.
|
2516
|
+
@namespace = Namespace.new(self)
|
2517
|
+
# Build the program object.
|
2518
|
+
High.space_push(@namespace)
|
2519
|
+
High.top_user.instance_eval(&ruby_block)
|
2520
|
+
High.space_pop
|
2521
|
+
end
|
2522
|
+
|
2505
2523
|
# Converts the if to HDLRuby::Low.
|
2506
2524
|
def to_low
|
2507
2525
|
# Create the resulting program.
|
2508
|
-
progL = HDLRuby::Low::Program.new(self.lang,self.function
|
2509
|
-
|
2510
|
-
|
2511
|
-
|
2526
|
+
progL = HDLRuby::Low::Program.new(self.lang,self.function)
|
2527
|
+
# Add the wakening events.
|
2528
|
+
self.each_event { |ev| progL.add_event(ev.to_low) }
|
2529
|
+
# Add the code files.
|
2530
|
+
self.each_code { |ev| progL.add_code(code) }
|
2531
|
+
# Add the input signals references.
|
2532
|
+
self.each_input { |ref| progL.add_input(ref.to_low) }
|
2533
|
+
# Add the output signals references.
|
2534
|
+
self.each_output { |ref| progL.add_output(ref.to_low) }
|
2512
2535
|
# Return the resulting program.
|
2513
2536
|
return progL
|
2514
2537
|
end
|
2538
|
+
|
2539
|
+
# Adds new activation ports.
|
2540
|
+
def actport(*evs)
|
2541
|
+
evs.each(&method(:add_actport))
|
2542
|
+
end
|
2543
|
+
|
2544
|
+
# Adds new code files.
|
2545
|
+
def code(*codes)
|
2546
|
+
codes.each(&method(:add_code))
|
2547
|
+
end
|
2548
|
+
|
2549
|
+
# Adds new input ports.
|
2550
|
+
def inport(ports = {})
|
2551
|
+
ports.each { |k,v| self.add_inport(k,v) }
|
2552
|
+
end
|
2553
|
+
|
2554
|
+
# Adds new output ports.
|
2555
|
+
def outport(ports = {})
|
2556
|
+
ports.each { |k,v| self.add_outport(k,v) }
|
2557
|
+
end
|
2515
2558
|
end
|
2516
2559
|
|
2517
2560
|
|
data/lib/HDLRuby/hruby_low.rb
CHANGED
@@ -844,10 +844,10 @@ module HDLRuby::Low
|
|
844
844
|
"Invalid class for a program: #{prog.class}"
|
845
845
|
end
|
846
846
|
# Set the parent of the program.
|
847
|
-
|
847
|
+
prog.parent = self
|
848
848
|
# Add the program.
|
849
|
-
@programs <<
|
850
|
-
|
849
|
+
@programs << prog
|
850
|
+
prog
|
851
851
|
end
|
852
852
|
|
853
853
|
# Iterates over the programs.
|
@@ -3006,57 +3006,101 @@ module HDLRuby::Low
|
|
3006
3006
|
attr_reader :language, :function
|
3007
3007
|
|
3008
3008
|
# Creates a new program in language +lang+ with start function
|
3009
|
-
# named +func
|
3010
|
-
|
3011
|
-
def initialize(lang,func,*args)
|
3009
|
+
# named +func+.
|
3010
|
+
def initialize(lang,func)
|
3012
3011
|
# Sets the language.
|
3013
3012
|
@language = lang.to_sym
|
3014
3013
|
# Sets the start function.
|
3015
3014
|
@function = func.to_s
|
3016
|
-
#
|
3017
|
-
@
|
3018
|
-
@
|
3019
|
-
@
|
3020
|
-
|
3021
|
-
|
3022
|
-
|
3023
|
-
|
3024
|
-
|
3025
|
-
|
3026
|
-
|
3027
|
-
|
3015
|
+
# Initializes the contents.
|
3016
|
+
@actports = [] # The activation ports.
|
3017
|
+
@codes = [] # The code files.
|
3018
|
+
@inports = {} # The input ports.
|
3019
|
+
@outports = {} # The output ports.
|
3020
|
+
end
|
3021
|
+
|
3022
|
+
# Add a new activation port.
|
3023
|
+
def add_actport(ev)
|
3024
|
+
unless ev.is_a?(Event) then
|
3025
|
+
raise AnyError, "Invalid class for an event: #{ev.class}"
|
3026
|
+
end
|
3027
|
+
@actports << ev
|
3028
|
+
end
|
3029
|
+
|
3030
|
+
# Add a new code file.
|
3031
|
+
def add_code(code)
|
3032
|
+
@codes << code.to_s
|
3033
|
+
end
|
3034
|
+
|
3035
|
+
# Add a new input port.
|
3036
|
+
def add_inport(name, sig)
|
3037
|
+
# Ensure name is a symbol.
|
3038
|
+
unless name.is_a?(Symbol) then
|
3039
|
+
name = name.to_s.to_sym
|
3028
3040
|
end
|
3041
|
+
# Ensure sig is a signal.
|
3042
|
+
unless sig.is_a?(SignalI) then
|
3043
|
+
raise AnyError, "Invalid class for a signal: #{sig.class}"
|
3044
|
+
end
|
3045
|
+
# Add the new port.
|
3046
|
+
@inports[name] = sig
|
3047
|
+
end
|
3048
|
+
|
3049
|
+
# Add a new output port.
|
3050
|
+
def add_outport(name, sig)
|
3051
|
+
# Ensure name is a symbol.
|
3052
|
+
unless name.is_a?(Symbol) then
|
3053
|
+
name = name.to_s.to_sym
|
3054
|
+
end
|
3055
|
+
# Ensure sig is a signal.
|
3056
|
+
unless sig.is_a?(SignalI) then
|
3057
|
+
raise AnyError, "Invalid class for a signal: #{sig.class}"
|
3058
|
+
end
|
3059
|
+
# Add the new port.
|
3060
|
+
@outports[name] = sig
|
3061
|
+
end
|
3062
|
+
|
3063
|
+
|
3064
|
+
# Iterates over each activation event.
|
3065
|
+
#
|
3066
|
+
# Returns an enumerator if no ruby block is given.
|
3067
|
+
def each_actport(&ruby_block)
|
3068
|
+
# No block? Return an enumerator.
|
3069
|
+
return to_enum(:each_actport) unless ruby_block
|
3070
|
+
# A block is given, apply it.
|
3071
|
+
@actports.each(&ruby_block)
|
3029
3072
|
end
|
3030
3073
|
|
3031
|
-
# Iterates over each
|
3074
|
+
# Iterates over each code file.
|
3032
3075
|
#
|
3033
3076
|
# Returns an enumerator if no ruby block is given.
|
3034
|
-
def
|
3077
|
+
def each_code(&ruby_block)
|
3035
3078
|
# No block? Return an enumerator.
|
3036
|
-
return to_enum(:
|
3079
|
+
return to_enum(:each_code) unless ruby_block
|
3037
3080
|
# A block is given, apply it.
|
3038
|
-
@
|
3081
|
+
@codes.each(&ruby_block)
|
3039
3082
|
end
|
3040
3083
|
|
3041
|
-
#
|
3084
|
+
# Iterate over each input port.
|
3042
3085
|
#
|
3043
3086
|
# Returns an enumerator if no ruby block is given.
|
3044
|
-
def
|
3087
|
+
def each_inport(&ruby_block)
|
3045
3088
|
# No block? Return an enumerator.
|
3046
|
-
return to_enum(:
|
3089
|
+
return to_enum(:each_inport) unless ruby_block
|
3047
3090
|
# A block is given, apply it.
|
3048
|
-
@
|
3091
|
+
@inports.each(&ruby_block)
|
3049
3092
|
end
|
3050
3093
|
|
3051
|
-
#
|
3094
|
+
# Iterate over each output port.
|
3052
3095
|
#
|
3053
3096
|
# Returns an enumerator if no ruby block is given.
|
3054
|
-
def
|
3097
|
+
def each_outport(&ruby_block)
|
3055
3098
|
# No block? Return an enumerator.
|
3056
|
-
return to_enum(:
|
3099
|
+
return to_enum(:each_outport) unless ruby_block
|
3057
3100
|
# A block is given, apply it.
|
3058
|
-
@
|
3101
|
+
@outports.each(&ruby_block)
|
3059
3102
|
end
|
3103
|
+
|
3060
3104
|
end
|
3061
3105
|
|
3062
3106
|
|
data/lib/HDLRuby/hruby_rcsim.rb
CHANGED
@@ -3,6 +3,8 @@ require 'HDLRuby'
|
|
3
3
|
require 'hruby_high_fullname'
|
4
4
|
require 'hruby_sim/hruby_sim'
|
5
5
|
|
6
|
+
require 'rubyHDL'
|
7
|
+
|
6
8
|
|
7
9
|
module HDLRuby::High
|
8
10
|
|
@@ -189,7 +191,6 @@ module HDLRuby::High
|
|
189
191
|
rcbehs = self.each_behavior.map {|beh| beh.to_rcsim(subowner)} # +
|
190
192
|
# self.each_connection.map {|cxt| cxt.to_rcsim(subowner) }
|
191
193
|
self.each_connection do |cnx|
|
192
|
-
# ICIICI
|
193
194
|
if !cnx.right.is_a?(RefObject) then
|
194
195
|
rcbehs << cnx.to_rcsim(subowner)
|
195
196
|
else
|
@@ -209,8 +210,11 @@ module HDLRuby::High
|
|
209
210
|
RCSim.rcsim_add_scope_behaviors(@rcscope,rcbehs)
|
210
211
|
end
|
211
212
|
|
212
|
-
# Create and add the
|
213
|
-
|
213
|
+
# Create and add the programs.
|
214
|
+
rcprogs = self.each_program.map {|prog| prog.to_rcsim(subowner)}
|
215
|
+
if rcprogs.any? then
|
216
|
+
RCSim.rcsim_add_scope_codes(@rcscope,rcprogs);
|
217
|
+
end
|
214
218
|
|
215
219
|
return @rcscope
|
216
220
|
end
|
@@ -512,12 +516,92 @@ module HDLRuby::High
|
|
512
516
|
|
513
517
|
class Chunk
|
514
518
|
## Extends the Chunk class for hybrid Ruby-C simulation.
|
515
|
-
#
|
519
|
+
# Deprecated!!
|
516
520
|
end
|
517
521
|
|
518
522
|
class Code
|
519
523
|
## Extends the Code class for hybrid Ruby-C simulation.
|
520
|
-
#
|
524
|
+
# Deprecated!!
|
525
|
+
end
|
526
|
+
|
527
|
+
class Program
|
528
|
+
## Extends the Program class for hybrid Ruby-C simulation.
|
529
|
+
# NOTE: produce a low-level Code, and not program. For now,
|
530
|
+
# Program is a high-level interface for software description and
|
531
|
+
# is not ment to be simulated as is. It may hcange in the future
|
532
|
+
# though.
|
533
|
+
|
534
|
+
attr_reader :rccode # The access to the C version of the code.
|
535
|
+
|
536
|
+
# Generate the C description of the code comming from object
|
537
|
+
# whose C description is +rcowner+.
|
538
|
+
# NOTE: also update the table of signals accessed from software
|
539
|
+
# code.
|
540
|
+
def to_rcsim(rcowner)
|
541
|
+
# puts "to_rcsim for program=#{self}"
|
542
|
+
|
543
|
+
# Create the code C object.
|
544
|
+
# puts "make code with self.class=#{self.class}"
|
545
|
+
@rccode = RCSim.rcsim_make_code(self.language.to_s, self.function.to_s)
|
546
|
+
|
547
|
+
# Set the owner.
|
548
|
+
RCSim.rcsim_set_owner(@rccode,rcowner)
|
549
|
+
|
550
|
+
# Create and add the events.
|
551
|
+
if self.each_actport.any? then
|
552
|
+
RCSim.rcsim_add_code_events(@rccode, self.each_actport.map do|ev|
|
553
|
+
ev.to_rcsim(@rccode)
|
554
|
+
end)
|
555
|
+
end
|
556
|
+
|
557
|
+
# Create the software interface.
|
558
|
+
if self.language == :ruby then
|
559
|
+
# Loads the code files.
|
560
|
+
self.each_code do |code|
|
561
|
+
Kernel.require("./"+code.to_s)
|
562
|
+
end
|
563
|
+
# Add the input ports.
|
564
|
+
self.each_inport do |sym, sig|
|
565
|
+
RubyHDL.inport(sym,sig.rcsignalI)
|
566
|
+
end
|
567
|
+
# Add the output ports.
|
568
|
+
self.each_outport do |sym, sig|
|
569
|
+
RubyHDL.outport(sym,sig.rcsignalI)
|
570
|
+
end
|
571
|
+
elsif self.language == :c then
|
572
|
+
# Loads the code file: only the last one remains.
|
573
|
+
self.each_code do |code|
|
574
|
+
code = code.to_s
|
575
|
+
# Check if the file exists.
|
576
|
+
unless File.file?(code) then
|
577
|
+
# The code name may be not complete,
|
578
|
+
# try ".so", ".bundle" or ".dll" extensions.
|
579
|
+
if File.file?(code+".so") then
|
580
|
+
code += ".so"
|
581
|
+
elsif File.file?(code + ".bundle") then
|
582
|
+
code += ".bundle"
|
583
|
+
elsif File.file?(code + ".dll") then
|
584
|
+
code += ".dll"
|
585
|
+
else
|
586
|
+
# Code not found.
|
587
|
+
raise "C code library not found: " + code
|
588
|
+
end
|
589
|
+
end
|
590
|
+
RCSim.rcsim_load_c(@rccode,code,self.function.to_s)
|
591
|
+
end
|
592
|
+
# Add the input ports.
|
593
|
+
self.each_inport do |sym, sig|
|
594
|
+
RCSim::CPorts[sym] = sig.rcsignalI
|
595
|
+
end
|
596
|
+
# Add the output ports.
|
597
|
+
self.each_outport do |sym, sig|
|
598
|
+
RCSim::CPorts[sym] = sig.rcsignalI
|
599
|
+
end
|
600
|
+
end
|
601
|
+
|
602
|
+
|
603
|
+
return @rccode
|
604
|
+
end
|
521
605
|
end
|
522
606
|
|
523
607
|
|
data/lib/HDLRuby/std/clocks.rb
CHANGED
@@ -4,10 +4,10 @@ module HDLRuby::High::Std
|
|
4
4
|
# Standard HDLRuby::High library: clocks
|
5
5
|
#
|
6
6
|
########################################################################
|
7
|
-
|
7
|
+
@@__clocks_rst = nil
|
8
8
|
|
9
9
|
# Initialize the clock generator with +rst+ as reset signal.
|
10
|
-
def configure_clocks(rst =
|
10
|
+
def configure_clocks(rst = nil)
|
11
11
|
@@__clocks_rst = rst
|
12
12
|
end
|
13
13
|
|
@@ -19,13 +19,22 @@ module HDLRuby::High::Std
|
|
19
19
|
HDLRuby::High.cur_system.open do
|
20
20
|
|
21
21
|
# Ensures times is a value.
|
22
|
-
times = times.to_value
|
22
|
+
times = times.to_value - 1
|
23
|
+
if (times == 0) then
|
24
|
+
AnyError.new("Clock multiplier must be >= 2.")
|
25
|
+
end
|
23
26
|
|
24
27
|
# Create the counter.
|
25
28
|
# Create the name of the counter.
|
26
29
|
name = HDLRuby.uniq_name
|
27
30
|
# Declare the counter.
|
28
|
-
|
31
|
+
if @@__clocks_rst then
|
32
|
+
# There is a reset, so no need to initialize.
|
33
|
+
[times.width].inner(name)
|
34
|
+
else
|
35
|
+
# There is no reset, so need to initialize.
|
36
|
+
[times.width].inner(name => times)
|
37
|
+
end
|
29
38
|
# Get the signal of the counter.
|
30
39
|
counter = get_inner(name)
|
31
40
|
|
@@ -33,51 +42,77 @@ module HDLRuby::High::Std
|
|
33
42
|
# Create the name of the clock.
|
34
43
|
name = HDLRuby.uniq_name
|
35
44
|
# Declares the clock.
|
36
|
-
|
45
|
+
if @@__clocks_rst then
|
46
|
+
# There is a reset, so no need to initialize.
|
47
|
+
bit.inner(name)
|
48
|
+
else
|
49
|
+
# There is no reset, so need to initialize.
|
50
|
+
bit.inner(name => times)
|
51
|
+
end
|
37
52
|
# Get the signal of the clock.
|
38
53
|
clock = get_inner(name)
|
39
54
|
|
40
55
|
# Control it.
|
41
56
|
par(event) do
|
42
|
-
|
43
|
-
|
44
|
-
|
45
|
-
|
46
|
-
|
47
|
-
|
48
|
-
|
49
|
-
|
50
|
-
|
51
|
-
|
57
|
+
if @@__clocks_rst then
|
58
|
+
# There is a reset, handle it.
|
59
|
+
hif(@@__clocks_rst) do
|
60
|
+
counter <= times
|
61
|
+
clock <= 0
|
62
|
+
end
|
63
|
+
helsif(counter.to_expr == 0) do
|
64
|
+
counter <= times
|
65
|
+
clock <= ~ clock
|
66
|
+
end
|
67
|
+
helse do
|
68
|
+
counter <= counter - 1
|
69
|
+
end
|
70
|
+
else
|
71
|
+
# There is no reset.
|
72
|
+
hif(counter == 0) do
|
73
|
+
counter <= times
|
74
|
+
clock <= ~ clock
|
75
|
+
end
|
76
|
+
helse do
|
77
|
+
counter <= counter - 1
|
78
|
+
end
|
52
79
|
end
|
53
80
|
end
|
54
81
|
end
|
55
82
|
return clock
|
56
83
|
end
|
57
84
|
|
58
|
-
# module clk_div3(clk,reset, clk_out);
|
59
|
-
|
60
|
-
# input clk;
|
61
|
-
# input reset;
|
62
|
-
# output clk_out;
|
63
|
-
|
64
|
-
# reg [1:0] pos_count, neg_count;
|
65
|
-
# wire [1:0] r_nxt;
|
66
|
-
|
67
|
-
# always @(posedge clk)
|
68
|
-
# if (reset)
|
69
|
-
# pos_count <=0;
|
70
|
-
# else if (pos_count ==2) pos_count <= 0;
|
71
|
-
# else pos_count<= pos_count +1;
|
72
85
|
|
73
|
-
|
74
|
-
|
75
|
-
|
76
|
-
|
77
|
-
|
86
|
+
# https://referencedesigner.com/tutorials/verilogexamples/verilog_ex_07.php
|
87
|
+
#
|
88
|
+
# module clk_divn #(
|
89
|
+
# parameter WIDTH = 3,
|
90
|
+
# parameter N = 5)
|
91
|
+
#
|
92
|
+
# (clk,reset, clk_out);
|
93
|
+
#
|
94
|
+
# input clk;
|
95
|
+
# input reset;
|
96
|
+
# output clk_out;
|
97
|
+
#
|
98
|
+
# reg [WIDTH-1:0] pos_count, neg_count;
|
99
|
+
# wire [WIDTH-1:0] r_nxt;
|
100
|
+
#
|
101
|
+
# always @(posedge clk)
|
102
|
+
# if (reset)
|
103
|
+
# pos_count <=0;
|
104
|
+
# else if (pos_count ==N-1) pos_count <= 0;
|
105
|
+
# else pos_count<= pos_count +1;
|
106
|
+
#
|
107
|
+
# always @(negedge clk)
|
108
|
+
# if (reset)
|
109
|
+
# neg_count <=0;
|
110
|
+
# else if (neg_count ==N-1) neg_count <= 0;
|
111
|
+
# else neg_count<= neg_count +1;
|
112
|
+
#
|
113
|
+
# assign clk_out = ((pos_count > (N>>1)) | (neg_count > (N>>1)));
|
114
|
+
# endmodule
|
78
115
|
|
79
|
-
# assign clk_out = ((pos_count == 2) | (neg_count == 2));
|
80
|
-
# endmodule
|
81
116
|
|
82
117
|
# Creates a clock inverted every +times+ occurence of an +event+ and its
|
83
118
|
# everted.
|
@@ -87,13 +122,22 @@ module HDLRuby::High::Std
|
|
87
122
|
# Enters the current system
|
88
123
|
HDLRuby::High.cur_system.open do
|
89
124
|
# Ensure times is a value.
|
90
|
-
times = times.to_value
|
125
|
+
times = times.to_value
|
126
|
+
if (times == 1) then
|
127
|
+
AnyError.new("Clock multiplier must be >= 2.")
|
128
|
+
end
|
91
129
|
|
92
130
|
# Create the event counter.
|
93
131
|
# Create the name of the counter.
|
94
132
|
name = HDLRuby.uniq_name
|
95
133
|
# Declare the counter.
|
96
|
-
|
134
|
+
if @@__clocks_rst then
|
135
|
+
# There is a reset, so no need to initialize.
|
136
|
+
[times.width].inner(name)
|
137
|
+
else
|
138
|
+
# There is no reset, so need to initialize.
|
139
|
+
[times.width].inner(name => 0)
|
140
|
+
end
|
97
141
|
# Get the signal of the counter.
|
98
142
|
counter = get_inner(name)
|
99
143
|
|
@@ -101,7 +145,13 @@ module HDLRuby::High::Std
|
|
101
145
|
# Create the name of the counter.
|
102
146
|
name = HDLRuby.uniq_name
|
103
147
|
# Declare the counter.
|
104
|
-
|
148
|
+
if @@__clocks_rst then
|
149
|
+
# There is a reset, so no need to initialize.
|
150
|
+
[times.width].inner(name)
|
151
|
+
else
|
152
|
+
# There is no reset, so need to initialize.
|
153
|
+
[times.width].inner(name => 0)
|
154
|
+
end
|
105
155
|
# Get the signal of the counter.
|
106
156
|
counter_inv = get_inner(name)
|
107
157
|
|
@@ -109,32 +159,50 @@ module HDLRuby::High::Std
|
|
109
159
|
# Create the name of the clock.
|
110
160
|
name = HDLRuby.uniq_name
|
111
161
|
# Declare the clock.
|
112
|
-
|
162
|
+
if @@__clocks_rst then
|
163
|
+
# There is a reset, so no need to initialize.
|
164
|
+
bit.inner(name)
|
165
|
+
else
|
166
|
+
# There is no reset, so need to initialize.
|
167
|
+
bit.inner(name => 0)
|
168
|
+
end
|
113
169
|
# Get the signal of the clock.
|
114
170
|
clock = get_inner(name)
|
115
171
|
|
116
|
-
# Control the
|
172
|
+
# Control the even counter.
|
117
173
|
par(event) do
|
118
|
-
|
119
|
-
counter
|
174
|
+
if @@__clocks_rst then
|
175
|
+
hif(@@__clocks_rst) { counter <= 0 }
|
176
|
+
helsif(counter == times-1) { counter <= 0 }
|
177
|
+
helse { counter <= counter + 1 }
|
178
|
+
else
|
179
|
+
hif(counter == times-1) { counter <= 0 }
|
180
|
+
helse { counter <= counter + 1 }
|
120
181
|
end
|
121
182
|
end
|
122
|
-
|
183
|
+
|
184
|
+
# Control the odd counter.
|
123
185
|
par(event.invert) do
|
124
|
-
|
125
|
-
counter_inv
|
186
|
+
if @@__clocks_rst then
|
187
|
+
hif(@@__clocks_rst) { counter_inv <= 0 }
|
188
|
+
helsif(counter == times-1) { counter_inv <= 0 }
|
189
|
+
helse { counter_inv <= counter_inv + 1 }
|
190
|
+
else
|
191
|
+
hif(counter == times-1) { counter_inv <= 0 }
|
192
|
+
helse { counter_inv <= counter_inv + 1 }
|
126
193
|
end
|
127
194
|
end
|
128
|
-
|
129
|
-
clock
|
130
|
-
(counter_inv.to_expr == times.to_expr/2 + 1)
|
195
|
+
|
196
|
+
clock <= ((counter > (times/2)) | (counter_inv > (times/2)))
|
131
197
|
end
|
132
|
-
# Return
|
198
|
+
# Return the clock.
|
133
199
|
return clock
|
134
200
|
end
|
201
|
+
|
135
202
|
end
|
136
203
|
|
137
204
|
|
205
|
+
|
138
206
|
class HDLRuby::High::Event
|
139
207
|
# Enhance the events with multiply operator.
|
140
208
|
|
data/lib/HDLRuby/std/std.rb
CHANGED
@@ -4,6 +4,8 @@
|
|
4
4
|
#
|
5
5
|
########################################################################
|
6
6
|
|
7
|
+
# Hardware libraries.
|
8
|
+
|
7
9
|
require 'std/clocks.rb'
|
8
10
|
require 'std/fixpoint.rb'
|
9
11
|
require 'std/decoder.rb'
|
@@ -12,3 +14,6 @@ require 'std/sequencer.rb'
|
|
12
14
|
require 'std/sequencer_channel.rb'
|
13
15
|
require 'std/sequencer_sync.rb'
|
14
16
|
require 'std/sequencer_func.rb'
|
17
|
+
|
18
|
+
# User interface libraries.
|
19
|
+
require 'ui/hruby_board.rb'
|