HDLRuby 3.2.0 → 3.3.0

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Files changed (44) hide show
  1. checksums.yaml +4 -4
  2. data/README.html +2330 -2670
  3. data/README.md +391 -101
  4. data/ext/hruby_sim/hruby_rcsim_build.c +400 -3
  5. data/ext/hruby_sim/hruby_sim.h +2 -1
  6. data/ext/hruby_sim/hruby_sim_calc.c +1 -1
  7. data/ext/hruby_sim/hruby_sim_core.c +15 -5
  8. data/ext/hruby_sim/hruby_sim_tree_calc.c +1 -1
  9. data/lib/HDLRuby/hdr_samples/c_program/echo.c +33 -0
  10. data/lib/HDLRuby/hdr_samples/ruby_program/echo.rb +9 -0
  11. data/lib/HDLRuby/hdr_samples/ruby_program/stdrw.rb +6 -0
  12. data/lib/HDLRuby/hdr_samples/ruby_program/sw_cpu_terminal.rb +614 -0
  13. data/lib/HDLRuby/hdr_samples/ruby_program/sw_inc_mem.rb +32 -0
  14. data/lib/HDLRuby/hdr_samples/ruby_program/sw_log.rb +33 -0
  15. data/lib/HDLRuby/hdr_samples/with_board.rb +63 -0
  16. data/lib/HDLRuby/hdr_samples/with_clocks.rb +42 -0
  17. data/lib/HDLRuby/hdr_samples/with_of.rb +1 -1
  18. data/lib/HDLRuby/hdr_samples/with_program_c.rb +28 -0
  19. data/lib/HDLRuby/hdr_samples/with_program_ruby.rb +28 -0
  20. data/lib/HDLRuby/hdr_samples/with_program_ruby_cpu.rb +234 -0
  21. data/lib/HDLRuby/hdr_samples/with_program_ruby_io.rb +23 -0
  22. data/lib/HDLRuby/hdr_samples/with_program_ruby_mem.rb +58 -0
  23. data/lib/HDLRuby/hdr_samples/with_program_ruby_threads.rb +56 -0
  24. data/lib/HDLRuby/hdr_samples/with_sequencer_func.rb +2 -4
  25. data/lib/HDLRuby/hdrcc.rb +60 -21
  26. data/lib/HDLRuby/hruby_error.rb +13 -0
  27. data/lib/HDLRuby/hruby_high.rb +50 -7
  28. data/lib/HDLRuby/hruby_low.rb +74 -30
  29. data/lib/HDLRuby/hruby_rcsim.rb +89 -5
  30. data/lib/HDLRuby/std/clocks.rb +118 -50
  31. data/lib/HDLRuby/std/std.rb +5 -0
  32. data/lib/HDLRuby/ui/hruby_board.rb +1079 -0
  33. data/lib/HDLRuby/version.rb +1 -1
  34. data/lib/c/Rakefile +8 -0
  35. data/lib/c/cHDL.h +12 -0
  36. data/lib/c/extconf.rb +7 -0
  37. data/lib/rubyHDL.rb +33 -0
  38. data/tuto/gui_accum.png +0 -0
  39. data/tuto/gui_board.png +0 -0
  40. data/tuto/tutorial_sw.html +2263 -1890
  41. data/tuto/tutorial_sw.md +957 -62
  42. metadata +24 -5
  43. data/README.pdf +0 -0
  44. data/tuto/tutorial_sw.pdf +0 -0
@@ -0,0 +1,63 @@
1
+
2
+ # A benchmark for testing the use of a board model implementing:
3
+ # * a simple adder whose input are set using slide switches, and
4
+ # whose output bits are showns on LEDs.
5
+ # * simple unsigned and signed counters whose values are shown using
6
+ # decimal or hexadecimal displays, and oscilloscopes.
7
+ system :with_board do
8
+ inner :clk, :clk2
9
+ [8].inner clk_cnt: 0
10
+ inner rst: 0
11
+ [8].inner :sw_a, :sw_b
12
+ [9].inner :led_z
13
+ [16].inner counter: 0
14
+ [8].inner :counter8
15
+ signed[8].inner :scounter8
16
+
17
+ # Description of the board.
18
+ # It is updated at each rising edge of +clk2+.
19
+ board(:some_board) do
20
+ actport clk2.posedge
21
+ bt reset: rst
22
+ row
23
+ sw sw_a: sw_a
24
+ sw sw_b: sw_b
25
+ led led_z: led_z
26
+ row
27
+ digit cnt_d: counter
28
+ hexa cnt_h: counter
29
+ digit cnt_s: scounter8
30
+ row
31
+ scope scope: counter8
32
+ scope scope_s:scounter8
33
+ end
34
+
35
+ # The adder.
36
+ led_z <= sw_a.as(bit[9]) + sw_b
37
+
38
+ # The counters and the generation of +clk2+.
39
+ counter8 <= counter[7..0]
40
+ scounter8 <= counter[7..0]
41
+
42
+ seq(clk.posedge) do
43
+ hif(rst) { counter <= 0 }
44
+ helse { counter <= counter + 1 }
45
+ clk_cnt <= clk_cnt + 1
46
+ hif(clk_cnt & 3 == 0) { clk2 <= ~clk2 }
47
+ end
48
+
49
+
50
+
51
+ timed do
52
+ clk <= 0
53
+ clk2 <= 0
54
+ !10.ns
55
+ repeat(1000) do
56
+ clk <= 1
57
+ !10.ns
58
+ clk <= 0
59
+ !10.ns
60
+ end
61
+
62
+ end
63
+ end
@@ -0,0 +1,42 @@
1
+ # A system for testing the clock generator.
2
+ system :with_clocks do
3
+ inner :clk, :rst
4
+ [8].inner :cnt1, :cnt2, :cnt3, :cnt4, :cnt5
5
+ [8].inner :cnta, :cntb, :cntc, :cntd
6
+
7
+ configure_clocks(rst)
8
+
9
+ (cnt1 <= cnt1 + 1).at(clk.posedge)
10
+ (cnt2 <= cnt2 + 1).at(clk.posedge*2)
11
+ (cnt3 <= cnt3 + 1).at(clk.posedge*3)
12
+ (cnt4 <= cnt4 + 1).at(clk.posedge*4)
13
+ (cnt5 <= cnt5 + 1).at(clk.posedge*5)
14
+
15
+ configure_clocks(nil)
16
+
17
+ (cnta <= cnta + 1).at(clk.posedge*2)
18
+ (cntb <= cntb + 1).at(clk.posedge*3)
19
+ (cntc <= cntc + 1).at(clk.posedge*4)
20
+ (cntd <= cntd + 1).at(clk.posedge*5)
21
+
22
+ timed do
23
+ clk <= 0
24
+ rst <= 0
25
+ !10.ns
26
+ clk <= 1
27
+ !10.ns
28
+ clk <= 0
29
+ rst <= 1
30
+ cnt1 <= 0; cnt2 <= 0; cnt3 <= 0; cnt4 <= 0; cnt5 <= 0
31
+ cnta <= 0; cntb <= 0; cntc <= 0; cntd <= 0
32
+ !10.ns
33
+ clk <= 1
34
+ !10.ns
35
+ clk <= 0
36
+ rst <= 0
37
+ repeat(100) do
38
+ !10.ns
39
+ clk <= ~clk
40
+ end
41
+ end
42
+ end
@@ -28,7 +28,7 @@ end
28
28
 
29
29
 
30
30
  # A system for testing inheritance and of?
31
- system :with_reconf do
31
+ system :with_of do
32
32
  input :clk,:rst
33
33
  input :d
34
34
  output :q
@@ -0,0 +1,28 @@
1
+
2
+ # A benchmark for testing the use of Ruby software code.
3
+ system :with_ruby_prog do
4
+ inner :clk
5
+ [8].inner :count, :echo
6
+
7
+ program(:c,:echo) do
8
+ actport clk.posedge
9
+ inport inP: count
10
+ outport outP: echo
11
+ code "c_program/c_program"
12
+ end
13
+
14
+
15
+ timed do
16
+ clk <= 0
17
+ count <= 0
18
+ !10.ns
19
+ repeat(10) do
20
+ clk <= 1
21
+ !10.ns
22
+ count <= count + 1
23
+ clk <= 0
24
+ !10.ns
25
+ end
26
+
27
+ end
28
+ end
@@ -0,0 +1,28 @@
1
+
2
+ # A benchmark for testing the use of Ruby software code.
3
+ system :with_ruby_prog do
4
+ inner :clk
5
+ [8].inner :count, :echo
6
+
7
+ program(:ruby,:echo) do
8
+ actport clk.posedge
9
+ inport inP: count
10
+ outport outP: echo
11
+ code "ruby_program/echo.rb"
12
+ end
13
+
14
+
15
+ timed do
16
+ clk <= 0
17
+ count <= 0
18
+ !10.ns
19
+ repeat(10) do
20
+ clk <= 1
21
+ !10.ns
22
+ count <= count + 1
23
+ clk <= 0
24
+ !10.ns
25
+ end
26
+
27
+ end
28
+ end
@@ -0,0 +1,234 @@
1
+
2
+ # A benchmark for testing the use of Ruby software code.
3
+ system :with_ruby_prog_cpu do
4
+ ## The processor interface signals.
5
+
6
+ inner :sim # The signal configuring the simulation.
7
+
8
+ inner :clk, :rst
9
+ inner :br, :bg, :rwb
10
+ [16].inner :addr
11
+ [8].inner :dout #, :din
12
+ inner :req, :ack
13
+
14
+ [8].inner :key_reg # Memory-mapped register containing the latest key.
15
+
16
+ ## The configuration parameters.
17
+ [9].inner :hSIZE, :hSTART, :hEND # Display horizontal size and borders.
18
+ [8].inner :vSIZE, :vSTART, :vEND # Display vertical size and borders.
19
+ [8].inner :rxCYCLE # Time for transmitting one bit with the UART
20
+ [16].inner :vADDR, :kADDR # The display and keyboard start addresses
21
+
22
+ program(:ruby,:configure) do
23
+ actport sim.posedge
24
+ outport hSIZE: hSIZE, hSTART: hSTART, hEND: hEND
25
+ outport vSIZE: vSIZE, vSTART: vSTART, vEND: vEND
26
+ outport rxCYCLE: rxCYCLE
27
+ outport vADDR: vADDR, kADDR: kADDR
28
+ code "ruby_program/sw_cpu_terminal.rb"
29
+ end
30
+
31
+ ## The processor model.
32
+
33
+ # This is the bus part of the CPU.
34
+ program(:ruby,:cpu_bus) do
35
+ actport clk.posedge
36
+ inport br: br # Bus request
37
+ outport bg: bg # Bus granted
38
+ inport ain: addr
39
+ inport aout: addr
40
+ inport rwb: rwb
41
+ # inport din: din
42
+ outport dout: dout
43
+
44
+ inport key_reg: key_reg
45
+
46
+ code "ruby_program/sw_cpu_terminal.rb"
47
+ end
48
+
49
+ # This is the reset part of the CPU.
50
+ program(:ruby, :cpu_rst) do
51
+ actport rst.posedge
52
+ code "ruby_program/sw_cpu_terminal.rb"
53
+ end
54
+
55
+ # This is the interrupt part of the CPU.
56
+ program(:ruby,:cpu_irq) do
57
+ actport req.posedge
58
+ outport ack: ack
59
+ code "ruby_program/sw_cpu_terminal.rb"
60
+ end
61
+
62
+
63
+ ## Simplistic circuitry that generates a monochrome video signal
64
+ # For a 320x200 screen with 512-320 pixels horizontal blank and
65
+ # 256-200 lines vertical blank and centered screen.
66
+ # The memory bus is requested at the begining of a line, and if it is
67
+ # not granted on time the pixels are skipped.
68
+
69
+ [1].inner :vclk_count
70
+ inner :vclk
71
+ [9].inner :hcount
72
+ [8].inner :vcount
73
+ [16].inner :vaddr
74
+ inner :hblank, :vblank
75
+ [8].inner :pixel
76
+
77
+ # Generate the video clock: every 4 cycles (for not too long simulation).
78
+ # NOTE: requires reset to last two cycles or more.
79
+ seq(clk.posedge) do
80
+ hif(rst) { vclk_count <= 0; vclk <=0 }
81
+ helse do
82
+ vclk_count <= vclk_count + 1
83
+ hif(vclk_count == 1) { vclk <= ~vclk }
84
+ end
85
+ end
86
+
87
+ # Generates the signal.
88
+ seq(vclk.posedge,rst.posedge) do
89
+ hif(rst) do
90
+ hcount <= 0; vcount <= 0
91
+ hblank <= 0; vblank <= 0
92
+ vaddr <= vADDR
93
+ pixel <= 0
94
+ end
95
+ helse do
96
+ hif((hcount >= hSIZE + hSTART) | (hcount < hSTART)) { hblank <= 1 }
97
+ hif((vcount >= vSIZE + vSTART) | (vcount < vSTART)) { vblank <= 1 }
98
+ hif((hcount < hSIZE+hSTART) & (vcount < vSIZE+vSTART) & (vcount >= vSTART)) { br <= 1 } #; rwb <= 1 }
99
+ helse { br <= 0} #; rwb <= 0 }
100
+ hif((hcount >= hSTART) & (hcount < hSIZE+hSTART) &
101
+ (vcount >= vSTART) & (vcount < vSIZE+vSTART)) do
102
+ hblank <= 0; vblank <= 0
103
+ hif(bg) { pixel <= dout }
104
+ vaddr <= vaddr + 1
105
+ end
106
+ hcount <= hcount + 1
107
+ hif(hcount >= hSIZE+hSTART+hEND) do
108
+ hcount <= 0
109
+ vcount <= vcount + 1
110
+ hif (vcount >= vSIZE+vSTART+vEND) do
111
+ vcount <= 0
112
+ vaddr <= vADDR
113
+ end
114
+ end
115
+ end
116
+ end
117
+
118
+ # Connect to the memory as well as the keyboard register.
119
+ rwb <= mux(bg, _b0, _b1)
120
+ # addr <= mux(bg, kADDR, vaddr)
121
+ addr <= mux(bg, _hzz, vaddr)
122
+
123
+ # # Connect the key register.
124
+ # din <= mux(~bg, _hzz, key_reg)
125
+
126
+ # This is the monitor simulator.
127
+ program(:ruby,:monitor) do
128
+ actport vclk.negedge
129
+ inport vblank: vblank, hblank: hblank, pixel: pixel
130
+ code "ruby_program/sw_cpu_terminal.rb"
131
+ end
132
+
133
+
134
+ ## Simplisitic circuitry that receives bytes from a UART and write them
135
+ # into a memory-map register before raising an interrupt.
136
+ # Only 8-bit values, and no parity.
137
+
138
+ # The clock signal generation of the keyboard device
139
+ [2].inner :uclk_count
140
+ inner :uclk, :urst
141
+
142
+ # Generate the UART chip clock: every 8 cycles (for not too long
143
+ # simulation).
144
+ seq(clk.posedge) do
145
+ hif(rst) { uclk_count <= 0; uclk <= 0; urst <= 1 }
146
+ helse do
147
+ uclk_count <= uclk_count + 1
148
+ hif(uclk_count == 1) { uclk <= ~uclk }
149
+ hif(uclk_count == 0) { urst <= 0 }
150
+ end
151
+ end
152
+
153
+ # The UART signals.
154
+ inner :rx
155
+
156
+ # This is the UART keyboard simulator.
157
+ program(:ruby,:keyboard) do
158
+ actport uclk.negedge
159
+ outport rx: rx
160
+ code "ruby_program/sw_cpu_terminal.rb"
161
+ end
162
+
163
+ # The signals for getting key values from UART
164
+ [2].inner :rx_bit_count # The received bit count.
165
+ [8].inner :rx_bits # The rx bit buffer (a shift register).
166
+
167
+ # The sequencer receiving the keyboard data and writing the to a
168
+ # memory-mapped register.
169
+ sequencer(uclk.posedge,urst) do
170
+ sloop do
171
+ # At first no interrupt and nothing received yet.
172
+ req <= 0
173
+ rx_bit_count <= 0
174
+ rx_bits <= 0
175
+ key_reg <= 0
176
+
177
+ # Wait for a start bit: falling edge of rx.
178
+ swhile(rx != 0)
179
+ # Now can get the 8 bits.
180
+ 8.stimes do
181
+ # Wait one Rx cycle.
182
+ rxCYCLE.stimes;
183
+ # Get one bit.
184
+ rx_bits <= [rx_bits[6..0],rx]
185
+ end
186
+ # All is done, wait end of transmission.
187
+ swhile(rx == 0)
188
+ # Save the received value.
189
+ key_reg <= rx_bits
190
+ # And wait the computer is ready to receive an interrupt
191
+ # and the BUS is not used by the video chip.
192
+ swhile((ack == 1) | (rwb == 1) )
193
+ # Now raise an interrupt.
194
+ req <= 1
195
+ # Wait for its process to start.
196
+ swhile(ack != 0)
197
+ end
198
+ end
199
+
200
+
201
+
202
+
203
+ ## The simulation part.
204
+
205
+ timed do
206
+ clk <= 0
207
+ rst <= 0
208
+ sim <= 0
209
+ !10.ns
210
+ sim <= 1
211
+ !10.ns
212
+ sim <= 0
213
+ repeat(5) do
214
+ !10.ns
215
+ clk <= 1
216
+ !10.ns
217
+ clk <= 0
218
+ end
219
+ rst <= 1
220
+ repeat(5) do
221
+ !10.ns
222
+ clk <= 1
223
+ !10.ns
224
+ clk <= 0
225
+ end
226
+ rst <= 0
227
+ repeat(10_000_000) do
228
+ !10.ns
229
+ clk <= 1
230
+ !10.ns
231
+ clk <= 0
232
+ end
233
+ end
234
+ end
@@ -0,0 +1,23 @@
1
+ system :accum do
2
+ inner :clk
3
+ [32].inner :sigI, :sigO
4
+
5
+ program(:ruby,:stdrw) do
6
+ actport clk.posedge
7
+ outport sigI: sigI
8
+ inport sigO: sigO
9
+ code "ruby_program/stdrw.rb"
10
+ end
11
+
12
+ (sigO <= sigO+sigI).at(clk.negedge)
13
+
14
+ timed do
15
+ clk <= 0
16
+ sigO <= 0
17
+ sigI <= 0
18
+ repeat(10) do
19
+ !10.ns
20
+ clk <= ~clk
21
+ end
22
+ end
23
+ end
@@ -0,0 +1,58 @@
1
+
2
+ # A benchmark for testing the use of Ruby software code.
3
+ system :with_ruby_prog_mem do
4
+ inner :clk, :req, :rwb
5
+ [8].inner :addr, :index, :count, :data
6
+
7
+ # This is actually a CPU embedded memory.
8
+ program(:ruby,:mem) do
9
+ actport clk.posedge
10
+ inport addr: addr
11
+ inport rwb: rwb
12
+ inport din: count
13
+ outport dout: data
14
+ code "ruby_program/sw_inc_mem.rb"
15
+ end
16
+
17
+ # This is real software.
18
+ program(:ruby,:inc_mem) do
19
+ actport req.posedge
20
+ inport index: index
21
+ code "ruby_program/sw_inc_mem.rb"
22
+ end
23
+
24
+
25
+ timed do
26
+ clk <= 0
27
+ addr <= 0
28
+ index <= 0
29
+ req <= 0
30
+ count <= 0
31
+ rwb <= 0
32
+ !10.ns
33
+ req <= 1
34
+ !10.ns
35
+ repeat(10) do
36
+ clk <= 1
37
+ req <= 0
38
+ !10.ns
39
+ req <= 1
40
+ clk <= 0
41
+ count <= count + 2
42
+ addr <= addr + 1
43
+ !10.ns
44
+ index <= index + 1
45
+ end
46
+ !10.ns
47
+ addr <= 0
48
+ clk <= 0
49
+ rwb <= 1
50
+ repeat(10) do
51
+ !10.ns
52
+ clk <= 1
53
+ !10.ns
54
+ clk <= 0
55
+ addr <= addr + 1
56
+ end
57
+ end
58
+ end
@@ -0,0 +1,56 @@
1
+
2
+ # A benchmark for testing the use of Ruby software code.
3
+ system :with_ruby_thread do
4
+ inner :clk, :rst, :req, :ack
5
+ [8].inner :count
6
+
7
+ program(:ruby,:boot) do
8
+ actport rst.negedge
9
+ inport din: count
10
+ outport ack: ack
11
+ code "ruby_program/sw_log.rb"
12
+ end
13
+
14
+ program(:ruby,:log) do
15
+ actport req.posedge
16
+ code "ruby_program/sw_log.rb"
17
+ end
18
+
19
+ par(ack.posedge) { count <= count + 1 }
20
+
21
+
22
+ timed do
23
+ clk <= 0
24
+ rst <= 0
25
+ count <= 0
26
+ req <= 0
27
+ !10.ns
28
+ clk <= 1
29
+ !10.ns
30
+ clk <= 0
31
+ rst <= 1
32
+ !10.ns
33
+ clk <= 1
34
+ !10.ns
35
+ clk <= 0
36
+ rst <= 0
37
+ !10.ns
38
+ clk <= 1
39
+ !10.ns
40
+ clk <= 0
41
+ !10.ns
42
+ repeat(100) do
43
+ clk <= 1
44
+ req <= 1
45
+ !10.ns
46
+ clk <= 0
47
+ !10.ns
48
+ clk <= 1
49
+ req <= 0
50
+ !10.ns
51
+ clk <= 0
52
+ !10.ns
53
+ end
54
+
55
+ end
56
+ end
@@ -1,7 +1,3 @@
1
- require 'std/sequencer_func.rb'
2
-
3
- include HDLRuby::High::Std
4
-
5
1
 
6
2
  # A factorial with default stack depth.
7
3
  sdef(:fact) do |n|
@@ -31,11 +27,13 @@ system :my_seqencer do
31
27
  5.stimes do |i|
32
28
  val <= i
33
29
  res <= fact(val)
30
+ hprint("res=",res,"\n")
34
31
  end
35
32
  hprint("Going to overflow...\n")
36
33
  4.stimes do |i|
37
34
  val <= i
38
35
  res <= fact_over(val)
36
+ hprint("res=",res,"\n")
39
37
  end
40
38
  hprint("stack_overflow_error=",stack_overflow_error,"\n")
41
39
  end
data/lib/HDLRuby/hdrcc.rb CHANGED
@@ -37,19 +37,19 @@ if ARGV.include?("-I") || ARGV.include?("--interactive") then
37
37
  end
38
38
 
39
39
 
40
- begin
41
- # We can check the memory.
42
- require 'get_process_mem'
43
- $memory_check = GetProcessMem.new
44
- def show_mem
45
- " | "+$memory_check.bytes.to_s+"B"
46
- end
47
- rescue LoadError
48
- # We cannot check the memory.
40
+ # begin
41
+ # # We can check the memory.
42
+ # require 'get_process_mem'
43
+ # $memory_check = GetProcessMem.new
44
+ # def show_mem
45
+ # " | "+$memory_check.bytes.to_s+"B"
46
+ # end
47
+ # rescue LoadError
48
+ # # We cannot check the memory.
49
49
  def show_mem
50
50
  ""
51
51
  end
52
- end
52
+ # end
53
53
 
54
54
 
55
55
  require 'fileutils'
@@ -367,25 +367,25 @@ $optparse = OptionParser.new do |opts|
367
367
  opts.on("-r", "--hdr","Output in HDLRuby format") do |v|
368
368
  $options[:hdr] = v
369
369
  end
370
- opts.on("-C", "--clang","Output in C format (simulator)") do |v|
371
- $options[:clang] = v
372
- $options[:multiple] = v
373
- end
374
- opts.on("--allocate=LOW,HIGH,WORD","Allocate signals to addresses") do |v|
375
- $options[:allocate] = v
376
- end
370
+ # opts.on("-C", "--clang","Output in C format (simulator, deprecated)") do |v|
371
+ # $options[:clang] = v
372
+ # $options[:multiple] = v
373
+ # end
374
+ # opts.on("--allocate=LOW,HIGH,WORD","Allocate signals to addresses") do |v|
375
+ # $options[:allocate] = v
376
+ # end
377
377
  opts.on("-S","--sim","Default simulator (hybrid C-Ruby)") do |v|
378
378
  $options[:rcsim] = v
379
379
  $options[:multiple] = v
380
380
  $sim = true
381
381
  end
382
- opts.on("--csim","Standalone C-based simulator") do |v|
382
+ opts.on("--csim","Standalone C-based simulator (deprecated)") do |v|
383
383
  $options[:clang] = v
384
384
  $options[:multiple] = v
385
385
  $options[:csim] = v
386
386
  $sim = true
387
387
  end
388
- opts.on("--rsim","Ruby-based simulator") do |v|
388
+ opts.on("--rsim","Ruby-based simulator (deprecated)") do |v|
389
389
  $options[:rsim] = v
390
390
  $options[:multiple] = v
391
391
  $sim = true
@@ -401,6 +401,33 @@ $optparse = OptionParser.new do |opts|
401
401
  opts.on("--vcd", "The simulator will generate a vcd file") do |v|
402
402
  $options[:vcd] = v
403
403
  end
404
+ opts.on("--ch dir", "Generates the files for compiling a software extension") do |dir|
405
+ # Check the target directory.
406
+ if !dir or dir.empty? then
407
+ raise "Need a program name for generating the compiling files."
408
+ end
409
+ # Create the source path.
410
+ src_path = File.dirname(__FILE__) + "/../c/"
411
+ # Create the target directory.
412
+ Dir.mkdir(dir) unless File.exist?(dir)
413
+ # Copy the header files.
414
+ ## FileUtils.copy(src_path + "cHDL.h",dir)
415
+ # And update it with any empty initialization function
416
+ # (not used but required for compiling for windows).
417
+ lines = nil
418
+ File.open(src_path + "cHDL.h","r") {|f| lines = f.readlines }
419
+ lines = ["void Init_#{dir}() {}\n\n"] + lines
420
+ File.open(dir + "/" + "cHDL.h", "w") {|f| lines.each {|l| f.write(l) } }
421
+ # Copy and modify the files for rake.
422
+ ["extconf.rb", "Rakefile"].each do |fname|
423
+ lines = nil
424
+ File.open(src_path + fname,"r") {|f| lines = f.readlines }
425
+ # puts "Checking dir: #{File.dirname(__FILE__)+"/../hruby_sim/"}"
426
+ lines = ["C_PROGRAM = '#{dir}'\nRCSIM_DIR = '#{File.dirname(__FILE__)+"/../hruby_sim/"}'\n"] + lines
427
+ File.open(dir + "/" + fname, "w") {|f| lines.each {|l| f.write(l) } }
428
+ end
429
+ exit
430
+ end
404
431
  opts.on("-v", "--verilog","Output in Verlog HDL format") do |v|
405
432
  $options[:verilog] = v
406
433
  $options[:multiple] = v
@@ -466,14 +493,26 @@ $optparse = OptionParser.new do |opts|
466
493
  $options[:dump] = v
467
494
  $options[:multiple] = v
468
495
  end
469
- opts.on("--get-samples", "Copy the sample directory (hdr_samples) to current one, the exit") do
496
+ opts.on("--get-samples", "Copy the sample directory (hdr_samples) to current one, then exit") do
470
497
  FileUtils.copy_entry(File.dirname(__FILE__) + "/hdr_samples","./hdr_samples")
498
+ FileUtils.copy_entry(File.dirname(__FILE__) + "/hdr_samples/c_program","./hdr_samples/c_program")
499
+ FileUtils.copy_entry(File.dirname(__FILE__) + "/hdr_samples/ruby_program","./hdr_samples/ruby_program")
500
+ exit
501
+ end
502
+ opts.on("--get-tuto", "Copy the tutorial directory (tuto) to current one, then exit") do
503
+ FileUtils.copy_entry(File.dirname(__FILE__) + "../../tuto","./tuto")
471
504
  exit
472
505
  end
473
506
  opts.on("--version", "Show the version of HDLRuby, then exit") do |v|
474
507
  puts VERSION
475
508
  exit
476
509
  end
510
+ opts.on("--path","Shows the path where HDLRuby is install.") do |v|
511
+ require 'pathname'
512
+ path = Pathname.new(__FILE__ + "../../../../").cleanpath
513
+ puts path.to_s
514
+ exit
515
+ end
477
516
  # opts.on_tail("-h", "--help", "Show this message") do
478
517
  opts.on("-h", "--help", "Show this message") do
479
518
  puts opts
@@ -583,7 +622,7 @@ if $options[:syntax] then
583
622
  $output << $loader.show_all
584
623
  exit
585
624
  end
586
- HDLRuby.show "#{Time.now}#{show_mem}"
625
+ # HDLRuby.show "#{Time.now}#{show_mem}"
587
626
  HDLRuby.show "##### Starting parser #####"
588
627
 
589
628
  if $options[:debug] then