HDLRuby 3.2.0 → 3.3.0
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- checksums.yaml +4 -4
- data/README.html +2330 -2670
- data/README.md +391 -101
- data/ext/hruby_sim/hruby_rcsim_build.c +400 -3
- data/ext/hruby_sim/hruby_sim.h +2 -1
- data/ext/hruby_sim/hruby_sim_calc.c +1 -1
- data/ext/hruby_sim/hruby_sim_core.c +15 -5
- data/ext/hruby_sim/hruby_sim_tree_calc.c +1 -1
- data/lib/HDLRuby/hdr_samples/c_program/echo.c +33 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/echo.rb +9 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/stdrw.rb +6 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/sw_cpu_terminal.rb +614 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/sw_inc_mem.rb +32 -0
- data/lib/HDLRuby/hdr_samples/ruby_program/sw_log.rb +33 -0
- data/lib/HDLRuby/hdr_samples/with_board.rb +63 -0
- data/lib/HDLRuby/hdr_samples/with_clocks.rb +42 -0
- data/lib/HDLRuby/hdr_samples/with_of.rb +1 -1
- data/lib/HDLRuby/hdr_samples/with_program_c.rb +28 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby.rb +28 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_cpu.rb +234 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_io.rb +23 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_mem.rb +58 -0
- data/lib/HDLRuby/hdr_samples/with_program_ruby_threads.rb +56 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_func.rb +2 -4
- data/lib/HDLRuby/hdrcc.rb +60 -21
- data/lib/HDLRuby/hruby_error.rb +13 -0
- data/lib/HDLRuby/hruby_high.rb +50 -7
- data/lib/HDLRuby/hruby_low.rb +74 -30
- data/lib/HDLRuby/hruby_rcsim.rb +89 -5
- data/lib/HDLRuby/std/clocks.rb +118 -50
- data/lib/HDLRuby/std/std.rb +5 -0
- data/lib/HDLRuby/ui/hruby_board.rb +1079 -0
- data/lib/HDLRuby/version.rb +1 -1
- data/lib/c/Rakefile +8 -0
- data/lib/c/cHDL.h +12 -0
- data/lib/c/extconf.rb +7 -0
- data/lib/rubyHDL.rb +33 -0
- data/tuto/gui_accum.png +0 -0
- data/tuto/gui_board.png +0 -0
- data/tuto/tutorial_sw.html +2263 -1890
- data/tuto/tutorial_sw.md +957 -62
- metadata +24 -5
- data/README.pdf +0 -0
- data/tuto/tutorial_sw.pdf +0 -0
@@ -0,0 +1,63 @@
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# A benchmark for testing the use of a board model implementing:
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# * a simple adder whose input are set using slide switches, and
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# whose output bits are showns on LEDs.
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# * simple unsigned and signed counters whose values are shown using
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# decimal or hexadecimal displays, and oscilloscopes.
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system :with_board do
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inner :clk, :clk2
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[8].inner clk_cnt: 0
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inner rst: 0
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[8].inner :sw_a, :sw_b
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[9].inner :led_z
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[16].inner counter: 0
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[8].inner :counter8
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signed[8].inner :scounter8
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# Description of the board.
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# It is updated at each rising edge of +clk2+.
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board(:some_board) do
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actport clk2.posedge
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bt reset: rst
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row
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sw sw_a: sw_a
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sw sw_b: sw_b
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led led_z: led_z
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row
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digit cnt_d: counter
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hexa cnt_h: counter
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digit cnt_s: scounter8
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row
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scope scope: counter8
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scope scope_s:scounter8
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end
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# The adder.
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led_z <= sw_a.as(bit[9]) + sw_b
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# The counters and the generation of +clk2+.
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counter8 <= counter[7..0]
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scounter8 <= counter[7..0]
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seq(clk.posedge) do
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hif(rst) { counter <= 0 }
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helse { counter <= counter + 1 }
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clk_cnt <= clk_cnt + 1
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hif(clk_cnt & 3 == 0) { clk2 <= ~clk2 }
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end
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timed do
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clk <= 0
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clk2 <= 0
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!10.ns
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repeat(1000) do
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clk <= 1
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!10.ns
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clk <= 0
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!10.ns
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end
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end
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end
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# A system for testing the clock generator.
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system :with_clocks do
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inner :clk, :rst
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[8].inner :cnt1, :cnt2, :cnt3, :cnt4, :cnt5
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[8].inner :cnta, :cntb, :cntc, :cntd
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configure_clocks(rst)
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(cnt1 <= cnt1 + 1).at(clk.posedge)
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(cnt2 <= cnt2 + 1).at(clk.posedge*2)
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(cnt3 <= cnt3 + 1).at(clk.posedge*3)
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(cnt4 <= cnt4 + 1).at(clk.posedge*4)
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(cnt5 <= cnt5 + 1).at(clk.posedge*5)
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configure_clocks(nil)
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(cnta <= cnta + 1).at(clk.posedge*2)
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(cntb <= cntb + 1).at(clk.posedge*3)
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(cntc <= cntc + 1).at(clk.posedge*4)
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(cntd <= cntd + 1).at(clk.posedge*5)
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timed do
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clk <= 0
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rst <= 0
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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rst <= 1
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cnt1 <= 0; cnt2 <= 0; cnt3 <= 0; cnt4 <= 0; cnt5 <= 0
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cnta <= 0; cntb <= 0; cntc <= 0; cntd <= 0
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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rst <= 0
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repeat(100) do
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!10.ns
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clk <= ~clk
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end
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end
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end
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# A benchmark for testing the use of Ruby software code.
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system :with_ruby_prog do
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inner :clk
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[8].inner :count, :echo
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program(:c,:echo) do
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actport clk.posedge
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inport inP: count
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outport outP: echo
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code "c_program/c_program"
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end
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timed do
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clk <= 0
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count <= 0
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!10.ns
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repeat(10) do
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clk <= 1
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!10.ns
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count <= count + 1
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clk <= 0
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!10.ns
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end
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end
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end
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# A benchmark for testing the use of Ruby software code.
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system :with_ruby_prog do
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inner :clk
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[8].inner :count, :echo
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program(:ruby,:echo) do
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actport clk.posedge
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inport inP: count
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outport outP: echo
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code "ruby_program/echo.rb"
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end
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timed do
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clk <= 0
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count <= 0
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!10.ns
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repeat(10) do
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clk <= 1
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!10.ns
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count <= count + 1
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clk <= 0
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!10.ns
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end
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end
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end
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# A benchmark for testing the use of Ruby software code.
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system :with_ruby_prog_cpu do
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## The processor interface signals.
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inner :sim # The signal configuring the simulation.
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inner :clk, :rst
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inner :br, :bg, :rwb
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[16].inner :addr
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[8].inner :dout #, :din
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inner :req, :ack
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[8].inner :key_reg # Memory-mapped register containing the latest key.
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## The configuration parameters.
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[9].inner :hSIZE, :hSTART, :hEND # Display horizontal size and borders.
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[8].inner :vSIZE, :vSTART, :vEND # Display vertical size and borders.
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[8].inner :rxCYCLE # Time for transmitting one bit with the UART
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[16].inner :vADDR, :kADDR # The display and keyboard start addresses
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program(:ruby,:configure) do
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actport sim.posedge
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outport hSIZE: hSIZE, hSTART: hSTART, hEND: hEND
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outport vSIZE: vSIZE, vSTART: vSTART, vEND: vEND
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outport rxCYCLE: rxCYCLE
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outport vADDR: vADDR, kADDR: kADDR
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code "ruby_program/sw_cpu_terminal.rb"
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end
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## The processor model.
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# This is the bus part of the CPU.
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program(:ruby,:cpu_bus) do
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actport clk.posedge
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inport br: br # Bus request
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outport bg: bg # Bus granted
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inport ain: addr
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inport aout: addr
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inport rwb: rwb
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# inport din: din
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outport dout: dout
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inport key_reg: key_reg
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code "ruby_program/sw_cpu_terminal.rb"
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end
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# This is the reset part of the CPU.
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program(:ruby, :cpu_rst) do
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actport rst.posedge
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code "ruby_program/sw_cpu_terminal.rb"
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end
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# This is the interrupt part of the CPU.
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program(:ruby,:cpu_irq) do
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actport req.posedge
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outport ack: ack
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code "ruby_program/sw_cpu_terminal.rb"
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end
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## Simplistic circuitry that generates a monochrome video signal
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# For a 320x200 screen with 512-320 pixels horizontal blank and
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# 256-200 lines vertical blank and centered screen.
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# The memory bus is requested at the begining of a line, and if it is
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# not granted on time the pixels are skipped.
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[1].inner :vclk_count
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inner :vclk
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[9].inner :hcount
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[8].inner :vcount
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[16].inner :vaddr
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inner :hblank, :vblank
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[8].inner :pixel
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# Generate the video clock: every 4 cycles (for not too long simulation).
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# NOTE: requires reset to last two cycles or more.
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seq(clk.posedge) do
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hif(rst) { vclk_count <= 0; vclk <=0 }
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helse do
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vclk_count <= vclk_count + 1
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hif(vclk_count == 1) { vclk <= ~vclk }
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end
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end
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# Generates the signal.
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seq(vclk.posedge,rst.posedge) do
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hif(rst) do
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hcount <= 0; vcount <= 0
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hblank <= 0; vblank <= 0
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vaddr <= vADDR
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pixel <= 0
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end
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helse do
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hif((hcount >= hSIZE + hSTART) | (hcount < hSTART)) { hblank <= 1 }
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hif((vcount >= vSIZE + vSTART) | (vcount < vSTART)) { vblank <= 1 }
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hif((hcount < hSIZE+hSTART) & (vcount < vSIZE+vSTART) & (vcount >= vSTART)) { br <= 1 } #; rwb <= 1 }
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helse { br <= 0} #; rwb <= 0 }
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hif((hcount >= hSTART) & (hcount < hSIZE+hSTART) &
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(vcount >= vSTART) & (vcount < vSIZE+vSTART)) do
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hblank <= 0; vblank <= 0
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hif(bg) { pixel <= dout }
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vaddr <= vaddr + 1
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end
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hcount <= hcount + 1
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hif(hcount >= hSIZE+hSTART+hEND) do
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hcount <= 0
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vcount <= vcount + 1
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hif (vcount >= vSIZE+vSTART+vEND) do
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vcount <= 0
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vaddr <= vADDR
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end
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end
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end
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end
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# Connect to the memory as well as the keyboard register.
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rwb <= mux(bg, _b0, _b1)
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# addr <= mux(bg, kADDR, vaddr)
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addr <= mux(bg, _hzz, vaddr)
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# # Connect the key register.
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# din <= mux(~bg, _hzz, key_reg)
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# This is the monitor simulator.
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program(:ruby,:monitor) do
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actport vclk.negedge
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inport vblank: vblank, hblank: hblank, pixel: pixel
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code "ruby_program/sw_cpu_terminal.rb"
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end
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## Simplisitic circuitry that receives bytes from a UART and write them
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# into a memory-map register before raising an interrupt.
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# Only 8-bit values, and no parity.
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# The clock signal generation of the keyboard device
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[2].inner :uclk_count
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inner :uclk, :urst
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# Generate the UART chip clock: every 8 cycles (for not too long
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# simulation).
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seq(clk.posedge) do
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hif(rst) { uclk_count <= 0; uclk <= 0; urst <= 1 }
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helse do
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uclk_count <= uclk_count + 1
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hif(uclk_count == 1) { uclk <= ~uclk }
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hif(uclk_count == 0) { urst <= 0 }
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end
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end
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# The UART signals.
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inner :rx
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# This is the UART keyboard simulator.
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program(:ruby,:keyboard) do
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actport uclk.negedge
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outport rx: rx
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code "ruby_program/sw_cpu_terminal.rb"
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end
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# The signals for getting key values from UART
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[2].inner :rx_bit_count # The received bit count.
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[8].inner :rx_bits # The rx bit buffer (a shift register).
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# The sequencer receiving the keyboard data and writing the to a
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# memory-mapped register.
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sequencer(uclk.posedge,urst) do
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sloop do
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# At first no interrupt and nothing received yet.
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req <= 0
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rx_bit_count <= 0
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rx_bits <= 0
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key_reg <= 0
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# Wait for a start bit: falling edge of rx.
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swhile(rx != 0)
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# Now can get the 8 bits.
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8.stimes do
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# Wait one Rx cycle.
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+
rxCYCLE.stimes;
|
183
|
+
# Get one bit.
|
184
|
+
rx_bits <= [rx_bits[6..0],rx]
|
185
|
+
end
|
186
|
+
# All is done, wait end of transmission.
|
187
|
+
swhile(rx == 0)
|
188
|
+
# Save the received value.
|
189
|
+
key_reg <= rx_bits
|
190
|
+
# And wait the computer is ready to receive an interrupt
|
191
|
+
# and the BUS is not used by the video chip.
|
192
|
+
swhile((ack == 1) | (rwb == 1) )
|
193
|
+
# Now raise an interrupt.
|
194
|
+
req <= 1
|
195
|
+
# Wait for its process to start.
|
196
|
+
swhile(ack != 0)
|
197
|
+
end
|
198
|
+
end
|
199
|
+
|
200
|
+
|
201
|
+
|
202
|
+
|
203
|
+
## The simulation part.
|
204
|
+
|
205
|
+
timed do
|
206
|
+
clk <= 0
|
207
|
+
rst <= 0
|
208
|
+
sim <= 0
|
209
|
+
!10.ns
|
210
|
+
sim <= 1
|
211
|
+
!10.ns
|
212
|
+
sim <= 0
|
213
|
+
repeat(5) do
|
214
|
+
!10.ns
|
215
|
+
clk <= 1
|
216
|
+
!10.ns
|
217
|
+
clk <= 0
|
218
|
+
end
|
219
|
+
rst <= 1
|
220
|
+
repeat(5) do
|
221
|
+
!10.ns
|
222
|
+
clk <= 1
|
223
|
+
!10.ns
|
224
|
+
clk <= 0
|
225
|
+
end
|
226
|
+
rst <= 0
|
227
|
+
repeat(10_000_000) do
|
228
|
+
!10.ns
|
229
|
+
clk <= 1
|
230
|
+
!10.ns
|
231
|
+
clk <= 0
|
232
|
+
end
|
233
|
+
end
|
234
|
+
end
|
@@ -0,0 +1,23 @@
|
|
1
|
+
system :accum do
|
2
|
+
inner :clk
|
3
|
+
[32].inner :sigI, :sigO
|
4
|
+
|
5
|
+
program(:ruby,:stdrw) do
|
6
|
+
actport clk.posedge
|
7
|
+
outport sigI: sigI
|
8
|
+
inport sigO: sigO
|
9
|
+
code "ruby_program/stdrw.rb"
|
10
|
+
end
|
11
|
+
|
12
|
+
(sigO <= sigO+sigI).at(clk.negedge)
|
13
|
+
|
14
|
+
timed do
|
15
|
+
clk <= 0
|
16
|
+
sigO <= 0
|
17
|
+
sigI <= 0
|
18
|
+
repeat(10) do
|
19
|
+
!10.ns
|
20
|
+
clk <= ~clk
|
21
|
+
end
|
22
|
+
end
|
23
|
+
end
|
@@ -0,0 +1,58 @@
|
|
1
|
+
|
2
|
+
# A benchmark for testing the use of Ruby software code.
|
3
|
+
system :with_ruby_prog_mem do
|
4
|
+
inner :clk, :req, :rwb
|
5
|
+
[8].inner :addr, :index, :count, :data
|
6
|
+
|
7
|
+
# This is actually a CPU embedded memory.
|
8
|
+
program(:ruby,:mem) do
|
9
|
+
actport clk.posedge
|
10
|
+
inport addr: addr
|
11
|
+
inport rwb: rwb
|
12
|
+
inport din: count
|
13
|
+
outport dout: data
|
14
|
+
code "ruby_program/sw_inc_mem.rb"
|
15
|
+
end
|
16
|
+
|
17
|
+
# This is real software.
|
18
|
+
program(:ruby,:inc_mem) do
|
19
|
+
actport req.posedge
|
20
|
+
inport index: index
|
21
|
+
code "ruby_program/sw_inc_mem.rb"
|
22
|
+
end
|
23
|
+
|
24
|
+
|
25
|
+
timed do
|
26
|
+
clk <= 0
|
27
|
+
addr <= 0
|
28
|
+
index <= 0
|
29
|
+
req <= 0
|
30
|
+
count <= 0
|
31
|
+
rwb <= 0
|
32
|
+
!10.ns
|
33
|
+
req <= 1
|
34
|
+
!10.ns
|
35
|
+
repeat(10) do
|
36
|
+
clk <= 1
|
37
|
+
req <= 0
|
38
|
+
!10.ns
|
39
|
+
req <= 1
|
40
|
+
clk <= 0
|
41
|
+
count <= count + 2
|
42
|
+
addr <= addr + 1
|
43
|
+
!10.ns
|
44
|
+
index <= index + 1
|
45
|
+
end
|
46
|
+
!10.ns
|
47
|
+
addr <= 0
|
48
|
+
clk <= 0
|
49
|
+
rwb <= 1
|
50
|
+
repeat(10) do
|
51
|
+
!10.ns
|
52
|
+
clk <= 1
|
53
|
+
!10.ns
|
54
|
+
clk <= 0
|
55
|
+
addr <= addr + 1
|
56
|
+
end
|
57
|
+
end
|
58
|
+
end
|
@@ -0,0 +1,56 @@
|
|
1
|
+
|
2
|
+
# A benchmark for testing the use of Ruby software code.
|
3
|
+
system :with_ruby_thread do
|
4
|
+
inner :clk, :rst, :req, :ack
|
5
|
+
[8].inner :count
|
6
|
+
|
7
|
+
program(:ruby,:boot) do
|
8
|
+
actport rst.negedge
|
9
|
+
inport din: count
|
10
|
+
outport ack: ack
|
11
|
+
code "ruby_program/sw_log.rb"
|
12
|
+
end
|
13
|
+
|
14
|
+
program(:ruby,:log) do
|
15
|
+
actport req.posedge
|
16
|
+
code "ruby_program/sw_log.rb"
|
17
|
+
end
|
18
|
+
|
19
|
+
par(ack.posedge) { count <= count + 1 }
|
20
|
+
|
21
|
+
|
22
|
+
timed do
|
23
|
+
clk <= 0
|
24
|
+
rst <= 0
|
25
|
+
count <= 0
|
26
|
+
req <= 0
|
27
|
+
!10.ns
|
28
|
+
clk <= 1
|
29
|
+
!10.ns
|
30
|
+
clk <= 0
|
31
|
+
rst <= 1
|
32
|
+
!10.ns
|
33
|
+
clk <= 1
|
34
|
+
!10.ns
|
35
|
+
clk <= 0
|
36
|
+
rst <= 0
|
37
|
+
!10.ns
|
38
|
+
clk <= 1
|
39
|
+
!10.ns
|
40
|
+
clk <= 0
|
41
|
+
!10.ns
|
42
|
+
repeat(100) do
|
43
|
+
clk <= 1
|
44
|
+
req <= 1
|
45
|
+
!10.ns
|
46
|
+
clk <= 0
|
47
|
+
!10.ns
|
48
|
+
clk <= 1
|
49
|
+
req <= 0
|
50
|
+
!10.ns
|
51
|
+
clk <= 0
|
52
|
+
!10.ns
|
53
|
+
end
|
54
|
+
|
55
|
+
end
|
56
|
+
end
|
@@ -1,7 +1,3 @@
|
|
1
|
-
require 'std/sequencer_func.rb'
|
2
|
-
|
3
|
-
include HDLRuby::High::Std
|
4
|
-
|
5
1
|
|
6
2
|
# A factorial with default stack depth.
|
7
3
|
sdef(:fact) do |n|
|
@@ -31,11 +27,13 @@ system :my_seqencer do
|
|
31
27
|
5.stimes do |i|
|
32
28
|
val <= i
|
33
29
|
res <= fact(val)
|
30
|
+
hprint("res=",res,"\n")
|
34
31
|
end
|
35
32
|
hprint("Going to overflow...\n")
|
36
33
|
4.stimes do |i|
|
37
34
|
val <= i
|
38
35
|
res <= fact_over(val)
|
36
|
+
hprint("res=",res,"\n")
|
39
37
|
end
|
40
38
|
hprint("stack_overflow_error=",stack_overflow_error,"\n")
|
41
39
|
end
|
data/lib/HDLRuby/hdrcc.rb
CHANGED
@@ -37,19 +37,19 @@ if ARGV.include?("-I") || ARGV.include?("--interactive") then
|
|
37
37
|
end
|
38
38
|
|
39
39
|
|
40
|
-
begin
|
41
|
-
|
42
|
-
|
43
|
-
|
44
|
-
|
45
|
-
|
46
|
-
|
47
|
-
rescue LoadError
|
48
|
-
|
40
|
+
# begin
|
41
|
+
# # We can check the memory.
|
42
|
+
# require 'get_process_mem'
|
43
|
+
# $memory_check = GetProcessMem.new
|
44
|
+
# def show_mem
|
45
|
+
# " | "+$memory_check.bytes.to_s+"B"
|
46
|
+
# end
|
47
|
+
# rescue LoadError
|
48
|
+
# # We cannot check the memory.
|
49
49
|
def show_mem
|
50
50
|
""
|
51
51
|
end
|
52
|
-
end
|
52
|
+
# end
|
53
53
|
|
54
54
|
|
55
55
|
require 'fileutils'
|
@@ -367,25 +367,25 @@ $optparse = OptionParser.new do |opts|
|
|
367
367
|
opts.on("-r", "--hdr","Output in HDLRuby format") do |v|
|
368
368
|
$options[:hdr] = v
|
369
369
|
end
|
370
|
-
opts.on("-C", "--clang","Output in C format (simulator)") do |v|
|
371
|
-
|
372
|
-
|
373
|
-
end
|
374
|
-
opts.on("--allocate=LOW,HIGH,WORD","Allocate signals to addresses") do |v|
|
375
|
-
|
376
|
-
end
|
370
|
+
# opts.on("-C", "--clang","Output in C format (simulator, deprecated)") do |v|
|
371
|
+
# $options[:clang] = v
|
372
|
+
# $options[:multiple] = v
|
373
|
+
# end
|
374
|
+
# opts.on("--allocate=LOW,HIGH,WORD","Allocate signals to addresses") do |v|
|
375
|
+
# $options[:allocate] = v
|
376
|
+
# end
|
377
377
|
opts.on("-S","--sim","Default simulator (hybrid C-Ruby)") do |v|
|
378
378
|
$options[:rcsim] = v
|
379
379
|
$options[:multiple] = v
|
380
380
|
$sim = true
|
381
381
|
end
|
382
|
-
opts.on("--csim","Standalone C-based simulator") do |v|
|
382
|
+
opts.on("--csim","Standalone C-based simulator (deprecated)") do |v|
|
383
383
|
$options[:clang] = v
|
384
384
|
$options[:multiple] = v
|
385
385
|
$options[:csim] = v
|
386
386
|
$sim = true
|
387
387
|
end
|
388
|
-
opts.on("--rsim","Ruby-based simulator") do |v|
|
388
|
+
opts.on("--rsim","Ruby-based simulator (deprecated)") do |v|
|
389
389
|
$options[:rsim] = v
|
390
390
|
$options[:multiple] = v
|
391
391
|
$sim = true
|
@@ -401,6 +401,33 @@ $optparse = OptionParser.new do |opts|
|
|
401
401
|
opts.on("--vcd", "The simulator will generate a vcd file") do |v|
|
402
402
|
$options[:vcd] = v
|
403
403
|
end
|
404
|
+
opts.on("--ch dir", "Generates the files for compiling a software extension") do |dir|
|
405
|
+
# Check the target directory.
|
406
|
+
if !dir or dir.empty? then
|
407
|
+
raise "Need a program name for generating the compiling files."
|
408
|
+
end
|
409
|
+
# Create the source path.
|
410
|
+
src_path = File.dirname(__FILE__) + "/../c/"
|
411
|
+
# Create the target directory.
|
412
|
+
Dir.mkdir(dir) unless File.exist?(dir)
|
413
|
+
# Copy the header files.
|
414
|
+
## FileUtils.copy(src_path + "cHDL.h",dir)
|
415
|
+
# And update it with any empty initialization function
|
416
|
+
# (not used but required for compiling for windows).
|
417
|
+
lines = nil
|
418
|
+
File.open(src_path + "cHDL.h","r") {|f| lines = f.readlines }
|
419
|
+
lines = ["void Init_#{dir}() {}\n\n"] + lines
|
420
|
+
File.open(dir + "/" + "cHDL.h", "w") {|f| lines.each {|l| f.write(l) } }
|
421
|
+
# Copy and modify the files for rake.
|
422
|
+
["extconf.rb", "Rakefile"].each do |fname|
|
423
|
+
lines = nil
|
424
|
+
File.open(src_path + fname,"r") {|f| lines = f.readlines }
|
425
|
+
# puts "Checking dir: #{File.dirname(__FILE__)+"/../hruby_sim/"}"
|
426
|
+
lines = ["C_PROGRAM = '#{dir}'\nRCSIM_DIR = '#{File.dirname(__FILE__)+"/../hruby_sim/"}'\n"] + lines
|
427
|
+
File.open(dir + "/" + fname, "w") {|f| lines.each {|l| f.write(l) } }
|
428
|
+
end
|
429
|
+
exit
|
430
|
+
end
|
404
431
|
opts.on("-v", "--verilog","Output in Verlog HDL format") do |v|
|
405
432
|
$options[:verilog] = v
|
406
433
|
$options[:multiple] = v
|
@@ -466,14 +493,26 @@ $optparse = OptionParser.new do |opts|
|
|
466
493
|
$options[:dump] = v
|
467
494
|
$options[:multiple] = v
|
468
495
|
end
|
469
|
-
opts.on("--get-samples", "Copy the sample directory (hdr_samples) to current one,
|
496
|
+
opts.on("--get-samples", "Copy the sample directory (hdr_samples) to current one, then exit") do
|
470
497
|
FileUtils.copy_entry(File.dirname(__FILE__) + "/hdr_samples","./hdr_samples")
|
498
|
+
FileUtils.copy_entry(File.dirname(__FILE__) + "/hdr_samples/c_program","./hdr_samples/c_program")
|
499
|
+
FileUtils.copy_entry(File.dirname(__FILE__) + "/hdr_samples/ruby_program","./hdr_samples/ruby_program")
|
500
|
+
exit
|
501
|
+
end
|
502
|
+
opts.on("--get-tuto", "Copy the tutorial directory (tuto) to current one, then exit") do
|
503
|
+
FileUtils.copy_entry(File.dirname(__FILE__) + "../../tuto","./tuto")
|
471
504
|
exit
|
472
505
|
end
|
473
506
|
opts.on("--version", "Show the version of HDLRuby, then exit") do |v|
|
474
507
|
puts VERSION
|
475
508
|
exit
|
476
509
|
end
|
510
|
+
opts.on("--path","Shows the path where HDLRuby is install.") do |v|
|
511
|
+
require 'pathname'
|
512
|
+
path = Pathname.new(__FILE__ + "../../../../").cleanpath
|
513
|
+
puts path.to_s
|
514
|
+
exit
|
515
|
+
end
|
477
516
|
# opts.on_tail("-h", "--help", "Show this message") do
|
478
517
|
opts.on("-h", "--help", "Show this message") do
|
479
518
|
puts opts
|
@@ -583,7 +622,7 @@ if $options[:syntax] then
|
|
583
622
|
$output << $loader.show_all
|
584
623
|
exit
|
585
624
|
end
|
586
|
-
HDLRuby.show "#{Time.now}#{show_mem}"
|
625
|
+
# HDLRuby.show "#{Time.now}#{show_mem}"
|
587
626
|
HDLRuby.show "##### Starting parser #####"
|
588
627
|
|
589
628
|
if $options[:debug] then
|