HDLRuby 2.4.12 → 2.4.19
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- checksums.yaml +4 -4
- data/lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_hs_32.v +1277 -0
- data/lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_213.v +1345 -0
- data/lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_222.v +1339 -0
- data/lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_rg_23.v +1248 -0
- data/lib/HDLRuby/hdr_samples/make_multi_channels_v.rb +24 -0
- data/lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb +17 -17
- data/lib/HDLRuby/hdr_samples/with_connector.rb +245 -0
- data/lib/HDLRuby/hdr_samples/with_connector_memory.rb +98 -0
- data/lib/HDLRuby/hdr_samples/with_multi_channels.rb +109 -201
- data/lib/HDLRuby/hruby_tools.rb +7 -1
- data/lib/HDLRuby/sim/hruby_sim_calc.c +3 -1
- data/lib/HDLRuby/std/connector.rb +110 -0
- data/lib/HDLRuby/version.rb +1 -1
- metadata +10 -2
data/lib/HDLRuby/hruby_tools.rb
CHANGED
@@ -29,8 +29,14 @@ module HDLRuby
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29
29
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class ::Integer
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30
30
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31
31
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# Gets the bit width
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32
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+
# NOTE: returns infinity if the number is negative.
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32
33
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def width
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33
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-
return Math.log2(self+1).ceil
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34
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+
return self >= 0 ? Math.log2(self+1).ceil : 1.0/0.0
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35
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+
end
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36
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+
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37
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+
# Tells if the value is a power of 2.
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38
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def pow2?
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39
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+
return self > 0 && (self & (self - 1) == 0)
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34
40
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end
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35
41
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end
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36
42
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@@ -1223,6 +1223,8 @@ static Value concat_value_bitstring_array(int num, int dir,
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1223
1223
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}
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1224
1224
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/* Resize the destination accordignly. */
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1225
1225
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resize_value(dst,width);
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1226
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+
/* Ensure it is not numeric. */
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1227
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dst->numeric = 0;
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1226
1228
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1227
1229
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/* Access the data of the destination. */
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1228
1230
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char* dst_data = dst->data_str;
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@@ -1233,7 +1235,7 @@ static Value concat_value_bitstring_array(int num, int dir,
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1233
1235
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unsigned int idx = dir ? (num-i-1) : i;
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1234
1236
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Value value = args[idx];
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1235
1237
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unsigned long long cw = type_width(value->type);
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1236
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-
// printf("value=%s cw=%llu\n",value->data_str,cw);
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1238
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+
// printf("value=%s cw=%llu pos=%llu\n",value->data_str,cw,pos);
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1237
1239
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memcpy(dst_data+pos,value->data_str,cw);
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1238
1240
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pos += cw;
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1239
1241
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}
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@@ -0,0 +1,110 @@
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1
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+
module HDLRuby::High::Std
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2
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3
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##
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4
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# Standard HDLRuby::High library: connectors between channels
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#
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6
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########################################################################
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7
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8
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# Function for generating a connector that duplicates the output of
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9
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# channel +in_ch+ and connect it to channels +out_chs+ with data of
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10
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# +typ+.
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11
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# The duplication is done according to event +ev+.
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12
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function :duplicator do |typ, ev, in_ch, out_chs|
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13
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+
ev = ev.poswedge unless ev.is_a?(Event)
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14
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+
inner :in_ack, :in_req
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15
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+
out_acks = out_chs.size.times.map { |i| inner(:"out_ack#{i}") }
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16
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+
typ.inner :data
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17
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par(ev) do
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18
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in_req <= 1
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19
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+
out_acks.each { |ack| ack <= 0 }
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20
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+
out_acks.each do |ack|
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21
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+
hif(ack == 1) { in_req <= 0 }
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22
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+
end
|
23
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+
hif(in_req) do
|
24
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+
in_ack <= 0
|
25
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+
in_ch.read(data) { in_ack <= 1 }
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26
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+
end
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27
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+
hif(in_ack) do
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28
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+
out_chs.zip(out_acks).each do |ch,ack|
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29
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+
hif(ack == 0) { ch.write(data) { ack <= 1 } }
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30
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+
end
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31
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+
hif (out_acks.reduce(_1) { |sum,ack| ack & sum }) do
|
32
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+
out_acks.each { |ack| ack <= 0 }
|
33
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+
end
|
34
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+
end
|
35
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end
|
36
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end
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37
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+
|
38
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+
# Function for generating a connector that merges the output of
|
39
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# channels +in_chs+ and connects the result to channel +out_ch+ with
|
40
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# data of types from +typs+.
|
41
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+
# The merge is done according to event +ev+.
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42
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function :merger do |typs, ev, in_chs, out_ch|
|
43
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+
ev = ev.posedge unless ev.is_a?(Event)
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44
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+
inner :out_ack
|
45
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+
in_reqs = in_chs.size.times.map { |i| inner(:"in_req#{i}") }
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46
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+
in_acks = in_chs.size.times.map { |i| inner(:"in_ack#{i}") }
|
47
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+
datas = typs.map.with_index { |typ,i| typ.inner(:"data#{i}") }
|
48
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+
par(ev) do
|
49
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+
in_reqs.each { |req| req <= 1 }
|
50
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+
out_ack <= 0
|
51
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+
hif(out_ack == 1) { in_reqs.each { |req| req <= 0 } }
|
52
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+
hif(in_reqs.reduce(_1) { |sum,req| req & sum }) do
|
53
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+
in_chs.each_with_index do |ch,i|
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54
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+
in_acks[i] <= 0
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55
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ch.read(datas[i]) { in_acks[i] <= 1 }
|
56
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+
end
|
57
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end
|
58
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+
hif(in_acks.reduce(_1) { |sum,req| req & sum }) do
|
59
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+
hif(out_ack == 0) { out_ch.write(datas) { out_ack <= 1 } }
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60
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+
hif (out_ack == 1) { out_ack <= 0 }
|
61
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end
|
62
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end
|
63
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end
|
64
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+
|
65
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+
|
66
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# Function for generating a connector that serialize to the output of
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67
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# channels +in_chs+ and connects the result to channel +out_ch+ with
|
68
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# data of +typ+.
|
69
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+
# The merge is done according to event +ev+.
|
70
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+
function :serializer do |typ, ev, in_chs, out_ch|
|
71
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+
ev = ev.posedge unless ev.is_a?(Event)
|
72
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+
size = in_chs.size
|
73
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+
inner :out_ack
|
74
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+
# in_reqs = size.times.map { |i| inner(:"in_req#{i}") }
|
75
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+
in_acks = size.times.map { |i| inner(:"in_ack#{i}") }
|
76
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+
datas = size.times.map { |i| typ.inner(:"data#{i}") }
|
77
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+
# The inpt channel selector
|
78
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+
[size.width].inner :idx
|
79
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+
inner :reading
|
80
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+
par(ev) do
|
81
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+
# in_reqs.each { |req| req <= 1 }
|
82
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+
idx <= 0
|
83
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+
reading <= 0
|
84
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+
out_ack <= 0
|
85
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+
hif(idx == size-1) { in_acks.each { |ack| ack <= 0 } }
|
86
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+
# hif((idx == 0) & (in_reqs.reduce(_1) { |sum,req| req & sum })) do
|
87
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+
hif(idx == 0) do
|
88
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+
hif(~reading) do
|
89
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+
size.times { |i| in_acks[i] <= 0 }
|
90
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+
end
|
91
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+
reading <= 1
|
92
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+
in_chs.each_with_index do |ch,i|
|
93
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+
hif(~in_acks[i]) do
|
94
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+
ch.read(datas[i]) { in_acks[i] <= 1 }
|
95
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+
end
|
96
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+
end
|
97
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+
end
|
98
|
+
hif(in_acks.reduce(_1) { |sum,req| req & sum }) do
|
99
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+
hcase(idx)
|
100
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+
datas.each_with_index do |data,i|
|
101
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+
hwhen(i) do
|
102
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+
out_ch.write(data) { idx <= idx + 1; out_ack <= 1 }
|
103
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+
end
|
104
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+
end
|
105
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+
end
|
106
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+
end
|
107
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+
end
|
108
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+
|
109
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+
|
110
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+
end
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data/lib/HDLRuby/version.rb
CHANGED
metadata
CHANGED
@@ -1,14 +1,14 @@
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|
1
1
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--- !ruby/object:Gem::Specification
|
2
2
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name: HDLRuby
|
3
3
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version: !ruby/object:Gem::Version
|
4
|
-
version: 2.4.
|
4
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+
version: 2.4.19
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5
5
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platform: ruby
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6
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authors:
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7
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- Lovic Gauthier
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8
8
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autorequire:
|
9
9
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bindir: exe
|
10
10
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cert_chain: []
|
11
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-
date: 2020-
|
11
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+
date: 2020-12-06 00:00:00.000000000 Z
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12
12
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dependencies:
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13
13
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- !ruby/object:Gem::Dependency
|
14
14
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name: bundler
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@@ -66,6 +66,10 @@ files:
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66
66
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- lib/HDLRuby/alcc.rb
|
67
67
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- lib/HDLRuby/backend/hruby_allocator.rb
|
68
68
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- lib/HDLRuby/backend/hruby_c_allocator.rb
|
69
|
+
- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_hs_32.v
|
70
|
+
- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_213.v
|
71
|
+
- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_222.v
|
72
|
+
- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_rg_23.v
|
69
73
|
- lib/HDLRuby/hdr_samples/adder.rb
|
70
74
|
- lib/HDLRuby/hdr_samples/adder_assign_error.rb
|
71
75
|
- lib/HDLRuby/hdr_samples/adder_bench.rb
|
@@ -84,6 +88,7 @@ files:
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|
84
88
|
- lib/HDLRuby/hdr_samples/include.rb
|
85
89
|
- lib/HDLRuby/hdr_samples/instance_open.rb
|
86
90
|
- lib/HDLRuby/hdr_samples/linear_test.rb
|
91
|
+
- lib/HDLRuby/hdr_samples/make_multi_channels_v.rb
|
87
92
|
- lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb
|
88
93
|
- lib/HDLRuby/hdr_samples/mei8.rb
|
89
94
|
- lib/HDLRuby/hdr_samples/mei8_bench.rb
|
@@ -120,6 +125,8 @@ files:
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|
120
125
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- lib/HDLRuby/hdr_samples/tuple.rb
|
121
126
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- lib/HDLRuby/hdr_samples/with_channel.rb
|
122
127
|
- lib/HDLRuby/hdr_samples/with_class.rb
|
128
|
+
- lib/HDLRuby/hdr_samples/with_connector.rb
|
129
|
+
- lib/HDLRuby/hdr_samples/with_connector_memory.rb
|
123
130
|
- lib/HDLRuby/hdr_samples/with_decoder.rb
|
124
131
|
- lib/HDLRuby/hdr_samples/with_fixpoint.rb
|
125
132
|
- lib/HDLRuby/hdr_samples/with_fsm.rb
|
@@ -272,6 +279,7 @@ files:
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|
272
279
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- lib/HDLRuby/sim/hruby_value_pool.c
|
273
280
|
- lib/HDLRuby/std/channel.rb
|
274
281
|
- lib/HDLRuby/std/clocks.rb
|
282
|
+
- lib/HDLRuby/std/connector.rb
|
275
283
|
- lib/HDLRuby/std/counters.rb
|
276
284
|
- lib/HDLRuby/std/decoder.rb
|
277
285
|
- lib/HDLRuby/std/fixpoint.rb
|