HDLRuby 2.4.12 → 2.4.19
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_hs_32.v +1277 -0
- data/lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_213.v +1345 -0
- data/lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_222.v +1339 -0
- data/lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_rg_23.v +1248 -0
- data/lib/HDLRuby/hdr_samples/make_multi_channels_v.rb +24 -0
- data/lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb +17 -17
- data/lib/HDLRuby/hdr_samples/with_connector.rb +245 -0
- data/lib/HDLRuby/hdr_samples/with_connector_memory.rb +98 -0
- data/lib/HDLRuby/hdr_samples/with_multi_channels.rb +109 -201
- data/lib/HDLRuby/hruby_tools.rb +7 -1
- data/lib/HDLRuby/sim/hruby_sim_calc.c +3 -1
- data/lib/HDLRuby/std/connector.rb +110 -0
- data/lib/HDLRuby/version.rb +1 -1
- metadata +10 -2
data/lib/HDLRuby/hruby_tools.rb
CHANGED
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@@ -29,8 +29,14 @@ module HDLRuby
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class ::Integer
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# Gets the bit width
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# NOTE: returns infinity if the number is negative.
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def width
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-
return Math.log2(self+1).ceil
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return self >= 0 ? Math.log2(self+1).ceil : 1.0/0.0
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end
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# Tells if the value is a power of 2.
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def pow2?
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return self > 0 && (self & (self - 1) == 0)
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end
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end
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@@ -1223,6 +1223,8 @@ static Value concat_value_bitstring_array(int num, int dir,
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}
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/* Resize the destination accordignly. */
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resize_value(dst,width);
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1226
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/* Ensure it is not numeric. */
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dst->numeric = 0;
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/* Access the data of the destination. */
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char* dst_data = dst->data_str;
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@@ -1233,7 +1235,7 @@ static Value concat_value_bitstring_array(int num, int dir,
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unsigned int idx = dir ? (num-i-1) : i;
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Value value = args[idx];
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unsigned long long cw = type_width(value->type);
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-
// printf("value=%s cw=%llu\n",value->data_str,cw);
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// printf("value=%s cw=%llu pos=%llu\n",value->data_str,cw,pos);
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memcpy(dst_data+pos,value->data_str,cw);
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pos += cw;
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}
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@@ -0,0 +1,110 @@
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1
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module HDLRuby::High::Std
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##
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# Standard HDLRuby::High library: connectors between channels
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#
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########################################################################
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# Function for generating a connector that duplicates the output of
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# channel +in_ch+ and connect it to channels +out_chs+ with data of
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# +typ+.
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# The duplication is done according to event +ev+.
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function :duplicator do |typ, ev, in_ch, out_chs|
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ev = ev.poswedge unless ev.is_a?(Event)
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inner :in_ack, :in_req
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out_acks = out_chs.size.times.map { |i| inner(:"out_ack#{i}") }
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typ.inner :data
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par(ev) do
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in_req <= 1
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out_acks.each { |ack| ack <= 0 }
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out_acks.each do |ack|
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hif(ack == 1) { in_req <= 0 }
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end
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hif(in_req) do
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in_ack <= 0
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in_ch.read(data) { in_ack <= 1 }
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end
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hif(in_ack) do
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out_chs.zip(out_acks).each do |ch,ack|
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hif(ack == 0) { ch.write(data) { ack <= 1 } }
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end
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hif (out_acks.reduce(_1) { |sum,ack| ack & sum }) do
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out_acks.each { |ack| ack <= 0 }
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end
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end
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end
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end
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# Function for generating a connector that merges the output of
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# channels +in_chs+ and connects the result to channel +out_ch+ with
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# data of types from +typs+.
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# The merge is done according to event +ev+.
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function :merger do |typs, ev, in_chs, out_ch|
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ev = ev.posedge unless ev.is_a?(Event)
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inner :out_ack
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in_reqs = in_chs.size.times.map { |i| inner(:"in_req#{i}") }
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in_acks = in_chs.size.times.map { |i| inner(:"in_ack#{i}") }
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datas = typs.map.with_index { |typ,i| typ.inner(:"data#{i}") }
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par(ev) do
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in_reqs.each { |req| req <= 1 }
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out_ack <= 0
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hif(out_ack == 1) { in_reqs.each { |req| req <= 0 } }
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hif(in_reqs.reduce(_1) { |sum,req| req & sum }) do
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in_chs.each_with_index do |ch,i|
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in_acks[i] <= 0
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ch.read(datas[i]) { in_acks[i] <= 1 }
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end
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end
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hif(in_acks.reduce(_1) { |sum,req| req & sum }) do
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hif(out_ack == 0) { out_ch.write(datas) { out_ack <= 1 } }
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hif (out_ack == 1) { out_ack <= 0 }
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end
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end
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end
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# Function for generating a connector that serialize to the output of
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# channels +in_chs+ and connects the result to channel +out_ch+ with
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# data of +typ+.
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# The merge is done according to event +ev+.
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function :serializer do |typ, ev, in_chs, out_ch|
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ev = ev.posedge unless ev.is_a?(Event)
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size = in_chs.size
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inner :out_ack
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# in_reqs = size.times.map { |i| inner(:"in_req#{i}") }
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in_acks = size.times.map { |i| inner(:"in_ack#{i}") }
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datas = size.times.map { |i| typ.inner(:"data#{i}") }
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# The inpt channel selector
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[size.width].inner :idx
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inner :reading
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par(ev) do
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# in_reqs.each { |req| req <= 1 }
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idx <= 0
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reading <= 0
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out_ack <= 0
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hif(idx == size-1) { in_acks.each { |ack| ack <= 0 } }
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# hif((idx == 0) & (in_reqs.reduce(_1) { |sum,req| req & sum })) do
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hif(idx == 0) do
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hif(~reading) do
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size.times { |i| in_acks[i] <= 0 }
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end
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reading <= 1
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in_chs.each_with_index do |ch,i|
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hif(~in_acks[i]) do
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ch.read(datas[i]) { in_acks[i] <= 1 }
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end
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end
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end
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hif(in_acks.reduce(_1) { |sum,req| req & sum }) do
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hcase(idx)
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datas.each_with_index do |data,i|
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hwhen(i) do
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out_ch.write(data) { idx <= idx + 1; out_ack <= 1 }
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end
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end
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end
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end
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end
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end
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data/lib/HDLRuby/version.rb
CHANGED
metadata
CHANGED
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@@ -1,14 +1,14 @@
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--- !ruby/object:Gem::Specification
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name: HDLRuby
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version: !ruby/object:Gem::Version
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version: 2.4.
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version: 2.4.19
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platform: ruby
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authors:
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- Lovic Gauthier
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autorequire:
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bindir: exe
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cert_chain: []
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date: 2020-
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date: 2020-12-06 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: bundler
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@@ -66,6 +66,10 @@ files:
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- lib/HDLRuby/alcc.rb
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- lib/HDLRuby/backend/hruby_allocator.rb
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- lib/HDLRuby/backend/hruby_c_allocator.rb
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- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_hs_32.v
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- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_213.v
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- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_222.v
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- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_rg_23.v
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- lib/HDLRuby/hdr_samples/adder.rb
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- lib/HDLRuby/hdr_samples/adder_assign_error.rb
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- lib/HDLRuby/hdr_samples/adder_bench.rb
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@@ -84,6 +88,7 @@ files:
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- lib/HDLRuby/hdr_samples/include.rb
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- lib/HDLRuby/hdr_samples/instance_open.rb
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- lib/HDLRuby/hdr_samples/linear_test.rb
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- lib/HDLRuby/hdr_samples/make_multi_channels_v.rb
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- lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb
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- lib/HDLRuby/hdr_samples/mei8.rb
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- lib/HDLRuby/hdr_samples/mei8_bench.rb
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@@ -120,6 +125,8 @@ files:
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- lib/HDLRuby/hdr_samples/tuple.rb
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- lib/HDLRuby/hdr_samples/with_channel.rb
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- lib/HDLRuby/hdr_samples/with_class.rb
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- lib/HDLRuby/hdr_samples/with_connector.rb
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- lib/HDLRuby/hdr_samples/with_connector_memory.rb
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- lib/HDLRuby/hdr_samples/with_decoder.rb
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- lib/HDLRuby/hdr_samples/with_fixpoint.rb
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- lib/HDLRuby/hdr_samples/with_fsm.rb
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@@ -272,6 +279,7 @@ files:
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- lib/HDLRuby/sim/hruby_value_pool.c
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- lib/HDLRuby/std/channel.rb
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- lib/HDLRuby/std/clocks.rb
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- lib/HDLRuby/std/connector.rb
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- lib/HDLRuby/std/counters.rb
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- lib/HDLRuby/std/decoder.rb
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- lib/HDLRuby/std/fixpoint.rb
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