HDLRuby 2.4.12 → 2.4.19

data/lib/HDLRuby/hdr_samples/make_multi_channels_v.rb

@@ -0,0 +1,24 @@
+#!/usr/bin/ruby
+# Script for generating the vcd files.
+
+# The configuration scenarii
+$scenarii = [
+              [:_clk2_clk2,      :register],    #  0
+              [:_clk2_nclk2,     :register],    #  1
+              [:_clk2_clk3,      :register],    #  2
+              [:_clk3_clk2,      :register],    #  3
+              [:_clk2_clk2,      :handshake],   #  4
+              [:_clk2_nclk2,     :handshake],   #  5
+              [:_clk2_clk3,      :handshake],   #  6
+              [:_clk3_clk2,      :handshake],   #  7
+              [:clk2_clk2_clk2,  :queue],       #  8
+              [:clk2_clk2_nclk2, :queue],       #  9
+              [:clk1_clk2_clk3,  :queue],       # 10
+              [:clk3_clk2_clk1,  :queue],       # 11
+              [:clk2_clk3_clk1,  :queue],       # 12
+              [:clk2_clk1_clk3,  :queue],       # 13
+            ]
+$scenarii.each_with_index do |scenarii,i|
+    puts "scenario: [#{i}] #{scenarii}"
+    `bundle exec ../hdrcc.rb --verilog with_multi_channels.rb WithMultiChannelPaper.V#{i} #{i}`
+end

data/lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb

@@ -3,23 +3,23 @@
 
 # The configuration scenarii
 $scenarii = [
-              [:sync,  :register],     # 00
-              [:sync,  :handshake],    # 01
-              [:sync,  :queue],        # 02
-              [:nsync, :register],     # 03
-              [:nsync, :handshake],    # 04
-              [:nsync, :queue],        # 05
-              [:async, :register],     # 06
-              [:async, :handshake],    # 07
-              [:async, :queue],        # 08
-              [:proco, :register],     # 09
-              [:proco, :handshake],    # 10
-              [:proco, :queue],        # 11
-              [:double,:register],     # 12
-              [:double,:handshake],    # 13 
-              [:double,:queue]         # 14
+              [:_clk2_clk2,      :register],    #  0
+              [:_clk2_nclk2,     :register],    #  1
+              [:_clk2_clk3,      :register],    #  2
+              [:_clk3_clk2,      :register],    #  3
+              [:_clk2_clk2,      :handshake],   #  4
+              [:_clk2_nclk2,     :handshake],   #  5
+              [:_clk2_clk3,      :handshake],   #  6
+              [:_clk3_clk2,      :handshake],   #  7
+              [:clk2_clk2_clk2,  :queue],       #  8
+              [:clk2_clk2_nclk2, :queue],       #  9
+              [:clk1_clk2_clk3,  :queue],       # 10
+              [:clk3_clk2_clk1,  :queue],       # 11
+              [:clk2_clk3_clk1,  :queue],       # 12
+              [:clk2_clk1_clk3,  :queue],       # 13
             ]
-(0..11).each do |i|
+$scenarii.each_with_index do |scenarii,i|
+    puts "scenario: [#{i}] #{scenarii}"
     `bundle exec ../hdrcc.rb -S --vcd with_multi_channels.rb WithMultiChannelPaper #{i}`
-    `mv WithMultiChannelPaper/hruby_simulator.vcd WithMultiChannelPaper/#{i.to_s.to_s.rjust(2,"0")}_#{$scenarii[i][0]}_#{$scenarii[i][1]}.vcd`
+    `mv WithMultiChannelPaper/hruby_simulator.vcd WithMultiChannelPaper/#{i.to_s.to_s.rjust(2,"0")}_#{scenarii[0]}_#{scenarii[1]}.vcd`
 end

data/lib/HDLRuby/hdr_samples/with_connector.rb

@@ -0,0 +1,245 @@
+require 'std/channel.rb'
+require 'std/connector.rb'
+
+include HDLRuby::High::Std
+
+# Sample for testing the connectors of channels.
+
+# Channel describing a buffered queue storing data of +typ+ type of +depth+,
+# synchronized through clk and reset on +rst+.
+channel(:queue) do |typ,depth,clk,rst|
+    # The inner buffer of the queue.
+    typ[-depth].inner :buffer
+    # The read and write pointers.
+    [depth.width].inner :rptr, :wptr
+    # The read and write command signals.
+    inner :rreq, :wreq
+    # The read and write ack signals.
+    inner :rack, :wack
+    # The read/write data registers.
+    typ.inner :rdata, :wdata
+
+    # The flags telling of the channel is synchronized
+    inner :rsync, :wsync
+
+    # The process handling the decoupled access to the buffer.
+    par(clk.posedge) do
+        hif(rst) { rptr <= 0; wptr <= 0 }
+        helse do
+            hif(~rsync) do
+                hif (~rreq) { rack <= 0 }
+                hif(rreq & (~rack) & (rptr != wptr)) do
+                    rdata <= buffer[rptr]
+                    rptr <= (rptr + 1) % depth
+                    rack <= 1
+                end
+            end
+
+            hif(~wsync) do
+                hif (~wreq) { wack <= 0 }
+                hif(wreq & (~wack) & (((wptr+1) % depth) != rptr)) do
+                    buffer[wptr] <= wdata
+                    wptr <= (wptr + 1) % depth
+                    wack <= 1
+                end
+            end
+        end
+    end
+
+    reader_output :rreq, :rptr, :rsync
+    reader_input :rdata, :rack, :wptr, :buffer
+
+    # The read primitive.
+    reader do |blk,target|
+        if (cur_behavior.on_event?(clk.posedge,clk.negedge)) then
+            # Same clk event, synchrone case: perform a direct access.
+            # Now perform the access.
+            top_block.unshift do
+                rsync <= 1
+                rreq <= 0
+            end
+            seq do
+                hif(rptr != wptr) do
+                    # target <= rdata
+                    target <= buffer[rptr]
+                    rptr <= (rptr + 1) % depth
+                    blk.call if blk
+                end
+            end
+        else
+            # Different clk event, perform a decoupled access.
+            top_block.unshift do
+                rsync <= 0
+                rreq <= 0
+            end
+            par do
+                hif (~rack) { rreq <= 1 }
+                helsif(rreq) do
+                    rreq <= 0
+                    target <= rdata
+                    blk.call if blk
+                end
+            end
+        end
+    end
+
+    writer_output :wreq, :wdata, :wptr, :wsync, :buffer
+    writer_input :wack, :rptr
+
+    # The write primitive.
+    writer do |blk,target|
+        if (cur_behavior.on_event?(clk.negedge,clk.posedge)) then
+            # Same clk event, synchrone case: perform a direct access.
+            top_block.unshift do
+                wsync <= 1
+                wreq <= 0
+            end
+            hif(((wptr+1) % depth) != rptr) do
+                buffer[wptr] <= target
+                wptr <= (wptr + 1) % depth
+                blk.call if blk
+            end
+        else
+            # Different clk event, asynchrone case: perform a decoupled access.
+            top_block.unshift do
+                wsync <= 0
+                wreq <= 0
+            end
+            seq do
+                hif (~wack) do
+                    wreq <= 1
+                    wdata <= target
+                end
+                helsif(wreq) do
+                    wreq <= 0
+                    blk.call if blk
+                end
+            end
+        end
+    end
+end
+
+
+
+
+# Module for testing the connector.
+system :with_connectors do
+    inner :clk, :rst
+
+    # First tester.
+    [4].inner :counter
+    [4*4].inner :res
+    inner :ack_in, :ack_out
+
+    # The input queue.
+    queue(bit[4],4,clk,rst).(:in_qu)
+
+    # The middle queues.
+    mid_qus = 4.times.map do |i|
+        queue(bit[4],4,clk,rst).(:"mid_qu#{i}")
+    end
+
+    # The output queue.
+    queue(bit[4*4],4,clk,rst).(:out_qu)
+
+    # Connect the input queue to the middle queues.
+    duplicator(bit[4],clk.negedge,in_qu,mid_qus)
+
+    # Connect the middle queues to the output queue.
+    merger([bit[4]]*4,clk.negedge,mid_qus,out_qu)
+
+
+    # Second tester.
+    [4].inner :counterb
+    [4].inner :resb
+    inner :ack_inb0, :ack_inb1, :ack_outb
+
+    # The input queues.
+    queue(bit[4],4,clk,rst).(:in_qub0)
+    queue(bit[4],4,clk,rst).(:in_qub1)
+
+    # The output queue.
+    queue(bit[4],4,clk,rst).(:out_qub)
+
+    # Connect then with a serializer.
+    serializer(bit[4],clk.negedge,[in_qub0,in_qub1],out_qub)
+
+    # # Slow version, always work
+    # par(clk.posedge) do
+    #     ack_in <= 0
+    #     ack_out <= 1
+    #     hif(rst) { counter <= 0 }
+    #     helse do
+    #         hif(ack_out) do
+    #             ack_out <= 0
+    #             in_qu.write(counter)  do
+    #                 ack_in <= 1
+    #                 counter <= counter + 1
+    #             end
+    #         end
+    #         hif(ack_in) do
+    #             mid_qu0.read(res_0)
+    #             mid_qu1.read(res_1)
+    #             mid_qu2.read(res_2)
+    #             mid_qu3.read(res_3) { ack_out <= 1 }
+    #         end
+    #     end
+    # end
+
+    # Fast version but assumes connected channels are blocking
+    par(clk.posedge) do
+        ack_in <= 0
+        ack_inb0 <= 0
+        ack_inb1 <= 0
+        hif(rst) { counter <= 0; counterb <= 0 }
+        helse do
+            in_qu.write(counter)  do
+                ack_in <= 1
+                counter <= counter + 1
+            end
+            hif(ack_in) do
+                out_qu.read(res)
+            end
+            hif(~ack_inb0) do
+                in_qub0.write(counterb) do
+                    ack_inb0 <= 1
+                    counterb <= counterb + 1
+                end
+            end
+            helse do
+                in_qub1.write(counterb) do
+                    ack_inb1 <= 1
+                    counterb <= counterb + 1
+                end
+            end
+            hif(ack_inb0 | ack_inb1) do
+                out_qub.read(resb)
+            end
+        end
+    end
+
+    timed do
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        16.times do
+            !10.ns
+            clk <= 1
+            !10.ns
+            clk <= 0
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_connector_memory.rb

@@ -0,0 +1,98 @@
+require 'std/memory.rb'
+require "std/fixpoint.rb"
+require 'std/channel.rb'
+require 'std/connector.rb'
+
+include HDLRuby::High::Std
+
+system :channel_connector do
+    # データ型の宣言
+    integer_width = 4 # 整数部のビット幅
+    decimal_width = 4 # 実数部のビット幅
+    address_width = 4 # lutのアドレスのビット幅
+    typ = signed[integer_width + decimal_width] # データ型
+    
+    inputs_x = _00010011
+    inputs_h = _10100001
+    columns = [2, 2, 1]
+
+    inner :clk,   # clock
+          :rst,   # reset
+          :req,   # request
+          :fill   # 入力値のメモリへの書き込み
+
+    # inputs_x = quantize(inputs_x, typ, decimal_width)
+    # inputs_h = quantize(inputs_h, typ, decimal_width)
+
+    mem_rom(typ, columns[0], clk, rst, inputs_x, rinc: :rst, winc: :rst).(:rom_inputs_x) # 入力値を格納するrom(x)
+
+    mem_rom(typ, columns[0], clk, rst, inputs_h, rinc: :rst, winc: :rst).(:rom_inputs_h) # 入力値を格納するrom(h)
+
+    mem_dual(typ, columns[0], clk, rst, rinc: :rst, winc: :rst).(:ram_inputs_serializer) #
+
+    mem_dual(typ, columns[0]*2, clk, rst, rinc: :rst, winc: :rst).(:ram_inputs_merger) #
+
+    reader_inputs_x = rom_inputs_x.branch(:rinc) #入力値xの読みだし用branch
+    reader_inputs_h = rom_inputs_h.branch(:rinc) #入力値hの読みだし用branch
+    writer_inputs_serializer = ram_inputs_serializer.branch(:winc) #入力値を合成した値の書き込み用branch
+    writer_inputs_meger = ram_inputs_merger.branch(:winc) #入力値を合成した値の書き込み用branch
+  
+
+    serializer(typ,clk.negedge,[reader_inputs_x,reader_inputs_h],writer_inputs_serializer)
+
+    # merger([typ]*2,clk.negedge,[reader_inputs_x,reader_inputs_h], writer_inputs_meger)
+
+    # duplicator(typ,clk.negedge,reader_inputs_r,[])
+
+
+    timed do
+      # リセット
+      clk <= 0
+      rst <= 0
+      req <= 0
+      fill <= 0
+      !10.ps
+
+      # メモリ読み出し位置の初期化
+      rst <= 1
+      !10.ps
+      clk <= 1
+      !10.ps
+      clk <= 0
+      !10.ps
+      clk <= 1
+      !10.ps
+
+      # パラメータのメモリへの書き込み
+      clk <= 0
+      rst <= 0
+      fill <= 1
+
+      !10.ps
+      10.times do |i|
+        clk <= 1
+        !10.ps
+        clk <= 0
+        !10.ps
+      end
+
+      fill <= 0
+      clk <= 1
+      !10.ps
+
+      # 計算の実行
+      clk <= 0
+      req <= 1
+      !10.ps
+      clk <= 1
+      !10.ps
+      clk <= 0
+      !10.ps
+      30.times do
+        clk <= 1
+        !10.ps
+        clk <= 0
+        !10.ps
+      end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_multi_channels.rb

@@ -10,36 +10,41 @@ channel(:queue) do |typ,depth,clk,rst|
     # The read and write pointers.
     [depth.width].inner :rptr, :wptr
     # The read and write command signals.
-    inner :rcmd, :wcmd
+    inner :rreq, :wreq
     # The read and write ack signals.
     inner :rack, :wack
-    # The ack check deactivator (for synchron accesses).
-    inner :hrack, :hwack
     # The read/write data registers.
     typ.inner :rdata, :wdata
 
+    # The flags telling of the channel is synchronized
+    inner :rsync, :wsync
+
     # The process handling the decoupled access to the buffer.
     par(clk.posedge) do
-        # rack <= 0
-        # wack <= 0
-        hif (~rcmd) { rack <= 0 }
-        hif (~wcmd) { wack <= 0 }
         hif(rst) { rptr <= 0; wptr <= 0 }
-        hif(rcmd & (hrack|~rack) & (rptr != wptr)) do
-            rptr <= (rptr + 1) % depth
-            rack <= 1
-        end
-        hif(wcmd & (hwack|~wack) & (((wptr+1) % depth) != rptr)) do
-            buffer[wptr] <= wdata
-            # buffer[1] <= wdata
-            wptr <= (wptr + 1) % depth
-            wack <= 1
+        helse do
+            hif(~rsync) do
+                hif (~rreq) { rack <= 0 }
+                hif(rreq & (~rack) & (rptr != wptr)) do
+                    rdata <= buffer[rptr]
+                    rptr <= (rptr + 1) % depth
+                    rack <= 1
+                end
+            end
+
+            hif(~wsync) do
+                hif (~wreq) { wack <= 0 }
+                hif(wreq & (~wack) & (((wptr+1) % depth) != rptr)) do
+                    buffer[wptr] <= wdata
+                    wptr <= (wptr + 1) % depth
+                    wack <= 1
+                end
+            end
         end
     end
-    par { rdata <= buffer[rptr] }
 
-    reader_output :rcmd, :rptr, :hrack
-    reader_input :rdata, :rack
+    reader_output :rreq, :rptr, :rsync
+    reader_input :rdata, :rack, :wptr, :buffer
 
     # The read primitive.
     reader do |blk,target|
@@ -47,66 +52,64 @@ channel(:queue) do |typ,depth,clk,rst|
             # Same clk event, synchrone case: perform a direct access.
             # Now perform the access.
             top_block.unshift do
-                rcmd <= 0
-                hrack <= 1
+                rsync <= 1
+                rreq <= 0
             end
             seq do
-                rptr <= (rptr + 1) % depth
-                target <= rdata
-                blk.call if blk
+                hif(rptr != wptr) do
+                    target <= buffer[rptr]
+                    rptr <= (rptr + 1) % depth
+                    blk.call if blk
+                end
             end
         else
             # Different clk event, perform a decoupled access.
             top_block.unshift do
-                rcmd <= 0
-                hrack <= 0
-                hif(rack) do
-                    blk.call if blk
-                end
+                rsync <= 0
+                rreq <= 0
             end
-            seq do
-                # hif(rack) do
-                #     blk.call if blk
-                # end
-                # helse do
-                hif(rack==0) do
-                    rcmd <= 1 
+            par do
+                hif (~rack) { rreq <= 1 }
+                helsif(rreq) do
+                    rreq <= 0
                     target <= rdata
+                    blk.call if blk
                 end
             end
         end
     end
 
-    writer_output :wcmd, :wdata, :hwack
-    writer_input :wack
+    writer_output :wreq, :wdata, :wptr, :wsync, :buffer
+    writer_input :wack, :rptr
 
     # The write primitive.
     writer do |blk,target|
         if (cur_behavior.on_event?(clk.negedge,clk.posedge)) then
             # Same clk event, synchrone case: perform a direct access.
             top_block.unshift do
-                wcmd <= 0
-                hwack <= 1
+                wsync <= 1
+                wreq <= 0
+            end
+            hif(((wptr+1) % depth) != rptr) do
+                buffer[wptr] <= target
+                wptr <= (wptr + 1) % depth
+                blk.call if blk
             end
-            wcmd <= 1
-            wdata <= target
-            blk.call if blk
         else
             # Different clk event, asynchrone case: perform a decoupled access.
             top_block.unshift do
-                wcmd <= 0
-                hwack <= 0
-                hif(wack) do
-                    blk.call if blk
-                end
+                wsync <= 0
+                wreq <= 0
             end
             seq do
-                # hif(wack) do
-                #     blk.call if blk
-                # end
-                # helse 
-                hif(wack==0) { wcmd <= 1 }
-                wdata <= target
+                hif (~wack) do
+                    wreq <= 1
+                    wdata <= target
+                end
+                helsif(wreq) do
+                    wreq <= 0
+                    blk.call if blk
+                end
             end
         end
     end
@@ -181,82 +184,28 @@ channel(:handshake) do |typ|
     end
 end
 
-# Channel describing a handshake for transmitting data of +typ+ type, reset
-# by +rst+
-channel(:handshake2) do |typ|
-    # The data signal.
-    typ.inner :data
-    # The request and acknowledge.
-    inner :req, :ack
-    # The write flag
-    inner :wf
-
-    reader_input :ack, :data
-    reader_output :req
-
-    # The read primitive.
-    reader do |blk,target|
-        top_block.unshift do
-            req <= 0
-            hif(ack & req == 1) do
-                target <= data
-                req <= 0
-                blk.call if blk
-            end
-        end
-        hif(ack == 0) do
-            req <= 1
-        end
-    end
-
-    writer_input :req
-    writer_output :ack, :data
-    writer_inout :wf
-
-    # The read primitive.
-    writer do |blk,target|
-        top_block.unshift do
-            ack <= 0
-            hif(wf & req & ~ack == 1) do
-                data <= target
-                ack <= 1
-                blk.call if blk
-            end
-            hif(~req) { wf <= 0 }
-        end
-        hif(~ack) do
-            wf <= 1
-        end
-    end
-end
-
 
-# $mode = :sync
-# $mode = :nsync
-# $mode = :async
-# $mode = :proco  # Producer / Consummer
-# $mode = :double # Producer and Consummer with double channels.
+# $mode: channel clock, producer clock, consumer clock (n: not clock)
 # $channel = :register
 # $channel = :handshake
 # $channel = :queue
 
 # The configuration scenarii
 $scenarii = [
-              [:sync,  :register],     #  0
-              [:sync,  :handshake],    #  1
-              [:sync,  :queue],        #  3
-              [:nsync, :register],     #  4
-              [:nsync, :handshake],    #  5
-              [:nsync, :queue],        #  6
-              [:async, :register],     #  7
-              [:async, :handshake],    #  8
-              [:async, :queue],        #  9
-              [:proco, :register],     # 10
-              [:proco, :handshake],    # 11
-              [:proco, :queue],        # 12
-              [:double,:register],     # 13
-              [:double,:handshake],    # 14
-              [:double,:queue]         # 15
+              [:_clk2_clk2,      :register],    #  0
+              [:_clk2_nclk2,     :register],    #  1
+              [:_clk2_clk3,      :register],    #  2
+              [:_clk3_clk2,      :register],    #  3
+              [:_clk2_clk2,      :handshake],   #  4
+              [:_clk2_nclk2,     :handshake],   #  5
+              [:_clk2_clk3,      :handshake],   #  6
+              [:_clk3_clk2,      :handshake],   #  7
+              [:clk2_clk2_clk2,  :queue],       #  8
+              [:clk2_clk2_nclk2, :queue],       #  9
+              [:clk1_clk2_clk3,  :queue],       # 10
+              [:clk3_clk2_clk1,  :queue],       # 11
+              [:clk2_clk3_clk1,  :queue],       # 12
+              [:clk2_clk1_clk3,  :queue],       # 13
             ]
 
 # The configuration
@@ -266,113 +215,72 @@ puts "scenario: #{$scenarii[ARGV[-1].to_i]}"
 
 # Testing the queue channel.
 system :test_queue do
-    inner :clk, :rst, :clk2, :clk3
+    inner :rst, :clk1, :clk2, :clk3
     [8].inner :idata, :odata, :odata2
     [4].inner :counter
 
+
+    # Assign the clocks
+    mode = $mode.to_s.split("_")
+    if ($channel == :queue) then
+        clk_que = send(mode[0])
+    end
+    ev_pro = mode[1][0] == "n" ? 
+        send(mode[1][1..-1]).negedge : send(mode[1]).posedge
+    ev_con = mode[2][0] == "n" ? 
+        send(mode[2][1..-1]).negedge : send(mode[2]).posedge
+
+    # Set up the channel
     if $channel == :register then
         register(bit[8]).(:my_ch)
-        register(bit[8]).(:my_ch2)
     elsif $channel == :handshake then
         handshake(bit[8],rst).(:my_ch)
-        handshake(bit[8],rst).(:my_ch2)
     elsif $channel == :queue then
-        queue(bit[8],5,clk,rst).(:my_ch)
-        queue(bit[8],5,clk,rst).(:my_ch2)
+        queue(bit[8],3,clk_que,rst).(:my_ch)
     end
 
-    ev = $mode == :sync ? clk.posedge : 
-         $mode == :nsync ? clk.negedge : clk2.posedge
-
-    if $mode != :proco && $mode != :double then
-        # Sync/Neg sync and async tests mode
-        par(ev) do
-            hif(rst) do
-                counter <= 0
-                idata <= 0
-                # odata <= 0
-            end
-            helse do
-                hif (counter < 4) do
-                    my_ch.write(idata) do
-                        idata <= idata + 1
-                        counter <= counter + 1
-                    end
-                end
-                helsif ((counter > 10) & (counter < 15)) do
-                    my_ch.read(odata) do
-                        # idata <= idata - odata
-                        counter <= counter + 1
-                    end
-                end
-                helse do
-                    counter <= counter + 1
-                end
-            end
+    # Producter/consumer mode
+    # Producer
+    par(ev_pro) do
+        hif(rst) do
+            idata <= 0
         end
-    elsif $mode == :proco then
-        # Producter/consumer mode
-        # Producer
-        par(clk2.posedge) do
-            hif(rst) do
-                idata <= 0
-            end
-            helse do
-                my_ch.write(idata) do
-                    idata <= idata + 1
-                end
+        helse do
+            my_ch.write(idata) do
+                idata <= idata + 1
             end
         end
-        # Consumer
-        par(clk3.posedge) do
-            hif(rst) do
-                counter <= 0
-            end
-            helse do
-                my_ch.read(odata) do
-                    counter <= counter + 1
-                end
-            end
+    end
+    # Consumer
+    par(ev_con) do
+        hif(rst) do
+            counter <= 0
         end
-    else
-        # Producer and consumer are commicating through two layers of channels
-        par(ev) do
-            hif(rst) do
-                counter <= 0
-                idata <= 0
-            end
-            helse do
-                my_ch.write(idata) do
-                    idata <= idata + 1
-                end
-                my_ch.read(odata) do
-                    my_ch2.write(odata)
-                end
-                my_ch2.read(odata2) do
-                    counter <= counter + 1
-                end
+        helse do
+            my_ch.read(odata) do
+                counter <= counter + 1
             end
         end
     end
 
     timed do
-        clk <= 0
+        clk1 <= 0
         clk2 <= 0
         clk3 <= 0
         rst <= 0
         !10.ns
-        clk <= 1
+        clk1 <= 1
         !10.ns
-        clk <= 0
+        clk1 <= 0
         rst <= 1
         !3.ns
         clk2 <= 1
         !3.ns
         clk3 <= 0
         !4.ns
-        clk <= 1
+        clk1 <= 1
         !10.ns
-        clk <= 0
+        clk1 <= 0
         !3.ns
         clk2 <= 0
         !3.ns
@@ -381,9 +289,9 @@ system :test_queue do
         rst <= 0
         !2.ns
         64.times do
-            clk <= 1
+            clk1 <= 1
             !10.ns
-            clk <= 0
+            clk1 <= 0
             !3.ns
             clk2 <= ~clk2
             !3.ns