HDLRuby 2.4.11 → 2.4.18

data/lib/HDLRuby/hruby_tools.rb

@@ -29,8 +29,14 @@ module HDLRuby
     class ::Integer
 
         # Gets the bit width
+        # NOTE: returns infinity if the number is negative.
         def width
-            return Math.log2(self+1).ceil
+            return self >= 0 ? Math.log2(self+1).ceil : 1.0/0.0
+        end
+
+        # Tells if the value is a power of 2.
+        def pow2?
+            return self > 0 && (self & (self - 1) == 0)
         end
     end
 

data/lib/HDLRuby/sim/hruby_sim_calc.c

@@ -1223,6 +1223,8 @@ static Value concat_value_bitstring_array(int num, int dir,
     }
     /* Resize the destination accordignly. */
     resize_value(dst,width);
+    /* Ensure it is not numeric. */
+    dst->numeric = 0;
 
     /* Access the data of the destination. */
     char* dst_data = dst->data_str;
@@ -1233,7 +1235,7 @@ static Value concat_value_bitstring_array(int num, int dir,
         unsigned int idx = dir ? (num-i-1) : i;
         Value value = args[idx];
         unsigned long long cw = type_width(value->type);
-        // printf("value=%s cw=%llu\n",value->data_str,cw);
+        // printf("value=%s cw=%llu pos=%llu\n",value->data_str,cw,pos);
         memcpy(dst_data+pos,value->data_str,cw);
         pos += cw;
     }

data/lib/HDLRuby/std/connector.rb

@@ -0,0 +1,108 @@
+module HDLRuby::High::Std
+
+##
+# Standard HDLRuby::High library: connectors between channels
+# 
+########################################################################
+
+    # Function for generating a connector that duplicates the output of
+    # channel +in_ch+ and connect it to channels +out_chs+ with data of
+    # +typ+.
+    # The duplication is done according to event +ev+.
+    function :duplicator do |typ, ev, in_ch, out_chs|
+        ev = ev.poswedge unless ev.is_a?(Event)
+        inner :in_ack, :in_req
+        out_acks = out_chs.size.times.map { |i| inner(:"out_ack#{i}") }
+        typ.inner :data
+        par(ev) do
+            in_req <= 1
+            out_acks.each { |ack| ack <= 0 }
+            out_acks.each do |ack| 
+                hif(ack == 1) { in_req <= 0 }
+            end
+            hif(in_req) do
+                in_ack <= 0
+                in_ch.read(data) { in_ack <= 1 }
+            end
+            hif(in_ack) do
+                out_chs.zip(out_acks).each do |ch,ack|
+                    hif(ack == 0) { ch.write(data) { ack <= 1 } }
+                end
+                hif (out_acks.reduce(_1) { |sum,ack| ack & sum }) do
+                    out_acks.each { |ack| ack <= 0 }
+                end
+            end
+        end
+    end
+
+    # Function for generating a connector that merges the output of
+    # channels +in_chs+ and connects the result to channel +out_ch+ with
+    # data of types from +typs+.
+    # The merge is done according to event +ev+.
+    function :merger do |typs, ev, in_chs, out_ch|
+        ev = ev.posedge unless ev.is_a?(Event)
+        inner :out_ack
+        in_reqs = in_chs.size.times.map { |i| inner(:"in_req#{i}") }
+        in_acks = in_chs.size.times.map { |i| inner(:"in_ack#{i}") }
+        datas =   typs.map.with_index { |typ,i| typ.inner(:"data#{i}") }
+        par(ev) do
+            in_reqs.each { |req| req <= 1 }
+            out_ack <= 0
+            hif(out_ack == 1) { in_reqs.each { |req| req <= 0 } }
+            hif(in_reqs.reduce(_1) { |sum,req| req & sum }) do
+                in_chs.each_with_index do |ch,i|
+                    in_acks[i] <= 0
+                    ch.read(datas[i]) { in_acks[i] <= 1 }
+                end
+            end
+            hif(in_acks.reduce(_1) { |sum,req| req & sum }) do
+                hif(out_ack == 0) { out_ch.write(datas) { out_ack <= 1 } }
+                hif (out_ack == 1) { out_ack <= 0 }
+            end
+        end
+    end
+
+
+    # Function for generating a connector that serialize to the output of
+    # channels +in_chs+ and connects the result to channel +out_ch+ with
+    # data of +typ+.
+    # The merge is done according to event +ev+.
+    function :serializer do |typ, ev, in_chs, out_ch|
+        ev = ev.posedge unless ev.is_a?(Event)
+        size = in_chs.size
+        inner :out_ack
+        # in_reqs = size.times.map { |i| inner(:"in_req#{i}") }
+        in_acks = size.times.map { |i| inner(:"in_ack#{i}") }
+        datas =   size.times.map { |i| typ.inner(:"data#{i}") }
+        # The inpt channel selector
+        [size.width].inner :idx
+        inner :reading
+        par(ev) do
+            # in_reqs.each { |req| req <= 1 }
+            idx <= 0
+            reading <= 0
+            out_ack <= 0
+            # hif(idx == size) { in_reqs.each { |req| req <= 0 } }
+            # hif((idx == 0) & (in_reqs.reduce(_1) { |sum,req| req & sum })) do
+            hif(idx == 0) do
+                hif(~reading) do
+                    size.times { |i| in_acks[i] <= 0 }
+                end
+                reading <= 1
+                in_chs.each_with_index do |ch,i|
+                    ch.read(datas[i]) { in_acks[i] <= 1 }
+                end
+            end
+            hif(in_acks.reduce(_1) { |sum,req| req & sum }) do
+                hcase(idx)
+                datas.each_with_index do |data,i|
+                    hwhen(i) do
+                        out_ch.write(data) { idx <= idx + 1; out_ack <= 1 }
+                    end
+                end
+            end
+        end
+    end
+
+
+end 

data/lib/HDLRuby/std/memory.rb

@@ -958,7 +958,7 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
         # Declares the address counter.
         awidth = (size-1).width
         awidth = 1 if awidth == 0
-        [size.width-1].inner :abus_r
+        [awidth].inner :abus_r
         reader_inout :abus_r
 
         # Defines the read procedure at address +addr+
@@ -1002,7 +1002,9 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
             writer_input rst_name
         end
         # Declares the address counter.
-        [size.width-1].inner :abus_w
+        awidth = (size-1).width
+        awidth = 1 if awidth == 0
+        [awidth].inner :abus_w
         writer_inout :abus_w
 
         # Defines the write procedure at address +addr+
@@ -1050,7 +1052,7 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
         # Declares the address counter.
         awidth = (size-1).width
         awidth = 1 if awidth == 0
-        [size.width-1].inner :abus_r
+        [awidth].inner :abus_r
         reader_inout :abus_r
 
         # Defines the read procedure at address +addr+
@@ -1094,7 +1096,9 @@ HDLRuby::High::Std.channel(:mem_file) do |typ,size,clk,rst,br_rsts = {}|
             reader_input rst_name
         end
         # Declares the address counter.
-        [size.width-1].inner :abus_w
+        awidth = (size-1).width
+        awidth = 1 if awidth == 0
+        [awidth].inner :abus_w
         reader_inout :abus_w
 
         # Defines the write procedure at address +addr+

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.4.11"
+  VERSION = "2.4.18"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.4.11
+  version: 2.4.18
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire: 
 bindir: exe
 cert_chain: []
-date: 2020-10-19 00:00:00.000000000 Z
+date: 2020-12-04 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -66,6 +66,10 @@ files:
 - lib/HDLRuby/alcc.rb
 - lib/HDLRuby/backend/hruby_allocator.rb
 - lib/HDLRuby/backend/hruby_c_allocator.rb
+- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_hs_32.v
+- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_213.v
+- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_222.v
+- lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_rg_23.v
 - lib/HDLRuby/hdr_samples/adder.rb
 - lib/HDLRuby/hdr_samples/adder_assign_error.rb
 - lib/HDLRuby/hdr_samples/adder_bench.rb
@@ -84,6 +88,8 @@ files:
 - lib/HDLRuby/hdr_samples/include.rb
 - lib/HDLRuby/hdr_samples/instance_open.rb
 - lib/HDLRuby/hdr_samples/linear_test.rb
+- lib/HDLRuby/hdr_samples/make_multi_channels_v.rb
+- lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb
 - lib/HDLRuby/hdr_samples/mei8.rb
 - lib/HDLRuby/hdr_samples/mei8_bench.rb
 - lib/HDLRuby/hdr_samples/memory_test.rb
@@ -119,6 +125,7 @@ files:
 - lib/HDLRuby/hdr_samples/tuple.rb
 - lib/HDLRuby/hdr_samples/with_channel.rb
 - lib/HDLRuby/hdr_samples/with_class.rb
+- lib/HDLRuby/hdr_samples/with_connector.rb
 - lib/HDLRuby/hdr_samples/with_decoder.rb
 - lib/HDLRuby/hdr_samples/with_fixpoint.rb
 - lib/HDLRuby/hdr_samples/with_fsm.rb
@@ -271,6 +278,7 @@ files:
 - lib/HDLRuby/sim/hruby_value_pool.c
 - lib/HDLRuby/std/channel.rb
 - lib/HDLRuby/std/clocks.rb
+- lib/HDLRuby/std/connector.rb
 - lib/HDLRuby/std/counters.rb
 - lib/HDLRuby/std/decoder.rb
 - lib/HDLRuby/std/fixpoint.rb