HDLRuby 2.4.11 → 2.4.18

data/lib/HDLRuby/hdr_samples/make_multi_channels_v.rb

@@ -0,0 +1,24 @@
+#!/usr/bin/ruby
+# Script for generating the vcd files.
+
+# The configuration scenarii
+$scenarii = [
+              [:_clk2_clk2,      :register],    #  0
+              [:_clk2_nclk2,     :register],    #  1
+              [:_clk2_clk3,      :register],    #  2
+              [:_clk3_clk2,      :register],    #  3
+              [:_clk2_clk2,      :handshake],   #  4
+              [:_clk2_nclk2,     :handshake],   #  5
+              [:_clk2_clk3,      :handshake],   #  6
+              [:_clk3_clk2,      :handshake],   #  7
+              [:clk2_clk2_clk2,  :queue],       #  8
+              [:clk2_clk2_nclk2, :queue],       #  9
+              [:clk1_clk2_clk3,  :queue],       # 10
+              [:clk3_clk2_clk1,  :queue],       # 11
+              [:clk2_clk3_clk1,  :queue],       # 12
+              [:clk2_clk1_clk3,  :queue],       # 13
+            ]
+$scenarii.each_with_index do |scenarii,i|
+    puts "scenario: [#{i}] #{scenarii}"
+    `bundle exec ../hdrcc.rb --verilog with_multi_channels.rb WithMultiChannelPaper.V#{i} #{i}`
+end

data/lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb

@@ -0,0 +1,25 @@
+#!/usr/bin/ruby
+# Script for generating the vcd files.
+
+# The configuration scenarii
+$scenarii = [
+              [:_clk2_clk2,      :register],    #  0
+              [:_clk2_nclk2,     :register],    #  1
+              [:_clk2_clk3,      :register],    #  2
+              [:_clk3_clk2,      :register],    #  3
+              [:_clk2_clk2,      :handshake],   #  4
+              [:_clk2_nclk2,     :handshake],   #  5
+              [:_clk2_clk3,      :handshake],   #  6
+              [:_clk3_clk2,      :handshake],   #  7
+              [:clk2_clk2_clk2,  :queue],       #  8
+              [:clk2_clk2_nclk2, :queue],       #  9
+              [:clk1_clk2_clk3,  :queue],       # 10
+              [:clk3_clk2_clk1,  :queue],       # 11
+              [:clk2_clk3_clk1,  :queue],       # 12
+              [:clk2_clk1_clk3,  :queue],       # 13
+            ]
+$scenarii.each_with_index do |scenarii,i|
+    puts "scenario: [#{i}] #{scenarii}"
+    `bundle exec ../hdrcc.rb -S --vcd with_multi_channels.rb WithMultiChannelPaper #{i}`
+    `mv WithMultiChannelPaper/hruby_simulator.vcd WithMultiChannelPaper/#{i.to_s.to_s.rjust(2,"0")}_#{scenarii[0]}_#{scenarii[1]}.vcd`
+end

data/lib/HDLRuby/hdr_samples/mei8_bench.rb

@@ -5,7 +5,7 @@ include HDLRuby::High::Std
 # A simple implementation of the MEI8 processor.
 #
 # In this implementation, the program is hard-coded in an internal ROM
-system :mei8 do |prog_file = "./prog_encrypt.obj"|
+system :mei8 do |prog_file = "./prog.obj"|
     # Clock and reset.
     input :clk, :rst
     # Bus.

data/lib/HDLRuby/hdr_samples/with_connector.rb

@@ -0,0 +1,245 @@
+require 'std/channel.rb'
+require 'std/connector.rb'
+
+include HDLRuby::High::Std
+
+# Sample for testing the connectors of channels.
+
+# Channel describing a buffered queue storing data of +typ+ type of +depth+,
+# synchronized through clk and reset on +rst+.
+channel(:queue) do |typ,depth,clk,rst|
+    # The inner buffer of the queue.
+    typ[-depth].inner :buffer
+    # The read and write pointers.
+    [depth.width].inner :rptr, :wptr
+    # The read and write command signals.
+    inner :rreq, :wreq
+    # The read and write ack signals.
+    inner :rack, :wack
+    # The read/write data registers.
+    typ.inner :rdata, :wdata
+
+    # The flags telling of the channel is synchronized
+    inner :rsync, :wsync
+
+    # The process handling the decoupled access to the buffer.
+    par(clk.posedge) do
+        hif(rst) { rptr <= 0; wptr <= 0 }
+        helse do
+            hif(~rsync) do
+                hif (~rreq) { rack <= 0 }
+                hif(rreq & (~rack) & (rptr != wptr)) do
+                    rdata <= buffer[rptr]
+                    rptr <= (rptr + 1) % depth
+                    rack <= 1
+                end
+            end
+
+            hif(~wsync) do
+                hif (~wreq) { wack <= 0 }
+                hif(wreq & (~wack) & (((wptr+1) % depth) != rptr)) do
+                    buffer[wptr] <= wdata
+                    wptr <= (wptr + 1) % depth
+                    wack <= 1
+                end
+            end
+        end
+    end
+
+    reader_output :rreq, :rptr, :rsync
+    reader_input :rdata, :rack, :wptr, :buffer
+
+    # The read primitive.
+    reader do |blk,target|
+        if (cur_behavior.on_event?(clk.posedge,clk.negedge)) then
+            # Same clk event, synchrone case: perform a direct access.
+            # Now perform the access.
+            top_block.unshift do
+                rsync <= 1
+                rreq <= 0
+            end
+            seq do
+                hif(rptr != wptr) do
+                    # target <= rdata
+                    target <= buffer[rptr]
+                    rptr <= (rptr + 1) % depth
+                    blk.call if blk
+                end
+            end
+        else
+            # Different clk event, perform a decoupled access.
+            top_block.unshift do
+                rsync <= 0
+                rreq <= 0
+            end
+            par do
+                hif (~rack) { rreq <= 1 }
+                helsif(rreq) do
+                    rreq <= 0
+                    target <= rdata
+                    blk.call if blk
+                end
+            end
+        end
+    end
+
+    writer_output :wreq, :wdata, :wptr, :wsync, :buffer
+    writer_input :wack, :rptr
+
+    # The write primitive.
+    writer do |blk,target|
+        if (cur_behavior.on_event?(clk.negedge,clk.posedge)) then
+            # Same clk event, synchrone case: perform a direct access.
+            top_block.unshift do
+                wsync <= 1
+                wreq <= 0
+            end
+            hif(((wptr+1) % depth) != rptr) do
+                buffer[wptr] <= target
+                wptr <= (wptr + 1) % depth
+                blk.call if blk
+            end
+        else
+            # Different clk event, asynchrone case: perform a decoupled access.
+            top_block.unshift do
+                wsync <= 0
+                wreq <= 0
+            end
+            seq do
+                hif (~wack) do
+                    wreq <= 1
+                    wdata <= target
+                end
+                helsif(wreq) do
+                    wreq <= 0
+                    blk.call if blk
+                end
+            end
+        end
+    end
+end
+
+
+
+
+# Module for testing the connector.
+system :with_connectors do
+    inner :clk, :rst
+
+    # First tester.
+    [4].inner :counter
+    [4*4].inner :res
+    inner :ack_in, :ack_out
+
+    # The input queue.
+    queue(bit[4],4,clk,rst).(:in_qu)
+
+    # The middle queues.
+    mid_qus = 4.times.map do |i|
+        queue(bit[4],4,clk,rst).(:"mid_qu#{i}")
+    end
+
+    # The output queue.
+    queue(bit[4*4],4,clk,rst).(:out_qu)
+
+    # Connect the input queue to the middle queues.
+    duplicator(bit[4],clk.negedge,in_qu,mid_qus)
+
+    # Connect the middle queues to the output queue.
+    merger([bit[4]]*4,clk.negedge,mid_qus,out_qu)
+
+
+    # Second tester.
+    [4].inner :counterb
+    [4].inner :resb
+    inner :ack_inb0, :ack_inb1, :ack_outb
+
+    # The input queues.
+    queue(bit[4],4,clk,rst).(:in_qub0)
+    queue(bit[4],4,clk,rst).(:in_qub1)
+
+    # The output queue.
+    queue(bit[4],4,clk,rst).(:out_qub)
+
+    # Connect then with a serializer.
+    serializer(bit[4],clk.negedge,[in_qub0,in_qub1],out_qub)
+
+    # # Slow version, always work
+    # par(clk.posedge) do
+    #     ack_in <= 0
+    #     ack_out <= 1
+    #     hif(rst) { counter <= 0 }
+    #     helse do
+    #         hif(ack_out) do
+    #             ack_out <= 0
+    #             in_qu.write(counter)  do
+    #                 ack_in <= 1
+    #                 counter <= counter + 1
+    #             end
+    #         end
+    #         hif(ack_in) do
+    #             mid_qu0.read(res_0)
+    #             mid_qu1.read(res_1)
+    #             mid_qu2.read(res_2)
+    #             mid_qu3.read(res_3) { ack_out <= 1 }
+    #         end
+    #     end
+    # end
+
+    # Fast version but assumes connected channels are blocking
+    par(clk.posedge) do
+        ack_in <= 0
+        ack_inb0 <= 0
+        ack_inb1 <= 0
+        hif(rst) { counter <= 0; counterb <= 0 }
+        helse do
+            in_qu.write(counter)  do
+                ack_in <= 1
+                counter <= counter + 1
+            end
+            hif(ack_in) do
+                out_qu.read(res)
+            end
+            hif(~ack_inb0) do
+                in_qub0.write(counterb) do
+                    ack_inb0 <= 1
+                    counterb <= counterb + 1
+                end
+            end
+            helse do
+                in_qub1.write(counterb) do
+                    ack_inb1 <= 1
+                    counterb <= counterb + 1
+                end
+            end
+            hif(ack_inb0 | ack_inb1) do
+                out_qub.read(resb)
+            end
+        end
+    end
+
+    timed do
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        16.times do
+            !10.ns
+            clk <= 1
+            !10.ns
+            clk <= 0
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_fixpoint.rb

@@ -32,6 +32,18 @@ system :fix_test do
         !10.ns
         d <= d + c 
         !10.ns
+        d <= d / c
+        !10.ns
+        d <= d / 3.to_fix(4)
+        !10.ns
+        d <= 1.to_fix(4) - d
+        !10.ns
+        d <= -d
+        !10.ns
+        d <= d * 3.to_fix(4)
+        !10.ns
+        d <= -d
+        !10.ns
         a <= -0.375.to_fix(4)
         b <= 1.625.to_fix(4)
         !10.ns

data/lib/HDLRuby/hdr_samples/with_multi_channels.rb

@@ -10,36 +10,41 @@ channel(:queue) do |typ,depth,clk,rst|
     # The read and write pointers.
     [depth.width].inner :rptr, :wptr
     # The read and write command signals.
-    inner :rcmd, :wcmd
+    inner :rreq, :wreq
     # The read and write ack signals.
     inner :rack, :wack
-    # The ack check deactivator (for synchron accesses).
-    inner :hrack, :hwack
     # The read/write data registers.
     typ.inner :rdata, :wdata
 
+    # The flags telling of the channel is synchronized
+    inner :rsync, :wsync
+
     # The process handling the decoupled access to the buffer.
     par(clk.posedge) do
-        # rack <= 0
-        # wack <= 0
-        hif (~rcmd) { rack <= 0 }
-        hif (~wcmd) { wack <= 0 }
         hif(rst) { rptr <= 0; wptr <= 0 }
-        hif(rcmd & (hrack|~rack) & (rptr != wptr)) do
-            rptr <= (rptr + 1) % depth
-            rack <= 1
-        end
-        hif(wcmd & (hwack|~wack) & (((wptr+1) % depth) != rptr)) do
-            buffer[wptr] <= wdata
-            # buffer[1] <= wdata
-            wptr <= (wptr + 1) % depth
-            wack <= 1
+        helse do
+            hif(~rsync) do
+                hif (~rreq) { rack <= 0 }
+                hif(rreq & (~rack) & (rptr != wptr)) do
+                    rdata <= buffer[rptr]
+                    rptr <= (rptr + 1) % depth
+                    rack <= 1
+                end
+            end
+
+            hif(~wsync) do
+                hif (~wreq) { wack <= 0 }
+                hif(wreq & (~wack) & (((wptr+1) % depth) != rptr)) do
+                    buffer[wptr] <= wdata
+                    wptr <= (wptr + 1) % depth
+                    wack <= 1
+                end
+            end
         end
     end
-    par { rdata <= buffer[rptr] }
 
-    reader_output :rcmd, :rptr, :hrack
-    reader_input :rdata, :rack
+    reader_output :rreq, :rptr, :rsync
+    reader_input :rdata, :rack, :wptr, :buffer
 
     # The read primitive.
     reader do |blk,target|
@@ -47,58 +52,64 @@ channel(:queue) do |typ,depth,clk,rst|
             # Same clk event, synchrone case: perform a direct access.
             # Now perform the access.
             top_block.unshift do
-                rcmd <= 0
-                hrack <= 1
+                rsync <= 1
+                rreq <= 0
             end
             seq do
-                rptr <= (rptr + 1) % depth
-                target <= rdata
-                blk.call if blk
+                hif(rptr != wptr) do
+                    target <= buffer[rptr]
+                    rptr <= (rptr + 1) % depth
+                    blk.call if blk
+                end
             end
         else
             # Different clk event, perform a decoupled access.
             top_block.unshift do
-                rcmd <= 0
-                hrack <= 0
+                rsync <= 0
+                rreq <= 0
             end
-            seq do
-                hif(rack) do
-                    blk.call if blk
-                end
-                helse do
-                    rcmd <= 1 
+            par do
+                hif (~rack) { rreq <= 1 }
+                helsif(rreq) do
+                    rreq <= 0
                     target <= rdata
+                    blk.call if blk
                 end
             end
         end
     end
 
-    writer_output :wcmd, :wdata, :hwack
-    writer_input :wack
+    writer_output :wreq, :wdata, :wptr, :wsync, :buffer
+    writer_input :wack, :rptr
 
     # The write primitive.
     writer do |blk,target|
         if (cur_behavior.on_event?(clk.negedge,clk.posedge)) then
             # Same clk event, synchrone case: perform a direct access.
             top_block.unshift do
-                wcmd <= 0
-                hwack <= 1
+                wsync <= 1
+                wreq <= 0
+            end
+            hif(((wptr+1) % depth) != rptr) do
+                buffer[wptr] <= target
+                wptr <= (wptr + 1) % depth
+                blk.call if blk
             end
-            wcmd <= 1
-            wdata <= target
-            blk.call if blk
         else
             # Different clk event, asynchrone case: perform a decoupled access.
             top_block.unshift do
-                wcmd <= 0
-                hwack <= 0
+                wsync <= 0
+                wreq <= 0
             end
             seq do
-                hif(wack) do
+                hif (~wack) do
+                    wreq <= 1
+                    wdata <= target
+                end
+                helsif(wreq) do
+                    wreq <= 0
                     blk.call if blk
                 end
-                helse { wcmd <= 1 }
-                wdata <= target
             end
         end
     end
@@ -174,110 +185,102 @@ channel(:handshake) do |typ|
 end
 
 
-# $mode = :sync
-# $mode = :nsync
-# $mode = :async
-# $mode = :proco  # Producter / Consummer
+# $mode: channel clock, producer clock, consumer clock (n: not clock)
 # $channel = :register
 # $channel = :handshake
 # $channel = :queue
 
 # The configuration scenarii
-$scenarii = [ [:sync,  :register], [:sync,  :handshake], [:sync,  :queue],
-              [:nsync, :register], [:nsync, :handshake], [:nsync, :queue],
-              [:async, :register], [:async, :handshake], [:async, :queue],
-              [:proco, :register], [:proco, :handshake], [:proco, :queue] ]
+$scenarii = [
+              [:_clk2_clk2,      :register],    #  0
+              [:_clk2_nclk2,     :register],    #  1
+              [:_clk2_clk3,      :register],    #  2
+              [:_clk3_clk2,      :register],    #  3
+              [:_clk2_clk2,      :handshake],   #  4
+              [:_clk2_nclk2,     :handshake],   #  5
+              [:_clk2_clk3,      :handshake],   #  6
+              [:_clk3_clk2,      :handshake],   #  7
+              [:clk2_clk2_clk2,  :queue],       #  8
+              [:clk2_clk2_nclk2, :queue],       #  9
+              [:clk1_clk2_clk3,  :queue],       # 10
+              [:clk3_clk2_clk1,  :queue],       # 11
+              [:clk2_clk3_clk1,  :queue],       # 12
+              [:clk2_clk1_clk3,  :queue],       # 13
+            ]
 
 # The configuration
-$mode, $channel = $scenarii[11]
+# $mode, $channel = $scenarii[11]
+$mode, $channel = $scenarii[ARGV[-1].to_i]
+puts "scenario: #{$scenarii[ARGV[-1].to_i]}"
 
 # Testing the queue channel.
 system :test_queue do
-    inner :clk, :rst, :clk2, :clk3
-    [8].inner :idata, :odata
+    inner :rst, :clk1, :clk2, :clk3
+    [8].inner :idata, :odata, :odata2
     [4].inner :counter
 
+
+    # Assign the clocks
+    mode = $mode.to_s.split("_")
+    if ($channel == :queue) then
+        clk_que = send(mode[0])
+    end
+    ev_pro = mode[1][0] == "n" ? 
+        send(mode[1][1..-1]).negedge : send(mode[1]).posedge
+    ev_con = mode[2][0] == "n" ? 
+        send(mode[2][1..-1]).negedge : send(mode[2]).posedge
+
+    # Set up the channel
     if $channel == :register then
         register(bit[8]).(:my_ch)
     elsif $channel == :handshake then
         handshake(bit[8],rst).(:my_ch)
     elsif $channel == :queue then
-        queue(bit[8],5,clk,rst).(:my_ch)
+        queue(bit[8],3,clk_que,rst).(:my_ch)
     end
 
-    ev = $mode == :sync ? clk.posedge : 
-         $mode == :nsync ? clk.negedge : clk2.posedge
-
-    if $mode != :proco then
-        # Sync/Neg sync and async tests mode
-        par(ev) do
-            hif(rst) do
-                counter <= 0
-                idata <= 0
-                odata <= 0
-            end
-            helse do
-                hif (counter < 4) do
-                    my_ch.write(idata) do
-                        idata <= idata + 1
-                        counter <= counter + 1
-                    end
-                end
-                helsif ((counter > 10) & (counter < 15)) do
-                    my_ch.read(odata) do
-                        idata <= idata - odata
-                        counter <= counter + 1
-                    end
-                end
-                helse do
-                    counter <= counter + 1
-                end
-            end
+    # Producter/consumer mode
+    # Producer
+    par(ev_pro) do
+        hif(rst) do
+            idata <= 0
         end
-    else
-        # Producter/consumer mode
-        # Producer
-        par(clk2.posedge) do
-            hif(rst) do
-                idata <= 0
-            end
-            helse do
-                my_ch.write(idata) do
-                    idata <= idata + 1
-                end
+        helse do
+            my_ch.write(idata) do
+                idata <= idata + 1
             end
         end
-        # Consumer
-        par(clk3.posedge) do
-            hif(rst) do
-                counter <= 0
-            end
-            helse do
-                my_ch.read(odata) do
-                    counter <= counter + 1
-                end
+    end
+    # Consumer
+    par(ev_con) do
+        hif(rst) do
+            counter <= 0
+        end
+        helse do
+            my_ch.read(odata) do
+                counter <= counter + 1
             end
         end
     end
 
     timed do
-        clk <= 0
+        clk1 <= 0
         clk2 <= 0
         clk3 <= 0
         rst <= 0
         !10.ns
-        clk <= 1
+        clk1 <= 1
         !10.ns
-        clk <= 0
+        clk1 <= 0
         rst <= 1
         !3.ns
         clk2 <= 1
         !3.ns
         clk3 <= 0
         !4.ns
-        clk <= 1
+        clk1 <= 1
         !10.ns
-        clk <= 0
+        clk1 <= 0
         !3.ns
         clk2 <= 0
         !3.ns
@@ -286,9 +289,9 @@ system :test_queue do
         rst <= 0
         !2.ns
         64.times do
-            clk <= 1
+            clk1 <= 1
             !10.ns
-            clk <= 0
+            clk1 <= 0
             !3.ns
             clk2 <= ~clk2
             !3.ns