HDLRuby 2.4.11 → 2.4.18
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_hs_32.v +1277 -0
- data/lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_213.v +1345 -0
- data/lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_qu_222.v +1339 -0
- data/lib/HDLRuby/hdr_samples/WithMultiChannelExpVerilog/with_multi_channels_rg_23.v +1248 -0
- data/lib/HDLRuby/hdr_samples/make_multi_channels_v.rb +24 -0
- data/lib/HDLRuby/hdr_samples/make_multi_channels_vcd.rb +25 -0
- data/lib/HDLRuby/hdr_samples/mei8_bench.rb +1 -1
- data/lib/HDLRuby/hdr_samples/with_connector.rb +245 -0
- data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +12 -0
- data/lib/HDLRuby/hdr_samples/with_multi_channels.rb +114 -111
- data/lib/HDLRuby/hruby_tools.rb +7 -1
- data/lib/HDLRuby/sim/hruby_sim_calc.c +3 -1
- data/lib/HDLRuby/std/connector.rb +108 -0
- data/lib/HDLRuby/std/memory.rb +8 -4
- data/lib/HDLRuby/version.rb +1 -1
- metadata +10 -2
@@ -0,0 +1,24 @@
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#!/usr/bin/ruby
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# Script for generating the vcd files.
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# The configuration scenarii
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$scenarii = [
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[:_clk2_clk2, :register], # 0
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[:_clk2_nclk2, :register], # 1
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[:_clk2_clk3, :register], # 2
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[:_clk3_clk2, :register], # 3
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[:_clk2_clk2, :handshake], # 4
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[:_clk2_nclk2, :handshake], # 5
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[:_clk2_clk3, :handshake], # 6
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[:_clk3_clk2, :handshake], # 7
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[:clk2_clk2_clk2, :queue], # 8
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[:clk2_clk2_nclk2, :queue], # 9
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[:clk1_clk2_clk3, :queue], # 10
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[:clk3_clk2_clk1, :queue], # 11
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[:clk2_clk3_clk1, :queue], # 12
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[:clk2_clk1_clk3, :queue], # 13
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]
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$scenarii.each_with_index do |scenarii,i|
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puts "scenario: [#{i}] #{scenarii}"
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`bundle exec ../hdrcc.rb --verilog with_multi_channels.rb WithMultiChannelPaper.V#{i} #{i}`
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end
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@@ -0,0 +1,25 @@
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#!/usr/bin/ruby
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# Script for generating the vcd files.
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# The configuration scenarii
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$scenarii = [
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[:_clk2_clk2, :register], # 0
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[:_clk2_nclk2, :register], # 1
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[:_clk2_clk3, :register], # 2
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[:_clk3_clk2, :register], # 3
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[:_clk2_clk2, :handshake], # 4
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[:_clk2_nclk2, :handshake], # 5
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[:_clk2_clk3, :handshake], # 6
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[:_clk3_clk2, :handshake], # 7
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[:clk2_clk2_clk2, :queue], # 8
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[:clk2_clk2_nclk2, :queue], # 9
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[:clk1_clk2_clk3, :queue], # 10
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[:clk3_clk2_clk1, :queue], # 11
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[:clk2_clk3_clk1, :queue], # 12
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[:clk2_clk1_clk3, :queue], # 13
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]
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$scenarii.each_with_index do |scenarii,i|
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puts "scenario: [#{i}] #{scenarii}"
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`bundle exec ../hdrcc.rb -S --vcd with_multi_channels.rb WithMultiChannelPaper #{i}`
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`mv WithMultiChannelPaper/hruby_simulator.vcd WithMultiChannelPaper/#{i.to_s.to_s.rjust(2,"0")}_#{scenarii[0]}_#{scenarii[1]}.vcd`
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end
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@@ -5,7 +5,7 @@ include HDLRuby::High::Std
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# A simple implementation of the MEI8 processor.
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#
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# In this implementation, the program is hard-coded in an internal ROM
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system :mei8 do |prog_file = "./
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system :mei8 do |prog_file = "./prog.obj"|
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# Clock and reset.
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input :clk, :rst
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# Bus.
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@@ -0,0 +1,245 @@
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require 'std/channel.rb'
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require 'std/connector.rb'
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include HDLRuby::High::Std
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# Sample for testing the connectors of channels.
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# Channel describing a buffered queue storing data of +typ+ type of +depth+,
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# synchronized through clk and reset on +rst+.
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channel(:queue) do |typ,depth,clk,rst|
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# The inner buffer of the queue.
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typ[-depth].inner :buffer
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# The read and write pointers.
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[depth.width].inner :rptr, :wptr
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# The read and write command signals.
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inner :rreq, :wreq
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# The read and write ack signals.
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inner :rack, :wack
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# The read/write data registers.
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typ.inner :rdata, :wdata
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# The flags telling of the channel is synchronized
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inner :rsync, :wsync
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# The process handling the decoupled access to the buffer.
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par(clk.posedge) do
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hif(rst) { rptr <= 0; wptr <= 0 }
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helse do
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hif(~rsync) do
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hif (~rreq) { rack <= 0 }
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hif(rreq & (~rack) & (rptr != wptr)) do
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rdata <= buffer[rptr]
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rptr <= (rptr + 1) % depth
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rack <= 1
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end
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end
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hif(~wsync) do
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hif (~wreq) { wack <= 0 }
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hif(wreq & (~wack) & (((wptr+1) % depth) != rptr)) do
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buffer[wptr] <= wdata
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wptr <= (wptr + 1) % depth
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wack <= 1
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end
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end
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end
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end
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reader_output :rreq, :rptr, :rsync
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reader_input :rdata, :rack, :wptr, :buffer
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# The read primitive.
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reader do |blk,target|
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if (cur_behavior.on_event?(clk.posedge,clk.negedge)) then
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# Same clk event, synchrone case: perform a direct access.
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# Now perform the access.
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top_block.unshift do
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rsync <= 1
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rreq <= 0
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end
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seq do
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hif(rptr != wptr) do
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# target <= rdata
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target <= buffer[rptr]
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rptr <= (rptr + 1) % depth
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blk.call if blk
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end
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end
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else
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# Different clk event, perform a decoupled access.
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top_block.unshift do
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rsync <= 0
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rreq <= 0
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end
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par do
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hif (~rack) { rreq <= 1 }
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helsif(rreq) do
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rreq <= 0
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target <= rdata
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blk.call if blk
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end
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end
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end
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end
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writer_output :wreq, :wdata, :wptr, :wsync, :buffer
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writer_input :wack, :rptr
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# The write primitive.
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writer do |blk,target|
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if (cur_behavior.on_event?(clk.negedge,clk.posedge)) then
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# Same clk event, synchrone case: perform a direct access.
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top_block.unshift do
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wsync <= 1
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wreq <= 0
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end
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hif(((wptr+1) % depth) != rptr) do
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buffer[wptr] <= target
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wptr <= (wptr + 1) % depth
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blk.call if blk
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end
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else
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# Different clk event, asynchrone case: perform a decoupled access.
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top_block.unshift do
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wsync <= 0
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wreq <= 0
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end
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seq do
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hif (~wack) do
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wreq <= 1
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wdata <= target
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end
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helsif(wreq) do
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wreq <= 0
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blk.call if blk
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end
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end
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end
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end
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end
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# Module for testing the connector.
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system :with_connectors do
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inner :clk, :rst
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# First tester.
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[4].inner :counter
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[4*4].inner :res
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inner :ack_in, :ack_out
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# The input queue.
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queue(bit[4],4,clk,rst).(:in_qu)
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# The middle queues.
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mid_qus = 4.times.map do |i|
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queue(bit[4],4,clk,rst).(:"mid_qu#{i}")
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end
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# The output queue.
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queue(bit[4*4],4,clk,rst).(:out_qu)
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# Connect the input queue to the middle queues.
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duplicator(bit[4],clk.negedge,in_qu,mid_qus)
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# Connect the middle queues to the output queue.
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merger([bit[4]]*4,clk.negedge,mid_qus,out_qu)
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# Second tester.
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[4].inner :counterb
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[4].inner :resb
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inner :ack_inb0, :ack_inb1, :ack_outb
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# The input queues.
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queue(bit[4],4,clk,rst).(:in_qub0)
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queue(bit[4],4,clk,rst).(:in_qub1)
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# The output queue.
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queue(bit[4],4,clk,rst).(:out_qub)
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# Connect then with a serializer.
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serializer(bit[4],clk.negedge,[in_qub0,in_qub1],out_qub)
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# # Slow version, always work
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# par(clk.posedge) do
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# ack_in <= 0
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# ack_out <= 1
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# hif(rst) { counter <= 0 }
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# helse do
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# hif(ack_out) do
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# ack_out <= 0
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# in_qu.write(counter) do
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# ack_in <= 1
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# counter <= counter + 1
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# end
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# end
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# hif(ack_in) do
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# mid_qu0.read(res_0)
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# mid_qu1.read(res_1)
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# mid_qu2.read(res_2)
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# mid_qu3.read(res_3) { ack_out <= 1 }
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# end
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# end
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# end
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# Fast version but assumes connected channels are blocking
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par(clk.posedge) do
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ack_in <= 0
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ack_inb0 <= 0
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ack_inb1 <= 0
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hif(rst) { counter <= 0; counterb <= 0 }
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helse do
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in_qu.write(counter) do
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ack_in <= 1
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counter <= counter + 1
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end
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hif(ack_in) do
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out_qu.read(res)
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end
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hif(~ack_inb0) do
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in_qub0.write(counterb) do
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ack_inb0 <= 1
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counterb <= counterb + 1
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end
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end
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helse do
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in_qub1.write(counterb) do
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ack_inb1 <= 1
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counterb <= counterb + 1
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end
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end
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hif(ack_inb0 | ack_inb1) do
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out_qub.read(resb)
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end
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end
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end
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timed do
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clk <= 0
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rst <= 0
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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rst <= 1
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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rst <= 0
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16.times do
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!10.ns
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clk <= 1
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!10.ns
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clk <= 0
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end
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end
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end
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@@ -32,6 +32,18 @@ system :fix_test do
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!10.ns
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d <= d + c
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!10.ns
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d <= d / c
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!10.ns
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d <= d / 3.to_fix(4)
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!10.ns
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d <= 1.to_fix(4) - d
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!10.ns
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d <= -d
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!10.ns
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d <= d * 3.to_fix(4)
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!10.ns
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d <= -d
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!10.ns
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a <= -0.375.to_fix(4)
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b <= 1.625.to_fix(4)
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!10.ns
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@@ -10,36 +10,41 @@ channel(:queue) do |typ,depth,clk,rst|
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# The read and write pointers.
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[depth.width].inner :rptr, :wptr
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# The read and write command signals.
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inner :
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inner :rreq, :wreq
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# The read and write ack signals.
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inner :rack, :wack
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# The ack check deactivator (for synchron accesses).
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inner :hrack, :hwack
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# The read/write data registers.
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typ.inner :rdata, :wdata
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# The flags telling of the channel is synchronized
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inner :rsync, :wsync
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# The process handling the decoupled access to the buffer.
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par(clk.posedge) do
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# rack <= 0
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# wack <= 0
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hif (~rcmd) { rack <= 0 }
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hif (~wcmd) { wack <= 0 }
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hif(rst) { rptr <= 0; wptr <= 0 }
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-
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-
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-
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helse do
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hif(~rsync) do
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hif (~rreq) { rack <= 0 }
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hif(rreq & (~rack) & (rptr != wptr)) do
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rdata <= buffer[rptr]
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rptr <= (rptr + 1) % depth
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+
rack <= 1
|
32
|
+
end
|
33
|
+
end
|
34
|
+
|
35
|
+
hif(~wsync) do
|
36
|
+
hif (~wreq) { wack <= 0 }
|
37
|
+
hif(wreq & (~wack) & (((wptr+1) % depth) != rptr)) do
|
38
|
+
buffer[wptr] <= wdata
|
39
|
+
wptr <= (wptr + 1) % depth
|
40
|
+
wack <= 1
|
41
|
+
end
|
42
|
+
end
|
37
43
|
end
|
38
44
|
end
|
39
|
-
par { rdata <= buffer[rptr] }
|
40
45
|
|
41
|
-
reader_output :
|
42
|
-
reader_input :rdata, :rack
|
46
|
+
reader_output :rreq, :rptr, :rsync
|
47
|
+
reader_input :rdata, :rack, :wptr, :buffer
|
43
48
|
|
44
49
|
# The read primitive.
|
45
50
|
reader do |blk,target|
|
@@ -47,58 +52,64 @@ channel(:queue) do |typ,depth,clk,rst|
|
|
47
52
|
# Same clk event, synchrone case: perform a direct access.
|
48
53
|
# Now perform the access.
|
49
54
|
top_block.unshift do
|
50
|
-
|
51
|
-
|
55
|
+
rsync <= 1
|
56
|
+
rreq <= 0
|
52
57
|
end
|
53
58
|
seq do
|
54
|
-
|
55
|
-
|
56
|
-
|
59
|
+
hif(rptr != wptr) do
|
60
|
+
target <= buffer[rptr]
|
61
|
+
rptr <= (rptr + 1) % depth
|
62
|
+
blk.call if blk
|
63
|
+
end
|
57
64
|
end
|
58
65
|
else
|
59
66
|
# Different clk event, perform a decoupled access.
|
60
67
|
top_block.unshift do
|
61
|
-
|
62
|
-
|
68
|
+
rsync <= 0
|
69
|
+
rreq <= 0
|
63
70
|
end
|
64
|
-
|
65
|
-
hif(rack)
|
66
|
-
|
67
|
-
|
68
|
-
helse do
|
69
|
-
rcmd <= 1
|
71
|
+
par do
|
72
|
+
hif (~rack) { rreq <= 1 }
|
73
|
+
helsif(rreq) do
|
74
|
+
rreq <= 0
|
70
75
|
target <= rdata
|
76
|
+
blk.call if blk
|
71
77
|
end
|
72
78
|
end
|
73
79
|
end
|
74
80
|
end
|
75
81
|
|
76
|
-
writer_output :
|
77
|
-
writer_input :wack
|
82
|
+
writer_output :wreq, :wdata, :wptr, :wsync, :buffer
|
83
|
+
writer_input :wack, :rptr
|
78
84
|
|
79
85
|
# The write primitive.
|
80
86
|
writer do |blk,target|
|
81
87
|
if (cur_behavior.on_event?(clk.negedge,clk.posedge)) then
|
82
88
|
# Same clk event, synchrone case: perform a direct access.
|
83
89
|
top_block.unshift do
|
84
|
-
|
85
|
-
|
90
|
+
wsync <= 1
|
91
|
+
wreq <= 0
|
92
|
+
end
|
93
|
+
hif(((wptr+1) % depth) != rptr) do
|
94
|
+
buffer[wptr] <= target
|
95
|
+
wptr <= (wptr + 1) % depth
|
96
|
+
blk.call if blk
|
86
97
|
end
|
87
|
-
wcmd <= 1
|
88
|
-
wdata <= target
|
89
|
-
blk.call if blk
|
90
98
|
else
|
91
99
|
# Different clk event, asynchrone case: perform a decoupled access.
|
92
100
|
top_block.unshift do
|
93
|
-
|
94
|
-
|
101
|
+
wsync <= 0
|
102
|
+
wreq <= 0
|
95
103
|
end
|
96
104
|
seq do
|
97
|
-
hif(wack) do
|
105
|
+
hif (~wack) do
|
106
|
+
wreq <= 1
|
107
|
+
wdata <= target
|
108
|
+
end
|
109
|
+
helsif(wreq) do
|
110
|
+
wreq <= 0
|
98
111
|
blk.call if blk
|
99
112
|
end
|
100
|
-
helse { wcmd <= 1 }
|
101
|
-
wdata <= target
|
102
113
|
end
|
103
114
|
end
|
104
115
|
end
|
@@ -174,110 +185,102 @@ channel(:handshake) do |typ|
|
|
174
185
|
end
|
175
186
|
|
176
187
|
|
177
|
-
# $mode
|
178
|
-
# $mode = :nsync
|
179
|
-
# $mode = :async
|
180
|
-
# $mode = :proco # Producter / Consummer
|
188
|
+
# $mode: channel clock, producer clock, consumer clock (n: not clock)
|
181
189
|
# $channel = :register
|
182
190
|
# $channel = :handshake
|
183
191
|
# $channel = :queue
|
184
192
|
|
185
193
|
# The configuration scenarii
|
186
|
-
$scenarii = [
|
187
|
-
[:
|
188
|
-
[:
|
189
|
-
[:
|
194
|
+
$scenarii = [
|
195
|
+
[:_clk2_clk2, :register], # 0
|
196
|
+
[:_clk2_nclk2, :register], # 1
|
197
|
+
[:_clk2_clk3, :register], # 2
|
198
|
+
[:_clk3_clk2, :register], # 3
|
199
|
+
[:_clk2_clk2, :handshake], # 4
|
200
|
+
[:_clk2_nclk2, :handshake], # 5
|
201
|
+
[:_clk2_clk3, :handshake], # 6
|
202
|
+
[:_clk3_clk2, :handshake], # 7
|
203
|
+
[:clk2_clk2_clk2, :queue], # 8
|
204
|
+
[:clk2_clk2_nclk2, :queue], # 9
|
205
|
+
[:clk1_clk2_clk3, :queue], # 10
|
206
|
+
[:clk3_clk2_clk1, :queue], # 11
|
207
|
+
[:clk2_clk3_clk1, :queue], # 12
|
208
|
+
[:clk2_clk1_clk3, :queue], # 13
|
209
|
+
]
|
190
210
|
|
191
211
|
# The configuration
|
192
|
-
$mode, $channel = $scenarii[11]
|
212
|
+
# $mode, $channel = $scenarii[11]
|
213
|
+
$mode, $channel = $scenarii[ARGV[-1].to_i]
|
214
|
+
puts "scenario: #{$scenarii[ARGV[-1].to_i]}"
|
193
215
|
|
194
216
|
# Testing the queue channel.
|
195
217
|
system :test_queue do
|
196
|
-
inner :
|
197
|
-
[8].inner :idata, :odata
|
218
|
+
inner :rst, :clk1, :clk2, :clk3
|
219
|
+
[8].inner :idata, :odata, :odata2
|
198
220
|
[4].inner :counter
|
199
221
|
|
222
|
+
|
223
|
+
# Assign the clocks
|
224
|
+
mode = $mode.to_s.split("_")
|
225
|
+
if ($channel == :queue) then
|
226
|
+
clk_que = send(mode[0])
|
227
|
+
end
|
228
|
+
ev_pro = mode[1][0] == "n" ?
|
229
|
+
send(mode[1][1..-1]).negedge : send(mode[1]).posedge
|
230
|
+
ev_con = mode[2][0] == "n" ?
|
231
|
+
send(mode[2][1..-1]).negedge : send(mode[2]).posedge
|
232
|
+
|
233
|
+
# Set up the channel
|
200
234
|
if $channel == :register then
|
201
235
|
register(bit[8]).(:my_ch)
|
202
236
|
elsif $channel == :handshake then
|
203
237
|
handshake(bit[8],rst).(:my_ch)
|
204
238
|
elsif $channel == :queue then
|
205
|
-
queue(bit[8],
|
239
|
+
queue(bit[8],3,clk_que,rst).(:my_ch)
|
206
240
|
end
|
207
241
|
|
208
|
-
|
209
|
-
|
210
|
-
|
211
|
-
|
212
|
-
|
213
|
-
par(ev) do
|
214
|
-
hif(rst) do
|
215
|
-
counter <= 0
|
216
|
-
idata <= 0
|
217
|
-
odata <= 0
|
218
|
-
end
|
219
|
-
helse do
|
220
|
-
hif (counter < 4) do
|
221
|
-
my_ch.write(idata) do
|
222
|
-
idata <= idata + 1
|
223
|
-
counter <= counter + 1
|
224
|
-
end
|
225
|
-
end
|
226
|
-
helsif ((counter > 10) & (counter < 15)) do
|
227
|
-
my_ch.read(odata) do
|
228
|
-
idata <= idata - odata
|
229
|
-
counter <= counter + 1
|
230
|
-
end
|
231
|
-
end
|
232
|
-
helse do
|
233
|
-
counter <= counter + 1
|
234
|
-
end
|
235
|
-
end
|
242
|
+
# Producter/consumer mode
|
243
|
+
# Producer
|
244
|
+
par(ev_pro) do
|
245
|
+
hif(rst) do
|
246
|
+
idata <= 0
|
236
247
|
end
|
237
|
-
|
238
|
-
|
239
|
-
|
240
|
-
par(clk2.posedge) do
|
241
|
-
hif(rst) do
|
242
|
-
idata <= 0
|
243
|
-
end
|
244
|
-
helse do
|
245
|
-
my_ch.write(idata) do
|
246
|
-
idata <= idata + 1
|
247
|
-
end
|
248
|
+
helse do
|
249
|
+
my_ch.write(idata) do
|
250
|
+
idata <= idata + 1
|
248
251
|
end
|
249
252
|
end
|
250
|
-
|
251
|
-
|
252
|
-
|
253
|
-
|
254
|
-
|
255
|
-
|
256
|
-
|
257
|
-
|
258
|
-
|
253
|
+
end
|
254
|
+
# Consumer
|
255
|
+
par(ev_con) do
|
256
|
+
hif(rst) do
|
257
|
+
counter <= 0
|
258
|
+
end
|
259
|
+
helse do
|
260
|
+
my_ch.read(odata) do
|
261
|
+
counter <= counter + 1
|
259
262
|
end
|
260
263
|
end
|
261
264
|
end
|
262
265
|
|
263
266
|
timed do
|
264
|
-
|
267
|
+
clk1 <= 0
|
265
268
|
clk2 <= 0
|
266
269
|
clk3 <= 0
|
267
270
|
rst <= 0
|
268
271
|
!10.ns
|
269
|
-
|
272
|
+
clk1 <= 1
|
270
273
|
!10.ns
|
271
|
-
|
274
|
+
clk1 <= 0
|
272
275
|
rst <= 1
|
273
276
|
!3.ns
|
274
277
|
clk2 <= 1
|
275
278
|
!3.ns
|
276
279
|
clk3 <= 0
|
277
280
|
!4.ns
|
278
|
-
|
281
|
+
clk1 <= 1
|
279
282
|
!10.ns
|
280
|
-
|
283
|
+
clk1 <= 0
|
281
284
|
!3.ns
|
282
285
|
clk2 <= 0
|
283
286
|
!3.ns
|
@@ -286,9 +289,9 @@ system :test_queue do
|
|
286
289
|
rst <= 0
|
287
290
|
!2.ns
|
288
291
|
64.times do
|
289
|
-
|
292
|
+
clk1 <= 1
|
290
293
|
!10.ns
|
291
|
-
|
294
|
+
clk1 <= 0
|
292
295
|
!3.ns
|
293
296
|
clk2 <= ~clk2
|
294
297
|
!3.ns
|