HDLRuby 2.2.15 → 2.3.2
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- checksums.yaml +4 -4
- data/README.md +14 -8
- data/lib/HDLRuby/hdr_samples/linear_test.rb +30 -2
- data/lib/HDLRuby/hdr_samples/rom.rb +2 -2
- data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb +96 -0
- data/lib/HDLRuby/hdr_samples/with_fixpoint.rb +3 -2
- data/lib/HDLRuby/hdr_samples/with_linear.rb +4 -1
- data/lib/HDLRuby/hdr_samples/with_loop.rb +69 -0
- data/lib/HDLRuby/hdr_samples/with_memory.rb +13 -3
- data/lib/HDLRuby/hdrcc.rb +3 -6
- data/lib/HDLRuby/hruby_check.rb +25 -1
- data/lib/HDLRuby/hruby_high.rb +12 -4
- data/lib/HDLRuby/hruby_low.rb +24 -9
- data/lib/HDLRuby/hruby_low2c.rb +10 -5
- data/lib/HDLRuby/hruby_low2high.rb +1 -1
- data/lib/HDLRuby/hruby_low2vhd.rb +63 -48
- data/lib/HDLRuby/hruby_low_fix_types.rb +6 -2
- data/lib/HDLRuby/hruby_low_resolve.rb +7 -4
- data/lib/HDLRuby/hruby_low_without_concat.rb +8 -4
- data/lib/HDLRuby/hruby_types.rb +82 -72
- data/lib/HDLRuby/hruby_verilog.rb +9 -1
- data/lib/HDLRuby/sim/hruby_sim.h +7 -0
- data/lib/HDLRuby/sim/hruby_sim_calc.c +83 -6
- data/lib/HDLRuby/std/channel.rb +39 -16
- data/lib/HDLRuby/std/fixpoint.rb +50 -39
- data/lib/HDLRuby/std/linear.rb +131 -11
- data/lib/HDLRuby/std/loop.rb +101 -0
- data/lib/HDLRuby/std/memory.rb +1000 -30
- data/lib/HDLRuby/std/task.rb +850 -0
- data/lib/HDLRuby/version.rb +1 -1
- metadata +6 -2
checksums.yaml
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@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 73fbfcef7b930ac266b56380159ffd3af64f84ce712f937f764559d8abe78ded
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data.tar.gz: 2c7ad1ac7fac5639f70278f28dce24cdfa4328797b2b031f698421a849ee5141
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 4112497c5716f1dd13ae9f45a4806773ae7f521b586415c2b0be4a735357765a45c2f524d33bff509f0dfc103ed47fc3aceee19e7eea98ec8d0c720d88af3153
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data.tar.gz: 1852065b8f05fb474f6f392df45cf08269196f2f481a55d84d1a5d20ad66713a5138eb739e0146ce1761fe3f22eccb01bcea06d19e94a19b3693a01dbba4e165
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data/README.md
CHANGED
@@ -1301,14 +1301,7 @@ __The vector operator__ `[]` is used for building types representing vectors of
|
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1301
1301
|
<type>[<range>]
|
1302
1302
|
```
|
1303
1303
|
|
1304
|
-
The `<range>` of a vector type indicates the position of the starting and ending bits
|
1305
|
-
is on the left side of the range, the vector is big endian, otherwise it is little endian. Negative values in a range are also possible and indicate positions bellow the radix point. For example, the following code describes a big-endian fixed-point type with 8 bits above the radix point and 4 bits
|
1306
|
-
bellow:
|
1307
|
-
|
1308
|
-
```ruby
|
1309
|
-
bit[7..-4]
|
1310
|
-
```
|
1311
|
-
|
1304
|
+
The `<range>` of a vector type indicates the position of the starting and ending bits.
|
1312
1305
|
A `n..0` range can also be abbreviated to `n+1`. For instance, the two following types are identical:
|
1313
1306
|
|
1314
1307
|
```ruby
|
@@ -2801,6 +2794,19 @@ bit[4,4].inner :sig
|
|
2801
2794
|
|
2802
2795
|
When performing computation with fixed point types, HDLRuby ensures that the result's decimal point position is correct.
|
2803
2796
|
|
2797
|
+
In addition to the fixed point data type, a method is added to the literal objects (Numeric) to convert them to fixed point representation:
|
2798
|
+
|
2799
|
+
```ruby
|
2800
|
+
<litteral>.to_fix(<number of bits after the decimal point>)
|
2801
|
+
```
|
2802
|
+
|
2803
|
+
For example the following code converts a floating point value to a fixed point value with 16 bits after the decimal point:
|
2804
|
+
|
2805
|
+
```
|
2806
|
+
3.178.to_fix(16)
|
2807
|
+
```
|
2808
|
+
|
2809
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+
|
2804
2810
|
## Channel
|
2805
2811
|
<a name="channel"></a>
|
2806
2812
|
|
@@ -102,6 +102,22 @@ system :linear_test do
|
|
102
102
|
mac_n1([8],clk.posedge,ack[3],ack[4], mem_macn1_left_inPs,
|
103
103
|
channel_port(5), mem_macn1_outPs)
|
104
104
|
|
105
|
+
# Circuit for testing the linearun with mac.
|
106
|
+
# Input memories
|
107
|
+
mem_dual([8],8,clk,rst, rinc: :rst, winc: :rst).(:mem_macrn_left_in)
|
108
|
+
mem_dual([8],8,clk,rst, rinc: :rst, winc: :rst).(:mem_macrn_right_in)
|
109
|
+
# Access ports.
|
110
|
+
mem_macrn_left_in.branch(:rinc).inner :mem_macrn_left_in_readP
|
111
|
+
mem_macrn_right_in.branch(:rinc).inner :mem_macrn_right_in_readP
|
112
|
+
# Output signal.
|
113
|
+
[8].inner :accr
|
114
|
+
|
115
|
+
# Build the linearun mac.
|
116
|
+
linearun(8,clk.posedge,ack[4],ack[5]) do |ev,req,ack|
|
117
|
+
mac([8],ev,req,ack,mem_macrn_left_in_readP,mem_macrn_right_in_readP,
|
118
|
+
channel_port(accr))
|
119
|
+
end
|
120
|
+
|
105
121
|
|
106
122
|
# The memory initializer.
|
107
123
|
# Writing ports
|
@@ -111,6 +127,8 @@ system :linear_test do
|
|
111
127
|
mem_muln_left_in.branch(:winc).inner :mem_muln_left_in_writeP
|
112
128
|
mem_muln_right_in.branch(:winc).inner :mem_muln_right_in_writeP
|
113
129
|
mem_macn1_left_in.branch(:winc).inner :mem_macn1_left_in_writeP
|
130
|
+
mem_macrn_left_in.branch(:winc).inner :mem_macrn_left_in_writeP
|
131
|
+
mem_macrn_right_in.branch(:winc).inner :mem_macrn_right_in_writeP
|
114
132
|
# Filling index
|
115
133
|
[8].inner :idx
|
116
134
|
# Filling counter
|
@@ -127,7 +145,7 @@ system :linear_test do
|
|
127
145
|
helse do
|
128
146
|
# Step index processing.
|
129
147
|
hif(cnt == 7) do
|
130
|
-
hif(idx <
|
148
|
+
hif(idx < 8) { idx <= idx + 1 }
|
131
149
|
end
|
132
150
|
# Memory filling steps.
|
133
151
|
hcase(idx)
|
@@ -161,6 +179,16 @@ system :linear_test do
|
|
161
179
|
cnt <= cnt + 1; val <= val + 1
|
162
180
|
end
|
163
181
|
end
|
182
|
+
hwhen(6) do
|
183
|
+
mem_macrn_left_in_writeP.write(val-48) do
|
184
|
+
cnt <= cnt + 1; val <= val + 1
|
185
|
+
end
|
186
|
+
end
|
187
|
+
hwhen(7) do
|
188
|
+
mem_macrn_right_in_writeP.write(val-48) do
|
189
|
+
cnt <= cnt + 1; val <= val + 1
|
190
|
+
end
|
191
|
+
end
|
164
192
|
# Computation steps.
|
165
193
|
helse do
|
166
194
|
hif(start) do
|
@@ -197,7 +225,7 @@ system :linear_test do
|
|
197
225
|
start <= 1
|
198
226
|
!10.ns
|
199
227
|
# Run
|
200
|
-
|
228
|
+
128.times do
|
201
229
|
clk <= 1
|
202
230
|
!10.ns
|
203
231
|
clk <= 0
|
@@ -4,8 +4,8 @@ system :rom4_8 do
|
|
4
4
|
[2..0].input :addr
|
5
5
|
[7..0].output :data0,:data1,:data2
|
6
6
|
|
7
|
-
bit[7..0][0..7].constant content0: [1,2,3,4,5,6,7]
|
8
|
-
bit[7..0][-8].constant content1: [1,2,3,4,5,6,7]
|
7
|
+
bit[7..0][0..7].constant content0: [0,1,2,3,4,5,6,7]
|
8
|
+
bit[7..0][-8].constant content1: [0,1,2,3,4,5,6,7]
|
9
9
|
bit[7..0][-8].constant content2: (8).times.to_a
|
10
10
|
|
11
11
|
data0 <= content0[addr]
|
@@ -0,0 +1,96 @@
|
|
1
|
+
require 'std/memory.rb'
|
2
|
+
require 'std/linear.rb'
|
3
|
+
# require 'std/timing.rb'
|
4
|
+
|
5
|
+
include HDLRuby::High::Std
|
6
|
+
|
7
|
+
|
8
|
+
system :fir do |typ,iChannel,oChannel,coefs|
|
9
|
+
input :clk, :rst, :req
|
10
|
+
output :ack
|
11
|
+
# Declare the input port.
|
12
|
+
iChannel.input :iPort
|
13
|
+
# Declare the output port.
|
14
|
+
oChannel.output :oPort
|
15
|
+
|
16
|
+
# Declares the data registers.
|
17
|
+
datas = coefs.map.with_index do |coef,id|
|
18
|
+
coef.type.inner :"data_#{id}"
|
19
|
+
end
|
20
|
+
|
21
|
+
inner :req2
|
22
|
+
|
23
|
+
|
24
|
+
# Generate the mac pipeline.
|
25
|
+
mac_np(typ,clk.posedge,req2,ack,
|
26
|
+
datas.map{|data| channel_port(data) },
|
27
|
+
coefs.map{|coef| channel_port(coef) }, oPort)
|
28
|
+
|
29
|
+
# Generate the data transfer through the pipeline.
|
30
|
+
par(clk.posedge) do
|
31
|
+
req2 <= 0
|
32
|
+
hif(rst) { datas.each { |d| d <= 0 } }
|
33
|
+
hif(req) do
|
34
|
+
iPort.read(datas[0]) do
|
35
|
+
# datas.each_cons(2) { |d0,d1| d1 <= d0 }
|
36
|
+
datas[1..-1] <= datas[0..-2]
|
37
|
+
end
|
38
|
+
req2 <= 1
|
39
|
+
end
|
40
|
+
end
|
41
|
+
end
|
42
|
+
|
43
|
+
|
44
|
+
|
45
|
+
|
46
|
+
|
47
|
+
system :work do
|
48
|
+
|
49
|
+
inner :clk,:rst,:req,:ack
|
50
|
+
|
51
|
+
# The input memory.
|
52
|
+
mem_rom([8],8,clk,rst,
|
53
|
+
[_00000001,_00000010,_00000011,_00000100,
|
54
|
+
_00000101,_00000110,_00000111,_00001000]).(:iMem)
|
55
|
+
# The output memory.
|
56
|
+
mem_dual([8],8,clk,rst).(:oMem)
|
57
|
+
# The coefficients.
|
58
|
+
coefs = [_11001100,_00110011,_10101010,_01010101,
|
59
|
+
_11110000,_00001111,_11100011,_00011100]
|
60
|
+
|
61
|
+
# The filter
|
62
|
+
fir([8],iMem.branch(:rinc),oMem.branch(:winc),coefs).(:my_fir).(clk,rst,req,ack)
|
63
|
+
|
64
|
+
# iMem.branch(:rinc).inner :port
|
65
|
+
# [8].inner :a
|
66
|
+
# par(clk.posedge) do
|
67
|
+
# hif(req) { port.read(a) }
|
68
|
+
# end
|
69
|
+
|
70
|
+
timed do
|
71
|
+
req <= 0
|
72
|
+
clk <= 0
|
73
|
+
rst <= 0
|
74
|
+
!10.ns
|
75
|
+
clk <= 1
|
76
|
+
!10.ns
|
77
|
+
clk <= 0
|
78
|
+
rst <= 1
|
79
|
+
!10.ns
|
80
|
+
clk <= 1
|
81
|
+
!10.ns
|
82
|
+
clk <= 0
|
83
|
+
rst <= 0
|
84
|
+
!10.ns
|
85
|
+
clk <= 1
|
86
|
+
!10.ns
|
87
|
+
req <= 1
|
88
|
+
clk <= 0
|
89
|
+
64.times do
|
90
|
+
!10.ns
|
91
|
+
clk <= 1
|
92
|
+
!10.ns
|
93
|
+
clk <= 0
|
94
|
+
end
|
95
|
+
end
|
96
|
+
end
|
@@ -15,7 +15,10 @@ system :testmat do
|
|
15
15
|
inner :clk,:rst, :req
|
16
16
|
|
17
17
|
# Input memories
|
18
|
-
mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memL0)
|
18
|
+
# mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memL0)
|
19
|
+
# The first memory is 4-bank for testing purpose.
|
20
|
+
mem_bank([8],4,256/4,clk,rst, rinc: :rst,winc: :rst).(:memL0)
|
21
|
+
# The others are standard dual-edge memories.
|
19
22
|
mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memL1)
|
20
23
|
mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memR)
|
21
24
|
# Access ports.
|
@@ -0,0 +1,69 @@
|
|
1
|
+
require 'std/loop.rb'
|
2
|
+
|
3
|
+
include HDLRuby::High::Std
|
4
|
+
|
5
|
+
system :with_loop do
|
6
|
+
|
7
|
+
# The clock and reset
|
8
|
+
inner :clk, :rst
|
9
|
+
# The running signals.
|
10
|
+
inner :doit0, :doit1
|
11
|
+
# The signal to check for finishing.
|
12
|
+
inner :over
|
13
|
+
|
14
|
+
# A counter.
|
15
|
+
[8].inner :count, :count2
|
16
|
+
|
17
|
+
# The first loop: basic while.
|
18
|
+
lp0 = while_loop(clk, proc{count<=0}, count<15) { count <= count + 1 }
|
19
|
+
|
20
|
+
# The second loop: 10 times.
|
21
|
+
lp1 = times_loop(clk,10) { count2 <= count2+2 }
|
22
|
+
# Control it using doit1 as req and over as ack.
|
23
|
+
rst_req_ack(clk.posedge,rst,doit1,over,lp1)
|
24
|
+
|
25
|
+
par(clk.posedge) do
|
26
|
+
doit1 <= 0
|
27
|
+
hif(rst) do
|
28
|
+
lp0.reset()
|
29
|
+
# lp1.reset()
|
30
|
+
# doit1 <= 0
|
31
|
+
count2 <= 0
|
32
|
+
over <= 0
|
33
|
+
end
|
34
|
+
helse do
|
35
|
+
hif(doit0) { lp0.run }
|
36
|
+
lp0.finish { doit0 <= 0; doit1 <= 1 }# ; lp1.run }
|
37
|
+
hif(doit1) { lp1.run; lp0.reset() }
|
38
|
+
# lp1.finish { over <= 1; doit1 <= 0 }
|
39
|
+
# Second pass for first loop.
|
40
|
+
hif(over) { lp0.run }
|
41
|
+
end
|
42
|
+
end
|
43
|
+
|
44
|
+
timed do
|
45
|
+
clk <= 0
|
46
|
+
rst <= 0
|
47
|
+
doit0 <= 0
|
48
|
+
!10.ns
|
49
|
+
clk <= 1
|
50
|
+
!10.ns
|
51
|
+
clk <= 0
|
52
|
+
rst <= 1
|
53
|
+
!10.ns
|
54
|
+
clk <= 1
|
55
|
+
!10.ns
|
56
|
+
clk <= 0
|
57
|
+
rst <= 0
|
58
|
+
doit0 <= 1
|
59
|
+
!10.ns
|
60
|
+
clk <= 1
|
61
|
+
!10.ns
|
62
|
+
64.times do
|
63
|
+
clk <= 0
|
64
|
+
!10.ns
|
65
|
+
clk <= 1
|
66
|
+
!10.ns
|
67
|
+
end
|
68
|
+
end
|
69
|
+
end
|
@@ -108,16 +108,26 @@ system :mem_test do
|
|
108
108
|
end
|
109
109
|
|
110
110
|
|
111
|
-
[8].inner :
|
111
|
+
[8].inner :sum0, :sum1
|
112
112
|
|
113
113
|
# Declares a dual edge 8-bit data and address memory.
|
114
114
|
mem_dual([8],256,clk,rst, raddr: :rst,waddr: :rst).(:memDI)
|
115
115
|
|
116
116
|
# Instantiate the producer to access port waddr of the memory.
|
117
|
-
producer(memDI.branch(:waddr)).(:
|
117
|
+
producer(memDI.branch(:waddr)).(:producerI0).(clk,rst)
|
118
118
|
|
119
119
|
# Instantiate the producer to access port raddr of the memory.
|
120
|
-
consumer(memDI.branch(:raddr)).(:
|
120
|
+
consumer(memDI.branch(:raddr)).(:consumerI0).(clk,rst,sum0)
|
121
|
+
|
122
|
+
|
123
|
+
# Declares a 4-bank 8-bit data and address memory.
|
124
|
+
mem_bank([8],4,256/4,clk,rst, raddr: :rst, waddr: :rst).(:memBI)
|
125
|
+
|
126
|
+
# Instantiate the producer to access port waddr of the memory.
|
127
|
+
producer(memBI.branch(:waddr)).(:producerI1).(clk,rst)
|
128
|
+
|
129
|
+
# Instantiate the producer to access port raddr of the memory.
|
130
|
+
consumer(memBI.branch(:raddr)).(:consumerI1).(clk,rst,sum1)
|
121
131
|
|
122
132
|
|
123
133
|
end
|
data/lib/HDLRuby/hdrcc.rb
CHANGED
@@ -113,12 +113,9 @@ module HDLRuby
|
|
113
113
|
return
|
114
114
|
end
|
115
115
|
# Get its required files.
|
116
|
-
requires = @checks[-1].get_all_requires
|
116
|
+
requires = @checks[-1].get_all_requires +
|
117
|
+
@checks[-1].get_all_require_relatives
|
117
118
|
requires.each do |file|
|
118
|
-
# if file != "HDLRuby" &&
|
119
|
-
# !@std_files.find { |std| std.include?(file) } then
|
120
|
-
# read_all(file)
|
121
|
-
# end
|
122
119
|
read_all(file)
|
123
120
|
end
|
124
121
|
@requires += requires
|
@@ -563,7 +560,7 @@ elsif $options[:clang] then
|
|
563
560
|
end
|
564
561
|
Dir.chdir($output)
|
565
562
|
# Kernel.system("make -s")
|
566
|
-
Kernel.system("cc -o3 -o hruby_simulator *.c")
|
563
|
+
Kernel.system("cc -o3 -o hruby_simulator *.c -lpthread")
|
567
564
|
Kernel.system("./hruby_simulator")
|
568
565
|
end
|
569
566
|
elsif $options[:verilog] then
|
data/lib/HDLRuby/hruby_check.rb
CHANGED
@@ -45,11 +45,20 @@ module HDLRuby
|
|
45
45
|
(code[1][1] == "require")
|
46
46
|
end
|
47
47
|
|
48
|
+
# Tells if +code+ is require_relative description.
|
49
|
+
def is_require_relative?(code)
|
50
|
+
# return code[0] && (code[0][0] == :command) &&
|
51
|
+
# (code[0][1][1] == "require_relative")
|
52
|
+
return code && (code[0] == :command) &&
|
53
|
+
(code[1][1] == "require_relative")
|
54
|
+
end
|
55
|
+
|
48
56
|
# Gets the required file from +code+.
|
49
57
|
def get_require(code)
|
50
58
|
# return (code[0][2][1][0][1][1][1])
|
51
59
|
return (code[2][1][0][1][1][1])
|
52
60
|
end
|
61
|
+
alias_method :get_require_relative, :get_require
|
53
62
|
|
54
63
|
# Gets all the required files of +code+.
|
55
64
|
def get_all_requires(code = @code)
|
@@ -66,6 +75,21 @@ module HDLRuby
|
|
66
75
|
end
|
67
76
|
end
|
68
77
|
|
78
|
+
# Gets all the require_relative files of +code+.
|
79
|
+
def get_all_require_relatives(code = @code)
|
80
|
+
if code.is_a?(Array) then
|
81
|
+
require_relatives = (code.select { |sub| is_require_relative?(sub) }).map! do |sub|
|
82
|
+
get_require_relative(sub)
|
83
|
+
end
|
84
|
+
code.each do |sub|
|
85
|
+
require_relatives += get_all_require_relatives(sub)
|
86
|
+
end
|
87
|
+
return require_relatives
|
88
|
+
else
|
89
|
+
return []
|
90
|
+
end
|
91
|
+
end
|
92
|
+
|
69
93
|
# Tells if +code+ is a system description.
|
70
94
|
def is_system?(code)
|
71
95
|
return code.is_a?(Array) && (code[0] == :command) &&
|
@@ -77,7 +101,7 @@ module HDLRuby
|
|
77
101
|
return code[2][1][0][1][1][1]
|
78
102
|
end
|
79
103
|
|
80
|
-
# Gets all the
|
104
|
+
# Gets all the systems of +code+.
|
81
105
|
def get_all_systems(code = @code)
|
82
106
|
return [] unless code.is_a?(Array)
|
83
107
|
return code.reduce([]) {|ar,sub| ar + get_all_systems(sub) } +
|
data/lib/HDLRuby/hruby_high.rb
CHANGED
@@ -1308,6 +1308,12 @@ module HDLRuby::High
|
|
1308
1308
|
return true
|
1309
1309
|
end
|
1310
1310
|
|
1311
|
+
# Converts to a type.
|
1312
|
+
# Returns self since it is already a type.
|
1313
|
+
def to_type
|
1314
|
+
return self
|
1315
|
+
end
|
1316
|
+
|
1311
1317
|
# Sets the +name+.
|
1312
1318
|
#
|
1313
1319
|
# NOTE: can only be done if the name is not already set.
|
@@ -1851,16 +1857,18 @@ module HDLRuby::High
|
|
1851
1857
|
# NOTE: a function is a short-cut for a method that creates a scope.
|
1852
1858
|
def function(name, &ruby_block)
|
1853
1859
|
if HDLRuby::High.in_system? then
|
1854
|
-
define_singleton_method(name.to_sym) do |*args|
|
1860
|
+
define_singleton_method(name.to_sym) do |*args,&other_block|
|
1855
1861
|
sub do
|
1856
|
-
HDLRuby::High.top_user.instance_exec(*args
|
1862
|
+
HDLRuby::High.top_user.instance_exec(*args,*other_block,
|
1863
|
+
&ruby_block)
|
1857
1864
|
# ruby_block.call(*args)
|
1858
1865
|
end
|
1859
1866
|
end
|
1860
1867
|
else
|
1861
|
-
define_method(name.to_sym) do |*args|
|
1868
|
+
define_method(name.to_sym) do |*args,&other_block|
|
1862
1869
|
sub do
|
1863
|
-
HDLRuby::High.top_user.instance_exec(*args
|
1870
|
+
HDLRuby::High.top_user.instance_exec(*args,*other_block,
|
1871
|
+
&ruby_block)
|
1864
1872
|
end
|
1865
1873
|
end
|
1866
1874
|
end
|