HDLRuby 2.2.15 → 2.3.2

checksums.yaml

@@ -1,7 +1,7 @@
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data/README.md

@@ -1301,14 +1301,7 @@ __The vector operator__ `[]` is used for building types representing vectors of
 <type>[<range>]
 ```
 
-The `<range>` of a vector type indicates the position of the starting and ending bits relatively to the radix point. If the position of the starting bit
-is on the left side of the range, the vector is big endian, otherwise it is little endian.  Negative values in a range are also possible and indicate positions bellow the radix point.  For example, the following code describes a big-endian fixed-point type with 8 bits above the radix point and 4 bits
-bellow:
-
-```ruby
-bit[7..-4]
-```
-
+The `<range>` of a vector type indicates the position of the starting and ending bits.
 A `n..0` range can also be abbreviated to `n+1`. For instance, the two following types are identical:
 
 ```ruby
@@ -2801,6 +2794,19 @@ bit[4,4].inner :sig
 
 When performing computation with fixed point types, HDLRuby ensures that the result's decimal point position is correct.
 
+In addition to the fixed point data type, a method is added to the literal objects (Numeric) to convert them to fixed point representation:
+
+```ruby
+<litteral>.to_fix(<number of bits after the decimal point>)
+```
+
+For example the following code converts a floating point value to a fixed point value with 16 bits after the decimal point:
+
+```
+3.178.to_fix(16)
+```
+
+
 ## Channel
 <a name="channel"></a>
 

data/lib/HDLRuby/hdr_samples/linear_test.rb

@@ -102,6 +102,22 @@ system :linear_test do
     mac_n1([8],clk.posedge,ack[3],ack[4], mem_macn1_left_inPs,
           channel_port(5), mem_macn1_outPs)
 
+    # Circuit for testing the linearun with mac.
+    # Input memories
+    mem_dual([8],8,clk,rst, rinc: :rst, winc: :rst).(:mem_macrn_left_in)
+    mem_dual([8],8,clk,rst, rinc: :rst, winc: :rst).(:mem_macrn_right_in)
+    # Access ports.
+    mem_macrn_left_in.branch(:rinc).inner :mem_macrn_left_in_readP
+    mem_macrn_right_in.branch(:rinc).inner :mem_macrn_right_in_readP
+    # Output signal.
+    [8].inner :accr
+
+    # Build the linearun mac.
+    linearun(8,clk.posedge,ack[4],ack[5]) do |ev,req,ack|
+        mac([8],ev,req,ack,mem_macrn_left_in_readP,mem_macrn_right_in_readP, 
+            channel_port(accr))
+    end
+
 
     # The memory initializer.
     # Writing ports
@@ -111,6 +127,8 @@ system :linear_test do
     mem_muln_left_in.branch(:winc).inner :mem_muln_left_in_writeP
     mem_muln_right_in.branch(:winc).inner :mem_muln_right_in_writeP
     mem_macn1_left_in.branch(:winc).inner :mem_macn1_left_in_writeP
+    mem_macrn_left_in.branch(:winc).inner :mem_macrn_left_in_writeP
+    mem_macrn_right_in.branch(:winc).inner :mem_macrn_right_in_writeP
     # Filling index
     [8].inner :idx
     # Filling counter
@@ -127,7 +145,7 @@ system :linear_test do
         helse do
             # Step index processing.
             hif(cnt == 7) do
-                hif(idx < 6) { idx <= idx + 1 }
+                hif(idx < 8) { idx <= idx + 1 }
             end
             # Memory filling steps.
             hcase(idx)
@@ -161,6 +179,16 @@ system :linear_test do
                     cnt <= cnt + 1; val <= val + 1
                 end
             end
+            hwhen(6) do
+                mem_macrn_left_in_writeP.write(val-48) do
+                    cnt <= cnt + 1; val <= val + 1
+                end
+            end
+            hwhen(7) do
+                mem_macrn_right_in_writeP.write(val-48) do
+                    cnt <= cnt + 1; val <= val + 1
+                end
+            end
             # Computation steps.
             helse do
                 hif(start) do
@@ -197,7 +225,7 @@ system :linear_test do
         start <= 1
         !10.ns
         # Run
-        64.times do
+        128.times do
             clk <= 1
             !10.ns
             clk <= 0

data/lib/HDLRuby/hdr_samples/rom.rb

@@ -4,8 +4,8 @@ system :rom4_8 do
     [2..0].input :addr
     [7..0].output :data0,:data1,:data2
 
-    bit[7..0][0..7].constant content0: [1,2,3,4,5,6,7]
-    bit[7..0][-8].constant content1: [1,2,3,4,5,6,7]
+    bit[7..0][0..7].constant content0: [0,1,2,3,4,5,6,7]
+    bit[7..0][-8].constant content1: [0,1,2,3,4,5,6,7]
     bit[7..0][-8].constant content2: (8).times.to_a
 
     data0 <= content0[addr]

data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb

@@ -0,0 +1,96 @@
+require 'std/memory.rb'
+require 'std/linear.rb'
+# require 'std/timing.rb'
+
+include HDLRuby::High::Std
+
+
+system :fir do |typ,iChannel,oChannel,coefs|
+    input :clk, :rst, :req
+    output :ack
+    # Declare the input port.
+    iChannel.input :iPort
+    # Declare the output port.
+    oChannel.output :oPort
+
+    # Declares the data registers.
+    datas = coefs.map.with_index do |coef,id|
+        coef.type.inner :"data_#{id}"
+    end
+
+    inner :req2
+    
+
+    # Generate the mac pipeline.
+    mac_np(typ,clk.posedge,req2,ack, 
+          datas.map{|data| channel_port(data) },
+          coefs.map{|coef| channel_port(coef) }, oPort)
+
+    # Generate the data transfer through the pipeline.
+    par(clk.posedge) do
+        req2 <= 0
+        hif(rst) { datas.each { |d| d <= 0 } }
+        hif(req) do
+            iPort.read(datas[0]) do
+                # datas.each_cons(2) { |d0,d1| d1 <= d0 }
+                datas[1..-1] <= datas[0..-2]
+            end
+            req2 <= 1
+        end
+    end
+end
+
+
+
+
+
+system :work do
+
+    inner :clk,:rst,:req,:ack
+
+    # The input memory.
+    mem_rom([8],8,clk,rst,
+            [_00000001,_00000010,_00000011,_00000100,
+             _00000101,_00000110,_00000111,_00001000]).(:iMem)
+    # The output memory.
+    mem_dual([8],8,clk,rst).(:oMem)
+    # The coefficients.
+    coefs = [_11001100,_00110011,_10101010,_01010101,
+             _11110000,_00001111,_11100011,_00011100]
+
+    # The filter
+    fir([8],iMem.branch(:rinc),oMem.branch(:winc),coefs).(:my_fir).(clk,rst,req,ack)
+
+    # iMem.branch(:rinc).inner :port
+    # [8].inner :a
+    # par(clk.posedge) do
+    #     hif(req) { port.read(a) }
+    # end
+
+    timed do
+        req <= 0
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        req <= 1
+        clk <= 0
+        64.times do
+            !10.ns
+            clk <= 1
+            !10.ns
+            clk <= 0
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_fixpoint.rb

@@ -12,8 +12,9 @@ system :fix_test do
 
     # Performs calculation between then
     timed do
-        x <= _00110011
-        y <= _01000000
+        # x <= _00110011 # 3.1875
+        x <= 3.1875.to_fix(4)
+        y <= _01000000 # 4
         !10.ns
         z <= x + y
         !10.ns

data/lib/HDLRuby/hdr_samples/with_linear.rb

@@ -15,7 +15,10 @@ system :testmat do
     inner :clk,:rst, :req
 
     # Input memories
-    mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memL0)
+    # mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memL0)
+    # The first memory is 4-bank for testing purpose.
+    mem_bank([8],4,256/4,clk,rst, rinc: :rst,winc: :rst).(:memL0)
+    # The others are standard dual-edge memories.
     mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memL1)
     mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memR)
     # Access ports.

data/lib/HDLRuby/hdr_samples/with_loop.rb

@@ -0,0 +1,69 @@
+require 'std/loop.rb'
+
+include HDLRuby::High::Std
+
+system :with_loop do
+
+    # The clock and reset
+    inner :clk, :rst
+    # The running signals.
+    inner :doit0, :doit1
+    # The signal to check for finishing.
+    inner :over
+
+    # A counter.
+    [8].inner :count, :count2
+
+    # The first loop: basic while.
+    lp0 = while_loop(clk, proc{count<=0}, count<15) { count <= count + 1 }
+
+    # The second loop: 10 times.
+    lp1 = times_loop(clk,10) { count2 <= count2+2 }
+    # Control it using doit1 as req and over as ack.
+    rst_req_ack(clk.posedge,rst,doit1,over,lp1)
+
+    par(clk.posedge) do
+        doit1 <= 0
+        hif(rst) do
+            lp0.reset()
+            # lp1.reset()
+            # doit1 <= 0
+            count2 <= 0
+            over <= 0
+        end
+        helse do
+            hif(doit0) { lp0.run }
+            lp0.finish { doit0 <= 0; doit1 <= 1 }# ; lp1.run }
+            hif(doit1) { lp1.run; lp0.reset() }
+            # lp1.finish { over <= 1; doit1 <= 0 }
+            # Second pass for first loop.
+            hif(over)  { lp0.run }
+        end
+    end
+
+    timed do
+        clk <= 0
+        rst <= 0
+        doit0 <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        doit0 <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        64.times do
+            clk <= 0
+            !10.ns
+            clk <= 1
+            !10.ns
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_memory.rb

@@ -108,16 +108,26 @@ system :mem_test do
     end
 
 
-    [8].inner :sum
+    [8].inner :sum0, :sum1
 
     # Declares a dual edge 8-bit data and address memory.
     mem_dual([8],256,clk,rst, raddr: :rst,waddr: :rst).(:memDI)
 
     # Instantiate the producer to access port waddr of the memory.
-    producer(memDI.branch(:waddr)).(:producerI).(clk,rst)
+    producer(memDI.branch(:waddr)).(:producerI0).(clk,rst)
 
     # Instantiate the producer to access port raddr of the memory.
-    consumer(memDI.branch(:raddr)).(:consumerI).(clk,rst,sum)
+    consumer(memDI.branch(:raddr)).(:consumerI0).(clk,rst,sum0)
+
+
+    # Declares a 4-bank 8-bit data and address memory.
+    mem_bank([8],4,256/4,clk,rst, raddr: :rst, waddr: :rst).(:memBI)
+
+    # Instantiate the producer to access port waddr of the memory.
+    producer(memBI.branch(:waddr)).(:producerI1).(clk,rst)
+
+    # Instantiate the producer to access port raddr of the memory.
+    consumer(memBI.branch(:raddr)).(:consumerI1).(clk,rst,sum1)
 
 
 end

data/lib/HDLRuby/hdrcc.rb

@@ -113,12 +113,9 @@ module HDLRuby
                 return
             end
             # Get its required files.
-            requires = @checks[-1].get_all_requires
+            requires = @checks[-1].get_all_requires +
+                       @checks[-1].get_all_require_relatives
             requires.each do |file|
-                # if file != "HDLRuby" &&
-                #         !@std_files.find { |std| std.include?(file) } then
-                #     read_all(file)
-                # end
                 read_all(file)
             end
             @requires += requires
@@ -563,7 +560,7 @@ elsif $options[:clang] then
         end
         Dir.chdir($output)
         # Kernel.system("make -s")
-        Kernel.system("cc -o3 -o hruby_simulator *.c")
+        Kernel.system("cc -o3 -o hruby_simulator *.c -lpthread")
         Kernel.system("./hruby_simulator")
     end
 elsif $options[:verilog] then

data/lib/HDLRuby/hruby_check.rb

@@ -45,11 +45,20 @@ module HDLRuby
                    (code[1][1] == "require")
         end
 
+        # Tells if +code+ is require_relative description.
+        def is_require_relative?(code)
+            # return code[0] && (code[0][0] == :command) &&
+            #        (code[0][1][1] == "require_relative")
+            return code && (code[0] == :command) &&
+                   (code[1][1] == "require_relative")
+        end
+
         # Gets the required file from +code+.
         def get_require(code)
             # return (code[0][2][1][0][1][1][1])
             return (code[2][1][0][1][1][1])
         end
+        alias_method :get_require_relative, :get_require
 
         # Gets all the required files of  +code+.
         def get_all_requires(code = @code)
@@ -66,6 +75,21 @@ module HDLRuby
             end
         end
 
+        # Gets all the require_relative files of  +code+.
+        def get_all_require_relatives(code = @code)
+            if code.is_a?(Array) then
+                require_relatives = (code.select { |sub| is_require_relative?(sub) }).map! do |sub|
+                    get_require_relative(sub)
+                end
+                code.each do |sub|
+                    require_relatives += get_all_require_relatives(sub)
+                end
+                return require_relatives
+            else
+                return []
+            end
+        end
+
         # Tells if +code+ is a system description.
         def is_system?(code)
             return code.is_a?(Array) && (code[0] == :command) &&
@@ -77,7 +101,7 @@ module HDLRuby
             return code[2][1][0][1][1][1]
         end
 
-        # Gets all the required files of  +code+.
+        # Gets all the systems of  +code+.
         def get_all_systems(code = @code)
             return [] unless code.is_a?(Array)
             return code.reduce([]) {|ar,sub| ar + get_all_systems(sub) } +

data/lib/HDLRuby/hruby_high.rb

@@ -1308,6 +1308,12 @@ module HDLRuby::High
             return true
         end
 
+        # Converts to a type.
+        # Returns self since it is already a type.
+        def to_type
+            return self
+        end
+
         # Sets the +name+.
         #
         # NOTE: can only be done if the name is not already set.
@@ -1851,16 +1857,18 @@ module HDLRuby::High
     # NOTE: a function is a short-cut for a method that creates a scope.
     def function(name, &ruby_block)
         if HDLRuby::High.in_system? then
-            define_singleton_method(name.to_sym) do |*args|
+            define_singleton_method(name.to_sym) do |*args,&other_block|
                 sub do
-                    HDLRuby::High.top_user.instance_exec(*args,&ruby_block)
+                    HDLRuby::High.top_user.instance_exec(*args,*other_block,
+                                                         &ruby_block)
                     # ruby_block.call(*args)
                 end
             end
         else
-            define_method(name.to_sym) do |*args|
+            define_method(name.to_sym) do |*args,&other_block|
                 sub do
-                    HDLRuby::High.top_user.instance_exec(*args,&ruby_block)
+                    HDLRuby::High.top_user.instance_exec(*args,*other_block,
+                                                         &ruby_block)
                 end
             end
         end