HDLRuby 2.2.13 → 2.3.0

data/lib/HDLRuby/hdr_samples/rom.rb

@@ -4,8 +4,8 @@ system :rom4_8 do
     [2..0].input :addr
     [7..0].output :data0,:data1,:data2
 
-    bit[7..0][0..7].constant content0: [1,2,3,4,5,6,7]
-    bit[7..0][-8].constant content1: [1,2,3,4,5,6,7]
+    bit[7..0][0..7].constant content0: [0,1,2,3,4,5,6,7]
+    bit[7..0][-8].constant content1: [0,1,2,3,4,5,6,7]
     bit[7..0][-8].constant content2: (8).times.to_a
 
     data0 <= content0[addr]

data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb

@@ -0,0 +1,96 @@
+require 'std/memory.rb'
+require 'std/linear.rb'
+# require 'std/timing.rb'
+
+include HDLRuby::High::Std
+
+
+system :fir do |typ,iChannel,oChannel,coefs|
+    input :clk, :rst, :req
+    output :ack
+    # Declare the input port.
+    iChannel.input :iPort
+    # Declare the output port.
+    oChannel.output :oPort
+
+    # Declares the data registers.
+    datas = coefs.map.with_index do |coef,id|
+        coef.type.inner :"data_#{id}"
+    end
+
+    inner :req2
+    
+
+    # Generate the mac pipeline.
+    mac_np(typ,clk.posedge,req2,ack, 
+          datas.map{|data| channel_port(data) },
+          coefs.map{|coef| channel_port(coef) }, oPort)
+
+    # Generate the data transfer through the pipeline.
+    par(clk.posedge) do
+        req2 <= 0
+        hif(rst) { datas.each { |d| d <= 0 } }
+        hif(req) do
+            iPort.read(datas[0]) do
+                # datas.each_cons(2) { |d0,d1| d1 <= d0 }
+                datas[1..-1] <= datas[0..-2]
+            end
+            req2 <= 1
+        end
+    end
+end
+
+
+
+
+
+system :work do
+
+    inner :clk,:rst,:req,:ack
+
+    # The input memory.
+    mem_rom([8],8,clk,rst,
+            [_00000001,_00000010,_00000011,_00000100,
+             _00000101,_00000110,_00000111,_00001000]).(:iMem)
+    # The output memory.
+    mem_dual([8],8,clk,rst).(:oMem)
+    # The coefficients.
+    coefs = [_11001100,_00110011,_10101010,_01010101,
+             _11110000,_00001111,_11100011,_00011100]
+
+    # The filter
+    fir([8],iMem.branch(:rinc),oMem.branch(:winc),coefs).(:my_fir).(clk,rst,req,ack)
+
+    # iMem.branch(:rinc).inner :port
+    # [8].inner :a
+    # par(clk.posedge) do
+    #     hif(req) { port.read(a) }
+    # end
+
+    timed do
+        req <= 0
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        req <= 1
+        clk <= 0
+        64.times do
+            !10.ns
+            clk <= 1
+            !10.ns
+            clk <= 0
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_fixpoint.rb

@@ -12,8 +12,9 @@ system :fix_test do
 
     # Performs calculation between then
     timed do
-        x <= _00110011
-        y <= _01000000
+        # x <= _00110011 # 3.1875
+        x <= 3.1875.to_fix(4)
+        y <= _01000000 # 4
         !10.ns
         z <= x + y
         !10.ns

data/lib/HDLRuby/hdr_samples/with_linear.rb

@@ -0,0 +1,166 @@
+require 'std/memory.rb'
+require 'std/linear.rb'
+
+include HDLRuby::High::Std
+
+# Tries for matrix-vector product.
+
+
+
+
+
+# Testing.
+system :testmat do
+
+    inner :clk,:rst, :req
+
+    # Input memories
+    # mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memL0)
+    # The first memory is 4-bank for testing purpose.
+    mem_bank([8],4,256/4,clk,rst, rinc: :rst,winc: :rst).(:memL0)
+    # The others are standard dual-edge memories.
+    mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memL1)
+    mem_dual([8],256,clk,rst, rinc: :rst,winc: :rst).(:memR)
+    # Access ports.
+    memL0.branch(:rinc).inner :readL0
+    memL1.branch(:rinc).inner :readL1
+    memR.branch(:rinc).inner :readR
+
+    # Prepares the left and acc arrays.
+    lefts = [readL0, readL1]
+
+    # Accumulators memory.
+    mem_file([8],2,clk,rst,rinc: :rst).(:memAcc)
+    memAcc.branch(:anum).inner :accs
+    accs_out = [accs.wrap(0), accs.wrap(1)]
+
+    # Layer 0 ack.
+    inner :ack0
+    
+    # Instantiate the matrix product.
+    mac_n1([8],clk,req,ack0,lefts,readR,accs_out)
+
+    # Translation.
+    # Translation memory.
+    mem_file([8],2,clk,rst,winc: :rst).(:memT)
+    # Tarnslation result
+    mem_file([8],2,clk,rst,rinc: :rst).(:memF)
+    # Access ports.
+    memT.branch(:anum).inner :readT
+    memF.branch(:anum).inner :writeF
+    regRs = [ readT.wrap(0), readT.wrap(1) ]
+    regLs = [ accs.wrap(0), accs.wrap(1) ]
+    regs =  [ writeF.wrap(0), writeF.wrap(1) ]
+
+    # Translater ack.
+    inner :ackT
+
+    # Instantiate the translater.
+    add_n([8],clk,ack0,ackT,regLs,regRs,regs)
+
+
+
+    # Second layer.
+    # Input memories.
+    mem_dual([8],2,clk,rst, rinc: :rst,winc: :rst).(:mem2L0)
+    # Access ports.
+    mem2L0.branch(:rinc).inner :read2L0
+    # memAcc.branch(:rinc).inner :accsR
+    memF.branch(:rinc).inner :readF
+
+    # Second layer ack.
+    inner :ack1
+
+    # Result.
+    [8].inner :res
+
+    sub do
+        # Instantiate the second matrix product.
+        # mac([8],clk,req,read2L0,accsR,res)
+        mac([8],clk,ackT,ack1,read2L0,readF,channel_port(res))
+    end
+
+
+
+    # The memory initializer.
+    memL0.branch(:winc).inner :writeL0
+    memL1.branch(:winc).inner :writeL1
+    memR.branch(:winc).inner :writeR
+    memT.branch(:winc).inner :writeT
+    mem2L0.branch(:winc).inner :write2L0
+    inner :fill, :fill2
+    [8].inner :val
+    par(clk.posedge) do
+        hif(fill) do
+            writeL0.write(val)
+            writeL1.write(val+1)
+            writeR.write(val+1)
+        end
+        hif(fill2) do
+            write2L0.write(val+2)
+            writeT.write(val+2)
+        end
+    end
+
+    timed do
+        req <= 0
+        clk <= 0
+        rst <= 0
+        fill <= 0
+        fill2 <= 0
+        val  <= 0
+        !10.ns
+        # Reset the memories.
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        # Fill the memories.
+        # First layer
+        clk <= 0
+        rst <= 0
+        fill <= 1
+        !10.ns
+        256.times do |i|
+            clk <= 1
+            !10.ns
+            clk <= 0
+            val <= val + 1
+            !10.ns
+        end
+        fill <= 0
+        clk <= 1
+        !10.ns
+        # Second layer
+        clk <= 0
+        rst <= 0
+        fill2 <= 1
+        !10.ns
+        2.times do |i|
+            clk <= 1
+            !10.ns
+            clk <= 0
+            val <= val + 1
+            !10.ns
+        end
+        fill2 <= 0
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        !10.ns
+        # Launch the computation
+        clk <= 0
+        req <= 1
+        !10.ns
+        300.times do
+            clk <= 1
+            !10.ns
+            clk <= 0
+            !10.ns
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_loop.rb

@@ -0,0 +1,69 @@
+require 'std/loop.rb'
+
+include HDLRuby::High::Std
+
+system :with_loop do
+
+    # The clock and reset
+    inner :clk, :rst
+    # The running signals.
+    inner :doit0, :doit1
+    # The signal to check for finishing.
+    inner :over
+
+    # A counter.
+    [8].inner :count, :count2
+
+    # The first loop: basic while.
+    lp0 = while_loop(clk, proc{count<=0}, count<15) { count <= count + 1 }
+
+    # The second loop: 10 times.
+    lp1 = times_loop(clk,10) { count2 <= count2+2 }
+    # Control it using doit1 as req and over as ack.
+    rst_req_ack(clk.posedge,rst,doit1,over,lp1)
+
+    par(clk.posedge) do
+        doit1 <= 0
+        hif(rst) do
+            lp0.reset()
+            # lp1.reset()
+            # doit1 <= 0
+            count2 <= 0
+            over <= 0
+        end
+        helse do
+            hif(doit0) { lp0.run }
+            lp0.finish { doit0 <= 0; doit1 <= 1 }# ; lp1.run }
+            hif(doit1) { lp1.run; lp0.reset() }
+            # lp1.finish { over <= 1; doit1 <= 0 }
+            # Second pass for first loop.
+            hif(over)  { lp0.run }
+        end
+    end
+
+    timed do
+        clk <= 0
+        rst <= 0
+        doit0 <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        doit0 <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        64.times do
+            clk <= 0
+            !10.ns
+            clk <= 1
+            !10.ns
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_memory.rb

@@ -108,16 +108,26 @@ system :mem_test do
     end
 
 
-    [8].inner :sum
+    [8].inner :sum0, :sum1
 
     # Declares a dual edge 8-bit data and address memory.
     mem_dual([8],256,clk,rst, raddr: :rst,waddr: :rst).(:memDI)
 
     # Instantiate the producer to access port waddr of the memory.
-    producer(memDI.branch(:waddr)).(:producerI).(clk,rst)
+    producer(memDI.branch(:waddr)).(:producerI0).(clk,rst)
 
     # Instantiate the producer to access port raddr of the memory.
-    consumer(memDI.branch(:raddr)).(:consumerI).(clk,rst,sum)
+    consumer(memDI.branch(:raddr)).(:consumerI0).(clk,rst,sum0)
+
+
+    # Declares a 4-bank 8-bit data and address memory.
+    mem_bank([8],4,256/4,clk,rst, raddr: :rst, waddr: :rst).(:memBI)
+
+    # Instantiate the producer to access port waddr of the memory.
+    producer(memBI.branch(:waddr)).(:producerI1).(clk,rst)
+
+    # Instantiate the producer to access port raddr of the memory.
+    consumer(memBI.branch(:raddr)).(:consumerI1).(clk,rst,sum1)
 
 
 end

data/lib/HDLRuby/hdrcc.rb

@@ -563,7 +563,7 @@ elsif $options[:clang] then
         end
         Dir.chdir($output)
         # Kernel.system("make -s")
-        Kernel.system("cc -o3 -o hruby_simulator *.c")
+        Kernel.system("cc -o3 -o hruby_simulator *.c -lpthread")
         Kernel.system("./hruby_simulator")
     end
 elsif $options[:verilog] then

data/lib/HDLRuby/hruby_high.rb

@@ -1308,6 +1308,12 @@ module HDLRuby::High
             return true
         end
 
+        # Converts to a type.
+        # Returns self since it is already a type.
+        def to_type
+            return self
+        end
+
         # Sets the +name+.
         #
         # NOTE: can only be done if the name is not already set.
@@ -1851,16 +1857,18 @@ module HDLRuby::High
     # NOTE: a function is a short-cut for a method that creates a scope.
     def function(name, &ruby_block)
         if HDLRuby::High.in_system? then
-            define_singleton_method(name.to_sym) do |*args|
+            define_singleton_method(name.to_sym) do |*args,&other_block|
                 sub do
-                    HDLRuby::High.top_user.instance_exec(*args,&ruby_block)
+                    HDLRuby::High.top_user.instance_exec(*args,*other_block,
+                                                         &ruby_block)
                     # ruby_block.call(*args)
                 end
             end
         else
-            define_method(name.to_sym) do |*args|
+            define_method(name.to_sym) do |*args,&other_block|
                 sub do
-                    HDLRuby::High.top_user.instance_exec(*args,&ruby_block)
+                    HDLRuby::High.top_user.instance_exec(*args,*other_block,
+                                                         &ruby_block)
                 end
             end
         end

data/lib/HDLRuby/hruby_low.rb

@@ -1385,7 +1385,8 @@ module HDLRuby::Low
     # NOTE: type definition are actually type with a name refering to another
     #       type (and equivalent to it).
     class TypeDef < Type
-        extend Forwardable
+        # Moved to constructor
+        # extend Forwardable
 
         # The definition of the type.
         attr_reader :def
@@ -1402,6 +1403,19 @@ module HDLRuby::Low
             end
             # Set the referened type.
             @def = type
+
+            # Sets the delegations
+            self.extend Forwardable
+            [ :signed?, :unsigned?, :fixed?, :float?, :leaf?,
+              :width, :range?, :range, :base?, :base, :types?,
+              :get_all_types, :get_type, :each, :each_type, 
+              :regular?,
+              :each_name,
+              :equivalent? ].each do |meth|
+                  if @def.respond_to?(meth)
+                      self.def_delegator :@def, meth
+                  end
+              end
         end
 
         # Comparison for hash: structural comparison.
@@ -1429,14 +1443,15 @@ module HDLRuby::Low
             @def.each_type_deep(&ruby_block)
         end
 
-        # Delegate the type methods to the ref.
-        def_delegators :@def,
-                       :signed?, :unsigned?, :fixed?, :float?, :leaf?,
-                       :width, :range?, :range, :base?, :base, :types?,
-                       :get_all_types, :get_type, :each, :each_type, 
-                       :regular?,
-                       :each_name,
-                       :equivalent?
+        # Moved to constructor
+        # # Delegate the type methods to the ref.
+        # def_delegators :@def,
+        #                :signed?, :unsigned?, :fixed?, :float?, :leaf?,
+        #                :width, :range?, :range, :base?, :base, :types?,
+        #                :get_all_types, :get_type, :each, :each_type, 
+        #                :regular?,
+        #                :each_name,
+        #                :equivalent?
     end
 
 
@@ -3059,24 +3074,6 @@ module HDLRuby::Low
             return [@value,@whens,@default].hash
         end
 
-        # # Adds a possible +match+ for the case's value that lead to the 
-        # # execution of +statement+.
-        # def add_when(match,statement)
-        #     # Checks the match.
-        #     unless match.is_a?(Expression)
-        #         raise AnyError, "Invalid class for a case match: #{match.class}"
-        #     end
-        #     # Checks statement.
-        #     unless statement.is_a?(Statement)
-        #         raise AnyError, "Invalid class for a statement: #{statement.class}"
-        #     end
-        #     # Add the case.
-        #     @whens << [match,statement]
-        #     # And set their parents.
-        #     match.parent = statement.parent = self
-        #     [match,statement]
-        # end
-
         # Adds possible when case +w+.
         def add_when(w)
             # Check +w+.
@@ -3178,7 +3175,7 @@ module HDLRuby::Low
         # Clones the Case (deeply)
         def clone
             # Clone the default if any.
-            defaut = @default ? @default.clone : nil
+            default = @default ? @default.clone : nil
             # Clone the case.
             return Case.new(@value.clone,default,(@whens.map do |w|
                 w.clone