HDLRuby 2.2.13 → 2.3.0

checksums.yaml

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data/README.md

@@ -1301,14 +1301,7 @@ __The vector operator__ `[]` is used for building types representing vectors of
 <type>[<range>]
 ```
 
-The `<range>` of a vector type indicates the position of the starting and ending bits relatively to the radix point. If the position of the starting bit
-is on the left side of the range, the vector is big endian, otherwise it is little endian.  Negative values in a range are also possible and indicate positions bellow the radix point.  For example, the following code describes a big-endian fixed-point type with 8 bits above the radix point and 4 bits
-bellow:
-
-```ruby
-bit[7..-4]
-```
-
+The `<range>` of a vector type indicates the position of the starting and ending bits.
 A `n..0` range can also be abbreviated to `n+1`. For instance, the two following types are identical:
 
 ```ruby
@@ -2801,6 +2794,19 @@ bit[4,4].inner :sig
 
 When performing computation with fixed point types, HDLRuby ensures that the result's decimal point position is correct.
 
+In addition to the fixed point data type, a method is added to the literal objects (Numeric) to convert them to fixed point representation:
+
+```ruby
+<litteral>.to_fix(<number of bits after the decimal point>)
+```
+
+For example the following code converts a floating point value to a fixed point value with 16 bits after the decimal point:
+
+```
+3.178.to_fix(16)
+```
+
+
 ## Channel
 <a name="channel"></a>
 

data/lib/HDLRuby/hdr_samples/linear_test.rb

@@ -0,0 +1,235 @@
+require 'std/memory.rb'
+require 'std/linear.rb'
+
+include HDLRuby::High::Std
+
+# Tries for matrix-vector product.
+
+
+
+
+
+# Sample code for testing the linear library.
+
+system :linear_test do
+
+    # Clock and reset.
+    inner :clk,:rst
+
+    # Request and acknoledge signals.
+    inner :req
+    [8].inner :ack
+
+
+    # Circuit for testing the scaling.
+
+    # Input memory
+    mem_file([8],8,clk,rst, rinc: :rst, winc: :rst).(:mem_scale_in)
+    # Output memory
+    mem_file([8],8,clk,rst, winc: :rst).(:mem_scale_out)
+    # Access ports.
+    mem_scale_in.branch(:anum).inner :mem_scale_inP
+    mem_scale_inPs = 8.times.map { |i| mem_scale_inP.wrap(i) }
+    mem_scale_out.branch(:anum).inner :mem_scale_outP
+    mem_scale_outPs = 8.times.map { |i| mem_scale_outP.wrap(i) }
+
+    # Build the scaler.
+    scale([8],clk.posedge,req,ack[0],channel_port(3),
+          mem_scale_inPs,mem_scale_outPs)
+
+
+    # Circuit for testing the parallel addition.
+
+    # Input memories
+    mem_file([8],8,clk,rst, rinc: :rst, winc: :rst).(:mem_addn_left_in)
+    mem_file([8],8,clk,rst, rinc: :rst, winc: :rst).(:mem_addn_right_in)
+    # Output memory
+    mem_file([8],8,clk,rst, winc: :rst).(:mem_addn_out)
+    # Access ports.
+    mem_addn_left_in.branch(:anum).inner :mem_addn_left_inP
+    mem_addn_left_inPs = 8.times.map { |i| mem_addn_left_inP.wrap(i) }
+    mem_addn_right_in.branch(:anum).inner :mem_addn_right_inP
+    mem_addn_right_inPs = 8.times.map { |i| mem_addn_right_inP.wrap(i) }
+    mem_addn_out.branch(:anum).inner :mem_addn_outP
+    mem_addn_outPs = 8.times.map { |i| mem_addn_outP.wrap(i) }
+
+    # Build the adder.
+    add_n([8],clk.posedge,ack[0],ack[1],mem_addn_left_inPs,
+          mem_addn_right_inPs,mem_addn_outPs)
+
+
+    # Circuit for testing the parallel multiplication.
+
+    # Input memories
+    mem_file([8],8,clk,rst, rinc: :rst, winc: :rst).(:mem_muln_left_in)
+    mem_file([8],8,clk,rst, rinc: :rst, winc: :rst).(:mem_muln_right_in)
+    # Output memory
+    mem_file([8],8,clk,rst, winc: :rst).(:mem_muln_out)
+    # Access ports.
+    mem_muln_left_in.branch(:anum).inner :mem_muln_left_inP
+    mem_muln_left_inPs = 8.times.map { |i| mem_muln_left_inP.wrap(i) }
+    mem_muln_right_in.branch(:anum).inner :mem_muln_right_inP
+    mem_muln_right_inPs = 8.times.map { |i| mem_muln_right_inP.wrap(i) }
+    mem_muln_out.branch(:anum).inner :mem_muln_outP
+    mem_muln_outPs = 8.times.map { |i| mem_muln_outP.wrap(i) }
+
+    # Build the multer.
+    mul_n([8],clk.posedge,ack[1],ack[2],mem_muln_left_inPs,
+          mem_muln_right_inPs,mem_muln_outPs)
+
+
+    # Circuit for testing the mac
+    # Output signal.
+    [8].inner :acc
+
+    # Build the mac.
+    mac([8],clk.posedge,ack[2],ack[3],channel_port(5), channel_port(6), 
+        channel_port(acc))
+
+
+    # Circuit for testing the parallel mac.
+    # Input memory
+    mem_file([8],8,clk,rst, winc: :rst).(:mem_macn1_left_in)
+    # Output memory
+    mem_file([8],8,clk,rst, winc: :rst).(:mem_macn1_out)
+    # Access ports.
+    mem_macn1_left_in.branch(:anum).inner :mem_macn1_left_inP
+    mem_macn1_left_inPs = 8.times.map { |i| mem_macn1_left_inP.wrap(i) }
+    mem_macn1_out.branch(:anum).inner :mem_macn1_outP
+    mem_macn1_outPs = 8.times.map { |i| mem_macn1_outP.wrap(i) }
+
+    # Build the mac.
+    mac_n1([8],clk.posedge,ack[3],ack[4], mem_macn1_left_inPs,
+          channel_port(5), mem_macn1_outPs)
+
+    # Circuit for testing the linearun with mac.
+    # Input memories
+    mem_dual([8],8,clk,rst, rinc: :rst, winc: :rst).(:mem_macrn_left_in)
+    mem_dual([8],8,clk,rst, rinc: :rst, winc: :rst).(:mem_macrn_right_in)
+    # Access ports.
+    mem_macrn_left_in.branch(:rinc).inner :mem_macrn_left_in_readP
+    mem_macrn_right_in.branch(:rinc).inner :mem_macrn_right_in_readP
+    # Output signal.
+    [8].inner :accr
+
+    # Build the linearun mac.
+    linearun(8,clk.posedge,ack[4],ack[5]) do |ev,req,ack|
+        mac([8],ev,req,ack,mem_macrn_left_in_readP,mem_macrn_right_in_readP, 
+            channel_port(accr))
+    end
+
+
+    # The memory initializer.
+    # Writing ports
+    mem_scale_in.branch(:winc).inner :mem_scale_in_writeP
+    mem_addn_left_in.branch(:winc).inner :mem_addn_left_in_writeP
+    mem_addn_right_in.branch(:winc).inner :mem_addn_right_in_writeP
+    mem_muln_left_in.branch(:winc).inner :mem_muln_left_in_writeP
+    mem_muln_right_in.branch(:winc).inner :mem_muln_right_in_writeP
+    mem_macn1_left_in.branch(:winc).inner :mem_macn1_left_in_writeP
+    mem_macrn_left_in.branch(:winc).inner :mem_macrn_left_in_writeP
+    mem_macrn_right_in.branch(:winc).inner :mem_macrn_right_in_writeP
+    # Filling index
+    [8].inner :idx
+    # Filling counter
+    [3].inner :cnt
+    # Filling value
+    [8].inner :val
+
+    # Start flag
+    inner :start
+
+    # The execution process
+    par(clk.posedge) do
+        hif(rst) { cnt <= 0; val <= 0 }
+        helse do
+            # Step index processing.
+            hif(cnt == 7) do
+                hif(idx < 8) { idx <= idx + 1 }
+            end
+            # Memory filling steps.
+            hcase(idx)
+            hwhen(0) do
+                mem_scale_in_writeP.write(val) do
+                    cnt <= cnt + 1; val <= val + 1
+                end
+            end
+            hwhen(1) do
+                mem_addn_left_in_writeP.write(val) do
+                    cnt <= cnt + 1; val <= val + 1
+                end
+            end
+            hwhen(2) do
+                mem_addn_right_in_writeP.write(val) do
+                    cnt <= cnt + 1; val <= val + 1
+                end
+            end
+            hwhen(3) do
+                mem_muln_left_in_writeP.write(val-24) do
+                    cnt <= cnt + 1; val <= val + 1
+                end
+            end
+            hwhen(4) do
+                mem_muln_right_in_writeP.write(val-24) do
+                    cnt <= cnt + 1; val <= val + 1
+                end
+            end
+            hwhen(5) do
+                mem_macn1_left_in_writeP.write(val-32) do
+                    cnt <= cnt + 1; val <= val + 1
+                end
+            end
+            hwhen(6) do
+                mem_macrn_left_in_writeP.write(val-48) do
+                    cnt <= cnt + 1; val <= val + 1
+                end
+            end
+            hwhen(7) do
+                mem_macrn_right_in_writeP.write(val-48) do
+                    cnt <= cnt + 1; val <= val + 1
+                end
+            end
+            # Computation steps.
+            helse do
+                hif(start) do
+                    req <= 1
+                    start <= 0
+                end
+                helse { req <= 0 }
+            end
+        end
+    end
+
+
+    # The test bench.
+    timed do
+        req <= 0
+        ack <= 0
+        clk <= 0
+        rst <= 0
+        cnt <= 0
+        idx <= 0
+        val <= 0
+        start <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        # Reset
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        start <= 1
+        !10.ns
+        # Run
+        128.times do
+            clk <= 1
+            !10.ns
+            clk <= 0
+            !10.ns
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/memory_test.rb

@@ -0,0 +1,272 @@
+require 'std/memory.rb'
+
+include HDLRuby::High::Std
+
+
+# Sample code for testing the memory library.
+
+system :memory_test do
+    
+    # The test step counter.
+    [8].inner :step
+    # The success counter.
+    [4].inner :yay
+
+    # The clock and reset.
+    inner :clk, :rst
+
+    # The memory address.
+    [3].inner :address
+    # The value to write to memories.
+    [8].inner :value
+    # The general result register.
+    [8].inner :result
+    # The specific result registers.
+    [8].inner :res0, :res1, :res2, :res3, :res4, :res5, :res6, :res7
+
+    # Declares a one-ports synchronous memory.
+    mem_sync(1,[8],8,clk.negedge,rst,[:rst]).(:mem_sync_1I)
+    # And the corresponding access ports.
+    mem_sync_1I.branch(0).inner :mem_sync_1P
+
+    # Declares a dual-edge memory for address-based accesses.
+    mem_dual([8],8,clk,rst,raddr: :rst, waddr: :rst).(:mem_dual0I)
+    # And the corresponding access ports.
+    mem_dual0I.branch(:raddr).inner :mem_dual_raddrP
+    mem_dual0I.branch(:waddr).inner :mem_dual_waddrP
+
+    # Declares a second dual-edge memory for incremeted accesses.
+    mem_dual([8],8,clk,rst, rinc:  :rst, winc:  :rst).(:mem_dual1I)
+    # And the corresponding access ports.
+    mem_dual1I.branch(:rinc).inner :mem_dual_rincP
+    mem_dual1I.branch(:winc).inner :mem_dual_wincP
+
+    # Declares a thrid dual-edge memory for decremented accesses.
+    mem_dual([8],8,clk,rst, rdec:  :rst, wdec:  :rst).(:mem_dual2I)
+    # And the corresponding access ports.
+    mem_dual2I.branch(:rdec).inner :mem_dual_rdecP
+    mem_dual2I.branch(:wdec).inner :mem_dual_wdecP
+
+    # Declares a first register file for address-based accesses.
+    mem_file([8],8,clk,rst,raddr: :rst, waddr: :rst).(:mem_file0I)
+    # And the corresponding access ports.
+    mem_file0I.branch(:raddr).inner :mem_file_raddrP
+    mem_file0I.branch(:waddr).inner :mem_file_waddrP
+
+    # Declares a second register file for incremeted accesses.
+    mem_file([8],8,clk,rst, rinc:  :rst, winc:  :rst).(:mem_file1I)
+    # And the corresponding access ports.
+    mem_file1I.branch(:rinc).inner :mem_file_rincP
+    mem_file1I.branch(:winc).inner :mem_file_wincP
+
+    # Declares a third register file for decremeted accesses.
+    mem_file([8],8,clk,rst, rdec:  :rst, wdec:  :rst).(:mem_file2I)
+    # And the corresponding access ports.
+    mem_file2I.branch(:rdec).inner :mem_file_rdecP
+    mem_file2I.branch(:wdec).inner :mem_file_wdecP
+
+    # Declares a forth register file for num accesses.
+    mem_file([8],8,clk,rst, anum:  :rst).(:mem_file3I)
+    # And the corresponding access port.
+    mem_file3I.branch(:anum).inner :mem_file_anumP
+
+    # Declares a fifth register file for num accesses.
+    mem_file([8],8,clk,rst, anum:  :rst).(:mem_file4I)
+    # And the corresponding access port: individual accesses.
+    mem_file4I.branch(:anum).inner :mem_file_anum1P
+    mem_file_fixP = [ mem_file_anum1P.wrap(0), mem_file_anum1P.wrap(1),
+                      mem_file_anum1P.wrap(2), mem_file_anum1P.wrap(3),
+                      mem_file_anum1P.wrap(4), mem_file_anum1P.wrap(5),
+                      mem_file_anum1P.wrap(6), mem_file_anum1P.wrap(7) ]
+
+
+    # Tests the accesses to the memories.
+    par(clk.posedge) do
+        # Initial address and value.
+        hif(rst) { address <= 0; value <= 0 }
+
+        # Handles the memory accesses.
+        hcase(step)
+        # Write to mem_sync_1
+        hwhen(1) do
+            mem_sync_1P.write(address,value) do
+                yay <= yay + 1 
+                address <= address + 1
+                value <= value + 1
+            end
+        end
+        # Read from to mem_sync_1
+        hwhen(2) do
+            mem_sync_1P.read(address,result) do
+                yay <= yay + 1 
+                address <= address + 1
+            end
+        end
+        # Write to mem_dual0 with address
+        hwhen(3) do
+            mem_dual_waddrP.write(address,value) do
+                yay <= yay + 1 
+                address <= address + 1
+                value <= value + 1
+            end
+        end
+        # Read from mem_dual0 with address
+        hwhen(4) do
+            mem_dual_raddrP.read(address,result) do
+                yay <= yay + 1 
+                address <= address + 1
+            end
+        end
+        # Write to mem_dual1 with increment
+        hwhen(5) do
+            mem_dual_wincP.write(value) do
+                yay <= yay + 1 
+                value <= value + 1
+            end
+        end
+        # Read from mem_dual1 with increment
+        hwhen(6) do
+            mem_dual_rincP.read(result) do
+                yay <= yay + 1 
+            end
+        end
+        # Write to mem_dual2 with decrement
+        hwhen(7) do
+            mem_dual_wdecP.write(value) do
+                yay <= yay + 1 
+                value <= value + 1
+            end
+        end
+        # Read from mem_dual1 with decrement
+        hwhen(8) do
+            mem_dual_rdecP.read(result) do
+                yay <= yay + 1 
+            end
+        end
+        # Write to mem_file0 with address
+        hwhen(9) do
+            mem_file_waddrP.write(address,value) do
+                yay <= yay + 1 
+                address <= address + 1
+                value <= value + 1
+            end
+        end
+        # Read from mem_file0 with address
+        hwhen(10) do
+            mem_file_raddrP.read(address,result) do
+                yay <= yay + 1 
+                address <= address + 1
+            end
+        end
+        # Write to mem_file1 with increment
+        hwhen(11) do
+            mem_file_wincP.write(value) do
+                yay <= yay + 1 
+                value <= value + 1
+            end
+        end
+        # Read from mem_file1 with increment
+        hwhen(12) do
+            mem_file_rincP.read(result) do
+                yay <= yay + 1 
+            end
+        end
+        # Write to mem_file2 with increment
+        hwhen(13) do
+            mem_file_wdecP.write(value) do
+                yay <= yay + 1 
+                value <= value + 1
+            end
+        end
+        # Read from mem_file2 with increment
+        hwhen(14) do
+            mem_file_rdecP.read(result) do
+                yay <= yay + 1 
+            end
+        end
+        # Write to mem_file3 with num access
+        hwhen(15) do
+            mem_file_anumP.write(0,0)
+            mem_file_anumP.write(1,1)
+            mem_file_anumP.write(2,2)
+            mem_file_anumP.write(3,3)
+            mem_file_anumP.write(4,4)
+            mem_file_anumP.write(5,5)
+            mem_file_anumP.write(6,6)
+            mem_file_anumP.write(7,7) do
+                yay <= 8
+            end
+        end
+        # Read from mem_file3 with num access
+        hwhen(16) do
+            mem_file_anumP.read(0,res0)
+            mem_file_anumP.read(1,res1)
+            mem_file_anumP.read(2,res2)
+            mem_file_anumP.read(3,res3)
+            mem_file_anumP.read(4,res4)
+            mem_file_anumP.read(5,res5)
+            mem_file_anumP.read(6,res6)
+            mem_file_anumP.read(7,res7) do
+                yay <= 8
+            end
+        end
+        # Write to mem_file3 with num access
+        hwhen(17) do
+            mem_file_fixP[0].write(1)
+            mem_file_fixP[1].write(2)
+            mem_file_fixP[2].write(4)
+            mem_file_fixP[3].write(8)
+            mem_file_fixP[4].write(16)
+            mem_file_fixP[5].write(32)
+            mem_file_fixP[6].write(64)
+            mem_file_fixP[7].write(128) do
+                yay <= 8
+            end
+        end
+        # Read from mem_file3 with num access
+        hwhen(18) do
+            mem_file_fixP[0].read(res0)
+            mem_file_fixP[1].read(res1)
+            mem_file_fixP[2].read(res2)
+            mem_file_fixP[3].read(res3)
+            mem_file_fixP[4].read(res4)
+            mem_file_fixP[5].read(res5)
+            mem_file_fixP[6].read(res6)
+            mem_file_fixP[7].read(res7) do
+                yay <= 8
+            end
+        end
+    end
+
+
+    timed do
+        # Initialize everything.
+        clk <= 0
+        rst <= 0
+        step <= 0
+        yay <= 0
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 1
+        !10.ns
+        clk <= 1
+        !10.ns
+        clk <= 0
+        rst <= 0
+        step <= 1
+
+        # Testing the synchronous memories.
+        256.times do
+            !10.ns
+            clk <= 1
+            !10.ns
+            hif(yay==8) do
+                step <= step + 1
+                yay <= 0
+            end
+            clk <= 0
+        end
+    end
+end