HDLRuby 2.11.12 → 3.1.0

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Files changed (91) hide show
  1. checksums.yaml +4 -4
  2. data/README.html +3274 -0
  3. data/README.md +660 -128
  4. data/ext/hruby_sim/hruby_sim_calc.c +2 -0
  5. data/lib/HDLRuby/backend/hruby_allocator.rb +2 -2
  6. data/lib/HDLRuby/backend/hruby_c_allocator.rb +7 -7
  7. data/lib/HDLRuby/hdr_samples/constant_in_function.rb +2 -1
  8. data/lib/HDLRuby/hdr_samples/mei8_bench.rb +1 -1
  9. data/lib/HDLRuby/hdr_samples/with_bram.rb +3 -3
  10. data/lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb +105 -0
  11. data/lib/HDLRuby/hdr_samples/with_bram_stack.rb +69 -0
  12. data/lib/HDLRuby/hdr_samples/with_ref_expr.rb +30 -0
  13. data/lib/HDLRuby/hdr_samples/with_sequencer.rb +185 -0
  14. data/lib/HDLRuby/hdr_samples/with_sequencer_deep.rb +91 -0
  15. data/lib/HDLRuby/hdr_samples/with_sequencer_enumerable.rb +439 -0
  16. data/lib/HDLRuby/hdr_samples/with_sequencer_enumerator.rb +89 -0
  17. data/lib/HDLRuby/hdr_samples/with_sequencer_func.rb +63 -0
  18. data/lib/HDLRuby/hdr_samples/with_sequencer_sync.rb +120 -0
  19. data/lib/HDLRuby/hdrcc.rb +16 -3
  20. data/lib/HDLRuby/hdrlib.rb +1 -1
  21. data/lib/HDLRuby/hruby_db.rb +2 -2
  22. data/lib/HDLRuby/hruby_high.rb +61 -25
  23. data/lib/HDLRuby/hruby_high_fullname.rb +3 -1
  24. data/lib/HDLRuby/hruby_low.rb +2 -2
  25. data/lib/HDLRuby/hruby_low2c.rb +58 -43
  26. data/lib/HDLRuby/hruby_low2hdr.rb +66 -40
  27. data/lib/HDLRuby/hruby_low2high.rb +86 -44
  28. data/lib/HDLRuby/hruby_low2seq.rb +26 -18
  29. data/lib/HDLRuby/hruby_low2sym.rb +14 -13
  30. data/lib/HDLRuby/hruby_low2vhd.rb +78 -43
  31. data/lib/HDLRuby/hruby_low_bool2select.rb +61 -46
  32. data/lib/HDLRuby/hruby_low_casts_without_expression.rb +56 -44
  33. data/lib/HDLRuby/hruby_low_cleanup.rb +18 -16
  34. data/lib/HDLRuby/hruby_low_fix_types.rb +64 -32
  35. data/lib/HDLRuby/hruby_low_mutable.rb +53 -118
  36. data/lib/HDLRuby/hruby_low_resolve.rb +26 -31
  37. data/lib/HDLRuby/hruby_low_with_bool.rb +33 -16
  38. data/lib/HDLRuby/hruby_low_with_port.rb +3 -3
  39. data/lib/HDLRuby/hruby_low_with_var.rb +23 -9
  40. data/lib/HDLRuby/hruby_low_without_concat.rb +19 -13
  41. data/lib/HDLRuby/hruby_low_without_namespace.rb +47 -32
  42. data/lib/HDLRuby/hruby_low_without_parinseq.rb +18 -12
  43. data/lib/HDLRuby/hruby_low_without_select.rb +36 -23
  44. data/lib/HDLRuby/hruby_low_without_subsignals.rb +79 -39
  45. data/lib/HDLRuby/hruby_rcsim.rb +79 -64
  46. data/lib/HDLRuby/hruby_rsim.rb +64 -15
  47. data/lib/HDLRuby/hruby_rsim_mute.rb +2 -3
  48. data/lib/HDLRuby/hruby_rsim_vcd.rb +28 -25
  49. data/lib/HDLRuby/hruby_types.rb +5 -5
  50. data/lib/HDLRuby/hruby_values.rb +19 -8
  51. data/lib/HDLRuby/hruby_verilog.rb +191 -65
  52. data/lib/HDLRuby/hruby_verilog_name.rb +49 -42
  53. data/lib/HDLRuby/soft/stacks.rb +219 -0
  54. data/lib/HDLRuby/std/bram.rb +9 -5
  55. data/lib/HDLRuby/std/clocks.rb +1 -1
  56. data/lib/HDLRuby/std/fsm.rb +39 -10
  57. data/lib/HDLRuby/std/sequencer.rb +2085 -0
  58. data/lib/HDLRuby/std/sequencer_func.rb +533 -0
  59. data/lib/HDLRuby/std/sequencer_sync.rb +400 -0
  60. data/lib/HDLRuby/std/std.rb +13 -0
  61. data/lib/HDLRuby/version.rb +1 -1
  62. data/tuto/adder_sat_flags_vcd.png +0 -0
  63. data/tuto/addsub_vcd.png +0 -0
  64. data/tuto/alu_vcd.png +0 -0
  65. data/tuto/bit_pong_vcd.png +0 -0
  66. data/tuto/checksum_vcd.png +0 -0
  67. data/tuto/circuit_hdr.odg +0 -0
  68. data/tuto/circuit_hdr.png +0 -0
  69. data/tuto/circuit_hie.odg +0 -0
  70. data/tuto/circuit_hie.png +0 -0
  71. data/tuto/circuit_view.odg +0 -0
  72. data/tuto/circuit_view.png +0 -0
  73. data/tuto/clock_counter_vcd.png +0 -0
  74. data/tuto/counter_ext_vcd.png +0 -0
  75. data/tuto/fact_vcd.png +0 -0
  76. data/tuto/hw_flow.odg +0 -0
  77. data/tuto/hw_flow.png +0 -0
  78. data/tuto/maxxer_vcd.png +0 -0
  79. data/tuto/pingpong0_vcd.png +0 -0
  80. data/tuto/pingpong1_vcd.png +0 -0
  81. data/tuto/pingpong2_vcd.png +0 -0
  82. data/tuto/ram_vcd.png +0 -0
  83. data/tuto/serializer_vcd.png +0 -0
  84. data/tuto/sw_flow.odg +0 -0
  85. data/tuto/sw_flow.png +0 -0
  86. data/tuto/the_counter_vcd.png +0 -0
  87. data/tuto/tutorial_sw.html +2359 -0
  88. data/tuto/tutorial_sw.md +2890 -0
  89. data/tuto/tutorial_sw.pdf +0 -0
  90. data/tuto/tutorial_sw_jp.md +417 -0
  91. metadata +46 -2
@@ -0,0 +1,400 @@
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+ require 'std/sequencer'
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+
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+ module HDLRuby::High::Std
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+
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+ ##
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+ # Standard HDLRuby::High library: sequencer synchronizer generator.
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+ # The idea is to be able to write sw-like sequential code.
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+ #
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+ ########################################################################
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+
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+
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+
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+ # Describes a signal with shared write.
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+ class SharedSignalI
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+
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+ # Create a new shared signal of type +typ+.
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+ # NOTE: for now the arbitration is the priority in order of write access
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+ # declaration.
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+ def initialize(typ, name, default_value = 0)
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+ # Process the arguments.
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+ typ = typ.to_type
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+ @type = typ
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+ name = name.to_sym
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+ @name = name
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+ @default_value = default_value
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+ # Create the name of the access process.
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+ @name_sub = HDLRuby.uniq_name(:"#{name}_sub")
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+ this = self
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+ # Register the shared signal.
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+ HDLRuby::High.space_reg(name) { this }
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+ # Create the output value and selection of the signal.
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+ value_out = nil
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+ select = nil
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+ HDLRuby::High.cur_system.open do
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+ value_out = typ.inner(HDLRuby.uniq_name(:"#{name}_out"))
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+ select = [1].inner(HDLRuby.uniq_name(:"#{name}_select") => 0)
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+ end
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+ @value_out = value_out
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+ @select = select
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+ # First no access point.
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+ @size = 0
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+ # Create the input values.
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+ values_in = nil
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+ HDLRuby::High.cur_system.open do
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+ values_in = typ[-1].inner(HDLRuby.uniq_name(:"#{name}_in"))
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+ end
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+ @values_in = values_in
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+ # The set of access points by sequencer.
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+ @points = { }
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+ end
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+
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+ # Adds an access point.
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+ def add_point
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+ # Maybe a point already exist for current sequencer.
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+ sequ = SequencerT.current
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+ point = @points[sequ]
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+ return @values_in[point] if point # Yes, return it.
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+ # No, do create a new one.
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+ point = @points[sequ] = @size
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+ # Resize the flag and value vectors.
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+ @size += 1
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+ size = @size
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+ @values_in.type.instance_variable_set(:@range,0..size-1)
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+ @select.type.instance_variable_set(:@range,(size-1).width-1..0)
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+ # (Re)Generate the access arbitrer.
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+ name_sub = @name_sub
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+ values_in = @values_in
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+ value_out = @value_out
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+ select = @select
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+ default_value = @default_value
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+ # The access arbitrer.
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+ HDLRuby::High.cur_system.open do
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+ sub(name_sub) do
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+ par do
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+ hcase(select)
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+ size.times do |i|
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+ hwhen(i) { value_out <= values_in[i] }
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+ end
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+ helse { value_out <= default_value }
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+ end
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+ end
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+ end
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+ # Return the current access point.
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+ return values_in[size-1]
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+ end
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+
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+ # Write access code generation.
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+ def <=(expr)
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+ # Create a new access point.
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+ value_in = self.add_point
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+ # Actually implement the access.
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+ value_in <= expr.to_expr
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+ return self
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+ end
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+
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+ # Read access code generation:
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+ # actually hidden in the conversion to expression.
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+ def to_expr
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+ # Return the resulting value.
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+ @value_out
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+ end
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+
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+ # Selection of the output value code generation.
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+ # +arg+ can be the index or directly the selected sequencer.
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+ # If no arg is given, return access to the selection signal direction.
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+ def select(arg = nil)
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+ return @select unless arg
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+ if arg.is_a?(SequencerT) then
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+ pt = @points[arg]
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+ @select <= @points[arg] if pt
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+ else
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+ @select <= arg
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+ end
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+ end
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+
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+ # For to_expr an all the other methods.
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+ def method_missing(m, *args, &ruby_block)
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+ self.to_expr.send(m,*args,&ruby_block)
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+ end
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+
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+ end
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+
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+
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+ # Describes an arbiter for a shared signal.
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+ class ArbiterT
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+
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+ # Create a new arbitrer named +name+ for shared signals +sigs+.
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+ def initialize(name,*sigs)
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+ # Sets the name.
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+ name = name.to_sym
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+ @name = name
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+ # Register the signals.
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+ @signals = []
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+ # Adds the signals.
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+ self.(*sigs)
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+ # Create the set of access points.
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+ @size = 0
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+ @points = {}
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+ # Create the acquire/release bit vector.
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+ acquires = nil
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+ HDLRuby::High.cur_system.open do
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+ acquires = [1].inner(HDLRuby.uniq_name(:"#{name}_acq") => 0)
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+ end
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+ @acquires = acquires
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+ # Register the arbiter.
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+ this = self
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+ HDLRuby::High.space_reg(name) { this }
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+ end
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+
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+ # Adds the signals.
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+ def call(*sigs)
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+ sigs.each do |sig|
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+ unless sig.is_a?(SharedSignalI) then
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+ raise "An arbitrer only works on a shared signal, not a #{sig.class}"
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+ end
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+ @signals << sig
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+ end
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+ end
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+
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+ # Adds an access point.
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+ def add_point
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+ # Maybe a point already exist for current sequencer.
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+ sequ = SequencerT.current
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+ point = @points[sequ]
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+ return point if point
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+ # No add it.
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+ point = @size
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+ @points[sequ] = point
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+ @size += 1
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+ # Resize the acquire vector according to the new point.
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+ @acquires.type.instance_variable_set(:@range,0..point)
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+ return point
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+ end
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+
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+ # Shared signal selection code generation.
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+ def select(point)
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+ @signals.each do |signal|
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+ signal.select(@points.key(point))
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+ end
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+ end
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+
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+ # Arbiter access code generation: 1 for acquire and 0 for release.
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+ def <=(val)
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+ # Add an access point if required.
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+ point = self.add_point
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+ # Do the access.
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+ @acquires[point] <= val
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+ end
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+ end
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+
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+
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+ # Describes a priority-based arbiter.
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+ class PriorityArbiterT < ArbiterT
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+
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+ # Create a new priority-based arbiter named +name+ with priority table
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+ # +tbl+ or priority algorithm +ruby_block+ for shared signals +sigs+.
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+ def initialize(name, tbl = nil, *sigs, &ruby_block)
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+ super(name,*sigs)
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+ # Set the priority policy.
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+ self.policy(tbl,&ruby_block)
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+ # Create the name of the access procedure sub.
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+ @name_sub = HDLRuby.uniq_name(:"#{name}_sub")
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+ end
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+
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+ # Set the policy either using a priority table +tbl+ by directly
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+ # providing the priority algorithm through +ruby_block+
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+ def policy(tbl = nil, &ruby_block)
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+ # By default the priority table is the points declaration order.
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+ if !tbl && ruby_block == nil then
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+ @priority = proc { |acquires,i| acquires[i] == 1 }
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+ elsif tbl then
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+ @priority = proc do |acquires,i|
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+ pri = tbl[i]
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+ raise "Invalid priority index: #{i}" unless pri
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+ acquires[pri] == 1
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+ end
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+ else
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+ @priority = ruby_block
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+ end
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+ end
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+
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+ # Add a point.
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+ def add_point
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+ point = super # The point is added by the parent class.
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+ # Update the access procedure.
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+ name_sub = @name_sub
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+ this = self
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+ size = @size
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+ acquires = @acquires
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+ priority = @priority
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+ HDLRuby::High.cur_system.open do
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+ sub(name_sub) do
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+ seq do
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+ if(size == 1) then
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+ # Anyway, only one accesser.
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+ this.select(0)
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+ else
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+ hif(priority.(acquires,0)) do
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+ this.select(0)
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+ end
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+ (1..size-1).each do |i|
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+ helsif(priority.(acquires,i)) do
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+ this.select(i)
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+ end
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+ end
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+ helse do # No acquire at all, select the first point.
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+ this.select(0)
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+ end
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+ end
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+ end
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+ end
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+ end
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+ return point
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+ end
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+ end
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+
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+
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+ # Describes priority-based monitor.
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+ class PriorityMonitorT < PriorityArbiterT
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+
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+ # Create a new priority-based arbiter named +name+ with priority table
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+ # +tbl+ or priority algorithm +ruby_block+ for shared signals +sigs+.
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+ def initialize(name, tbl = nil, *sigs, &ruby_block)
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+ super(name,tbl,*sigs,&ruby_block)
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+ # Declare the current selected point.
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+ selected_point = nil
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+ name = @name
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+ HDLRuby::High.cur_system.open do
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+ selected_point = [1].inner(HDLRuby.uniq_name(:"#{name}_selected"))
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+ end
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+ @selected_point = selected_point
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+ end
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+
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+ # Add a point.
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+ def add_point
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+ # Redefine to update the size of @selected_point.
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+ point = super
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+ @selected_point.type.instance_variable_set(:@range,(@size-1).width-1..0)
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+ return point
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+ end
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+
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+ # Shared signal selection code generation.
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+ def select(point)
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+ # Redefine to remember which point is selected.
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+ super(point)
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+ @selected_point <= point
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+ end
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+
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+ # # Arbiter access code generation: 1 for acquire and 0 for release.
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+ # def <=(val)
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+ # # Fully redefine to lock until selected if acquiring.
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+ # # Add an access point if required.
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+ # point = self.add_point
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+ # # Do the access.
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+ # res = (@acquires[point] <= val)
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+ # selected_point = @selected_point
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+ # # Lock until not selected.
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+ # if val.respond_to?(:to_i) then
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+ # if val.to_i == 1 then
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+ # SequencerT.current.swhile(selected_point != point)
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+ # end
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+ # else
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+ # SequencerT.current.swhile((val.to_expr == 1) & (selected_point != point))
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+ # end
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+ # return res
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+ # end
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+
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+ # Arbiter access code generation: 1 for acquire and 0 for release.
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+ def <=(val)
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+ raise "For monitors, you must use the methods lock and unlock."
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+ end
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+
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+ # Monitor lock code generation
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+ def lock
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+ # Fully redefine to lock until selected if acquiring.
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+ # Add an access point if required.
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+ point = self.add_point
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+ # Do the access.
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+ res = (@acquires[point] <= 1)
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+ selected_point = @selected_point
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+ # Lock until not selected.
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+ SequencerT.current.swhile(selected_point != point)
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+ return res
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+ end
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+
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+ # Monitor unlock code generation
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+ def unlock
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+ # Fully redefine to lock until selected if acquiring.
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+ # Add an access point if required.
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+ point = self.add_point
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+ # Do the access.
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+ res = (@acquires[point] <= 0)
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+ selected_point = @selected_point
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+ return res
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+ end
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+ end
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+
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+
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+ # Declares an arbiter named +name+ with priority table +tbl+ or priority
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+ # procedure +rubyblock+.
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+ def arbiter(name,tbl = nil, &ruby_block)
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+ return PriorityArbiterT.new(name,tbl,&ruby_block)
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+ end
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+
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+ # Declares a monitor named +name+ with priority table +tbl+ or priority
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+ # procedure +rubyblock+.
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+ def monitor(name,tbl = nil, &ruby_block)
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+ return PriorityMonitorT.new(name,tbl,&ruby_block)
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+ end
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+
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+
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+
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+
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+ # Enhance the Htype module for creating a shared signal.
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+ module HDLRuby::High::Htype
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+
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+ # Create new shared signals from +args+.
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+ # +args+ can be a name of list of names or a hash associating names to
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+ # default values.
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+ def shared(*args)
361
+ # # Process the arguments.
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+ # Create the shared signal.
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+ sig = nil
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+ args.each do |arg|
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+ if arg.is_a?(Hash) then
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+ arg.each do |k,v|
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+ sig = SharedSignalI.new(self,k,v)
368
+ end
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+ else
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+ sig = SharedSignalI.new(self,arg)
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+ end
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+ end
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+ return sig
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+ end
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+ end
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+
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+
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+ class ::Array
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+ # Enhance the Array type for creating shared signals.
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+
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+ # Create new shared signals from +args+.
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+ def shared(*names)
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+ return self.to_type.shared(*names)
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+ end
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+ end
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+
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+
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+ class ::Hash
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+ # Enhance the Struct type for creating shared signals.
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+
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+ # Create new shared signals from +args+.
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+ def shared(*names)
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+ return self.to_type.shared(*names)
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+ end
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+ end
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+
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+
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+
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+
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+ end
@@ -0,0 +1,13 @@
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+
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+ ##
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+ # Standard HDLRuby::High library: all the stable functionalities.
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+ #
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+ ########################################################################
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+
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+ require 'std/clocks.rb'
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+ require 'std/fixpoint.rb'
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+ require 'std/decoder.rb'
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+ require 'std/fsm.rb'
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+ require 'std/sequencer.rb'
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+ require 'std/sequencer_sync.rb'
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+ require 'std/sequencer_func.rb'
@@ -1,3 +1,3 @@
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  module HDLRuby
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- VERSION = "2.11.12"
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+ VERSION = "3.1.0"
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  end
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