HDLRuby 2.11.12 → 3.1.0

data/lib/HDLRuby/hruby_verilog.rb

@@ -4,10 +4,8 @@ require "HDLRuby/hruby_verilog_name.rb"
 require 'HDLRuby/hruby_low_mutable'
 
 
-# module HDLRuby::Verilog
 include HDLRuby::Verilog
 
-#include HDLRuby::Low
 module HDLRuby::Low
 
 
@@ -38,12 +36,16 @@ module HDLRuby::Low
     $vector_reg = ""   # For storing signal type at structure declaration. (temporary)
     $vector_cnt = 0    # For allocating numbers at structure declaration.  (temporary)
 
+    
     class ::Integer
+        ## Extends the Integer class with generation of verilog text.
+
         def to_verilog
             to_s
         end
     end
 
+    
     # Class summarizing "hash" used for "par" or "seq" conversion.
     class Fm
         attr_reader :fm_seq, :fm_par, :rep, :rep_sharp
@@ -87,10 +89,10 @@ module HDLRuby::Low
             # Convert the ranges to arrays.
             rngI,rngS = self.r2a(rngI), self.r2a(rngS)
             # Generate the name.
-            return "trunc_#{rngI[0]}_#{rngI[1]}_#{rngS[0]}_#{rngS[1]}"
+            return "truncer_#{rngI[0]}_#{rngI[1]}_#{rngS[0]}_#{rngS[1]}"
         end
 
-        # Generate the truncating functionds.
+        # Generate the truncating functions.
         def dump
             # Ensure there is only one truncating function per range.
             @truncers.sort!.uniq!
@@ -115,8 +117,56 @@ module HDLRuby::Low
     TruncersI = Truncers.new
 
 
-    # A class that translates the left-hand side, operator, and right-hand side into form of expression.
+    # Class for generating the truncating functions in verilog.
+    # Such function are necessary as expression cannot be truncated directly.
+    class Indexers
+        def initialize
+            @indexers = []
+        end
+
+        # Add an indexer to of expression of verilog type +typI+ returning 
+        # verilog type +typR+.
+        def add(typI,typR)
+            # Add them
+            @indexers << [typI,typR]
+        end
+        alias_method :<<, :add
+
+
+        # Generate an indexer function name for expression of verilog type
+        # +typI+ returning verilog type +typR+.
+        def indexer_name(typI,typR)
+            # Generate the name.
+            return "indexer_#{name_to_verilog(typI)}_#{name_to_verilog(typR)}"
+        end
+
+        # Generate the indexing functions.
+        def dump
+            # Ensure there is only one indexing function per range.
+            @indexers.sort!.uniq!
+            # Generate the resulting code.
+            codeT = ""
+            @indexers.each do |(typI,typR)|
+                codeT << "     function #{typR} "
+                codeT << self.indexer_name(typI,typR) 
+                codeT << "(input #{typI} val, input integer idx);\n"
+                codeT << "         " << self.indexer_name(typI,typR) << " = "
+                codeT << "val[idx];\n"
+                codeT << "      endfunction\n\n"
+            end
+            # Clears the indexers.
+            @indexers = []
+            return codeT
+        end
+    end
+
+    # Declaration of the truncating function generator.
+    IndexersI = Indexers.new
+
+
     class Binary
+        ## Enhances Binary with verilog generation.
+
         # Converts the system to Verilog code.
         def to_verilog
             return "(#{self.left.to_verilog} #{self.operator} #{self.right.to_verilog})"
@@ -158,9 +208,10 @@ module HDLRuby::Low
         end
     end
 
-    # class of Represent blocking substitution or nonblocking assignment.
-    # Enhance Transmit with generation of verilog code.
+
     class Transmit
+        ## Enhances Transmit with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog(spc = 3)
             # Determine blocking assignment or nonblocking substitution from mode and return it.
@@ -169,8 +220,10 @@ module HDLRuby::Low
         end
     end
 
-    # Enhance Print with generation of verilog code.
+
     class Print
+        ## Enhances Print with generation of verilog code.
+
         # Converts the print to Verilog code.
         def to_verilog(spc = 3)
             code = "#{" " * spc}$write(#{self.each_arg.map do |arg|
@@ -180,17 +233,20 @@ module HDLRuby::Low
         end
     end
 
-    # Enhance TimeTerminate with generation of verilog code.
+
     class TimeTerminate
+        ## Enhances TimeTerminate with generation of verilog code.
+
         # Converts the terminate to Verilog code.
         def to_verilog(spc = 3)
             return "#{" " * spc}$finish;"
         end
     end
 
-    # To scheduling to the Block.
-    # Enhance Block with generation of verilog code.
+
     class Block
+        ## Enhances Block with generation of verilog code.
+        # To scheduling to the Block.
 
         # Converts the system to Verilog code adding 'spc' spaces at the begining
         # of each line.
@@ -1439,9 +1495,10 @@ module HDLRuby::Low
         end
     end
 
-    # Used to display variable names.
-    # Enhance RefName with generation of verilog code.
+
     class RefName
+        ## Enhances RefName with generation of verilog code.
+
         # Converts the system to Verilog code using +renamer+ for producing Verilog-compatible names.
         def to_verilog
             vname = name_to_verilog(self.name)
@@ -1463,19 +1520,29 @@ module HDLRuby::Low
         end
     end
 
-    # Used to convert an array.
-    # Enhance RefIndex with generation of verilog code.
+    
     class RefIndex
+        ## Enhances RefIndex with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog
-            return "#{self.ref.to_verilog}[#{self.index.to_verilog}]"
+            # return "#{self.ref.to_verilog}[#{self.index.to_verilog}]"
+            if self.ref.is_a?(RefName) then
+                return "#{self.ref.to_verilog}[#{self.index.to_verilog}]"
+            else
+                # No a pure signal, need to use a function for accessing.
+                at = self.ref.type.to_verilog
+                rt = self.type.to_verilog
+                IndexersI.add(at,rt)
+                return "#{IndexersI.indexer_name(at,rt)}(#{self.ref.to_verilog},#{self.index.to_verilog})"
+            end
         end
     end
 
 
-    # Used to indicate the number of bits.
-    # Enhance TypeVector with generation of verilog code.
     class TypeVector
+        ## Enhances TypeVector with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog
             # if self.base.name.to_s != "bit"
@@ -1486,16 +1553,30 @@ module HDLRuby::Low
         end
     end
 
-    # Necessary for displaying bit width (eg, specify and assign).
+
     class RefRange
+        ## Enhances RefRange with generation of verilog code.
+
+        # Necessary for displaying bit width (eg, specify and assign).
+
         # Converts the system to Verilog code.
         def to_verilog(unknown = false)
-            return "#{self.ref.to_verilog}[#{self.range.first.to_getrange}:#{self.range.last.to_getrange}]"
+            if self.ref.is_a?(RefName) then
+                return "#{self.ref.to_verilog}[#{self.range.first.to_getrange}:#{self.range.last.to_getrange}]"
+            else
+                # No a pure signal, need to use a function for accessing.
+                sr = self.range.first.to_i..self.range.last.to_i
+                cr = (self.type.width-1)..0
+                TruncersI.add(cr,sr)
+                return "#{TruncersI.truncer_name(cr,sr)}(#{self.ref.to_verilog})"
+            end
         end
     end
 
-    # Use it when collecting references.
+
     class RefConcat
+        ## Enhances RefConcat with generation of verilog code.
+
         def to_verilog    
             ref = self.each_ref.to_a
 
@@ -1509,18 +1590,20 @@ module HDLRuby::Low
         end
     end
 
-    # Used to output bitstring.
-    # Enhance HDLRuby with generation of verilog code.
+
     class HDLRuby::BitString
+        ## Enhances BitString with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog
             return "#{self.to_s}"
         end
     end
 
-    # Used for connection using choice.
-    # Enhance Select with generation of verilog code.
+
     class Select
+        ## Enhances Select with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog
             # Outputs the first and second choices (choice (0) and choice (1)).
@@ -1535,9 +1618,10 @@ module HDLRuby::Low
         end
     end
 
-    # Used to output numbers.
-    # Enhance Value with generation of verilog code.
+
     class Value
+        ## Enhances Value with generation of verilog code.
+
         # Converts the system to Verilog code.
         # If it is bit, it is b, and if it is int, it is represented by d. (Example: 4'b0000, 32'd1)
         def to_verilog(unknown = nil)
@@ -1556,20 +1640,28 @@ module HDLRuby::Low
             # end
             # return "#{self.type.range.first + 1}'b#{self.content.to_verilog}"
             if self.content.is_a?(Numeric) then
-                if self.content < 0 then
-                    # str = (2**self.type.width + self.content).to_s(2)
-                    str = self.content.to_s(2)
-                    str = "0" * (self.type.width-str.length+1) + str[1..-1]
-                    return "-#{self.type.width}'b#{str}"
+                if self.type.signed? then
+                    if self.content < 0 then
+                        # str = (2**self.type.width + self.content).to_s(2)
+                        str = self.content.to_s(2)
+                        str = "0" * (self.type.width-str.length+1) + str[1..-1]
+                        return "-#{self.type.width}'sb#{str}"
+                    else
+                        str = self.content.to_s(2)
+                        str = "0" * (self.type.width-str.length) + str
+                        return "#{self.type.width}'sb#{str}"
+                    end
                 else
-                    str = self.content.to_s(2)
-                    str = "0" * (self.type.width-str.length) + str
-                    return "#{self.type.width}'b#{str}"
+                    return "#{self.type.width}'b#{self.content.to_s(2)}"
                 end
                 # return "#{self.type.width}'b#{str}"
             else
                 str = self.content.to_verilog
-                return "#{str.length}'b#{str}"
+                if self.content.negative? then
+                    return "#{str.length}'sb#{str}"
+                else
+                    return "#{str.length}'b#{str}"
+                end
             end
         end
         # How to use when simply obtaining the width
@@ -1579,9 +1671,9 @@ module HDLRuby::Low
     end
 
 
-    # Used to transrate if.
-    # Enhance If with generation of verilog code.
     class If
+        ## Enhances If with generation of verilog code.
+
         # # Converts the system to Verilog code.
         # def to_verilog(mode = nil)
         # Converts to Verilog code, checking adding 'spc' spaces at the begining
@@ -1617,10 +1709,10 @@ module HDLRuby::Low
         end
     end
 
-    # Used to translate case
+
     class Case
-        # def to_verilog(mode = nil)
-        #
+        ## Enhances Case with generation of verilog code.
+
         # Converts to Verilog code, checking if variables are register
         # or wire adding 'spc' spaces at the begining of each line.
         def to_verilog(spc = 3)
@@ -1656,9 +1748,10 @@ module HDLRuby::Low
         end
     end
 
-    # Translate expression of combination circuit.
-    # Enhance Connection with generation of verilog code.
+    
     class Connection
+        ## Enhances Connection with generation of verilog code.
+
         # Converts the system to Verilog code.
 
         # Method used for array.
@@ -1715,23 +1808,29 @@ module HDLRuby::Low
         end
     end
 
-    # It could be used for instantiation.
+    
     class RefThis
+        ## Enhances RefThis with generation of verilog code.
+
         def to_another_verilog
             return ""
         end
     end
 
-    # Used when using "~" for expressions.
+    
     class Unary
+        ## Enhances Unary with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog
             return "#{self.operator[0]}#{self.child.to_verilog}"
         end
     end
 
-    # Used when casting expressions.
+    
     class Cast
+        ## Enhances Cast with generation of verilog code.
+
         # Converts the system to Verilog code.
         # NOTE: the cast is rounded up size bit-width cast is not supported
         #       by traditional verilog.
@@ -1743,10 +1842,20 @@ module HDLRuby::Low
             cw = self.child.type.width
             sw = self.type.width
             if self.type.signed? then
-                if (sw>cw) then
-                    # Need to sign extend.
-                    return "$signed({{#{sw-cw}{#{self.child.to_verilog}[#{cw-1}]}}," +
-                        "#{self.child.to_verilog}})"
+                # Need to sign extend.
+                if cw == 1 then
+                    return "$signed({#{sw}{#{self.child.to_verilog}}})"
+                elsif (sw>cw) then
+                    # return "$signed({{#{sw-cw}{#{self.child.to_verilog}[#{cw-1}]}}," + "#{self.child.to_verilog}})"
+                    if self.child.is_a?(RefName) then
+                        return "$signed({{#{sw-cw}{#{self.child.to_verilog}[#{cw-1}]}}," + "#{self.child.to_verilog}})"
+                    else
+                        # No a pure signal, need to use a function for accessing.
+                        at = self.child.type.to_verilog
+                        rt = bit.to_verilog
+                        IndexersI.add(at,rt)
+                        return "$signed({{#{sw-cw}{#{IndexersI.indexer_name(at,rt)}(#{self.child.to_verilog},#{cw-1})}}," + "#{self.child.to_verilog}})"
+                    end
                 elsif (sw<cw) then
                     # Need to truncate
                     # return "$signed(#{self.child.to_verilog}[#{sw-1}:0])"
@@ -1773,9 +1882,10 @@ module HDLRuby::Low
         end
     end
 
-    # For declaring variables.
-    # Enhance SignalI with generation of verilog code.
+
     class SignalI
+        ## Enhances SignalI with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog
             # Convert unusable characters and return them.
@@ -1785,25 +1895,30 @@ module HDLRuby::Low
         end
     end
 
-    # If it is signed, it outputs signed.
-    # Enhance Type with generation of verilog code.
+    
     class Type
+        ## Enhances Type with generation of verilog code.
+
         # Converts the type to Verilog code.
         def to_verilog
             return self.name == :signed ? "#{self.name.to_s} " : ""
         end
     end
 
-    # Replace type by refered type.
+    
     class TypeDef
+        ## Enhances TypeDef with generation of verilog code.
+
         # Converts the type to verilog code.
         def to_verilog
             return self.def.to_verilog
         end
     end
 
-    # Use it when collecting.
+    
     class Concat
+        ## Enhances Concat with generation of verilog code.
+
         def to_verilog    
             expression = self.each_expression.to_a
 
@@ -1817,14 +1932,19 @@ module HDLRuby::Low
         end
     end
 
-    # Look at the unit of time, convert the time to ps and output it.
-    # One of two people, TimeWait and Delay.
+    
     class TimeWait
+        ## Enhances TimeWait with generation of verilog code.
+
         def to_verilog(spc = 3)
             return (" " * spc) + self.delay.to_verilog + "\n"
         end
     end
+
+
     class Delay
+        ## Enhances Delay with generation of verilog code.
+
         def to_verilog
             time = self.value.to_s
             if(self.unit.to_s == "ps") then
@@ -1842,8 +1962,9 @@ module HDLRuby::Low
     end
 
 
-    # Generate verilog code for the TimeRepeat.
     class TimeRepeat
+        ## Enhances TimeRepeat with generation of verilog code.
+
         def to_verilog(spc = 3)
             result = (" " * spc) + "repeat(#{self.number})" + "\n"
             result << self.statement.to_verilog(spc+3)
@@ -1855,8 +1976,9 @@ module HDLRuby::Low
     #class TypeTuple
     #class Event
 
-    # Enhance SystemT with generation of verilog code.
+    
     class SystemT
+        ## Enhances SystemT with generation of verilog code.
 
         ## Tells if a connection is actually a port connection.
         def port_output_connection?(connection)
@@ -2163,9 +2285,10 @@ module HDLRuby::Low
                         codeC << "),"
                     end
                 end
-                # Remove the last "," for conforming with Verilog syntax.
-                # and close the port connection.
-                codeC[-1] = ");\n"
+                # Remove the last "," if any for conforming with Verilog syntax.
+                codeC.chop! if codeC[-1] == ","
+                # And close the port connection.
+                codeC << ");\n"
             end
 
 
@@ -2247,6 +2370,8 @@ module HDLRuby::Low
 
             # Adds the truncing functions.
             code << TruncersI.dump
+            # Adds the indexing functions.
+            code << IndexersI.dump
             # Adds the content code.
             code << codeC
             return code
@@ -2254,8 +2379,9 @@ module HDLRuby::Low
     end
 
 
-    # Enhance StringE with generation of verilog code.
     class StringE
+        ## Enhances stringE with generation of verilog code.
+
         # Converts the system to Verilog code.
         def to_verilog(spc = 3)
             code = "\"#{Low.v_string(self.content)}" +
@@ -2270,8 +2396,8 @@ end
 
 
 
-## Extends the Numeric class with generation of verilog text.
 class ::Numeric
+## Extends the Numeric class with generation of verilog text.
 
     # Generates the text of the equivalent verilog code.
     # +level+ is the hierachical level of the object.

data/lib/HDLRuby/hruby_verilog_name.rb

@@ -1,42 +1,49 @@
-# Program with inverse conversion
-# last update 2019 01 29
-
-module HDLRuby::Verilog
-
-  # This is sample.
-  # n = "abc_ABC_いろは"
-  # puts n            
-  # name = n.split("")
-
-  @@hdr2verilog = {}
-
-  # Since it is possible to use $ and numbers other than the beginning of the character string, it is divided.
-  def name_to_verilog(name)
-      # name = name.to_s
-      # # Convert special characters.
-      # name = name.each_char.map do |c|
-      #     if c=~ /[a-z0-9]/ then
-      #         c
-      #     elsif c == "_" then
-      #         "__"
-      #     else
-      #         "_" + c.ord.to_s
-      #     end
-      # end.join
-      # # First character: only letter is possible.
-      # unless name[0] =~ /[a-z_]/ then
-      #     name = "_" + name
-      # end
-      # return name
-      name = name.to_s
-      vname = @@hdr2verilog[name]
-      unless vname then
-          vname = "_v#{@@hdr2verilog.size}_#{name.split(/[^a-zA-Z_0-9]/)[-1]}"
-            @@hdr2verilog[name] = vname
-      end
-      return vname
-  end
-
-  #puts ref
-
-end
+# Program with inverse conversion
+# last update 2019 01 29
+
+module HDLRuby::Verilog
+
+  # This is sample.
+  # n = "abc_ABC_いろは"
+  # puts n            
+  # name = n.split("")
+
+  @@hdr2verilog = {}
+
+  # Since it is possible to use $ and numbers other than the beginning of the character string, it is divided.
+  def name_to_verilog(name)
+      # name = name.to_s
+      # # Convert special characters.
+      # name = name.each_char.map do |c|
+      #     if c=~ /[a-z0-9]/ then
+      #         c
+      #     elsif c == "_" then
+      #         "__"
+      #     else
+      #         "_" + c.ord.to_s
+      #     end
+      # end.join
+      # # First character: only letter is possible.
+      # unless name[0] =~ /[a-z_]/ then
+      #     name = "_" + name
+      # end
+      # return name
+      name = name.to_s
+      vname = @@hdr2verilog[name]
+      unless vname then
+          # Shall we change the string?
+          if name.match?(/^[_a-zA-Z][_a-zA-Z0-9]*$/) then
+              # No, just clone
+              vname = name.clone
+          else
+              # Yes, ensure it is a verilog-compatible name.
+              vname = "_v#{@@hdr2verilog.size}_#{name.split(/[^a-zA-Z_0-9]/)[-1]}"
+          end
+          @@hdr2verilog[name] = vname
+      end
+      return vname
+  end
+
+  #puts ref
+
+end