HDLRuby 2.11.12 → 3.1.0
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- checksums.yaml +4 -4
- data/README.html +3274 -0
- data/README.md +660 -128
- data/ext/hruby_sim/hruby_sim_calc.c +2 -0
- data/lib/HDLRuby/backend/hruby_allocator.rb +2 -2
- data/lib/HDLRuby/backend/hruby_c_allocator.rb +7 -7
- data/lib/HDLRuby/hdr_samples/constant_in_function.rb +2 -1
- data/lib/HDLRuby/hdr_samples/mei8_bench.rb +1 -1
- data/lib/HDLRuby/hdr_samples/with_bram.rb +3 -3
- data/lib/HDLRuby/hdr_samples/with_bram_frame_stack.rb +105 -0
- data/lib/HDLRuby/hdr_samples/with_bram_stack.rb +69 -0
- data/lib/HDLRuby/hdr_samples/with_ref_expr.rb +30 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer.rb +185 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_deep.rb +91 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_enumerable.rb +439 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_enumerator.rb +89 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_func.rb +63 -0
- data/lib/HDLRuby/hdr_samples/with_sequencer_sync.rb +120 -0
- data/lib/HDLRuby/hdrcc.rb +16 -3
- data/lib/HDLRuby/hdrlib.rb +1 -1
- data/lib/HDLRuby/hruby_db.rb +2 -2
- data/lib/HDLRuby/hruby_high.rb +61 -25
- data/lib/HDLRuby/hruby_high_fullname.rb +3 -1
- data/lib/HDLRuby/hruby_low.rb +2 -2
- data/lib/HDLRuby/hruby_low2c.rb +58 -43
- data/lib/HDLRuby/hruby_low2hdr.rb +66 -40
- data/lib/HDLRuby/hruby_low2high.rb +86 -44
- data/lib/HDLRuby/hruby_low2seq.rb +26 -18
- data/lib/HDLRuby/hruby_low2sym.rb +14 -13
- data/lib/HDLRuby/hruby_low2vhd.rb +78 -43
- data/lib/HDLRuby/hruby_low_bool2select.rb +61 -46
- data/lib/HDLRuby/hruby_low_casts_without_expression.rb +56 -44
- data/lib/HDLRuby/hruby_low_cleanup.rb +18 -16
- data/lib/HDLRuby/hruby_low_fix_types.rb +64 -32
- data/lib/HDLRuby/hruby_low_mutable.rb +53 -118
- data/lib/HDLRuby/hruby_low_resolve.rb +26 -31
- data/lib/HDLRuby/hruby_low_with_bool.rb +33 -16
- data/lib/HDLRuby/hruby_low_with_port.rb +3 -3
- data/lib/HDLRuby/hruby_low_with_var.rb +23 -9
- data/lib/HDLRuby/hruby_low_without_concat.rb +19 -13
- data/lib/HDLRuby/hruby_low_without_namespace.rb +47 -32
- data/lib/HDLRuby/hruby_low_without_parinseq.rb +18 -12
- data/lib/HDLRuby/hruby_low_without_select.rb +36 -23
- data/lib/HDLRuby/hruby_low_without_subsignals.rb +79 -39
- data/lib/HDLRuby/hruby_rcsim.rb +79 -64
- data/lib/HDLRuby/hruby_rsim.rb +64 -15
- data/lib/HDLRuby/hruby_rsim_mute.rb +2 -3
- data/lib/HDLRuby/hruby_rsim_vcd.rb +28 -25
- data/lib/HDLRuby/hruby_types.rb +5 -5
- data/lib/HDLRuby/hruby_values.rb +19 -8
- data/lib/HDLRuby/hruby_verilog.rb +191 -65
- data/lib/HDLRuby/hruby_verilog_name.rb +49 -42
- data/lib/HDLRuby/soft/stacks.rb +219 -0
- data/lib/HDLRuby/std/bram.rb +9 -5
- data/lib/HDLRuby/std/clocks.rb +1 -1
- data/lib/HDLRuby/std/fsm.rb +39 -10
- data/lib/HDLRuby/std/sequencer.rb +2085 -0
- data/lib/HDLRuby/std/sequencer_func.rb +533 -0
- data/lib/HDLRuby/std/sequencer_sync.rb +400 -0
- data/lib/HDLRuby/std/std.rb +13 -0
- data/lib/HDLRuby/version.rb +1 -1
- data/tuto/adder_sat_flags_vcd.png +0 -0
- data/tuto/addsub_vcd.png +0 -0
- data/tuto/alu_vcd.png +0 -0
- data/tuto/bit_pong_vcd.png +0 -0
- data/tuto/checksum_vcd.png +0 -0
- data/tuto/circuit_hdr.odg +0 -0
- data/tuto/circuit_hdr.png +0 -0
- data/tuto/circuit_hie.odg +0 -0
- data/tuto/circuit_hie.png +0 -0
- data/tuto/circuit_view.odg +0 -0
- data/tuto/circuit_view.png +0 -0
- data/tuto/clock_counter_vcd.png +0 -0
- data/tuto/counter_ext_vcd.png +0 -0
- data/tuto/fact_vcd.png +0 -0
- data/tuto/hw_flow.odg +0 -0
- data/tuto/hw_flow.png +0 -0
- data/tuto/maxxer_vcd.png +0 -0
- data/tuto/pingpong0_vcd.png +0 -0
- data/tuto/pingpong1_vcd.png +0 -0
- data/tuto/pingpong2_vcd.png +0 -0
- data/tuto/ram_vcd.png +0 -0
- data/tuto/serializer_vcd.png +0 -0
- data/tuto/sw_flow.odg +0 -0
- data/tuto/sw_flow.png +0 -0
- data/tuto/the_counter_vcd.png +0 -0
- data/tuto/tutorial_sw.html +2359 -0
- data/tuto/tutorial_sw.md +2890 -0
- data/tuto/tutorial_sw.pdf +0 -0
- data/tuto/tutorial_sw_jp.md +417 -0
- metadata +46 -2
@@ -52,9 +52,9 @@ module HDLRuby::Low
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end
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## Extends the SystemT class with functionality for converting select
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# expressions to case statements.
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class SystemT
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## Extends the SystemT class with functionality for converting select
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# expressions to case statements.
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# Converts the Select expressions to Case statements.
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def select2case!
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end
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class Scope
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## Extends the Scope class with functionality for converting select
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# expressions to case statements.
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class Scope
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# Converts the Select expressions to Case statements.
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def select2case!
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end
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## Extends the TimeWait class with functionality for converting booleans
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# in assignments to select operators.
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class TimeWait
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## Extends the TimeWait class with functionality for converting booleans
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# in assignments to select operators.
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# Extract the Select expressions.
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def extract_selects!
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# Nothing to extract.
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end
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## Extends the TimeRepeat class with functionality for converting booleans
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# in assignments to select operators.
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class TimeRepeat
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## Extends the TimeRepeat class with functionality for converting
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# booleans in assignments to select operators.
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# Extract the Select expressions.
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def extract_selects!
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# Simply recruse on the statement.
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end
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## Extends the Block class with functionality for converting select
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class Block
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## Extends the Block class with functionality for converting select
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# expressions to case statements.
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# Breaks the assignments to concats.
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#
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end
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end
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# expressions to case statements.
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class Transmit
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## Extends the Transmit class with functionality for converting select
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# expressions to case statements.
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# Extract the Select expressions.
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def extract_selects!
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selects = []
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end
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class Print
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## Extends the Print class with functionality for converting select
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# expressions to case statements.
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# Extract the Select expressions.
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def extract_selects!
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selects = []
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end
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end
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class TimeTerminate
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## Extends the TimeTerminate class with functionality for converting
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# select expressions to case statements.
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# Extract the Select expressions.
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def extract_selects!
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return []
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end
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end
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## Extends the If class with functionality for converting select
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class If
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## Extends the If class with functionality for converting select
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# Extract the Select expressions.
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#
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end
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class When
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## Extends the If class with functionality for converting select
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# Extract the Select expressions.
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#
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end
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class Case
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class Expression
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## Extends the Expression class with functionality for converting select
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# Extract the Select expressions and put them into +selects+
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def extract_selects_to!(selects)
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# Makes handling by some synthesis tools easier.
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########################################################################
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class SystemT
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## Extends the SystemT class with functionality for decomposing the
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# hierachical signals in the statements.
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# # Decompose the hierarchical signals in the statements.
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# def signal2subs!
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# self.scope.signal2subs!
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# end
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# Decompose the hierarchical signals in the statements.
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# If +decompose_vec2d+ is true then also decompose 2 dimension vectors
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# (e.g., for Verilog HDL that does not support handling such signals
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# as usual expressions).
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def signal2subs!(decompose_vec2d = false)
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@@decompose_vec2d = decompose_vec2d == true
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self.scope.signal2subs!
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end
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## Tell if 2d vector signals must be decomposed too.
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def self.decompose_vec2d?
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@@decompose_vec2d
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end
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end
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class Scope
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## Extends the Scope class with functionality for decomposing the
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def signal2subs!
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class Behavior
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## Extends the Behavior class with functionality for decomposing the
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def signal2subs!
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class TimeWait
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def signal2subs!
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class TimeRepeat
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def signal2subs!
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class Transmit
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def signal2subs!
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class Print
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class TimeTerminate
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## Extends the Print class with functionality for decomposing the
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class If
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end
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class When
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class Case
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# Decompose the hierarchical signals in the statements.
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def signal2subs!
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@@ -221,24 +236,49 @@ module HDLRuby::Low
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end
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-
## Extends the RefName class with functionality for decomposing the
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# hierachical signals in the statements.
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class RefName
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+
## Extends the RefName class with functionality for decomposing the
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+
# hierachical signals in the statements.
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# Flatten a reference to a list of reference to leaf signals
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# from signal +sig+ and add to result to +subrefs+
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def flatten_to(sig,subrefs)
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# puts "flatten_to with sig name=#{sig.name}"
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-
#
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-
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-
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-
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#
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-
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-
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-
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-
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-
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+
# Shall we decompose 2d vectors, and is the current signal
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+
# for one of them?
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+
if SystemT.decompose_vec2d? and sig.type.is_a?(TypeVector) and
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+
sig.type.base.is_a?(TypeVector) then
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+
# Is the reference used other than for a memory access?
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+
unless self.parent.is_a?(RefIndex) then
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+
# Yes, do the decomposition.
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+
# Selects the direction.
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+
rng = sig.type.range
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+
if rng.first > rng.last then
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+
itr = (rng.last..rng.first).each
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+
else
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+
itr = rng.reverse_each
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+
end
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+
# Iterate on each element.
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+
itr.each do |i|
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+
# Create a reference fo the sub.
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+
subref = RefIndex.new(sig.type.base,self.clone,
|
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+
Value.new(TypeUnsigned.new(:""),i))
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+
# Add it.
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+
subrefs << subref
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+
end
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+
end
|
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+
else
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+
# Work on the sub signals if any.
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+
sig.each_signal do |sub|
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+
# Create a reference for the sub.
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+
subref = RefName.new(sub.type,self.clone,sub.name)
|
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+
# Recurse on it.
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|
+
subref.flatten_to(sub,subrefs)
|
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+
# Was it a leaf?
|
278
|
+
unless sub.each_signal.any? then
|
279
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+
# Yes, add its new ref to the list of subs.
|
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|
+
subrefs << subref
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|
+
end
|
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|
end
|
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|
end
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|
end
|