HDLRuby 2.11.10 → 2.11.12

data/lib/HDLRuby/hruby_rsim_vcd.rb

@@ -94,9 +94,10 @@ module HDLRuby::High
 
         ## Gets the VCD variables with their long name.
         def get_vars_with_fullname(vars_with_fullname = {})
-            # Adds the signals of the interface of the system.
+            # Recurse on the signals.
             self.each_signal do |sig|
-                vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
+                sig.get_vars_with_fullname(vars_with_fullname)
+                # vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
             end
             # Recurse on the scope.
             return self.scope.get_vars_with_fullname(vars_with_fullname)
@@ -104,9 +105,13 @@ module HDLRuby::High
 
         ## Gets the VCD variables with their id string.
         def get_vars_with_idstr(vars_with_idstr = {})
-            # Adds the signals of the interface of the system.
+            # # Adds the signals of the interface of the system.
+            # self.each_signal do |sig|
+            #     vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
+            # end
+            # Recurse on the signals.
             self.each_signal do |sig|
-                vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
+                sig.get_vars_with_idstr(vars_with_idstr)
             end
             # Recurse on the scope.
             return self.scope.get_vars_with_idstr(vars_with_idstr)
@@ -119,11 +124,11 @@ module HDLRuby::High
             vcdout << "$scope module #{HDLRuby::High.vcd_name(self.name)} $end\n"
             # Shows the interface signals.
             self.each_signal do |sig|
-                # puts "showing signal #{HDLRuby::High.vcd_name(sig.fullname)}"
-                vcdout << "$var wire #{sig.type.width} "
-                # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
-                vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
-                vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
+                sig.show_hierarchy(vcdout)
+                # # puts "showing signal #{HDLRuby::High.vcd_name(sig.fullname)}"
+                # vcdout << "$var wire #{sig.type.width} "
+                # vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
+                # vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
             end
             # Recurse on the scope.
             self.scope.show_hierarchy(vcdout)
@@ -170,11 +175,12 @@ module HDLRuby::High
             end
             # Shows the inner signals.
             self.each_inner do |sig|
-                # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
-                vcdout << "$var wire #{sig.type.width} "
-                # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
-                vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
-                vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
+                sig.show_hierarchy(vcdout)
+                # # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
+                # vcdout << "$var wire #{sig.type.width} "
+                # # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
+                # vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
+                # vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
             end
             # Recurse on the behaviors' blocks
             self.each_behavior do |beh|
@@ -196,9 +202,14 @@ module HDLRuby::High
 
         ## Gets the VCD variables with their long name.
         def get_vars_with_fullname(vars_with_fullname = {})
-            # Adds the inner signals.
+            # # Adds the inner signals.
+            # self.each_inner do |sig|
+            #     vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
+            # end
+            # Recurse on the inner signals.
             self.each_inner do |sig|
-                vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
+                sig.get_vars_with_fullname(vars_with_fullname)
+                # vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
             end
             # Recurse on the behaviors' blocks
             self.each_behavior do |beh|
@@ -217,9 +228,13 @@ module HDLRuby::High
 
         ## Gets the VCD variables with their id string.
         def get_vars_with_idstr(vars_with_idstr = {})
-            # Adds the inner signals.
+            # # Adds the inner signals.
+            # self.each_inner do |sig|
+            #     vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
+            # end
+            # Recurse on the inner signals.
             self.each_inner do |sig|
-                vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
+                sig.get_vars_with_idstr(vars_with_idstr)
             end
             # Recurse on the behaviors' blocks
             self.each_behavior do |beh|
@@ -237,6 +252,53 @@ module HDLRuby::High
         end
     end
 
+    ##
+    # Enhance the signals class with VCD support.
+    module SimSignal
+        ## Shows the hierarchy of the variables.
+        def show_hierarchy(vcdout)
+            # puts "show_hierarcy for signal=#{self.name}"
+            if self.each_signal.any? then
+                # The signal is hierarchical, recurse on the sub signals.
+                vcdout << "$scope module #{HDLRuby::High.vcd_name(self.name)} $end\n"
+                self.each_signal { |sig| sig.show_hierarchy(vcdout) }
+                vcdout << "$upscope $end\n"
+            else
+                # This is a signal to show.
+                vcdout << "$var wire #{self.type.width} "
+                vcdout << "#{HDLRuby::High.vcd_idstr(self)} "
+                vcdout << "#{HDLRuby::High.vcd_name(self.name)} $end\n"
+            end
+        end
+
+        ## Gets the VCD variables with their long name.
+        def get_vars_with_fullname(vars_with_fullname = {})
+            if self.each_signal.any? then
+                # There are sub signals, recurse on them.
+                self.each_signal do |sig|
+                    sig.get_vars_with_fullname(vars_with_fullname)
+                end
+            else
+                # No add the current signal.
+                vars_with_fullname[self] = HDLRuby::High.vcd_name(self.fullname)
+            end
+            return vars_with_full_name
+        end
+
+        ## Gets the VCD variables with their id string.
+        def get_vars_with_idstr(vars_with_idstr = {})
+            if self.each_signal.any? then
+                # There are sub signals, recurse on them.
+                self.each_signal do |sig|
+                    sig.get_vars_with_idstr(vars_with_idstr)
+                end
+            else
+                # No add the current signal.
+                vars_with_idstr[self] = HDLRuby::High.vcd_idstr(self)
+            end
+            return vars_with_idstr
+        end
+    end
 
     ##
     # Enhance the Transmit class with VCD support.
@@ -329,11 +391,12 @@ module HDLRuby::High
             end
             # Shows the inner signals.
             self.each_inner do |sig|
-                # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
-                vcdout << "$var wire #{sig.type.width} "
-                # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
-                vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
-                vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
+                sig.show_hierarchy(vcdout)
+                # # puts "showing inner signal #{HDLRuby::High.vcd_name(sig.fullname)}"
+                # vcdout << "$var wire #{sig.type.width} "
+                # # vcdout << "#{HDLRuby::High.vcd_name(sig.fullname)} "
+                # vcdout << "#{HDLRuby::High.vcd_idstr(sig)} "
+                # vcdout << "#{HDLRuby::High.vcd_name(sig.name)} $end\n"
             end
             # Recurse on the statements
             self.each_statement do |stmnt|
@@ -347,9 +410,14 @@ module HDLRuby::High
 
         ## Gets the VCD variables with their long name.
         def get_vars_with_fullname(vars_with_fullname = {})
-            # Adds the inner signals.
+            # # Adds the inner signals.
+            # self.each_inner do |sig|
+            #     vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
+            # end
+            # Recurse on the inner signals.
             self.each_inner do |sig|
-                vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
+                sig.get_vars_with_fullname(vars_with_fullname)
+                # vars_with_fullname[sig] = HDLRuby::High.vcd_name(sig.fullname)
             end
             # Recurse on the statements.
             self.each_statement do |stmnt|
@@ -360,9 +428,13 @@ module HDLRuby::High
 
         ## Gets the VCD variables with their id string.
         def get_vars_with_idstr(vars_with_idstr = {})
-            # Adds the inner signals.
+            # # Adds the inner signals.
+            # self.each_inner do |sig|
+            #     vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
+            # end
+            # Recurse on the inner signals.
             self.each_inner do |sig|
-                vars_with_idstr[sig] = HDLRuby::High.vcd_idstr(sig)
+                sif.get_vars_with_idstr(vars_with_idstr)
             end
             # Recurse on the statements.
             self.each_statement do |stmnt|

data/lib/HDLRuby/hruby_values.rb

@@ -13,6 +13,9 @@ module HDLRuby
 
         # Truncs integer +val+ to +width+
         def trunc(val,width)
+            if val.is_a?(BitString) then
+                return val[(width-1)..0]
+            end
             if val.bit_length > width then
                 if val >= 0 then
                     # return val & (2**width-1)
@@ -38,8 +41,9 @@ module HDLRuby
                 unless val.to_value? then
                     # Not computable, use the former method that generates
                     # HDLRuby code.
-                    return self.send(orig_operator(op),value)
+                    return self.send(orig_operator(op),val)
                 end
+                val = val.to_value unless val.is_a?(Value)
                 # Handle Numeric op BitString case.
                 if self.content.is_a?(Numeric) && val.content.is_a?(BitString)
                     if val.content.specified? then
@@ -80,27 +84,29 @@ module HDLRuby
                     return self.send(orig_operator(op),val)
                 end
                 # Process left.
-                # unless left.is_a?(Numeric) || left.is_a?(BitString) then
-                #     left = left.to_value.content
-                # end
-                left = left.content
-                if left.is_a?(BitString) && !left.specified? then
-                    return self.class.new(self.type.base,
-                                          BitString::UNKNOWN.clone)
+                if left.is_a?(Value) then
+                    left = left.content
+                    if left.is_a?(BitString) && !left.specified? then
+                        return self.class.new(self.type.base,
+                                              BitString::UNKNOWN.clone)
+                    end
+                    # left = left.to_i
+                    left = self.trunc(left.to_i,val.first.type.width)
+                else
+                    left = left.to_i
                 end
-                # left = left.to_i
-                left = self.trunc(left.to_i,val.first.type.width)
                 # Process right.
-                # unless right.is_a?(Numeric) || right.is_a?(BitString) then
-                #     right = right.to_value.content
-                # end
-                right = right.content
-                if right.is_a?(BitString) && !right.specified? then
-                    return self.class.new(self.type.base,
-                                          BitString::UNKNOWN.clone)
+                if right.is_a?(Value) then
+                    right = right.content
+                    if right.is_a?(BitString) && !right.specified? then
+                        return self.class.new(self.type.base,
+                                              BitString::UNKNOWN.clone)
+                    end
+                    # right = right.to_i
+                    right = self.trunc(right.to_i,val.last.type.width)
+                else
+                    right = right.to_i
                 end
-                # right = right.to_i
-                right = self.trunc(right.to_i,val.last.type.width)
                 # Generate the resulting type.
                 res_type = self.type.base[(left-right+1).abs]
                 # Generate the resulting value.
@@ -124,18 +130,16 @@ module HDLRuby
                     return self.send(orig_operator(op),val)
                 end
                 # Process val.
-                index = val.content
-                if index.is_a?(BitString) && !index.specified? then
-                    return self.class.new(self.type.base,
-                                          BitString::UNKNOWN.clone)
+                if val.is_a?(Value) then
+                    index = val.content
+                    if index.is_a?(BitString) && !index.specified? then
+                        return self.class.new(self.type.base,
+                                              BitString::UNKNOWN.clone)
+                    end
+                    index = self.trunc(index.to_i,val.type.width)
+                else
+                    index = val.to_i
                 end
-                index = self.trunc(index.to_i,val.type.width)
-                # index = index.to_i
-                # if index >= self.type.size then
-                #     # puts "index=#{index}"
-                #     index %= self.type.size
-                #     # puts "now index=#{index}"
-                # end
                 # Generate the resulting type.
                 res_type = self.type.base
                 # Generate the resulting value.
@@ -308,7 +312,7 @@ module HDLRuby
                         break if count == width
                     end
                     if count < width then
-                        res_content.concat(res_content[-1] * (width-count))
+                        res_content.concat([res_content[-1]] * (width-count))
                     end
                 else
                     width.times do |p|

data/lib/HDLRuby/std/bram.rb

@@ -0,0 +1,22 @@
+module HDLRuby::High::Std
+
+    # Describe a RAM compatibile with BRAM of FPGAs.
+    # - 'widthA': address bit width
+    # - 'widthD': data bit width
+    system :bram do |widthA, widthD|
+        input :clk, :rwb
+        [widthA].input :addr
+        [widthD].input :din
+        [widthD].output :dout
+
+        # puts "widthA=#{widthA} widthD=#{widthD}"
+
+        bit[widthD][-2**widthA].inner mem: [ :"_b#{"0"*widthD}".to_value ] * 2**widthA
+
+        par(clk.negedge) do
+            hif(rwb == 1) { mem[addr] <= din }
+            dout <= mem[addr]
+        end
+    end
+
+end

data/lib/HDLRuby/std/fixpoint.rb

@@ -55,14 +55,14 @@ module HDLRuby::High::Std
                             if (typ.signed?) then
                                 (left.as(signed[isize+fsize*2])*right) >> fsize
                             else
-                                (left.as([isize+fsize*2])*right) >> fsize
+                                (left.as(bit[isize+fsize*2])*right) >> fsize
                             end
                         end
                         typ.define_operator(:/) do |left,right|
                             if (typ.signed?) then
                                 (left.as(signed[isize+fsize*2]) << fsize) / right
                             else
-                                (left.as([isize+fsize*2]) << fsize) / right
+                                (left.as(bit[isize+fsize*2]) << fsize) / right
                             end
                         end
                         # Define the removal of the point.

data/lib/HDLRuby/std/fsm.rb

@@ -38,7 +38,8 @@ module HDLRuby::High::Std
             @name = name.to_sym
             # Check and set the type of fsm depending of the options.
             @dual = false
-            @type = :sync
+            @type = :sync      # By default, the FSM is synchronous.
+            @sequential = true # By default, the default next state is the next one in the list.
             options.each do |opt|
                 case opt
                 when :sync,:synchronous then
@@ -47,6 +48,8 @@ module HDLRuby::High::Std
                     @type = :async
                 when :dual then
                     @dual = true
+                when :static then
+                    @sequential = false
                 else
                     raise AnyError, "Invalid option for a fsm: :#{type}"
                 end
@@ -112,6 +115,7 @@ module HDLRuby::High::Std
             mk_rst = @mk_rst
             type = @type
             dual = @dual
+            sequential = @sequential
             extra_syncs   = @extra_syncs
             extra_asyncs  = @extra_asyncs
             default_codes = @default_codes
@@ -238,8 +242,10 @@ module HDLRuby::High::Std
                             else
                                 # No gotos, by default the next step is
                                 # current + 1
-                                # this.next_state_sig <= mux(mk_rst.call , 0, this.cur_state_sig + 1)
-                                this.next_state_sig <=  this.cur_state_sig + 1
+                                # this.next_state_sig <=  this.cur_state_sig + 1
+                                if sequential then
+                                    this.next_state_sig <= this.cur_state_sig + 1
+                                end
                             end
                         end
                     end
@@ -406,6 +412,17 @@ module HDLRuby::High::Std
             return result
         end
 
+        # Get a state by +name+.
+        def get_state(name)
+            name = name.to_sym
+            (@states.detect { |st| st.name == name }).value
+        end
+
+        # Sets the next state by +name+.
+        def next_state(name)
+            @next_state_sig <= get_state(name)
+        end
+
         # Sets the next state. Arguments can be:
         #
         # +name+: the name of the next state.

data/lib/HDLRuby/std/function_generator.rb

@@ -75,7 +75,7 @@ module HDLRuby::High::Std
         base <= lut[address]
 
         # Assign the next_data discrete value.
-        next_data <= lut[address+1]
+        next_data <= lut[address+_b1.as(address.type)]
     end
 
 
@@ -107,7 +107,7 @@ module HDLRuby::High::Std
         end
 
         # Make the interpolation.
-        par do
+        seq do
             diff <= (next_data-base).as(diff.type) * remaining
             if(otyp.signed?) then
                 interpolated_value <= base + 

data/lib/HDLRuby/version.rb

@@ -1,3 +1,3 @@
 module HDLRuby
-  VERSION = "2.11.10"
+  VERSION = "2.11.12"
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: HDLRuby
 version: !ruby/object:Gem::Version
-  version: 2.11.10
+  version: 2.11.12
 platform: ruby
 authors:
 - Lovic Gauthier
 autorequire:
 bindir: exe
 cert_chain: []
-date: 2022-12-01 00:00:00.000000000 Z
+date: 2023-01-08 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -158,13 +158,13 @@ files:
 - lib/HDLRuby/hdr_samples/seqpar_bench.rb
 - lib/HDLRuby/hdr_samples/simple_counter_bench.rb
 - lib/HDLRuby/hdr_samples/struct.rb
-- lib/HDLRuby/hdr_samples/sumprod.rb
 - lib/HDLRuby/hdr_samples/sw_encrypt_bench.rb
 - lib/HDLRuby/hdr_samples/sw_encrypt_cpu_bench.rb
 - lib/HDLRuby/hdr_samples/sw_encrypt_cpusim_bench.rb
 - lib/HDLRuby/hdr_samples/system_open.rb
 - lib/HDLRuby/hdr_samples/tuple.rb
 - lib/HDLRuby/hdr_samples/type_minmax_bench.rb
+- lib/HDLRuby/hdr_samples/with_bram.rb
 - lib/HDLRuby/hdr_samples/with_casts.rb
 - lib/HDLRuby/hdr_samples/with_channel.rb
 - lib/HDLRuby/hdr_samples/with_channel_other.rb
@@ -174,6 +174,7 @@ files:
 - lib/HDLRuby/hdr_samples/with_connector_memory.rb
 - lib/HDLRuby/hdr_samples/with_decoder.rb
 - lib/HDLRuby/hdr_samples/with_def.rb
+- lib/HDLRuby/hdr_samples/with_define_operator.rb
 - lib/HDLRuby/hdr_samples/with_delay.rb
 - lib/HDLRuby/hdr_samples/with_fixpoint.rb
 - lib/HDLRuby/hdr_samples/with_fsm.rb
@@ -181,6 +182,7 @@ files:
 - lib/HDLRuby/hdr_samples/with_handshake.rb
 - lib/HDLRuby/hdr_samples/with_init.rb
 - lib/HDLRuby/hdr_samples/with_instance.rb
+- lib/HDLRuby/hdr_samples/with_leftright.rb
 - lib/HDLRuby/hdr_samples/with_linear.rb
 - lib/HDLRuby/hdr_samples/with_loop.rb
 - lib/HDLRuby/hdr_samples/with_memory.rb
@@ -287,6 +289,7 @@ files:
 - lib/HDLRuby/hruby_low_without_outread.rb
 - lib/HDLRuby/hruby_low_without_parinseq.rb
 - lib/HDLRuby/hruby_low_without_select.rb
+- lib/HDLRuby/hruby_low_without_subsignals.rb
 - lib/HDLRuby/hruby_rcsim.rb
 - lib/HDLRuby/hruby_rsim.rb
 - lib/HDLRuby/hruby_rsim_mute.rb
@@ -339,6 +342,7 @@ files:
 - lib/HDLRuby/low_samples/with_seq.yaml
 - lib/HDLRuby/low_samples/yaml2hdr.rb
 - lib/HDLRuby/low_samples/yaml2vhd.rb
+- lib/HDLRuby/std/bram.rb
 - lib/HDLRuby/std/channel.rb
 - lib/HDLRuby/std/clocks.rb
 - lib/HDLRuby/std/connector.rb

data/lib/HDLRuby/hdr_samples/sumprod.rb

@@ -1,29 +0,0 @@
-system :sumprod do |typ,coefs|
-    typ[coefs.size].input :ins
-    typ.output :o
-
-    o <= coefs.each_with_index.reduce(_0) do |sum,(coef,i)|
-        sum + ins[i]*coef
-    end
-end
-
-
-typedef :sat do |width, max|
-    signed[width]
-end
-
-
-sat.define_operator(:+) do |width,max, x,y|
-    [width].inner :res
-    seq do
-        res <= x + y
-        ( res <= max ).hif(res > max)
-    end
-end
-
-
-
-system :sumprod_sat_16_1000, sumprod(sat(16,1000),
-                             [3,78,43,246, 3,67,1,8, 47,82,99,13, 5,77,2,4]) do
-end
-