HDLRuby 2.11.10 → 2.11.12

data/lib/HDLRuby/hruby_rcsim.rb

@@ -17,7 +17,6 @@ module HDLRuby::High
 
         ## Gives the width of an int in the current computer.
         def self.int_width
-            # puts "int_width=#{[1.to_i].pack("i").size*8}"
             return [1.to_i].pack("i").size*8
         end
 
@@ -105,30 +104,18 @@ module HDLRuby::High
                 RCSim.rcsim_set_owner(@rcsystemT,rcowner)
             end
             # Create and add the interface signals.
-            # self.each_input do |sig|
-            #     rcsig = sig.to_rcsim(@rcsystemT)
-            #     RCSim.rcsim_add_systemT_input(@rcsystemT,rcsig)
-            # end
             if self.each_input.any? then
                 RCSim.rcsim_add_systemT_inputs(@rcsystemT,
                                                self.each_input.map do |sig|
                     sig.to_rcsim(@rcsystemT)
                 end)
             end
-            # self.each_output do |sig|
-            #     rcsig = sig.to_rcsim(@rcsystemT)
-            #     RCSim.rcsim_add_systemT_output(@rcsystemT,rcsig)
-            # end
             if self.each_output.any? then
                 RCSim.rcsim_add_systemT_outputs(@rcsystemT,
                                                 self.each_output.map do |sig|
                     sig.to_rcsim(@rcsystemT)
                 end)
             end
-            # self.each_inout do |sig|
-            #     rcsig = sig.to_rcsim(@rcsystemT)
-            #     RCSim.rcsim_add_systemT_inout(@rcsystemT,rcsig)
-            # end
             if self.each_inout.any? then
                 RCSim.rcsim_add_systemT_inouts(@rcsystemT,
                                                self.each_inout.map do |sig|
@@ -174,10 +161,6 @@ module HDLRuby::High
             subowner = self.parent.is_a?(SystemT) ? rcowner : @rcscope
 
             # Create and add the inner signals.
-            # self.each_inner do |sig|
-            #     rcsig = sig.to_rcsim(@rcscope)
-            #     RCSim.rcsim_add_scope_inner(@rcscope,rcsig)
-            # end
             if self.each_inner.any? then
                 RCSim.rcsim_add_scope_inners(@rcscope,self.each_inner.map do|sig|
                     # sig.to_rcsim(@rcscope)
@@ -186,10 +169,6 @@ module HDLRuby::High
             end
             
             # Create and add the system instances.
-            # self.each_systemI do |sys|
-            #     rcsys = sys.to_rcsim(@rcscope)
-            #     RCSim.rcsim_add_scope_systemI(@rcscope,rcsys)
-            # end
             if self.each_systemI.any? then
                 RCSim.rcsim_add_scope_systemIs(@rcscope,
                                                self.each_systemI.map do |sys|
@@ -198,32 +177,7 @@ module HDLRuby::High
                 end)
             end
 
-            # Create and add the behaviors.
-            if self.each_behavior.any? then
-                RCSim.rcsim_add_scope_behaviors(@rcscope,
-                                                self.each_behavior.map do |beh|
-                    # beh.to_rcsim(@rcscope)
-                    beh.to_rcsim(subowner)
-                end)
-            end
-
-            # Create and add the connections.
-            if self.each_connection.any? then
-                RCSim.rcsim_add_scope_behaviors(@rcscope, 
-                                                self.each_connection.map do |cxt|
-                    # cxt.to_rcsim(@rcscope)
-                    cxt.to_rcsim(subowner)
-                end)
-            end
-
-            # Create and add the codes.
-            # TODO!!
-
             # Create and add the sub scopes.
-            # self.each_scope do |sub|
-            #     rcsub = sub.to_rcsim(@rcscope)
-            #     RCSim.rcsim_add_scope_scope(@rcscope,rcsub)
-            # end
             if self.each_scope.any? then
                 RCSim.rcsim_add_scope_scopes(@rcscope,self.each_scope.map do|sub|
                     # sub.to_rcsim(@rcscope)
@@ -231,6 +185,32 @@ module HDLRuby::High
                 end)
             end
 
+            # # Create and add the behaviors.
+            # if self.each_behavior.any? then
+            #     RCSim.rcsim_add_scope_behaviors(@rcscope,
+            #                                     self.each_behavior.map do |beh|
+            #         # beh.to_rcsim(@rcscope)
+            #         beh.to_rcsim(subowner)
+            #     end)
+            # end
+
+            # # Create and add the connections.
+            # if self.each_connection.any? then
+            #     RCSim.rcsim_add_scope_behaviors(@rcscope, 
+            #                                     self.each_connection.map do |cxt|
+            #         # cxt.to_rcsim(@rcscope)
+            #         cxt.to_rcsim(subowner)
+            #     end)
+            # end
+            rcbehs = self.each_behavior.map {|beh| beh.to_rcsim(subowner)} +
+                self.each_connection.map {|cxt| cxt.to_rcsim(subowner) }
+            if rcbehs.any? then
+                RCSim.rcsim_add_scope_behaviors(@rcscope,rcbehs)
+            end
+
+            # Create and add the codes.
+            # TODO!!
+
             return @rcscope
         end
     end
@@ -317,6 +297,20 @@ module HDLRuby::High
 
         attr_reader :rcbehavior
 
+        # Add sub leaf events from +sig+ of +type+.
+        def add_sub_events(type,sig)
+            if sig.each_signal.any? then
+                # The event is hierarchical, recurse.
+                sig.each_signal do |sub|
+                    self.add_sub_events(type,sub)
+                end
+            else
+                # Te event is not hierarchical, add it.
+                ref = RefObject.new(this,sig)
+                self.add_event(Event.new(type,ref))
+            end
+        end
+
         # Generate the C description of the behavior comming from object
         # whose C description is +rcowner+
         def to_rcsim(rcowner)
@@ -345,6 +339,16 @@ module HDLRuby::High
                 events = refs.map {|ref| Event.new(:anyedge,ref.clone) }
                 # Add them to the behavior for further processing.
                 events.each {|event| self.add_event(event) }
+            else
+                # Maybe there are event on hierachical signals.
+                events.each do |event|
+                    if event.ref.object.each_signal.any? then
+                        # This is a hierarchical event, remove it.
+                        self.delete_event!(event)
+                        # And replace it by event of the subs of the signal.
+                        self.add_sub_events(event.type,event.ref)
+                    end
+                end
             end
 
             # Create the behavior C object.
@@ -355,13 +359,9 @@ module HDLRuby::High
             RCSim.rcsim_set_owner(@rcbehavior,rcowner)
 
             # Create and add the events.
-            # self.each_event do |ev|
-            #     RCSim.rcsim_add_behavior_event(@rcbehavior,ev.to_rcsim)
-            # end
             if self.each_event.any? then
                 RCSim.rcsim_add_behavior_events(@rcbehavior,
                                                 self.each_event.map do |ev|
-                    # puts "adding event: #{ev.ref.object.name}(#{ev.type})"
                     ev.to_rcsim(@rcbehavior)
                 end)
             end
@@ -420,6 +420,12 @@ module HDLRuby::High
             # Set the owner.
             RCSim.rcsim_set_owner(@rcsignalI,rcowner)
 
+            # Create and add the sub signals if any.
+            RCSim.rcsim_add_signal_signals(@rcsignalI,
+                                           self.each_signal.each.map do |sig|
+                sig.to_rcsim(@rcsignalI)
+            end)
+
             # Set the initial value if any.
             if self.value then
                 RCSim.rcsim_set_signal_value(@rcsignalI,self.value.to_rcsim)
@@ -475,10 +481,6 @@ module HDLRuby::High
             RCSim.rcsim_set_owner(@rcsystemI,rcowner)
 
             # Add the alternate system types.
-            # self.each_systemT do |systemT|
-            #     rcsys = systemT.to_rcsim(@rcsystemI)
-            #     RCSim.rcsim_add_systemI_systemT(@rcsystemI,rcsys)
-            # end
             if self.each_systemI.any? then
                 RCSim.rcsim_add_systemI_systemTs(@rcsystemI,
                                                  self.each_systemT.select do|sys|
@@ -542,9 +544,6 @@ module HDLRuby::High
             @rcstatement = RCSim.rcsim_make_print()
 
             # Adds the arguments.
-            # self.each_arg do |arg|
-            #     RCSim.rcsim_add_print_arg(@rcstatement,arg.to_rcsim)
-            # end
             if self.each_arg.any? then
                 RCSim.rcsim_add_print_args(@rcstatement,
                                            self.each_arg.map(&:to_rcsim))
@@ -587,9 +586,6 @@ module HDLRuby::High
                                           self.no ? self.no.to_rcsim : nil)
 
             # Add the alternate ifs if any.
-            # self.each_noif do |cond,stmnt|
-            #     RCSim.rcsim_add_hif_noif(@rcstatement,cond.to_rcsim,stmnt.to_rcsim)
-            # end
             rcsim_conds = self.each_noif.map {|cond,stmnt| cond.to_rcsim }
             rcsim_stmnts = self.each_noif.map {|cond,stmnt| stmnt.to_rcsim }
             if rcsim_conds.any? then
@@ -617,10 +613,6 @@ module HDLRuby::High
                                     self.default ? self.default.to_rcsim : nil)
 
             # Add the hardware whens.
-            # self.each_when do |wh|
-            #     RCSim.rcsim_add_hcase_when(@rcstatement,
-            #                          wh.match.to_rcsim,wh.statement.to_rcsim)
-            # end
             rcsim_matches = self.each_when.map {|wh| wh.match.to_rcsim }
             rcsim_stmnts = self.each_when.map {|wh| wh.statement.to_rcsim }
             if rcsim_matches.any? then
@@ -690,9 +682,6 @@ module HDLRuby::High
             end
 
             # Add the inner signals.
-            # self.each_inner do |inner|
-            #     RCSim.rcsim_add_block_inner(@rcstatement,inner.to_rcsim(@rcstatement))
-            # end
             if self.each_inner.any? then
                 RCSim.rcsim_add_block_inners(@rcstatement,
                                              self.each_inner.map do |sig|
@@ -701,9 +690,6 @@ module HDLRuby::High
             end
 
             # Add the statements.
-            # self.each_statement do |stmnt|
-            #     RCSim.rcsim_add_block_statement(@rcstatement,stmnt.to_rcsim)
-            # end
             if self.each_statement.any? then
                 RCSim.rcsim_add_block_statements(@rcstatement,
                                             self.each_statement.map do |stmnt|
@@ -730,6 +716,20 @@ module HDLRuby::High
     class Connection
         attr_reader :rcbehavior
 
+        # Add recursively any event to +rcevs+ for activativing the 
+        # connection from signal +sig+ attached to +rcbehavior+
+        def self.add_rcevents(sig,rcevs,rcbehavior)
+            # Recurse on sub signals if any.
+            sig.each_signal do |sub|
+                Connection.add_rcevents(sub,rcevs,rcbehavior)
+            end
+            # Apply on the current node.
+            rcsig = sig.is_a?(SignalI) ? sig.rcsignalI : sig.rcsignalC
+            ev = RCSim.rcsim_make_event(:anyedge,rcsig)
+            RCSim.rcsim_set_owner(ev,rcbehavior)
+            rcevs << ev
+        end
+
         # Generate the C description of the connection.
         # +rcowner+ is a link to the C description of the owner scope.
         def to_rcsim(rcowner)
@@ -744,9 +744,10 @@ module HDLRuby::High
             rcevs = []
             self.right.each_node_deep do |node|
                 if node.is_a?(RefObject) && !node.parent.is_a?(RefObject) then
-                    ev = RCSim.rcsim_make_event(:anyedge,node.to_rcsim)
-                    RCSim.rcsim_set_owner(ev,@rcbehavior)
-                    rcevs << ev
+                    Connection.add_rcevents(node.object,rcevs,@rcbehavior)
+                    # ev = RCSim.rcsim_make_event(:anyedge,node.to_rcsim)
+                    # RCSim.rcsim_set_owner(ev,@rcbehavior)
+                    # rcevs << ev
                 end
             end
             if rcevs.any? then
@@ -755,9 +756,7 @@ module HDLRuby::High
 
             # Create and set the block.
             rcblock = RCSim.rcsim_make_block(:par)
-            # RCSim.rcsim_add_block_statement(
-            #     RCSim.rcsim_make_transmit(self.left.to_rcsim,
-            #                         self.right.to_rcsim))
+            RCSim.rcsim_set_owner(rcblock,@rcbehavior)
             # puts "self.left=#{self.left} self.right=#{self.right}"
             RCSim.rcsim_add_block_statements(rcblock,
                 [RCSim.rcsim_make_transmit(self.left.to_rcsim, self.right.to_rcsim)])
@@ -889,9 +888,6 @@ module HDLRuby::High
                                               self.select.to_rcsim)
 
             # Add the choice expressions. */
-            # self.each_choice do |choice|
-            #     rcsim_add_select_choice(rcexpression,choice.to_rcsim)
-            # end
             if self.each_choice.any? then
                 RCSim.rcsim_add_select_choices(rcexpression,
                                                self.each_choice.map(&:to_rcsim))
@@ -913,9 +909,6 @@ module HDLRuby::High
                                              self.type.direction)
 
             # Add the concatenated expressions. */
-            # self.each_expression do |expr|
-            #     RCSim.rcsim_add_concat_expression(rcexpression,expr.to_rcsim)
-            # end
             if self.each_expression.any? then
                 RCSim.rcsim_add_concat_expressions(rcexpression,
                                          self.each_expression.map(&:to_rcsim))
@@ -951,9 +944,6 @@ module HDLRuby::High
                                          self.type.direction)
 
             # Add the concatenated expressions. */
-            # self.each_ref do |ref|
-            #     RCSim.rcsim_add_refConcat_ref(rcref,ref.to_rcsim)
-            # end
             if self.each_ref.any? then
                 RCSim.rcsim_add_refConcat_refs(rcref,self.each_ref.map(&:to_rcsim))
             end
@@ -1015,14 +1005,36 @@ module HDLRuby::High
     class RefObject
         # attr_reader :rcref
         # alias_method :rcexpression, :rcref
+        
+        # Generate the C description of the reference object with sub signals.
+        def to_rcsim_subs
+            # Create the reference concat C object.
+            # The reference is always big endian, it is the sequence
+            # of element which is reversed if necessary.
+            rcref = RCSim.rcsim_make_refConcat(self.type.to_rcsim,:big)
+                                         # self.type.direction)
+
+            # Add the concatenated expressions. */
+            if self.object.each_signal.any? then
+                iter = self.object.each_signal
+                iter = iter.reverse_each if self.type.direction == :big
+                RCSim.rcsim_add_refConcat_refs(rcref, iter.map do|sig|
+                    sig.is_a?(SignalI) ? sig.rcsignalI : sig.rcsignalC
+                end)
+            end
+            
+            return rcref
+        end
 
         # Generate the C description of the reference object.
         def to_rcsim
             # puts "object=#{self.object.name}(#{self.object})"
             if self.object.is_a?(SignalI)
-                return self.object.rcsignalI
+                return self.object.each_signal.any? ? self.to_rcsim_subs :
+                    self.object.rcsignalI
             elsif self.object.is_a?(SignalC)
-                return self.object.rcsignalC
+                return self.object.each_signal.any? ? self.to_rcsim_subs :
+                    self.object.rcsignalC
             else
                 raise "Invalid object: #{self.object}"
             end

data/lib/HDLRuby/hruby_rsim.rb

@@ -66,7 +66,6 @@ module HDLRuby::High
                 @sig_active.each do |sig|
                     next if (sig.c_value.eql?(sig.f_value))
                     # next if (sig.c_value.to_vstr == sig.f_value.to_vstr)
-                    # puts "sig.c_value: #{sig.c_value.to_vstr}, sig.f_value=#{sig.f_value.to_vstr}"
                     sig.each_anyedge { |beh| @sig_exec << beh }
                     if (sig.c_value.zero?) then
                         # puts "sig.c_value=#{sig.c_value.content}"
@@ -108,6 +107,8 @@ module HDLRuby::High
             HDLRuby.show "#{Time.now}#{show_mem}"
             # Merge the included.
             self.merge_included!
+            # Process par in seq.
+            self.par_in_seq2seq!
             # Initializes the time.
             @time = 0
             # Initializes the time and signals execution buffers.
@@ -131,6 +132,9 @@ module HDLRuby::High
             self.init_untimeds
             # puts "End of init_untimed."
 
+            # Maybe there is nothing to execute.
+            return if @total_timed_behaviors == 0
+
             # Is there more than one timed behavior.
             if @total_timed_behaviors <= 1 then
                 # No, no need of multithreading.
@@ -490,6 +494,12 @@ module HDLRuby::High
 
         ## Initialize the simulation for +systemT+
         def init_sim(systemT)
+            # Recurse on the sub signals if any.
+            if self.each_signal.any? then
+                self.each_signal {|sig| sig.init_sim(systemT) }
+                return
+            end
+            # No sub signal, really initialize the current signal.
             if self.value then
                 @c_value = self.value.execute(:par).to_value
                 @f_value = @c_value.to_value
@@ -506,18 +516,27 @@ module HDLRuby::High
 
         ## Adds behavior +beh+ activated on a positive edge of the signal.
         def add_posedge(beh)
+            # Recurse on the sub signals.
+            self.each_signal {|sig| sig.add_posedge(beh) }
+            # Apply on current signal.
             @posedge_behaviors ||= []
             @posedge_behaviors << beh
         end
 
         ## Adds behavior +beh+ activated on a negative edge of the signal.
         def add_negedge(beh)
+            # Recurse on the sub signals.
+            self.each_signal {|sig| sig.add_negedge(beh) }
+            # Apply on current signal.
             @negedge_behaviors ||= []
             @negedge_behaviors << beh
         end
 
         ## Adds behavior +beh+ activated on a any edge of the signal.
         def add_anyedge(beh)
+            # Recurse on the sub signals.
+            self.each_signal {|sig| sig.add_anyedge(beh) }
+            # Apply on current signal.
             @anyedge_behaviors ||= []
             @anyedge_behaviors << beh
         end
@@ -543,9 +562,9 @@ module HDLRuby::High
 
         ## Execute the expression.
         def execute(mode)
-            # puts "Executing signal=#{self.fullname}"
-            # return mode == :par ? self.c_value : self.f_value
+            # puts "Executing signal=#{self.fullname} in mode=#{mode}  with c_value=#{self.c_value} and f_value=#{self.f_value}"
             return @mode == :seq ? self.f_value : self.c_value
+            # return @mode == :seq || mode == :seq ? self.f_value : self.c_value
         end
 
         ## Assigns +value+ the the reference.
@@ -649,10 +668,12 @@ module HDLRuby::High
         ## Initialize the simulation for system +systemT+.
         def init_sim(systemT)
             self.left.init_sim(systemT)
+            self.right.init_sim(systemT)
         end
 
         ## Executes the statement.
         def execute(mode)
+            # puts "execute Transmit in mode=#{mode} for left=#{self.left.object.name}"
             self.left.assign(mode,self.right.execute(mode))
         end
     end
@@ -670,6 +691,7 @@ module HDLRuby::High
 
         ## Executes the statement.
         def execute(mode)
+            # puts "execute hif with mode=#{mode}"
             # Check the main condition.
             if !(self.condition.execute(mode).zero?) then
                 self.yes.execute(mode)
@@ -848,6 +870,7 @@ module HDLRuby::High
 
         ## Executes the statement.
         def execute(mode)
+            # puts "execute block of mode=#{self.mode}"
             self.each_statement { |stmnt| stmnt.execute(self.mode) }
         end
 
@@ -858,6 +881,27 @@ module HDLRuby::High
         end
     end
 
+    class If
+        ## Returns the name of the signal with its hierarchy.
+        def fullname
+            return self.parent.fullname
+        end
+    end
+
+    class When
+        ## Returns the name of the signal with its hierarchy.
+        def fullname
+            return self.parent.fullname
+        end
+    end
+
+    class Case
+        ## Returns the name of the signal with its hierarchy.
+        def fullname
+            return self.parent.fullname
+        end
+    end
+
     # Describes a timed block.
     #
     # NOTE: 
@@ -889,8 +933,9 @@ module HDLRuby::High
         def init_sim(systemT)
             # Add the connection to the list of untimed objets.
             systemT.add_untimed(self)
-            # Recurse on the left.
+            # Recurse on the left and right.
             self.left.init_sim(systemT)
+            self.right.init_sim(systemT)
             # Process the sensitivity list.
             # Is it a clocked behavior?
             events = []
@@ -914,7 +959,7 @@ module HDLRuby::High
 
         ## Executes the statement.
         def execute(mode)
-            # puts "connection = #{self}" if self.left.is_a?(RefObject) && self.left.object.name.to_s.include?("xnor")
+            # puts "connection left=#{left} right=#{right}"
             self.left.assign(mode,self.right.execute(mode))
         end
     end
@@ -926,6 +971,11 @@ module HDLRuby::High
     #
     # NOTE: this is an abstract class which is not to be used directly.
     class Expression
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # By default: do nothing.
+        end
+
         ## Executes the expression in +mode+ (:blocking or :nonblocking)
         #  NOTE: to be overrided.
         def execute(mode)
@@ -937,6 +987,11 @@ module HDLRuby::High
     ##
     # Describes a value.
     class Value
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Nothing to do.
+        end
+
         # include Vprocess
 
         ## Executes the expression.
@@ -949,10 +1004,16 @@ module HDLRuby::High
     ##
     # Describes a cast.
     class Cast
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Recurse on the child.
+            self.child.init_sim(systemT)
+        end
+
         ## Executes the expression.
         def execute(mode)
-            # Recurse on the child.
-            # res = tocast.execute(mode)
+            # puts "child=#{self.child}"
+            # puts "child object=#{self.child.object}(#{self.child.object.name})" if self.child.is_a?(RefObject)
             # Shall we reverse the content of a concat.
             if self.child.is_a?(Concat) && 
                     self.type.direction != self.child.type.direction then
@@ -961,6 +1022,7 @@ module HDLRuby::High
             else
                 res = self.child.execute(mode)
             end
+            # puts "res=#{res}"
             # Cast it.
             res = res.cast(self.type,true)
             # Returns the result.
@@ -981,6 +1043,12 @@ module HDLRuby::High
     ## 
     # Describes an unary operation.
     class Unary
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Recurse on the child.
+            self.child.init_sim(systemT)
+        end
+
         ## Execute the expression.
         def execute(mode)
             # puts "Unary with operator=#{self.operator}"
@@ -996,6 +1064,13 @@ module HDLRuby::High
     ##
     # Describes an binary operation.
     class Binary
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Recurse on the children.
+            self.left.init_sim(systemT)
+            self.right.init_sim(systemT)
+        end
+
         ## Execute the expression.
         def execute(mode)
             # Recurse on the children.
@@ -1012,6 +1087,13 @@ module HDLRuby::High
     #
     # NOTE: choice is using the value of +select+ as an index.
     class Select
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Recurse on the children.
+            self.select.init_sim(systemT)
+            self.each_choice { |choice| choice.init_sim(systemT) }
+        end
+
         ## Execute the expression.
         def execute(mode)
             unless @mask then
@@ -1033,6 +1115,12 @@ module HDLRuby::High
     ## 
     # Describes a concatenation expression.
     class Concat
+        ## Initialize the simulation for system +systemT+.
+        def init_sim(systemT)
+            # Recurse on the children.
+            self.each_expression { |expr| expr.init_sim(systemT) }
+        end
+
         ## Execute the expression.
         def execute(mode, reverse=false)
             # Recurse on the children.
@@ -1218,7 +1306,44 @@ module HDLRuby::High
     class RefObject
         ## Initialize the simulation for system +systemT+.
         def init_sim(systemT)
+            # puts "init_sim for RefObject=#{self}"
             @sim = systemT
+
+            # Modify the exectute and assign methods if the object has
+            # sub signals (for faster execution).
+            if self.object.each_signal.any? then
+                ## Execute the expression.
+                self.define_singleton_method(:execute) do |mode|
+                    # Recurse on the children.
+                    iter = self.object.each_signal
+                    iter = iter.reverse_each unless self.object.type.direction == :big
+                    tmpe = iter.map {|sig| sig.execute(mode) }
+                    # Concatenate the result.
+                    # return tmpe.reduce(:concat)
+                    return Vprocess.concat(*tmpe)
+                end
+                ## Assigns +value+ the the reference.
+                self.define_singleton_method(:assign) do |mode,value|
+                    # puts "RefObject #{self} assign with object=#{self.object}"
+                    # Flatten the value type.
+                    value.type = [value.type.width].to_type
+                    pos = 0
+                    width = 0
+                    # Recurse on the children.
+                    iter = self.object.each_signal
+                    iter = iter.reverse_each unless self.object.type.direction == :big
+                    iter.each do |sig|
+                        width = sig.type.width
+                        sig.assign(mode,value[(pos+width-1).to_expr..pos.to_expr])
+                        # Tell the signal changed.
+                        if !(sig.c_value.eql?(sig.f_value)) then
+                            @sim.add_sig_active(sig)
+                        end
+                        # Prepare for the next reference.
+                        pos += width
+                    end
+                end
+            end
         end
 
         ## Execute the expression.