HDLRuby 2.11.10 → 2.11.12

data/ext/hruby_sim/hruby_sim_list.c

@@ -19,7 +19,7 @@ Elem get_element(void* data) {
     /* Is the pool empty? */
     if (empty_list(&pool_elements)) {
         /* Yes, allocates a new element. */
-        elem = malloc(sizeof(ElemS));
+        elem = (Elem)malloc(sizeof(ElemS));
         elem->data = data;
         elem->next = NULL;
     } else {

data/ext/hruby_sim/hruby_sim_stack_calc.c

@@ -14,7 +14,7 @@
  **/
 
 /* The stack variables. */
-#define STACK_SIZE 0x10000
+#define STACK_SIZE 0x100000
 static Value stack[STACK_SIZE];
 static int head = STACK_SIZE;
 
@@ -86,7 +86,8 @@ Value unary(Value (*oper)(Value,Value)) {
     // dst = oper(pop(),dst);
     // push(dst);
     // return dst;
-    return oper(pop(),peek());
+    Value v = pop();
+    return oper(v,peek());
 }
 
 /** Binary calculation.

data/ext/hruby_sim/hruby_sim_tree_calc.c

@@ -181,7 +181,7 @@ Value calc_expression(Expression expr, Value res) {
  *  @param behavior the behavior in execution. */
 void execute_statement(Statement stmnt, int mode, Behavior behavior) {
     /* Depending on the kind of statement. */
-    // printf("Executing statement=%p with kind=%d\n",stmnt,stmnt->kind);fflush(stdout);
+    // printf("Executing statement=%p with kind=%d in mode=%d\n",stmnt,stmnt->kind,mode);fflush(stdout);
     switch(stmnt->kind) {
         case TRANSMIT: 
             {
@@ -236,6 +236,7 @@ void execute_statement(Statement stmnt, int mode, Behavior behavior) {
                             lastV = calc_expression(refr->last,lastV);
                             long long last = value2integer(lastV);
                             free_value();
+                            // printf("firstV=%lld lastV=%lld right=%lld mode=%d\n",firstV->data_int,lastV->data_int,right->data_int,mode);
                             /* Generate the reference inside the left value. */
                             RefRangeS ref = 
                                 make_ref_rangeS((SignalI)(refr->ref),refr->type,
@@ -399,9 +400,15 @@ void execute_statement(Statement stmnt, int mode, Behavior behavior) {
                 }
                 break;
             }
+        case TIME_TERMINATE:
+            {
+                terminate();
+                break;
+            }
         case BLOCK:
             {
                 Block block = (Block)stmnt;
+                // printf("Block mode=%d\n",block->mode);
                 /* Execute each statement of the block. */
                 for(int i=0; i<block->num_stmnts; ++i)
                     execute_statement(block->stmnts[i],block->mode,behavior);

data/ext/hruby_sim/hruby_sim_vcd.c

@@ -155,12 +155,28 @@ static void vcd_print_value(Value value) {
 /** Prints a signal declaration.
  *  @param signal the signal to declare */
 static void vcd_print_var(SignalI signal) {
-    vcd_print("$var wire %d ",type_width(signal->type));
-    // vcd_print_full_name((Object)signal);
-    vcd_print_signal_id(signal);
-    vcd_print(" ");
-    vcd_print_name((Object)signal);
-    vcd_print(" $end\n");
+    if (signal->num_signals > 0) {
+        int i;
+        /* The signal is hierarchical, declare its sub signals. */
+        /* Declares the hierachical name. */
+        vcd_print("$scope module ");
+        vcd_print_name((Object)signal);
+        vcd_print(" $end\n");
+        /* Declare the inners of the systems. */
+        for(i=0; i<signal->num_signals; ++i) {
+            vcd_print_var(signal->signals[i]);
+        }
+        /* Close the hierarchy. */
+        vcd_print("$upscope $end\n");
+    } else {
+        /* The signal is flat, can declarate it directly. */
+        vcd_print("$var wire %d ",type_width(signal->type));
+        // vcd_print_full_name((Object)signal);
+        vcd_print_signal_id(signal);
+        vcd_print(" ");
+        vcd_print_name((Object)signal);
+        vcd_print(" $end\n");
+    }
 }
 
 
@@ -180,7 +196,8 @@ static void vcd_print_signal_fvalue(SignalI signal) {
 /** Prints a signal with its current value if any
  *  @param signal the signal to show */
 static void vcd_print_signal_cvalue(SignalI signal) {
-    if (signal->c_value) {
+    if ((signal->num_signals == 0) && signal->c_value) {
+        /* The signal is not hierachical and has a current value. */
         vcd_print_value(signal->c_value);
         // vcd_print(" ");
         // vcd_print_full_name((Object)signal);

data/ext/hruby_sim/hruby_sim_vizualize.c

@@ -63,8 +63,15 @@ void default_print_name(Object object) {
     }
     /* Depending on the kind of object. */
     switch(object->kind) {
-        case SYSTEMT:
         case SIGNALI:
+            /* Print the name if name. */
+            /* Trick: SystemT, SignalI, Scope and SystemI have the
+             * field name at the same place. */
+            if (((SignalI)object)->name != NULL) {
+                printf("%s",((SignalI)object)->name);
+            }
+            break;
+        case SYSTEMT:
         case SCOPE:
         case SYSTEMI:
             /* Print the name if name. */
@@ -73,6 +80,7 @@ void default_print_name(Object object) {
             if (((SystemI)object)->name != NULL) {
                 printf("%s",((SystemI)object)->name);
             }
+            break;
         default: /* Nothing to do */
             break;
     }

data/lib/HDLRuby/hdr_samples/constant_in_function.rb

@@ -2,7 +2,7 @@
 
 
 function :func do |addr|
-    bit[4][-4].constant tbl: [ _1000, _1001, _1010, _1011 ]
+    bit[4][-4].constant tbl: [ _b1000, _b1001, _b1010, _b1011 ]
     
     tbl[addr]
 end
@@ -10,9 +10,11 @@ end
 
 system :with_func do
     [4].inner :addr, :val
+    # bit[4][-4].constant tbl: [ _b1000, _b1001, _b1010, _b1011 ]
 
     val <= func(addr)
     # val <= 1
+    # val <= tbl[addr]
 
     timed do
         addr <= 0

data/lib/HDLRuby/hdr_samples/counter_dff_bench.rb

@@ -1,7 +1,7 @@
 # A simple D-FF
 system :dff do
     input  :clk, :d
-    output q: 0
+    output :q
 
     (q <= d).at(clk.posedge)
 end
@@ -18,6 +18,8 @@ system :dff_bench do
     d1 <= ~q1
 
     timed do
+        d0 <= 0
+        d1 <= 0
         clk <= 0
         !10.ns
         clk <= 1

data/lib/HDLRuby/hdr_samples/huge_rom.rb

@@ -3,7 +3,7 @@ system :huge_rom do
     [15..0].input :addr
     [7..0].output :data
 
-    bit[7..0][-65536].constant content: 65536.times.to_a
+    bit[7..0][-65536].constant content: 65536.times.map {|i| i.to_value.as(bit[8]) }
 
     data <= content[addr]
 end

data/lib/HDLRuby/hdr_samples/mei8.rb

@@ -117,7 +117,7 @@ system :mei8 do |prog_file = "./prog.obj"|
                 # Format 1
                 entry("01oooyyy") { wf <= 1
                                     # Destination is also y in case of inc/dec
-                                    hif (ir[6..4] == _101) { dst <= y }
+                                    hif (ir[6..4] == _b101) { dst <= y }
                                     alu.(o,a,src1) }      # binary alu
                 # Format 1 extended.
                 entry("10000yyy") { wr <= 0; wf <= 1
@@ -128,17 +128,17 @@ system :mei8 do |prog_file = "./prog.obj"|
                 entry("10011yyy") { branch <= 1           # jr y, must inc y
                                     alu.(2,src1) }        # since pc-1 is used
                 # Format 2
-                entry("1010iiii") { alu.(7,[_0000,i]) }   # movl i
+                entry("1010iiii") { alu.(7,[_b0000,i]) }   # movl i
                 entry("1011iiii") { alu.(7,[i,a[3..0]]) } # movh i
                 # Format 4
                 entry("11110110") { branch <= 1           # trap
                                     alu.(7,0xFC)  }       
-                entry("11110ooo") { wf <= 1; alu.([_1,o],a) } # unary alu
+                entry("11110ooo") { wf <= 1; alu.([_b1,o],a) } # unary alu
                 entry("111110os") { st <= s; ld <= ~s     # ++--ld / ++--st
-                                    alu.([_001,o],g); dst <= 6 }
+                                    alu.([_b001,o],g); dst <= 6 }
                 entry("1111110i") { branch <= i
                                     st <= ~i; ld <= i
-                                    alu.([_001,~i],h)
+                                    alu.([_b001,~i],h)
                                     dst <= 7; io_out <= pc } # push / pop pc
                 # Format 3
                 entry("11cccsii") { branch <= cc; wr <= 0
@@ -180,7 +180,7 @@ system :mei8 do |prog_file = "./prog.obj"|
             [a,b,c,d,e,f,g,h,zf,cf,sf,vf,nbr,npc,s].each { |r| r <= 0 }
         end
         # Ensures a is 0 and enable interrupts when starting.
-        helsif(init) { a<= 0; s <= _00000011; } 
+        helsif(init) { a<= 0; s <= _b00000011; } 
         helsif(iq_calc) do
             s[7] <= 1
             hif(iq1) { s[1] <= 0 }
@@ -195,14 +195,14 @@ system :mei8 do |prog_file = "./prog.obj"|
                 zf <= alu.zf; cf <= alu.cf; sf <= alu.sf; vf <= alu.vf
             end
             # Specific cases
-            hif(ir == _11110111) { s <= a; a <= s } # xs
-            hif(ir == _11110110) { s[7] <= 1 }      # trap
+            hif(ir == _b11110111) { s <= a; a <= s } # xs
+            hif(ir == _b11110110) { s[7] <= 1 }      # trap
             hif(branch) { npc <= alu.z; nbr <= 1 }  # Branch
         end
         # Write memory read result to a register if any.
         helsif (io_r_done) do
             hif(branch) { npc <= data; nbr <= 1 }   # pop case  
-            helsif(ir[7..3] == _10001) do           # ld case
+            helsif(ir[7..3] == _b10001) do           # ld case
                 [a,b,c,d,e,f,g,h].hcase(dst) {|r| r <= data }
             end
             helse { a <= data }                     # ld++-- case
@@ -231,8 +231,8 @@ system :mei8 do |prog_file = "./prog.obj"|
                        goto(iq_chk,:iq_s)         # Interrupt / No interrupt
                        goto(branch,:br)           # Branch instruction
                        goto((ld|st) & ~io_done,:ld_st) # ld/st instruction
-                       goto(ir == _11111110,:ht)       # Halt instruction
-                       goto(ir == _11111111,:re) }     # Reset instruction
+                       goto(ir == _b11111110,:ht)       # Halt instruction
+                       goto(ir == _b11111111,:re) }     # Reset instruction
         # Branch state.
         state(:br)   { goto(iq_chk,:iq_s,:fe) }   # Interrupt / No interrupt
         sync(:br)    { hif(nbr) { pc <= npc-1 } } # Next pc is the branch target

data/lib/HDLRuby/hdr_samples/mei8_bench.rb

@@ -119,7 +119,7 @@ system :mei8 do |prog_file = "./prog.obj"|
                 # Format 1
                 entry("01oooyyy") { wf <= 1
                                     # Destination is also y in case of inc/dec
-                                    hif (ir[6..4] == _101) { dst <= y }
+                                    hif (ir[6..4] == _b101) { dst <= y }
                                     alu.(o,a,src1) }      # binary alu
                 # Format 1 extended.
                 entry("10000yyy") { wr <= 0; wf <= 1
@@ -130,17 +130,17 @@ system :mei8 do |prog_file = "./prog.obj"|
                 entry("10011yyy") { branch <= 1           # jr y, must inc y
                                     alu.(2,src1) }        # since pc-1 is used
                 # Format 2
-                entry("1010iiii") { alu.(7,[_0000,i]) }   # movl i
+                entry("1010iiii") { alu.(7,[_b0000,i]) }   # movl i
                 entry("1011iiii") { alu.(7,[i,a[3..0]]) } # movh i
                 # Format 4
                 entry("11110110") { branch <= 1           # trap
                                     alu.(7,0xFC)  }       
-                entry("11110ooo") { wf <= 1; alu.([_1,o],a) } # unary alu
+                entry("11110ooo") { wf <= 1; alu.([_b1,o],a) } # unary alu
                 entry("111110os") { st <= s; ld <= ~s     # ++--ld / ++--st
-                                    alu.([_001,o],g); dst <= 6 }
+                                    alu.([_b001,o],g); dst <= 6 }
                 entry("1111110i") { branch <= i
                                     st <= ~i; ld <= i
-                                    alu.([_001,~i],h)
+                                    alu.([_b001,~i],h)
                                     dst <= 7; io_out <= pc } # push / pop pc
                 # Format 3
                 entry("11cccsii") { branch <= cc; wr <= 0
@@ -182,7 +182,7 @@ system :mei8 do |prog_file = "./prog.obj"|
             [a,b,c,d,e,f,g,h,zf,cf,sf,vf,nbr,npc,s].each { |r| r <= 0 }
         end
         # Ensures a is 0 and enable interrupts when starting.
-        helsif(init) { a<= 0; s <= _00000011; } 
+        helsif(init) { a<= 0; s <= _b00000011; } 
         helsif(iq_calc) do
             s[7] <= 1
             hif(iq1) { s[1] <= 0 }
@@ -197,14 +197,14 @@ system :mei8 do |prog_file = "./prog.obj"|
                 zf <= alu.zf; cf <= alu.cf; sf <= alu.sf; vf <= alu.vf
             end
             # Specific cases
-            hif(ir == _11110111) { s <= a; a <= s } # xs
-            hif(ir == _11110110) { s[7] <= 1 }      # trap
+            hif(ir == _b11110111) { s <= a; a <= s } # xs
+            hif(ir == _b11110110) { s[7] <= 1 }      # trap
             hif(branch) { npc <= alu.z; nbr <= 1 }  # Branch
         end
         # Write memory read result to a register if any.
         helsif (io_r_done) do
             hif(branch) { npc <= data; nbr <= 1 }   # pop case  
-            helsif(ir[7..3] == _10001) do           # ld case
+            helsif(ir[7..3] == _b10001) do           # ld case
                 [a,b,c,d,e,f,g,h].hcase(dst) {|r| r <= data }
             end
             helse { a <= data }                     # ld++-- case
@@ -233,8 +233,8 @@ system :mei8 do |prog_file = "./prog.obj"|
                        goto(iq_chk,:iq_s)         # Interrupt / No interrupt
                        goto(branch,:br)           # Branch instruction
                        goto((ld|st) & ~io_done,:ld_st) # ld/st instruction
-                       goto(ir == _11111110,:ht)       # Halt instruction
-                       goto(ir == _11111111,:re) }     # Reset instruction
+                       goto(ir == _b11111110,:ht)       # Halt instruction
+                       goto(ir == _b11111111,:re) }     # Reset instruction
         # Branch state.
         state(:br)   { goto(iq_chk,:iq_s,:fe) }   # Interrupt / No interrupt
         sync(:br)    { hif(nbr) { pc <= npc-1 } } # Next pc is the branch target

data/lib/HDLRuby/hdr_samples/neg_arith_bench.rb

@@ -42,15 +42,15 @@ system :neg_arith_bench do
         z <= x * y
         cmp <= (x < y)
         !10.ns
-        x <= _000000011010
-        y <= _000011111010
+        x <= _b000000011010
+        y <= _b000011111010
         z <= 0
         !10.ns
         z <= x * y
         cmp <= (x < y)
         !10.ns
-        x <= _000000011010
-        y <= _111111111010
+        x <= _b000000011010
+        y <= _b111111111010
         z <= 0
         !10.ns
         z <= x * y

data/lib/HDLRuby/hdr_samples/rom_nest.rb

@@ -1,6 +1,6 @@
 # Rom access generator, def case.
 def rom_gen(addr,&func)
-    bit[8][-8].constant tbl? => 8.times.map {|i| func.(i).to_i }
+    bit[8][-8].constant tbl? => 8.times.map {|i| func.(i).to_value.as(bit[8]) }
     tbl![addr]
 end
 

data/lib/HDLRuby/hdr_samples/ruby_fir_hw.rb

@@ -50,13 +50,13 @@ system :work do
 
     # The input memory.
     mem_rom([8],8,clk,rst,
-            [_00000001,_00000010,_00000011,_00000100,
-             _00000101,_00000110,_00000111,_00001000]).(:iMem)
+            [_b00000001,_b00000010,_b00000011,_b00000100,
+             _b00000101,_b00000110,_b00000111,_b00001000]).(:iMem)
     # The output memory.
     mem_dual([8],8,clk,rst).(:oMem)
     # The coefficients.
-    coefs = [_11001100,_00110011,_10101010,_01010101,
-             _11110000,_00001111,_11100011,_00011100]
+    coefs = [_b11001100,_b00110011,_b10101010,_b01010101,
+             _b11110000,_b00001111,_b11100011,_b00011100]
 
     # The filter
     fir([8],iMem.branch(:rinc),oMem.branch(:winc),coefs).(:my_fir).(clk,rst,req,ack)

data/lib/HDLRuby/hdr_samples/struct.rb

@@ -1,14 +1,48 @@
-system :dff do
-   input :clk, :rst, :d
-   output :q
-
-   par(clk.posedge) { q <= d & ~rst }
+typedef(:some_struct) do
+    { sub2: bit, sub3: bit[2] }
 end
 
 system :my_system do
-   input :clk, :rst
-   { sub0: bit, sub1: bit}.inner :sig
-   
-   dff(:dff0).(clk: clk, rst: rst)
-   dff0.d <= sig.sub0
+    inner :x
+    [3].inner :y
+    inner :z
+    { sub0: bit, sub1: bit[2]}.inner :sigA
+    some_struct.inner :sigB, :sigC
+
+    sigC <= sigA
+
+    par(sigA) { z <= ~z }
+
+
+    timed do
+        z <= 0
+        x <= 1
+        y <= _b000
+        !10.ns
+        sigA.sub0 <= 0
+        sigA.sub1 <= x
+        sigB.sub2 <= 0
+        sigB.sub3 <= x
+        !10.ns
+        sigA.sub0 <= x
+        sigA.sub1 <= ~sigB.sub3
+        sigB.sub2 <= x
+        sigB.sub3 <= ~sigA.sub1
+        !10.ns
+        sigA <= _b111
+        sigB <= _b111
+        !10.ns
+        sigA <= _b100
+        !10.ns
+        y <= sigA
+        sigB <= sigA
+        !10.ns
+        sigA <= _b011
+        !10.ns
+        sigB <= sigA
+        !10.ns
+        sigB <= sigA + 1
+        !10.ns
+    end
+
 end

data/lib/HDLRuby/hdr_samples/with_bram.rb

@@ -0,0 +1,45 @@
+require 'std/bram.rb'
+
+include HDLRuby::High::Std
+
+
+# A system testing the memory.
+system :bram_test do
+
+    widthA = 16
+    widthD = 8
+
+
+    input :clk,:rwb
+    [widthA].inner :addr
+    [widthD].inner  :din,:dout
+
+    bram(widthA,widthD).(:bramI).(clk,rwb,addr,din,dout)
+
+    timed do
+        clk  <= 0
+        rwb  <= 1
+        addr <= 0
+        din  <= 0
+        !10.ns
+        clk  <= 1
+        !10.ns
+        rwb <= 1
+        repeat(16) do
+            clk <= 0
+            !10.ns
+            clk <= 1
+            addr <= addr + 1
+            din <= din + 1
+            !10.ns
+        end
+        rwb <= 0
+        repeat(16) do
+            clk <= 0
+            !10.ns
+            clk <= 1
+            addr <= addr-1
+            !10.ns
+        end
+    end
+end

data/lib/HDLRuby/hdr_samples/with_casts.rb

@@ -6,9 +6,9 @@ system :with_cast do
     [9].inner :val2,:val3
 
     timed do
-        val0 <= _11111111
-        val1 <= _00000010
-        val3 <= _000000000
+        val0 <= _b11111111
+        val1 <= _b00000010
+        val3 <= _b000000000
         count <= 0
         !10.ns
         count <= 1

data/lib/HDLRuby/hdr_samples/with_concat.rb

@@ -10,16 +10,16 @@ system :with_concat do
     val3 <= [val2,val0]
 
     timed do
-        val0 <= _1111
-        val1 <= _0000
+        val0 <= _b1111
+        val1 <= _b0000
         count <= 0
         !10.ns
-        val0 <= _1001
-        val1 <= _0110
+        val0 <= _b1001
+        val1 <= _b0110
         count <= 1
         !10.ns
-        val0 <= _1010
-        val1 <= _0101
+        val0 <= _b1010
+        val1 <= _b0101
         count <= 2
         !10.ns
     end

data/lib/HDLRuby/hdr_samples/with_connector_memory.rb

@@ -12,8 +12,8 @@ system :channel_connector do
     address_width = 4 # lutのアドレスのビット幅
     typ = signed[integer_width + decimal_width] # データ型
     
-    inputs_x = _00010011
-    inputs_h = _10100001
+    inputs_x = _b00010011
+    inputs_h = _b10100001
     columns = [2, 2, 1]
 
     inner :clk,   # clock

data/lib/HDLRuby/hdr_samples/with_def.rb

@@ -9,11 +9,18 @@ end
 system :def_bench do
 
     [2].inner :addr
-    [8].inner :val0, :val1
+    [8].inner :val0, :val1, :val2, :val3
 
     par do
-        val0 <= lut84([0,1,4,9],addr)
-        val1 <= lut84([0,1,4,9],3-addr)
+        val0 <= lut84([_b8d0,_b8d1,_b8d4,_b8d9],addr)
+        val1 <= lut84([_b8d0,_b8d1,_b8d4,_b8d9],3-addr)
+    end
+
+    bit[8][-4].inner otbl: [_b8d0,_b8d1,_b8d4,_b8d9]
+
+    par do
+        val2 <= otbl[addr]
+        val3 <= otbl[3-addr]
     end
 
     timed do

data/lib/HDLRuby/hdr_samples/with_define_operator.rb

@@ -0,0 +1,44 @@
+# A sample for testing define operator.
+
+typedef :sat100 do |width|
+    signed[width]
+end
+
+sat100.define_operator(:+) do |width, x,y|
+    tmp = x.as(bit[width]) + y.as(bit[width])
+    mux(tmp > 100,tmp,100)
+end
+
+typedef :sat do |width, max|
+    signed[width]
+end
+
+sat.define_operator(:+) do |width,max, x,y|
+    tmp = x.as(bit[width]) + y.as(bit[width])
+    mux(tmp > max, tmp, max)
+end
+
+
+system :bench_sat do
+    sat100(8).inner :x,:y,:z
+    sat(8,55).inner :u,:v,:w
+
+    timed do
+        x <= 40
+        y <= 32
+        z <= x+y
+        !10.ns
+        u <= 20
+        v <= 24
+        w <= u+v
+        !10.ns
+        x <= 70
+        y <= 32
+        z <= x+y
+        !10.ns
+        u <= 50
+        v <= 24
+        w <= u+v
+        !10.ns
+    end
+end

data/lib/HDLRuby/hdr_samples/with_fixpoint.rb

@@ -14,9 +14,9 @@ system :fix_test do
 
     # Performs calculation between then
     timed do
-        # x <= _00110011 # 3.1875
+        # x <= _b00110011 # 3.1875
         x <= 3.1875.to_fix(4)
-        y <= _01000000 # 4
+        y <= _b01000000 # 4
         !10.ns
         z <= x + y
         !10.ns
@@ -24,8 +24,8 @@ system :fix_test do
         !10.ns
         z <= z / x
         !10.ns
-        a <= _00010000
-        b <= _00001111
+        a <= _b00010000
+        b <= _b00001111
         !10.ns
         c <= a * b
         d <= 0
@@ -49,15 +49,15 @@ system :fix_test do
         !10.ns
         c <= a * b
         !10.ns
-        # a <= _00010000
-        # b <= _00010101
-        a <= _0000111x
-        b <= _1110011x
+        # a <= _b00010000
+        # b <= _b00010101
+        a <= _sb0000111x
+        b <= _sb1110011x
         !10.ns
-        # a <= a & _11111110
-        # b <= b | _00000001
-        a <= a | _00000001
-        b <= b | _00000001
+        # a <= a & _b11111110
+        # b <= b | _b00000001
+        a <= a | _b00000001
+        b <= b | _b00000001
         !10.ns
         c <= a * b
         !10.ns

data/lib/HDLRuby/hdr_samples/with_init.rb

@@ -2,9 +2,9 @@
 # A benchmark for testing the initialization of signals.
 system :with_init do
     [8].constant cst0: 127
-    constant cst1: _1
-    [8].inner sig0: _10000000
-    inner sig1: _1
+    constant cst1: _b1
+    [8].inner sig0: _b10000000
+    inner sig1: _b1
     [8].inner :sig2
 
     timed do