xmos-ai-tools 1.3.2.dev80__py3-none-macosx_10_15_universal2.whl

xmos_ai_tools/runtime/include/lib_nn/api/xs3a_registers.h

@@ -0,0 +1,2869 @@
+/*
+ *
+ * Copyright XMOS - (c) 2007 - 2018
+ *
+ * AUTOGENERATED - DO NOT EDIT
+ * by lib_xmosutils/Scripts/CreateXS1.pl
+ *
+ */
+#ifndef _xs3a_registers_h_
+#define _xs3a_registers_h_
+#define XS1_PS_RAM_BASE 0xb
+#define XS1_PS_VECTOR_BASE 0x10b
+#define XS1_PS_XCORE_CTRL0 0x20b
+#define XS1_PS_BOOT_CONFIG 0x30b
+#define XS1_PS_BOOT_STATUS 0x40b
+#define XS1_PS_SECURITY_CONFIG 0x50b
+#define XS1_PS_RING_OSC_CTRL 0x60b
+#define XS1_PS_RING_OSC_DATA0 0x70b
+#define XS1_PS_RING_OSC_DATA1 0x80b
+#define XS1_PS_RING_OSC_DATA2 0x90b
+#define XS1_PS_RING_OSC_DATA3 0xa0b
+#define XS1_PS_UNAVAILABLE_RESOURCE 0xb0b
+#define XS1_PS_RAM_SIZE 0xc0b
+#define XS1_PS_ROM_RMA 0xf0b
+#define XS1_PS_DBG_SSR 0x100b
+#define XS1_PS_DBG_SPC 0x110b
+#define XS1_PS_DBG_SSP 0x120b
+#define XS1_PS_DBG_T_NUM_NUM 0x13
+#define XS1_PS_DBG_T_NUM 0x130b
+#define XS1_PS_DBG_T_REG 0x140b
+#define XS1_PS_DBG_TYPE 0x150b
+#define XS1_PS_DBG_DATA 0x160b
+#define XS1_PS_DBG_RUN_CTRL 0x180b
+#define XS1_PS_DBG_SCRATCH_0 0x200b
+#define XS1_PS_DBG_SCRATCH_1 0x210b
+#define XS1_PS_DBG_SCRATCH_2 0x220b
+#define XS1_PS_DBG_SCRATCH_3 0x230b
+#define XS1_PS_DBG_SCRATCH_4 0x240b
+#define XS1_PS_DBG_SCRATCH_5 0x250b
+#define XS1_PS_DBG_SCRATCH_6 0x260b
+#define XS1_PS_DBG_SCRATCH_7 0x270b
+#define XS1_PS_DBG_IBREAK_ADDR_0 0x300b
+#define XS1_NUM_PS_DBG_IBREAK_ADDR 0x4
+#define XS1_PS_DBG_IBREAK_ADDR_1 0x310b
+#define XS1_PS_DBG_IBREAK_ADDR_2 0x320b
+#define XS1_PS_DBG_IBREAK_ADDR_3 0x330b
+#define XS1_PS_DBG_IBREAK_CTRL_0 0x400b
+#define XS1_NUM_PS_DBG_IBREAK_CTRL 0x4
+#define XS1_PS_DBG_IBREAK_CTRL_1 0x410b
+#define XS1_PS_DBG_IBREAK_CTRL_2 0x420b
+#define XS1_PS_DBG_IBREAK_CTRL_3 0x430b
+#define XS1_PS_DBG_DWATCH_ADDR1_0 0x500b
+#define XS1_NUM_PS_DBG_DWATCH_ADDR1 0x4
+#define XS1_PS_DBG_DWATCH_ADDR1_1 0x510b
+#define XS1_PS_DBG_DWATCH_ADDR1_2 0x520b
+#define XS1_PS_DBG_DWATCH_ADDR1_3 0x530b
+#define XS1_PS_DBG_DWATCH_ADDR2_0 0x600b
+#define XS1_NUM_PS_DBG_DWATCH_ADDR2 0x4
+#define XS1_PS_DBG_DWATCH_ADDR2_1 0x610b
+#define XS1_PS_DBG_DWATCH_ADDR2_2 0x620b
+#define XS1_PS_DBG_DWATCH_ADDR2_3 0x630b
+#define XS1_PS_DBG_DWATCH_CTRL_0 0x700b
+#define XS1_NUM_PS_DBG_DWATCH_CTRL 0x4
+#define XS1_PS_DBG_DWATCH_CTRL_1 0x710b
+#define XS1_PS_DBG_DWATCH_CTRL_2 0x720b
+#define XS1_PS_DBG_DWATCH_CTRL_3 0x730b
+#define XS1_PS_DBG_RWATCH_ADDR1_0 0x800b
+#define XS1_NUM_PS_DBG_RWATCH_ADDR1 0x4
+#define XS1_PS_DBG_RWATCH_ADDR1_1 0x810b
+#define XS1_PS_DBG_RWATCH_ADDR1_2 0x820b
+#define XS1_PS_DBG_RWATCH_ADDR1_3 0x830b
+#define XS1_PS_DBG_RWATCH_ADDR2_0 0x900b
+#define XS1_NUM_PS_DBG_RWATCH_ADDR2 0x4
+#define XS1_PS_DBG_RWATCH_ADDR2_1 0x910b
+#define XS1_PS_DBG_RWATCH_ADDR2_2 0x920b
+#define XS1_PS_DBG_RWATCH_ADDR2_3 0x930b
+#define XS1_PS_DBG_RWATCH_CTRL_0 0x9c0b
+#define XS1_NUM_PS_DBG_RWATCH_CTRL 0x4
+#define XS1_PS_DBG_RWATCH_CTRL_1 0x9d0b
+#define XS1_PS_DBG_RWATCH_CTRL_2 0x9e0b
+#define XS1_PS_DBG_RWATCH_CTRL_3 0x9f0b
+#define XS1_PS_CACHE_MISS_CNT 0xa00b
+#define XS1_PS_CACHE_ACCESS_CNT 0xa10b
+#define XS1_SSWITCH_DEVICE_ID0_NUM 0x0
+#define XS1_SSWITCH_DEVICE_ID1_NUM 0x1
+#define XS1_SSWITCH_DEVICE_ID2_NUM 0x2
+#define XS1_SSWITCH_DEVICE_ID3_NUM 0x3
+#define XS1_SSWITCH_NODE_CONFIG_NUM 0x4
+#define XS1_SSWITCH_NODE_ID_NUM 0x5
+#define XS1_SSWITCH_PLL_CTL_NUM 0x6
+#define XS1_SSWITCH_CLK_DIVIDER_NUM 0x7
+#define XS1_SSWITCH_REF_CLK_DIVIDER_NUM 0x8
+#define XS1_SSWITCH_JTAG_DEVICE_ID_NUM 0x9
+#define XS1_SSWITCH_JTAG_USERCODE_NUM 0xa
+#define XS1_SSWITCH_DDR_CLK_DIVIDER_NUM 0xb
+#define XS1_SSWITCH_DIMENSION_DIRECTION0_NUM 0xc
+#define XS1_SSWITCH_DIMENSION_DIRECTION1_NUM 0xd
+#define XS1_SSWITCH_SS_APP_CLK_DIVIDER_NUM 0xe
+#define XS1_SSWITCH_SS_APP_PLL_CTL_NUM 0xf
+#define XS1_SSWITCH_XCORE0_GLOBAL_DEBUG_CONFIG_NUM 0x10
+#define XS1_SSWITCH_XCORE1_GLOBAL_DEBUG_CONFIG_NUM 0x11
+#define XS1_SSWITCH_SS_APP_PLL_FRAC_N_DIVIDER_NUM 0x12
+#define XS1_SSWITCH_MIPI_CLK_DIVIDER_NUM 0x14
+#define XS1_SSWITCH_MIPI_CFG_CLK_DIVIDER_NUM 0x15
+#define XS1_SSWITCH_GLOBAL_DEBUG_SOURCE_NUM 0x1f
+#define XS1_SSWITCH_SLINK_0_NUM 0x20
+#define XS1_NUM_SSWITCH_SLINK 0x9
+#define XS1_SSWITCH_SLINK_1_NUM 0x21
+#define XS1_SSWITCH_SLINK_2_NUM 0x22
+#define XS1_SSWITCH_SLINK_3_NUM 0x23
+#define XS1_SSWITCH_SLINK_4_NUM 0x24
+#define XS1_SSWITCH_SLINK_5_NUM 0x25
+#define XS1_SSWITCH_SLINK_6_NUM 0x26
+#define XS1_SSWITCH_SLINK_7_NUM 0x27
+#define XS1_SSWITCH_SLINK_8_NUM 0x28
+#define XS1_SSWITCH_PLINK_0_NUM 0x40
+#define XS1_NUM_SSWITCH_PLINK 0x8
+#define XS1_SSWITCH_PLINK_1_NUM 0x41
+#define XS1_SSWITCH_PLINK_2_NUM 0x42
+#define XS1_SSWITCH_PLINK_3_NUM 0x43
+#define XS1_SSWITCH_PLINK_4_NUM 0x44
+#define XS1_SSWITCH_PLINK_5_NUM 0x45
+#define XS1_SSWITCH_PLINK_6_NUM 0x46
+#define XS1_SSWITCH_PLINK_7_NUM 0x47
+#define XS1_SSWITCH_XLINK_0_NUM 0x80
+#define XS1_NUM_SSWITCH_XLINK 0x9
+#define XS1_SSWITCH_XLINK_1_NUM 0x81
+#define XS1_SSWITCH_XLINK_2_NUM 0x82
+#define XS1_SSWITCH_XLINK_3_NUM 0x83
+#define XS1_SSWITCH_XLINK_4_NUM 0x84
+#define XS1_SSWITCH_XLINK_5_NUM 0x85
+#define XS1_SSWITCH_XLINK_6_NUM 0x86
+#define XS1_SSWITCH_XLINK_7_NUM 0x87
+#define XS1_SSWITCH_XLINK_8_NUM 0x88
+#define XS1_SSWITCH_XSTATIC_0_NUM 0xa0
+#define XS1_NUM_SSWITCH_XSTATIC 0x8
+#define XS1_SSWITCH_XSTATIC_1_NUM 0xa1
+#define XS1_SSWITCH_XSTATIC_2_NUM 0xa2
+#define XS1_SSWITCH_XSTATIC_3_NUM 0xa3
+#define XS1_SSWITCH_XSTATIC_4_NUM 0xa4
+#define XS1_SSWITCH_XSTATIC_5_NUM 0xa5
+#define XS1_SSWITCH_XSTATIC_6_NUM 0xa6
+#define XS1_SSWITCH_XSTATIC_7_NUM 0xa7
+#define XS1_SSWITCH_USB_XCFGI_REG0_NUM 0xf000
+#define XS1_SSWITCH_USB_XCFGI_REG1_NUM 0xf001
+#define XS1_SSWITCH_USB_XCFGI_REG2_NUM 0xf002
+#define XS1_SSWITCH_USB_XCFG_COARSE_TUNE_NUM 0xf003
+#define XS1_SSWITCH_USB_XCFG_FINE_TUNE_NUM 0xf004
+#define XS1_SSWITCH_USB_XCFG_LOCK_RANGE_MAX_NUM 0xf005
+#define XS1_SSWITCH_USB_XCFG_LOCK_RANGE_MIN_NUM 0xf006
+#define XS1_SSWITCH_USB_PHY_CFG0_NUM 0xf008
+#define XS1_SSWITCH_USB_PHY_CFG1_NUM 0xf009
+#define XS1_SSWITCH_USB_PHY_CFG2_NUM 0xf00a
+#define XS1_SSWITCH_USB_PHY_CFG3_NUM 0xf00b
+#define XS1_SSWITCH_USB_SHIM_CFG_NUM 0xf00c
+#define XS1_SSWITCH_USB_PHY_XCFGO_REG0_NUM 0xf010
+#define XS1_SSWITCH_USB_PHY_STATUS_NUM 0xf011
+#define XS1_SSWITCH_WATCHDOG_CFG_NUM 0xf020
+#define XS1_SSWITCH_WATCHDOG_PRESCALER_NUM 0xf021
+#define XS1_SSWITCH_WATCHDOG_PRESCALER_WRAP_NUM 0xf022
+#define XS1_SSWITCH_WATCHDOG_COUNT_NUM 0xf023
+#define XS1_SSWITCH_WATCHDOG_STATUS_NUM 0xf024
+#define XS1_SSWITCH_MIPI_XCFGI_REG0_NUM 0xe000
+#define XS1_SSWITCH_MIPI_XCFGI_REG1_NUM 0xe001
+#define XS1_SSWITCH_MIPI_XCFGI_REG2_NUM 0xe002
+#define XS1_SSWITCH_MIPI_XCFGI_REG3_NUM 0xe003
+#define XS1_SSWITCH_MIPI_XCFGI_REG4_NUM 0xe004
+#define XS1_SSWITCH_MIPI_XCFGI_REG5_NUM 0xe005
+#define XS1_SSWITCH_MIPI_XCFGI_REG6_NUM 0xe006
+#define XS1_SSWITCH_MIPI_XCFGI_REG7_NUM 0xe007
+#define XS1_SSWITCH_MIPI_XCFGI_REG8_NUM 0xe008
+#define XS1_SSWITCH_MIPI_XCFGI_REG9_NUM 0xe009
+#define XS1_SSWITCH_MIPI_XCFGI_REG10_NUM 0xe00a
+#define XS1_SSWITCH_MIPI_XCFGI_REG11_NUM 0xe00b
+#define XS1_SSWITCH_MIPI_XCFGI_REG12_NUM 0xe00c
+#define XS1_SSWITCH_MIPI_XCFGI_REG13_NUM 0xe00d
+#define XS1_SSWITCH_MIPI_XCFGI_REG14_NUM 0xe00e
+#define XS1_SSWITCH_MIPI_XCFGI_REG15_NUM 0xe00f
+#define XS1_SSWITCH_MIPI_XCFGI_REG16_NUM 0xe010
+#define XS1_SSWITCH_MIPI_XCFGI_REG17_NUM 0xe011
+#define XS1_SSWITCH_MIPI_XCFGI_REG18_NUM 0xe012
+#define XS1_SSWITCH_MIPI_STATUS0_NUM 0xe013
+#define XS1_SSWITCH_MIPI_SHIM_STATUS_NUM 0xe014
+#define XS1_SSWITCH_MIPI_DPHY_CFG0_NUM 0xe018
+#define XS1_SSWITCH_MIPI_DPHY_CFG1_NUM 0xe019
+#define XS1_SSWITCH_MIPI_DPHY_CFG2_NUM 0xe01a
+#define XS1_SSWITCH_MIPI_DPHY_CFG3_NUM 0xe01b
+#define XS1_SSWITCH_MIPI_DPHY_CFG4_NUM 0xe01c
+#define XS1_SSWITCH_MIPI_DPHY_CFG5_NUM 0xe01d
+#define XS1_SSWITCH_MIPI_SHIM_CFG0_NUM 0xe01f
+#define XS1_SSWITCH_MIPI_XCFGO_REG0_NUM 0xe020
+#define XS1_SSWITCH_MIPI_XCFGO_REG1_NUM 0xe021
+#define XS1_SSWITCH_MIPI_XCFGO_REG2_NUM 0xe022
+#define XS1_SSWITCH_LPDDR_IID_ENABLE_NUM 0xc000
+#define XS1_SSWITCH_LPDDR_IID_0_7_NUM 0xc001
+#define XS1_SSWITCH_LPDDR_IID_8_15_NUM 0xc002
+#define XS1_SSWITCH_LPDDR_QUEUE_CONT_NUM 0xc003
+#define XS1_SSWITCH_LPDDR_RO_COMMAND_QUEUE_PRIORITY_NUM 0xc008
+#define XS1_SSWITCH_LPDDR_RW_COMMAND_QUEUE_PRIORITY_NUM 0xc009
+#define XS1_SSWITCH_LPDDR_ARBITRATION_TIMEOUT_NUM 0xc00a
+#define XS1_SSWITCH_LPDDR_ARBITRATION_MTG_COMMAND_NUM 0xc010
+#define XS1_SSWITCH_LPDDR_DLL_CONTROL_NUM 0xc014
+#define XS1_SSWITCH_LPDDR_DLL_MEASUREMENT_STATUS_NUM 0xc015
+#define XS1_SSWITCH_LPDDR_DLL_MANUAL_CONTROL_NUM 0xc016
+#define XS1_SSWITCH_LPDDR_DLL_PHY_CALIBRATION_DATA_NUM 0xc017
+#define XS1_SSWITCH_LPDDR_PHY_CONTROL_NUM 0xc01d
+#define XS1_SSWITCH_LPDDR_LMR_OPCODE_NUM 0xc01e
+#define XS1_SSWITCH_LPDDR_EMR_OPCODE_NUM 0xc01f
+#define XS1_SSWITCH_LPDDR_PROTOCOL_ENGINE_CONF_0_NUM 0xc020
+#define XS1_SSWITCH_LPDDR_PROTOCOL_ENGINE_CONF_1_NUM 0xc021
+#define XS1_SSWITCH_LPDDR_PROTOCOL_ENGINE_STATUS_NUM 0xc022
+#define XS1_SSWITCH_PADCTRL_CLK_NUM 0xd000
+#define XS1_SSWITCH_PADCTRL_CKE_NUM 0xd001
+#define XS1_SSWITCH_PADCTRL_CS_N_NUM 0xd002
+#define XS1_SSWITCH_PADCTRL_WE_N_NUM 0xd003
+#define XS1_SSWITCH_PADCTRL_CAS_N_NUM 0xd004
+#define XS1_SSWITCH_PADCTRL_RAS_N_NUM 0xd005
+#define XS1_SSWITCH_PADCTRL_ADDR_NUM 0xd006
+#define XS1_SSWITCH_PADCTRL_BA_NUM 0xd007
+#define XS1_SSWITCH_PADCTRL_DQ_NUM 0xd008
+#define XS1_SSWITCH_PADCTRL_DQS_NUM 0xd009
+#define XS1_SSWITCH_PADCTRL_DM_NUM 0xd00a
+#define XS1_PSWITCH_DEVICE_ID0_NUM 0x0
+#define XS1_PSWITCH_DEVICE_ID1_NUM 0x1
+#define XS1_PSWITCH_DEVICE_ID2_NUM 0x2
+#define XS1_PSWITCH_DEVICE_ID3_NUM 0x3
+#define XS1_PSWITCH_DBG_CTRL_NUM 0x4
+#define XS1_PSWITCH_DBG_INT_NUM 0x5
+#define XS1_PSWITCH_PLL_CLK_DIVIDER_NUM 0x6
+#define XS1_PSWITCH_SECU_CONFIG_NUM 0x7
+#define XS1_PSWITCH_DBG_SCRATCH_0_NUM 0x20
+#define XS1_NUM_PSWITCH_DBG_SCRATCH 0x8
+#define XS1_PSWITCH_DBG_SCRATCH_1_NUM 0x21
+#define XS1_PSWITCH_DBG_SCRATCH_2_NUM 0x22
+#define XS1_PSWITCH_DBG_SCRATCH_3_NUM 0x23
+#define XS1_PSWITCH_DBG_SCRATCH_4_NUM 0x24
+#define XS1_PSWITCH_DBG_SCRATCH_5_NUM 0x25
+#define XS1_PSWITCH_DBG_SCRATCH_6_NUM 0x26
+#define XS1_PSWITCH_DBG_SCRATCH_7_NUM 0x27
+#define XS1_PSWITCH_T0_PC_NUM 0x40
+#define XS1_PSWITCH_T1_PC_NUM 0x41
+#define XS1_PSWITCH_T2_PC_NUM 0x42
+#define XS1_PSWITCH_T3_PC_NUM 0x43
+#define XS1_PSWITCH_T4_PC_NUM 0x44
+#define XS1_PSWITCH_T5_PC_NUM 0x45
+#define XS1_PSWITCH_T6_PC_NUM 0x46
+#define XS1_PSWITCH_T7_PC_NUM 0x47
+#define XS1_PSWITCH_T0_SR_NUM 0x60
+#define XS1_PSWITCH_T1_SR_NUM 0x61
+#define XS1_PSWITCH_T2_SR_NUM 0x62
+#define XS1_PSWITCH_T3_SR_NUM 0x63
+#define XS1_PSWITCH_T4_SR_NUM 0x64
+#define XS1_PSWITCH_T5_SR_NUM 0x65
+#define XS1_PSWITCH_T6_SR_NUM 0x66
+#define XS1_PSWITCH_T7_SR_NUM 0x67
+#define XS1_ID_ID_SHIFT 0x0
+#define XS1_ID_ID_SIZE 0x6
+#define XS1_ID_ID_MASK (((1 << XS1_ID_ID_SIZE) - 1) << XS1_ID_ID_SHIFT)
+#define XS1_ID_ID(x) (((x)&XS1_ID_ID_MASK) >> XS1_ID_ID_SHIFT)
+#define XS1_ID_ID_SET(x, v) \
+  (((x) & ~XS1_ID_ID_MASK) | (((v) << XS1_ID_ID_SHIFT) & XS1_ID_ID_MASK))
+#define XS1_EXCEPTION_TYPE_SHIFT 0x0
+#define XS1_EXCEPTION_TYPE_SIZE 0x5
+#define XS1_EXCEPTION_TYPE_MASK \
+  (((1 << XS1_EXCEPTION_TYPE_SIZE) - 1) << XS1_EXCEPTION_TYPE_SHIFT)
+#define XS1_EXCEPTION_TYPE(x) \
+  (((x)&XS1_EXCEPTION_TYPE_MASK) >> XS1_EXCEPTION_TYPE_SHIFT)
+#define XS1_EXCEPTION_TYPE_SET(x, v)  \
+  (((x) & ~XS1_EXCEPTION_TYPE_MASK) | \
+   (((v) << XS1_EXCEPTION_TYPE_SHIFT) & XS1_EXCEPTION_TYPE_MASK))
+#define XS1_DBG_T_NUM_NUM_SHIFT 0x0
+#define XS1_DBG_T_NUM_NUM_SIZE 0x8
+#define XS1_DBG_T_NUM_NUM_MASK \
+  (((1 << XS1_DBG_T_NUM_NUM_SIZE) - 1) << XS1_DBG_T_NUM_NUM_SHIFT)
+#define XS1_DBG_T_NUM_NUM(x) \
+  (((x)&XS1_DBG_T_NUM_NUM_MASK) >> XS1_DBG_T_NUM_NUM_SHIFT)
+#define XS1_DBG_T_NUM_NUM_SET(x, v)  \
+  (((x) & ~XS1_DBG_T_NUM_NUM_MASK) | \
+   (((v) << XS1_DBG_T_NUM_NUM_SHIFT) & XS1_DBG_T_NUM_NUM_MASK))
+#define XS1_DBG_T_REG_REG_SHIFT 0x0
+#define XS1_DBG_T_REG_REG_SIZE 0x5
+#define XS1_DBG_T_REG_REG_MASK \
+  (((1 << XS1_DBG_T_REG_REG_SIZE) - 1) << XS1_DBG_T_REG_REG_SHIFT)
+#define XS1_DBG_T_REG_REG(x) \
+  (((x)&XS1_DBG_T_REG_REG_MASK) >> XS1_DBG_T_REG_REG_SHIFT)
+#define XS1_DBG_T_REG_REG_SET(x, v)  \
+  (((x) & ~XS1_DBG_T_REG_REG_MASK) | \
+   (((v) << XS1_DBG_T_REG_REG_SHIFT) & XS1_DBG_T_REG_REG_MASK))
+#define XS1_BRK_ENABLE_SHIFT 0x0
+#define XS1_BRK_ENABLE_SIZE 0x1
+#define XS1_BRK_ENABLE_MASK \
+  (((1 << XS1_BRK_ENABLE_SIZE) - 1) << XS1_BRK_ENABLE_SHIFT)
+#define XS1_BRK_ENABLE(x) (((x)&XS1_BRK_ENABLE_MASK) >> XS1_BRK_ENABLE_SHIFT)
+#define XS1_BRK_ENABLE_SET(x, v)  \
+  (((x) & ~XS1_BRK_ENABLE_MASK) | \
+   (((v) << XS1_BRK_ENABLE_SHIFT) & XS1_BRK_ENABLE_MASK))
+#define XS1_ALL_BITS_SHIFT 0x0
+#define XS1_ALL_BITS_SIZE 0x20
+#define XS1_ALL_BITS_MASK (((1 << XS1_ALL_BITS_SIZE) - 1) << XS1_ALL_BITS_SHIFT)
+#define XS1_ALL_BITS(x) (((x)&XS1_ALL_BITS_MASK) >> XS1_ALL_BITS_SHIFT)
+#define XS1_ALL_BITS_SET(x, v)  \
+  (((x) & ~XS1_ALL_BITS_MASK) | \
+   (((v) << XS1_ALL_BITS_SHIFT) & XS1_ALL_BITS_MASK))
+#define XS1_KEP_ADDRESS_BITS_SHIFT 0x7
+#define XS1_KEP_ADDRESS_BITS_SIZE 0x19
+#define XS1_KEP_ADDRESS_BITS_MASK \
+  (((1 << XS1_KEP_ADDRESS_BITS_SIZE) - 1) << XS1_KEP_ADDRESS_BITS_SHIFT)
+#define XS1_KEP_ADDRESS_BITS(x) \
+  (((x)&XS1_KEP_ADDRESS_BITS_MASK) >> XS1_KEP_ADDRESS_BITS_SHIFT)
+#define XS1_KEP_ADDRESS_BITS_SET(x, v)  \
+  (((x) & ~XS1_KEP_ADDRESS_BITS_MASK) | \
+   (((v) << XS1_KEP_ADDRESS_BITS_SHIFT) & XS1_KEP_ADDRESS_BITS_MASK))
+#define XS1_WORD_ADDRESS_BITS_SHIFT 0x2
+#define XS1_WORD_ADDRESS_BITS_SIZE 0x1e
+#define XS1_WORD_ADDRESS_BITS_MASK \
+  (((1 << XS1_WORD_ADDRESS_BITS_SIZE) - 1) << XS1_WORD_ADDRESS_BITS_SHIFT)
+#define XS1_WORD_ADDRESS_BITS(x) \
+  (((x)&XS1_WORD_ADDRESS_BITS_MASK) >> XS1_WORD_ADDRESS_BITS_SHIFT)
+#define XS1_WORD_ADDRESS_BITS_SET(x, v)  \
+  (((x) & ~XS1_WORD_ADDRESS_BITS_MASK) | \
+   (((v) << XS1_WORD_ADDRESS_BITS_SHIFT) & XS1_WORD_ADDRESS_BITS_MASK))
+#define XS1_VECTOR_BASE_SHIFT 0x13
+#define XS1_VECTOR_BASE_SIZE 0xd
+#define XS1_VECTOR_BASE_MASK \
+  (((1 << XS1_VECTOR_BASE_SIZE) - 1) << XS1_VECTOR_BASE_SHIFT)
+#define XS1_VECTOR_BASE(x) (((x)&XS1_VECTOR_BASE_MASK) >> XS1_VECTOR_BASE_SHIFT)
+#define XS1_VECTOR_BASE_SET(x, v)  \
+  (((x) & ~XS1_VECTOR_BASE_MASK) | \
+   (((v) << XS1_VECTOR_BASE_SHIFT) & XS1_VECTOR_BASE_MASK))
+#define XS1_IBRK_CONDITION_SHIFT 0x1
+#define XS1_IBRK_CONDITION_SIZE 0x1
+#define XS1_IBRK_CONDITION_MASK \
+  (((1 << XS1_IBRK_CONDITION_SIZE) - 1) << XS1_IBRK_CONDITION_SHIFT)
+#define XS1_IBRK_CONDITION(x) \
+  (((x)&XS1_IBRK_CONDITION_MASK) >> XS1_IBRK_CONDITION_SHIFT)
+#define XS1_IBRK_CONDITION_SET(x, v)  \
+  (((x) & ~XS1_IBRK_CONDITION_MASK) | \
+   (((v) << XS1_IBRK_CONDITION_SHIFT) & XS1_IBRK_CONDITION_MASK))
+#define XS1_DBRK_CONDITION_SHIFT 0x1
+#define XS1_DBRK_CONDITION_SIZE 0x1
+#define XS1_DBRK_CONDITION_MASK \
+  (((1 << XS1_DBRK_CONDITION_SIZE) - 1) << XS1_DBRK_CONDITION_SHIFT)
+#define XS1_DBRK_CONDITION(x) \
+  (((x)&XS1_DBRK_CONDITION_MASK) >> XS1_DBRK_CONDITION_SHIFT)
+#define XS1_DBRK_CONDITION_SET(x, v)  \
+  (((x) & ~XS1_DBRK_CONDITION_MASK) | \
+   (((v) << XS1_DBRK_CONDITION_SHIFT) & XS1_DBRK_CONDITION_MASK))
+#define XS1_RBRK_CONDITION_SHIFT 0x1
+#define XS1_RBRK_CONDITION_SIZE 0x1
+#define XS1_RBRK_CONDITION_MASK \
+  (((1 << XS1_RBRK_CONDITION_SIZE) - 1) << XS1_RBRK_CONDITION_SHIFT)
+#define XS1_RBRK_CONDITION(x) \
+  (((x)&XS1_RBRK_CONDITION_MASK) >> XS1_RBRK_CONDITION_SHIFT)
+#define XS1_RBRK_CONDITION_SET(x, v)  \
+  (((x) & ~XS1_RBRK_CONDITION_MASK) | \
+   (((v) << XS1_RBRK_CONDITION_SHIFT) & XS1_RBRK_CONDITION_MASK))
+#define XS1_BRK_LOAD_SHIFT 0x2
+#define XS1_BRK_LOAD_SIZE 0x1
+#define XS1_BRK_LOAD_MASK (((1 << XS1_BRK_LOAD_SIZE) - 1) << XS1_BRK_LOAD_SHIFT)
+#define XS1_BRK_LOAD(x) (((x)&XS1_BRK_LOAD_MASK) >> XS1_BRK_LOAD_SHIFT)
+#define XS1_BRK_LOAD_SET(x, v)  \
+  (((x) & ~XS1_BRK_LOAD_MASK) | \
+   (((v) << XS1_BRK_LOAD_SHIFT) & XS1_BRK_LOAD_MASK))
+#define XS1_BRK_THREADS_SHIFT 0x10
+#define XS1_BRK_THREADS_SIZE 0x8
+#define XS1_BRK_THREADS_MASK \
+  (((1 << XS1_BRK_THREADS_SIZE) - 1) << XS1_BRK_THREADS_SHIFT)
+#define XS1_BRK_THREADS(x) (((x)&XS1_BRK_THREADS_MASK) >> XS1_BRK_THREADS_SHIFT)
+#define XS1_BRK_THREADS_SET(x, v)  \
+  (((x) & ~XS1_BRK_THREADS_MASK) | \
+   (((v) << XS1_BRK_THREADS_SHIFT) & XS1_BRK_THREADS_MASK))
+#define XS1_DBG_TYPE_CAUSE_SHIFT 0x0
+#define XS1_DBG_TYPE_CAUSE_SIZE 0x3
+#define XS1_DBG_TYPE_CAUSE_MASK \
+  (((1 << XS1_DBG_TYPE_CAUSE_SIZE) - 1) << XS1_DBG_TYPE_CAUSE_SHIFT)
+#define XS1_DBG_TYPE_CAUSE(x) \
+  (((x)&XS1_DBG_TYPE_CAUSE_MASK) >> XS1_DBG_TYPE_CAUSE_SHIFT)
+#define XS1_DBG_TYPE_CAUSE_SET(x, v)  \
+  (((x) & ~XS1_DBG_TYPE_CAUSE_MASK) | \
+   (((v) << XS1_DBG_TYPE_CAUSE_SHIFT) & XS1_DBG_TYPE_CAUSE_MASK))
+#define XS1_DBG_TYPE_T_NUM_SHIFT 0x8
+#define XS1_DBG_TYPE_T_NUM_SIZE 0x8
+#define XS1_DBG_TYPE_T_NUM_MASK \
+  (((1 << XS1_DBG_TYPE_T_NUM_SIZE) - 1) << XS1_DBG_TYPE_T_NUM_SHIFT)
+#define XS1_DBG_TYPE_T_NUM(x) \
+  (((x)&XS1_DBG_TYPE_T_NUM_MASK) >> XS1_DBG_TYPE_T_NUM_SHIFT)
+#define XS1_DBG_TYPE_T_NUM_SET(x, v)  \
+  (((x) & ~XS1_DBG_TYPE_T_NUM_MASK) | \
+   (((v) << XS1_DBG_TYPE_T_NUM_SHIFT) & XS1_DBG_TYPE_T_NUM_MASK))
+#define XS1_DBG_TYPE_HW_NUM_SHIFT 0x10
+#define XS1_DBG_TYPE_HW_NUM_SIZE 0x2
+#define XS1_DBG_TYPE_HW_NUM_MASK \
+  (((1 << XS1_DBG_TYPE_HW_NUM_SIZE) - 1) << XS1_DBG_TYPE_HW_NUM_SHIFT)
+#define XS1_DBG_TYPE_HW_NUM(x) \
+  (((x)&XS1_DBG_TYPE_HW_NUM_MASK) >> XS1_DBG_TYPE_HW_NUM_SHIFT)
+#define XS1_DBG_TYPE_HW_NUM_SET(x, v)  \
+  (((x) & ~XS1_DBG_TYPE_HW_NUM_MASK) | \
+   (((v) << XS1_DBG_TYPE_HW_NUM_SHIFT) & XS1_DBG_TYPE_HW_NUM_MASK))
+#define XS1_DBG_RUN_CTRL_STOP_SHIFT 0x0
+#define XS1_DBG_RUN_CTRL_STOP_SIZE 0x8
+#define XS1_DBG_RUN_CTRL_STOP_MASK \
+  (((1 << XS1_DBG_RUN_CTRL_STOP_SIZE) - 1) << XS1_DBG_RUN_CTRL_STOP_SHIFT)
+#define XS1_DBG_RUN_CTRL_STOP(x) \
+  (((x)&XS1_DBG_RUN_CTRL_STOP_MASK) >> XS1_DBG_RUN_CTRL_STOP_SHIFT)
+#define XS1_DBG_RUN_CTRL_STOP_SET(x, v)  \
+  (((x) & ~XS1_DBG_RUN_CTRL_STOP_MASK) | \
+   (((v) << XS1_DBG_RUN_CTRL_STOP_SHIFT) & XS1_DBG_RUN_CTRL_STOP_MASK))
+#define XS1_XCORE_CTRL0_USB_ENABLE_SHIFT 0x1
+#define XS1_XCORE_CTRL0_USB_ENABLE_SIZE 0x1
+#define XS1_XCORE_CTRL0_USB_ENABLE_MASK         \
+  (((1 << XS1_XCORE_CTRL0_USB_ENABLE_SIZE) - 1) \
+   << XS1_XCORE_CTRL0_USB_ENABLE_SHIFT)
+#define XS1_XCORE_CTRL0_USB_ENABLE(x) \
+  (((x)&XS1_XCORE_CTRL0_USB_ENABLE_MASK) >> XS1_XCORE_CTRL0_USB_ENABLE_SHIFT)
+#define XS1_XCORE_CTRL0_USB_ENABLE_SET(x, v)    \
+  (((x) & ~XS1_XCORE_CTRL0_USB_ENABLE_MASK) |   \
+   (((v) << XS1_XCORE_CTRL0_USB_ENABLE_SHIFT) & \
+    XS1_XCORE_CTRL0_USB_ENABLE_MASK))
+#define XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SHIFT 0x4
+#define XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SIZE 0x1
+#define XS1_XCORE_CTRL0_CLK_DIVIDER_EN_MASK         \
+  (((1 << XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SIZE) - 1) \
+   << XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SHIFT)
+#define XS1_XCORE_CTRL0_CLK_DIVIDER_EN(x)       \
+  (((x)&XS1_XCORE_CTRL0_CLK_DIVIDER_EN_MASK) >> \
+   XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SHIFT)
+#define XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SET(x, v)    \
+  (((x) & ~XS1_XCORE_CTRL0_CLK_DIVIDER_EN_MASK) |   \
+   (((v) << XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SHIFT) & \
+    XS1_XCORE_CTRL0_CLK_DIVIDER_EN_MASK))
+#define XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SHIFT 0x5
+#define XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SIZE 0x1
+#define XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_MASK         \
+  (((1 << XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SIZE) - 1) \
+   << XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SHIFT)
+#define XS1_XCORE_CTRL0_CLK_DIVIDER_DYN(x)       \
+  (((x)&XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_MASK) >> \
+   XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SHIFT)
+#define XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SET(x, v)    \
+  (((x) & ~XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_MASK) |   \
+   (((v) << XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SHIFT) & \
+    XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_MASK))
+#define XS1_BOOT_CONFIG_SECURE_BOOT_SHIFT 0x8
+#define XS1_BOOT_CONFIG_SECURE_BOOT_SIZE 0x1
+#define XS1_BOOT_CONFIG_SECURE_BOOT_MASK         \
+  (((1 << XS1_BOOT_CONFIG_SECURE_BOOT_SIZE) - 1) \
+   << XS1_BOOT_CONFIG_SECURE_BOOT_SHIFT)
+#define XS1_BOOT_CONFIG_SECURE_BOOT(x) \
+  (((x)&XS1_BOOT_CONFIG_SECURE_BOOT_MASK) >> XS1_BOOT_CONFIG_SECURE_BOOT_SHIFT)
+#define XS1_BOOT_CONFIG_SECURE_BOOT_SET(x, v)    \
+  (((x) & ~XS1_BOOT_CONFIG_SECURE_BOOT_MASK) |   \
+   (((v) << XS1_BOOT_CONFIG_SECURE_BOOT_SHIFT) & \
+    XS1_BOOT_CONFIG_SECURE_BOOT_MASK))
+#define XS1_BOOT_CONFIG_PROCESSOR_SHIFT 0x10
+#define XS1_BOOT_CONFIG_PROCESSOR_SIZE 0x8
+#define XS1_BOOT_CONFIG_PROCESSOR_MASK         \
+  (((1 << XS1_BOOT_CONFIG_PROCESSOR_SIZE) - 1) \
+   << XS1_BOOT_CONFIG_PROCESSOR_SHIFT)
+#define XS1_BOOT_CONFIG_PROCESSOR(x) \
+  (((x)&XS1_BOOT_CONFIG_PROCESSOR_MASK) >> XS1_BOOT_CONFIG_PROCESSOR_SHIFT)
+#define XS1_BOOT_CONFIG_PROCESSOR_SET(x, v)    \
+  (((x) & ~XS1_BOOT_CONFIG_PROCESSOR_MASK) |   \
+   (((v) << XS1_BOOT_CONFIG_PROCESSOR_SHIFT) & \
+    XS1_BOOT_CONFIG_PROCESSOR_MASK))
+#define XS1_BOOT_STATUS_LEDS_SHIFT 0x0
+#define XS1_BOOT_STATUS_LEDS_SIZE 0x4
+#define XS1_BOOT_STATUS_LEDS_MASK \
+  (((1 << XS1_BOOT_STATUS_LEDS_SIZE) - 1) << XS1_BOOT_STATUS_LEDS_SHIFT)
+#define XS1_BOOT_STATUS_LEDS(x) \
+  (((x)&XS1_BOOT_STATUS_LEDS_MASK) >> XS1_BOOT_STATUS_LEDS_SHIFT)
+#define XS1_BOOT_STATUS_LEDS_SET(x, v)  \
+  (((x) & ~XS1_BOOT_STATUS_LEDS_MASK) | \
+   (((v) << XS1_BOOT_STATUS_LEDS_SHIFT) & XS1_BOOT_STATUS_LEDS_MASK))
+#define XS1_BOOT_STATUS_BITS_SHIFT 0x4
+#define XS1_BOOT_STATUS_BITS_SIZE 0x1c
+#define XS1_BOOT_STATUS_BITS_MASK \
+  (((1 << XS1_BOOT_STATUS_BITS_SIZE) - 1) << XS1_BOOT_STATUS_BITS_SHIFT)
+#define XS1_BOOT_STATUS_BITS(x) \
+  (((x)&XS1_BOOT_STATUS_BITS_MASK) >> XS1_BOOT_STATUS_BITS_SHIFT)
+#define XS1_BOOT_STATUS_BITS_SET(x, v)  \
+  (((x) & ~XS1_BOOT_STATUS_BITS_MASK) | \
+   (((v) << XS1_BOOT_STATUS_BITS_SHIFT) & XS1_BOOT_STATUS_BITS_MASK))
+#define XS1_RING_OSC_PERPH_ENABLE_SHIFT 0x0
+#define XS1_RING_OSC_PERPH_ENABLE_SIZE 0x1
+#define XS1_RING_OSC_PERPH_ENABLE_MASK         \
+  (((1 << XS1_RING_OSC_PERPH_ENABLE_SIZE) - 1) \
+   << XS1_RING_OSC_PERPH_ENABLE_SHIFT)
+#define XS1_RING_OSC_PERPH_ENABLE(x) \
+  (((x)&XS1_RING_OSC_PERPH_ENABLE_MASK) >> XS1_RING_OSC_PERPH_ENABLE_SHIFT)
+#define XS1_RING_OSC_PERPH_ENABLE_SET(x, v)    \
+  (((x) & ~XS1_RING_OSC_PERPH_ENABLE_MASK) |   \
+   (((v) << XS1_RING_OSC_PERPH_ENABLE_SHIFT) & \
+    XS1_RING_OSC_PERPH_ENABLE_MASK))
+#define XS1_RING_OSC_CORE_ENABLE_SHIFT 0x1
+#define XS1_RING_OSC_CORE_ENABLE_SIZE 0x1
+#define XS1_RING_OSC_CORE_ENABLE_MASK \
+  (((1 << XS1_RING_OSC_CORE_ENABLE_SIZE) - 1) << XS1_RING_OSC_CORE_ENABLE_SHIFT)
+#define XS1_RING_OSC_CORE_ENABLE(x) \
+  (((x)&XS1_RING_OSC_CORE_ENABLE_MASK) >> XS1_RING_OSC_CORE_ENABLE_SHIFT)
+#define XS1_RING_OSC_CORE_ENABLE_SET(x, v)  \
+  (((x) & ~XS1_RING_OSC_CORE_ENABLE_MASK) | \
+   (((v) << XS1_RING_OSC_CORE_ENABLE_SHIFT) & XS1_RING_OSC_CORE_ENABLE_MASK))
+#define XS1_RING_OSC_DATA_SHIFT 0x0
+#define XS1_RING_OSC_DATA_SIZE 0x10
+#define XS1_RING_OSC_DATA_MASK \
+  (((1 << XS1_RING_OSC_DATA_SIZE) - 1) << XS1_RING_OSC_DATA_SHIFT)
+#define XS1_RING_OSC_DATA(x) \
+  (((x)&XS1_RING_OSC_DATA_MASK) >> XS1_RING_OSC_DATA_SHIFT)
+#define XS1_RING_OSC_DATA_SET(x, v)  \
+  (((x) & ~XS1_RING_OSC_DATA_MASK) | \
+   (((v) << XS1_RING_OSC_DATA_SHIFT) & XS1_RING_OSC_DATA_MASK))
+#define XS1_PLL_CLK_DIVIDER_SHIFT 0x0
+#define XS1_PLL_CLK_DIVIDER_SIZE 0x10
+#define XS1_PLL_CLK_DIVIDER_MASK \
+  (((1 << XS1_PLL_CLK_DIVIDER_SIZE) - 1) << XS1_PLL_CLK_DIVIDER_SHIFT)
+#define XS1_PLL_CLK_DIVIDER(x) \
+  (((x)&XS1_PLL_CLK_DIVIDER_MASK) >> XS1_PLL_CLK_DIVIDER_SHIFT)
+#define XS1_PLL_CLK_DIVIDER_SET(x, v)  \
+  (((x) & ~XS1_PLL_CLK_DIVIDER_MASK) | \
+   (((v) << XS1_PLL_CLK_DIVIDER_SHIFT) & XS1_PLL_CLK_DIVIDER_MASK))
+#define XS1_PLL_CLK_DISABLE_SHIFT 0x1f
+#define XS1_PLL_CLK_DISABLE_SIZE 0x1
+#define XS1_PLL_CLK_DISABLE_MASK \
+  (((1 << XS1_PLL_CLK_DISABLE_SIZE) - 1) << XS1_PLL_CLK_DISABLE_SHIFT)
+#define XS1_PLL_CLK_DISABLE(x) \
+  (((x)&XS1_PLL_CLK_DISABLE_MASK) >> XS1_PLL_CLK_DISABLE_SHIFT)
+#define XS1_PLL_CLK_DISABLE_SET(x, v)  \
+  (((x) & ~XS1_PLL_CLK_DISABLE_MASK) | \
+   (((v) << XS1_PLL_CLK_DISABLE_SHIFT) & XS1_PLL_CLK_DISABLE_MASK))
+#define XS1_THREAD_CTRL0_INUSE_SHIFT 0x0
+#define XS1_THREAD_CTRL0_INUSE_SIZE 0x1
+#define XS1_THREAD_CTRL0_INUSE_MASK \
+  (((1 << XS1_THREAD_CTRL0_INUSE_SIZE) - 1) << XS1_THREAD_CTRL0_INUSE_SHIFT)
+#define XS1_THREAD_CTRL0_INUSE(x) \
+  (((x)&XS1_THREAD_CTRL0_INUSE_MASK) >> XS1_THREAD_CTRL0_INUSE_SHIFT)
+#define XS1_THREAD_CTRL0_INUSE_SET(x, v)  \
+  (((x) & ~XS1_THREAD_CTRL0_INUSE_MASK) | \
+   (((v) << XS1_THREAD_CTRL0_INUSE_SHIFT) & XS1_THREAD_CTRL0_INUSE_MASK))
+#define XS1_THREAD_CTRL0_MSYNC_SHIFT 0x1
+#define XS1_THREAD_CTRL0_MSYNC_SIZE 0x1
+#define XS1_THREAD_CTRL0_MSYNC_MASK \
+  (((1 << XS1_THREAD_CTRL0_MSYNC_SIZE) - 1) << XS1_THREAD_CTRL0_MSYNC_SHIFT)
+#define XS1_THREAD_CTRL0_MSYNC(x) \
+  (((x)&XS1_THREAD_CTRL0_MSYNC_MASK) >> XS1_THREAD_CTRL0_MSYNC_SHIFT)
+#define XS1_THREAD_CTRL0_MSYNC_SET(x, v)  \
+  (((x) & ~XS1_THREAD_CTRL0_MSYNC_MASK) | \
+   (((v) << XS1_THREAD_CTRL0_MSYNC_SHIFT) & XS1_THREAD_CTRL0_MSYNC_MASK))
+#define XS1_THREAD_CTRL0_SSYNC_SHIFT 0x2
+#define XS1_THREAD_CTRL0_SSYNC_SIZE 0x1
+#define XS1_THREAD_CTRL0_SSYNC_MASK \
+  (((1 << XS1_THREAD_CTRL0_SSYNC_SIZE) - 1) << XS1_THREAD_CTRL0_SSYNC_SHIFT)
+#define XS1_THREAD_CTRL0_SSYNC(x) \
+  (((x)&XS1_THREAD_CTRL0_SSYNC_MASK) >> XS1_THREAD_CTRL0_SSYNC_SHIFT)
+#define XS1_THREAD_CTRL0_SSYNC_SET(x, v)  \
+  (((x) & ~XS1_THREAD_CTRL0_SSYNC_MASK) | \
+   (((v) << XS1_THREAD_CTRL0_SSYNC_SHIFT) & XS1_THREAD_CTRL0_SSYNC_MASK))
+#define XS1_THREAD_CTRL0_MASTER_SHIFT 0x8
+#define XS1_THREAD_CTRL0_MASTER_SIZE 0x8
+#define XS1_THREAD_CTRL0_MASTER_MASK \
+  (((1 << XS1_THREAD_CTRL0_MASTER_SIZE) - 1) << XS1_THREAD_CTRL0_MASTER_SHIFT)
+#define XS1_THREAD_CTRL0_MASTER(x) \
+  (((x)&XS1_THREAD_CTRL0_MASTER_MASK) >> XS1_THREAD_CTRL0_MASTER_SHIFT)
+#define XS1_THREAD_CTRL0_MASTER_SET(x, v)  \
+  (((x) & ~XS1_THREAD_CTRL0_MASTER_MASK) | \
+   (((v) << XS1_THREAD_CTRL0_MASTER_SHIFT) & XS1_THREAD_CTRL0_MASTER_MASK))
+#define XS1_PORT_CTRL0_INUSE_SHIFT 0x0
+#define XS1_PORT_CTRL0_INUSE_SIZE 0x1
+#define XS1_PORT_CTRL0_INUSE_MASK \
+  (((1 << XS1_PORT_CTRL0_INUSE_SIZE) - 1) << XS1_PORT_CTRL0_INUSE_SHIFT)
+#define XS1_PORT_CTRL0_INUSE(x) \
+  (((x)&XS1_PORT_CTRL0_INUSE_MASK) >> XS1_PORT_CTRL0_INUSE_SHIFT)
+#define XS1_PORT_CTRL0_INUSE_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL0_INUSE_MASK) | \
+   (((v) << XS1_PORT_CTRL0_INUSE_SHIFT) & XS1_PORT_CTRL0_INUSE_MASK))
+#define XS1_PORT_CTRL0_IE_MODE_SHIFT 0x1
+#define XS1_PORT_CTRL0_IE_MODE_SIZE 0x1
+#define XS1_PORT_CTRL0_IE_MODE_MASK \
+  (((1 << XS1_PORT_CTRL0_IE_MODE_SIZE) - 1) << XS1_PORT_CTRL0_IE_MODE_SHIFT)
+#define XS1_PORT_CTRL0_IE_MODE(x) \
+  (((x)&XS1_PORT_CTRL0_IE_MODE_MASK) >> XS1_PORT_CTRL0_IE_MODE_SHIFT)
+#define XS1_PORT_CTRL0_IE_MODE_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL0_IE_MODE_MASK) | \
+   (((v) << XS1_PORT_CTRL0_IE_MODE_SHIFT) & XS1_PORT_CTRL0_IE_MODE_MASK))
+#define XS1_PORT_CTRL0_IE_ENABLED_SHIFT 0x2
+#define XS1_PORT_CTRL0_IE_ENABLED_SIZE 0x1
+#define XS1_PORT_CTRL0_IE_ENABLED_MASK         \
+  (((1 << XS1_PORT_CTRL0_IE_ENABLED_SIZE) - 1) \
+   << XS1_PORT_CTRL0_IE_ENABLED_SHIFT)
+#define XS1_PORT_CTRL0_IE_ENABLED(x) \
+  (((x)&XS1_PORT_CTRL0_IE_ENABLED_MASK) >> XS1_PORT_CTRL0_IE_ENABLED_SHIFT)
+#define XS1_PORT_CTRL0_IE_ENABLED_SET(x, v)    \
+  (((x) & ~XS1_PORT_CTRL0_IE_ENABLED_MASK) |   \
+   (((v) << XS1_PORT_CTRL0_IE_ENABLED_SHIFT) & \
+    XS1_PORT_CTRL0_IE_ENABLED_MASK))
+#define XS1_PORT_CTRL0_DIRECTION_SHIFT 0x3
+#define XS1_PORT_CTRL0_DIRECTION_SIZE 0x1
+#define XS1_PORT_CTRL0_DIRECTION_MASK \
+  (((1 << XS1_PORT_CTRL0_DIRECTION_SIZE) - 1) << XS1_PORT_CTRL0_DIRECTION_SHIFT)
+#define XS1_PORT_CTRL0_DIRECTION(x) \
+  (((x)&XS1_PORT_CTRL0_DIRECTION_MASK) >> XS1_PORT_CTRL0_DIRECTION_SHIFT)
+#define XS1_PORT_CTRL0_DIRECTION_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL0_DIRECTION_MASK) | \
+   (((v) << XS1_PORT_CTRL0_DIRECTION_SHIFT) & XS1_PORT_CTRL0_DIRECTION_MASK))
+#define XS1_PORT_CTRL0_COND_SHIFT 0x4
+#define XS1_PORT_CTRL0_COND_SIZE 0x4
+#define XS1_PORT_CTRL0_COND_MASK \
+  (((1 << XS1_PORT_CTRL0_COND_SIZE) - 1) << XS1_PORT_CTRL0_COND_SHIFT)
+#define XS1_PORT_CTRL0_COND(x) \
+  (((x)&XS1_PORT_CTRL0_COND_MASK) >> XS1_PORT_CTRL0_COND_SHIFT)
+#define XS1_PORT_CTRL0_COND_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL0_COND_MASK) | \
+   (((v) << XS1_PORT_CTRL0_COND_SHIFT) & XS1_PORT_CTRL0_COND_MASK))
+#define XS1_PORT_CTRL0_MASTER_SLAVE_SHIFT 0x8
+#define XS1_PORT_CTRL0_MASTER_SLAVE_SIZE 0x1
+#define XS1_PORT_CTRL0_MASTER_SLAVE_MASK         \
+  (((1 << XS1_PORT_CTRL0_MASTER_SLAVE_SIZE) - 1) \
+   << XS1_PORT_CTRL0_MASTER_SLAVE_SHIFT)
+#define XS1_PORT_CTRL0_MASTER_SLAVE(x) \
+  (((x)&XS1_PORT_CTRL0_MASTER_SLAVE_MASK) >> XS1_PORT_CTRL0_MASTER_SLAVE_SHIFT)
+#define XS1_PORT_CTRL0_MASTER_SLAVE_SET(x, v)    \
+  (((x) & ~XS1_PORT_CTRL0_MASTER_SLAVE_MASK) |   \
+   (((v) << XS1_PORT_CTRL0_MASTER_SLAVE_SHIFT) & \
+    XS1_PORT_CTRL0_MASTER_SLAVE_MASK))
+#define XS1_PORT_CTRL0_BUFFERS_SHIFT 0x9
+#define XS1_PORT_CTRL0_BUFFERS_SIZE 0x1
+#define XS1_PORT_CTRL0_BUFFERS_MASK \
+  (((1 << XS1_PORT_CTRL0_BUFFERS_SIZE) - 1) << XS1_PORT_CTRL0_BUFFERS_SHIFT)
+#define XS1_PORT_CTRL0_BUFFERS(x) \
+  (((x)&XS1_PORT_CTRL0_BUFFERS_MASK) >> XS1_PORT_CTRL0_BUFFERS_SHIFT)
+#define XS1_PORT_CTRL0_BUFFERS_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL0_BUFFERS_MASK) | \
+   (((v) << XS1_PORT_CTRL0_BUFFERS_SHIFT) & XS1_PORT_CTRL0_BUFFERS_MASK))
+#define XS1_PORT_CTRL0_READY_MODE_SHIFT 0xa
+#define XS1_PORT_CTRL0_READY_MODE_SIZE 0x2
+#define XS1_PORT_CTRL0_READY_MODE_MASK         \
+  (((1 << XS1_PORT_CTRL0_READY_MODE_SIZE) - 1) \
+   << XS1_PORT_CTRL0_READY_MODE_SHIFT)
+#define XS1_PORT_CTRL0_READY_MODE(x) \
+  (((x)&XS1_PORT_CTRL0_READY_MODE_MASK) >> XS1_PORT_CTRL0_READY_MODE_SHIFT)
+#define XS1_PORT_CTRL0_READY_MODE_SET(x, v)    \
+  (((x) & ~XS1_PORT_CTRL0_READY_MODE_MASK) |   \
+   (((v) << XS1_PORT_CTRL0_READY_MODE_SHIFT) & \
+    XS1_PORT_CTRL0_READY_MODE_MASK))
+#define XS1_PORT_CTRL0_PORT_TYPE_SHIFT 0xc
+#define XS1_PORT_CTRL0_PORT_TYPE_SIZE 0x2
+#define XS1_PORT_CTRL0_PORT_TYPE_MASK \
+  (((1 << XS1_PORT_CTRL0_PORT_TYPE_SIZE) - 1) << XS1_PORT_CTRL0_PORT_TYPE_SHIFT)
+#define XS1_PORT_CTRL0_PORT_TYPE(x) \
+  (((x)&XS1_PORT_CTRL0_PORT_TYPE_MASK) >> XS1_PORT_CTRL0_PORT_TYPE_SHIFT)
+#define XS1_PORT_CTRL0_PORT_TYPE_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL0_PORT_TYPE_MASK) | \
+   (((v) << XS1_PORT_CTRL0_PORT_TYPE_SHIFT) & XS1_PORT_CTRL0_PORT_TYPE_MASK))
+#define XS1_PORT_CTRL0_INVERT_SHIFT 0xe
+#define XS1_PORT_CTRL0_INVERT_SIZE 0x1
+#define XS1_PORT_CTRL0_INVERT_MASK \
+  (((1 << XS1_PORT_CTRL0_INVERT_SIZE) - 1) << XS1_PORT_CTRL0_INVERT_SHIFT)
+#define XS1_PORT_CTRL0_INVERT(x) \
+  (((x)&XS1_PORT_CTRL0_INVERT_MASK) >> XS1_PORT_CTRL0_INVERT_SHIFT)
+#define XS1_PORT_CTRL0_INVERT_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL0_INVERT_MASK) | \
+   (((v) << XS1_PORT_CTRL0_INVERT_SHIFT) & XS1_PORT_CTRL0_INVERT_MASK))
+#define XS1_PORT_CTRL0_SDELAY_SHIFT 0xf
+#define XS1_PORT_CTRL0_SDELAY_SIZE 0x1
+#define XS1_PORT_CTRL0_SDELAY_MASK \
+  (((1 << XS1_PORT_CTRL0_SDELAY_SIZE) - 1) << XS1_PORT_CTRL0_SDELAY_SHIFT)
+#define XS1_PORT_CTRL0_SDELAY(x) \
+  (((x)&XS1_PORT_CTRL0_SDELAY_MASK) >> XS1_PORT_CTRL0_SDELAY_SHIFT)
+#define XS1_PORT_CTRL0_SDELAY_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL0_SDELAY_MASK) | \
+   (((v) << XS1_PORT_CTRL0_SDELAY_SHIFT) & XS1_PORT_CTRL0_SDELAY_MASK))
+#define XS1_PORT_CTRL0_EV_VALID_SHIFT 0x16
+#define XS1_PORT_CTRL0_EV_VALID_SIZE 0x1
+#define XS1_PORT_CTRL0_EV_VALID_MASK \
+  (((1 << XS1_PORT_CTRL0_EV_VALID_SIZE) - 1) << XS1_PORT_CTRL0_EV_VALID_SHIFT)
+#define XS1_PORT_CTRL0_EV_VALID(x) \
+  (((x)&XS1_PORT_CTRL0_EV_VALID_MASK) >> XS1_PORT_CTRL0_EV_VALID_SHIFT)
+#define XS1_PORT_CTRL0_EV_VALID_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL0_EV_VALID_MASK) | \
+   (((v) << XS1_PORT_CTRL0_EV_VALID_SHIFT) & XS1_PORT_CTRL0_EV_VALID_MASK))
+#define XS1_PORT_CTRL0_T_WAITING_SHIFT 0x17
+#define XS1_PORT_CTRL0_T_WAITING_SIZE 0x1
+#define XS1_PORT_CTRL0_T_WAITING_MASK \
+  (((1 << XS1_PORT_CTRL0_T_WAITING_SIZE) - 1) << XS1_PORT_CTRL0_T_WAITING_SHIFT)
+#define XS1_PORT_CTRL0_T_WAITING(x) \
+  (((x)&XS1_PORT_CTRL0_T_WAITING_MASK) >> XS1_PORT_CTRL0_T_WAITING_SHIFT)
+#define XS1_PORT_CTRL0_T_WAITING_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL0_T_WAITING_MASK) | \
+   (((v) << XS1_PORT_CTRL0_T_WAITING_SHIFT) & XS1_PORT_CTRL0_T_WAITING_MASK))
+#define XS1_PORT_CTRL0_T_NUM_SHIFT 0x18
+#define XS1_PORT_CTRL0_T_NUM_SIZE 0x8
+#define XS1_PORT_CTRL0_T_NUM_MASK \
+  (((1 << XS1_PORT_CTRL0_T_NUM_SIZE) - 1) << XS1_PORT_CTRL0_T_NUM_SHIFT)
+#define XS1_PORT_CTRL0_T_NUM(x) \
+  (((x)&XS1_PORT_CTRL0_T_NUM_MASK) >> XS1_PORT_CTRL0_T_NUM_SHIFT)
+#define XS1_PORT_CTRL0_T_NUM_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL0_T_NUM_MASK) | \
+   (((v) << XS1_PORT_CTRL0_T_NUM_SHIFT) & XS1_PORT_CTRL0_T_NUM_MASK))
+#define XS1_PORT_CTRL1_DRIVE_SHIFT 0x0
+#define XS1_PORT_CTRL1_DRIVE_SIZE 0x8
+#define XS1_PORT_CTRL1_DRIVE_MASK \
+  (((1 << XS1_PORT_CTRL1_DRIVE_SIZE) - 1) << XS1_PORT_CTRL1_DRIVE_SHIFT)
+#define XS1_PORT_CTRL1_DRIVE(x) \
+  (((x)&XS1_PORT_CTRL1_DRIVE_MASK) >> XS1_PORT_CTRL1_DRIVE_SHIFT)
+#define XS1_PORT_CTRL1_DRIVE_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL1_DRIVE_MASK) | \
+   (((v) << XS1_PORT_CTRL1_DRIVE_SHIFT) & XS1_PORT_CTRL1_DRIVE_MASK))
+#define XS1_PORT_CTRL1_TWIDTH_SHIFT 0x8
+#define XS1_PORT_CTRL1_TWIDTH_SIZE 0x8
+#define XS1_PORT_CTRL1_TWIDTH_MASK \
+  (((1 << XS1_PORT_CTRL1_TWIDTH_SIZE) - 1) << XS1_PORT_CTRL1_TWIDTH_SHIFT)
+#define XS1_PORT_CTRL1_TWIDTH(x) \
+  (((x)&XS1_PORT_CTRL1_TWIDTH_MASK) >> XS1_PORT_CTRL1_TWIDTH_SHIFT)
+#define XS1_PORT_CTRL1_TWIDTH_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL1_TWIDTH_MASK) | \
+   (((v) << XS1_PORT_CTRL1_TWIDTH_SHIFT) & XS1_PORT_CTRL1_TWIDTH_MASK))
+#define XS1_PORT_CTRL1_SREG_COUNT_SHIFT 0x10
+#define XS1_PORT_CTRL1_SREG_COUNT_SIZE 0x8
+#define XS1_PORT_CTRL1_SREG_COUNT_MASK         \
+  (((1 << XS1_PORT_CTRL1_SREG_COUNT_SIZE) - 1) \
+   << XS1_PORT_CTRL1_SREG_COUNT_SHIFT)
+#define XS1_PORT_CTRL1_SREG_COUNT(x) \
+  (((x)&XS1_PORT_CTRL1_SREG_COUNT_MASK) >> XS1_PORT_CTRL1_SREG_COUNT_SHIFT)
+#define XS1_PORT_CTRL1_SREG_COUNT_SET(x, v)    \
+  (((x) & ~XS1_PORT_CTRL1_SREG_COUNT_MASK) |   \
+   (((v) << XS1_PORT_CTRL1_SREG_COUNT_SHIFT) & \
+    XS1_PORT_CTRL1_SREG_COUNT_MASK))
+#define XS1_PORT_CTRL1_TREG_FULL_SHIFT 0x18
+#define XS1_PORT_CTRL1_TREG_FULL_SIZE 0x1
+#define XS1_PORT_CTRL1_TREG_FULL_MASK \
+  (((1 << XS1_PORT_CTRL1_TREG_FULL_SIZE) - 1) << XS1_PORT_CTRL1_TREG_FULL_SHIFT)
+#define XS1_PORT_CTRL1_TREG_FULL(x) \
+  (((x)&XS1_PORT_CTRL1_TREG_FULL_MASK) >> XS1_PORT_CTRL1_TREG_FULL_SHIFT)
+#define XS1_PORT_CTRL1_TREG_FULL_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL1_TREG_FULL_MASK) | \
+   (((v) << XS1_PORT_CTRL1_TREG_FULL_SHIFT) & XS1_PORT_CTRL1_TREG_FULL_MASK))
+#define XS1_PORT_CTRL1_CHANGE_DIR_SHIFT 0x19
+#define XS1_PORT_CTRL1_CHANGE_DIR_SIZE 0x1
+#define XS1_PORT_CTRL1_CHANGE_DIR_MASK         \
+  (((1 << XS1_PORT_CTRL1_CHANGE_DIR_SIZE) - 1) \
+   << XS1_PORT_CTRL1_CHANGE_DIR_SHIFT)
+#define XS1_PORT_CTRL1_CHANGE_DIR(x) \
+  (((x)&XS1_PORT_CTRL1_CHANGE_DIR_MASK) >> XS1_PORT_CTRL1_CHANGE_DIR_SHIFT)
+#define XS1_PORT_CTRL1_CHANGE_DIR_SET(x, v)    \
+  (((x) & ~XS1_PORT_CTRL1_CHANGE_DIR_MASK) |   \
+   (((v) << XS1_PORT_CTRL1_CHANGE_DIR_SHIFT) & \
+    XS1_PORT_CTRL1_CHANGE_DIR_MASK))
+#define XS1_PORT_CTRL1_SYNCR_SHIFT 0x1a
+#define XS1_PORT_CTRL1_SYNCR_SIZE 0x1
+#define XS1_PORT_CTRL1_SYNCR_MASK \
+  (((1 << XS1_PORT_CTRL1_SYNCR_SIZE) - 1) << XS1_PORT_CTRL1_SYNCR_SHIFT)
+#define XS1_PORT_CTRL1_SYNCR(x) \
+  (((x)&XS1_PORT_CTRL1_SYNCR_MASK) >> XS1_PORT_CTRL1_SYNCR_SHIFT)
+#define XS1_PORT_CTRL1_SYNCR_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL1_SYNCR_MASK) | \
+   (((v) << XS1_PORT_CTRL1_SYNCR_SHIFT) & XS1_PORT_CTRL1_SYNCR_MASK))
+#define XS1_PORT_CTRL1_INST_COMMITTED_SHIFT 0x1b
+#define XS1_PORT_CTRL1_INST_COMMITTED_SIZE 0x1
+#define XS1_PORT_CTRL1_INST_COMMITTED_MASK         \
+  (((1 << XS1_PORT_CTRL1_INST_COMMITTED_SIZE) - 1) \
+   << XS1_PORT_CTRL1_INST_COMMITTED_SHIFT)
+#define XS1_PORT_CTRL1_INST_COMMITTED(x)       \
+  (((x)&XS1_PORT_CTRL1_INST_COMMITTED_MASK) >> \
+   XS1_PORT_CTRL1_INST_COMMITTED_SHIFT)
+#define XS1_PORT_CTRL1_INST_COMMITTED_SET(x, v)    \
+  (((x) & ~XS1_PORT_CTRL1_INST_COMMITTED_MASK) |   \
+   (((v) << XS1_PORT_CTRL1_INST_COMMITTED_SHIFT) & \
+    XS1_PORT_CTRL1_INST_COMMITTED_MASK))
+#define XS1_PORT_CTRL1_HOLD_DATA_SHIFT 0x1c
+#define XS1_PORT_CTRL1_HOLD_DATA_SIZE 0x1
+#define XS1_PORT_CTRL1_HOLD_DATA_MASK \
+  (((1 << XS1_PORT_CTRL1_HOLD_DATA_SIZE) - 1) << XS1_PORT_CTRL1_HOLD_DATA_SHIFT)
+#define XS1_PORT_CTRL1_HOLD_DATA(x) \
+  (((x)&XS1_PORT_CTRL1_HOLD_DATA_MASK) >> XS1_PORT_CTRL1_HOLD_DATA_SHIFT)
+#define XS1_PORT_CTRL1_HOLD_DATA_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL1_HOLD_DATA_MASK) | \
+   (((v) << XS1_PORT_CTRL1_HOLD_DATA_SHIFT) & XS1_PORT_CTRL1_HOLD_DATA_MASK))
+#define XS1_PORT_CTRL1_WAIT_FOR_TIME_SHIFT 0x1d
+#define XS1_PORT_CTRL1_WAIT_FOR_TIME_SIZE 0x1
+#define XS1_PORT_CTRL1_WAIT_FOR_TIME_MASK         \
+  (((1 << XS1_PORT_CTRL1_WAIT_FOR_TIME_SIZE) - 1) \
+   << XS1_PORT_CTRL1_WAIT_FOR_TIME_SHIFT)
+#define XS1_PORT_CTRL1_WAIT_FOR_TIME(x)       \
+  (((x)&XS1_PORT_CTRL1_WAIT_FOR_TIME_MASK) >> \
+   XS1_PORT_CTRL1_WAIT_FOR_TIME_SHIFT)
+#define XS1_PORT_CTRL1_WAIT_FOR_TIME_SET(x, v)    \
+  (((x) & ~XS1_PORT_CTRL1_WAIT_FOR_TIME_MASK) |   \
+   (((v) << XS1_PORT_CTRL1_WAIT_FOR_TIME_SHIFT) & \
+    XS1_PORT_CTRL1_WAIT_FOR_TIME_MASK))
+#define XS1_PORT_CTRL1_TIMEMET_SHIFT 0x1e
+#define XS1_PORT_CTRL1_TIMEMET_SIZE 0x1
+#define XS1_PORT_CTRL1_TIMEMET_MASK \
+  (((1 << XS1_PORT_CTRL1_TIMEMET_SIZE) - 1) << XS1_PORT_CTRL1_TIMEMET_SHIFT)
+#define XS1_PORT_CTRL1_TIMEMET(x) \
+  (((x)&XS1_PORT_CTRL1_TIMEMET_MASK) >> XS1_PORT_CTRL1_TIMEMET_SHIFT)
+#define XS1_PORT_CTRL1_TIMEMET_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL1_TIMEMET_MASK) | \
+   (((v) << XS1_PORT_CTRL1_TIMEMET_SHIFT) & XS1_PORT_CTRL1_TIMEMET_MASK))
+#define XS1_PORT_CTRL1_ENDIN_SHIFT 0x1f
+#define XS1_PORT_CTRL1_ENDIN_SIZE 0x1
+#define XS1_PORT_CTRL1_ENDIN_MASK \
+  (((1 << XS1_PORT_CTRL1_ENDIN_SIZE) - 1) << XS1_PORT_CTRL1_ENDIN_SHIFT)
+#define XS1_PORT_CTRL1_ENDIN(x) \
+  (((x)&XS1_PORT_CTRL1_ENDIN_MASK) >> XS1_PORT_CTRL1_ENDIN_SHIFT)
+#define XS1_PORT_CTRL1_ENDIN_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL1_ENDIN_MASK) | \
+   (((v) << XS1_PORT_CTRL1_ENDIN_SHIFT) & XS1_PORT_CTRL1_ENDIN_MASK))
+#define XS1_PORT_CTRL2_TIME_SHIFT 0x0
+#define XS1_PORT_CTRL2_TIME_SIZE 0x10
+#define XS1_PORT_CTRL2_TIME_MASK \
+  (((1 << XS1_PORT_CTRL2_TIME_SIZE) - 1) << XS1_PORT_CTRL2_TIME_SHIFT)
+#define XS1_PORT_CTRL2_TIME(x) \
+  (((x)&XS1_PORT_CTRL2_TIME_MASK) >> XS1_PORT_CTRL2_TIME_SHIFT)
+#define XS1_PORT_CTRL2_TIME_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL2_TIME_MASK) | \
+   (((v) << XS1_PORT_CTRL2_TIME_SHIFT) & XS1_PORT_CTRL2_TIME_MASK))
+#define XS1_PORT_CTRL2_PIN_DELAY_SHIFT 0x10
+#define XS1_PORT_CTRL2_PIN_DELAY_SIZE 0x3
+#define XS1_PORT_CTRL2_PIN_DELAY_MASK \
+  (((1 << XS1_PORT_CTRL2_PIN_DELAY_SIZE) - 1) << XS1_PORT_CTRL2_PIN_DELAY_SHIFT)
+#define XS1_PORT_CTRL2_PIN_DELAY(x) \
+  (((x)&XS1_PORT_CTRL2_PIN_DELAY_MASK) >> XS1_PORT_CTRL2_PIN_DELAY_SHIFT)
+#define XS1_PORT_CTRL2_PIN_DELAY_SET(x, v)  \
+  (((x) & ~XS1_PORT_CTRL2_PIN_DELAY_MASK) | \
+   (((v) << XS1_PORT_CTRL2_PIN_DELAY_SHIFT) & XS1_PORT_CTRL2_PIN_DELAY_MASK))
+#define XS1_PORT_PAD_CTRL_OEN_SHIFT 0x0
+#define XS1_PORT_PAD_CTRL_OEN_SIZE 0x1
+#define XS1_PORT_PAD_CTRL_OEN_MASK \
+  (((1 << XS1_PORT_PAD_CTRL_OEN_SIZE) - 1) << XS1_PORT_PAD_CTRL_OEN_SHIFT)
+#define XS1_PORT_PAD_CTRL_OEN(x) \
+  (((x)&XS1_PORT_PAD_CTRL_OEN_MASK) >> XS1_PORT_PAD_CTRL_OEN_SHIFT)
+#define XS1_PORT_PAD_CTRL_OEN_SET(x, v)  \
+  (((x) & ~XS1_PORT_PAD_CTRL_OEN_MASK) | \
+   (((v) << XS1_PORT_PAD_CTRL_OEN_SHIFT) & XS1_PORT_PAD_CTRL_OEN_MASK))
+#define XS1_PORT_PAD_CTRL_REN_SHIFT 0x1
+#define XS1_PORT_PAD_CTRL_REN_SIZE 0x1
+#define XS1_PORT_PAD_CTRL_REN_MASK \
+  (((1 << XS1_PORT_PAD_CTRL_REN_SIZE) - 1) << XS1_PORT_PAD_CTRL_REN_SHIFT)
+#define XS1_PORT_PAD_CTRL_REN(x) \
+  (((x)&XS1_PORT_PAD_CTRL_REN_MASK) >> XS1_PORT_PAD_CTRL_REN_SHIFT)
+#define XS1_PORT_PAD_CTRL_REN_SET(x, v)  \
+  (((x) & ~XS1_PORT_PAD_CTRL_REN_MASK) | \
+   (((v) << XS1_PORT_PAD_CTRL_REN_SHIFT) & XS1_PORT_PAD_CTRL_REN_MASK))
+#define XS1_PORT_PAD_CTRL_P_SHIFT 0x2
+#define XS1_PORT_PAD_CTRL_P_SIZE 0x2
+#define XS1_PORT_PAD_CTRL_P_MASK \
+  (((1 << XS1_PORT_PAD_CTRL_P_SIZE) - 1) << XS1_PORT_PAD_CTRL_P_SHIFT)
+#define XS1_PORT_PAD_CTRL_P(x) \
+  (((x)&XS1_PORT_PAD_CTRL_P_MASK) >> XS1_PORT_PAD_CTRL_P_SHIFT)
+#define XS1_PORT_PAD_CTRL_P_SET(x, v)  \
+  (((x) & ~XS1_PORT_PAD_CTRL_P_MASK) | \
+   (((v) << XS1_PORT_PAD_CTRL_P_SHIFT) & XS1_PORT_PAD_CTRL_P_MASK))
+#define XS1_PORT_PAD_CTRL_E_SHIFT 0x4
+#define XS1_PORT_PAD_CTRL_E_SIZE 0x2
+#define XS1_PORT_PAD_CTRL_E_MASK \
+  (((1 << XS1_PORT_PAD_CTRL_E_SIZE) - 1) << XS1_PORT_PAD_CTRL_E_SHIFT)
+#define XS1_PORT_PAD_CTRL_E(x) \
+  (((x)&XS1_PORT_PAD_CTRL_E_MASK) >> XS1_PORT_PAD_CTRL_E_SHIFT)
+#define XS1_PORT_PAD_CTRL_E_SET(x, v)  \
+  (((x) & ~XS1_PORT_PAD_CTRL_E_MASK) | \
+   (((v) << XS1_PORT_PAD_CTRL_E_SHIFT) & XS1_PORT_PAD_CTRL_E_MASK))
+#define XS1_PORT_PAD_CTRL_SR_SHIFT 0x6
+#define XS1_PORT_PAD_CTRL_SR_SIZE 0x1
+#define XS1_PORT_PAD_CTRL_SR_MASK \
+  (((1 << XS1_PORT_PAD_CTRL_SR_SIZE) - 1) << XS1_PORT_PAD_CTRL_SR_SHIFT)
+#define XS1_PORT_PAD_CTRL_SR(x) \
+  (((x)&XS1_PORT_PAD_CTRL_SR_MASK) >> XS1_PORT_PAD_CTRL_SR_SHIFT)
+#define XS1_PORT_PAD_CTRL_SR_SET(x, v)  \
+  (((x) & ~XS1_PORT_PAD_CTRL_SR_MASK) | \
+   (((v) << XS1_PORT_PAD_CTRL_SR_SHIFT) & XS1_PORT_PAD_CTRL_SR_MASK))
+#define XS1_PORT_PAD_CTRL_SMT_SHIFT 0x7
+#define XS1_PORT_PAD_CTRL_SMT_SIZE 0x1
+#define XS1_PORT_PAD_CTRL_SMT_MASK \
+  (((1 << XS1_PORT_PAD_CTRL_SMT_SIZE) - 1) << XS1_PORT_PAD_CTRL_SMT_SHIFT)
+#define XS1_PORT_PAD_CTRL_SMT(x) \
+  (((x)&XS1_PORT_PAD_CTRL_SMT_MASK) >> XS1_PORT_PAD_CTRL_SMT_SHIFT)
+#define XS1_PORT_PAD_CTRL_SMT_SET(x, v)  \
+  (((x) & ~XS1_PORT_PAD_CTRL_SMT_MASK) | \
+   (((v) << XS1_PORT_PAD_CTRL_SMT_SHIFT) & XS1_PORT_PAD_CTRL_SMT_MASK))
+#define XS1_TIMER_CTRL0_INUSE_SHIFT 0x0
+#define XS1_TIMER_CTRL0_INUSE_SIZE 0x1
+#define XS1_TIMER_CTRL0_INUSE_MASK \
+  (((1 << XS1_TIMER_CTRL0_INUSE_SIZE) - 1) << XS1_TIMER_CTRL0_INUSE_SHIFT)
+#define XS1_TIMER_CTRL0_INUSE(x) \
+  (((x)&XS1_TIMER_CTRL0_INUSE_MASK) >> XS1_TIMER_CTRL0_INUSE_SHIFT)
+#define XS1_TIMER_CTRL0_INUSE_SET(x, v)  \
+  (((x) & ~XS1_TIMER_CTRL0_INUSE_MASK) | \
+   (((v) << XS1_TIMER_CTRL0_INUSE_SHIFT) & XS1_TIMER_CTRL0_INUSE_MASK))
+#define XS1_TIMER_CTRL0_IE_MODE_SHIFT 0x1
+#define XS1_TIMER_CTRL0_IE_MODE_SIZE 0x1
+#define XS1_TIMER_CTRL0_IE_MODE_MASK \
+  (((1 << XS1_TIMER_CTRL0_IE_MODE_SIZE) - 1) << XS1_TIMER_CTRL0_IE_MODE_SHIFT)
+#define XS1_TIMER_CTRL0_IE_MODE(x) \
+  (((x)&XS1_TIMER_CTRL0_IE_MODE_MASK) >> XS1_TIMER_CTRL0_IE_MODE_SHIFT)
+#define XS1_TIMER_CTRL0_IE_MODE_SET(x, v)  \
+  (((x) & ~XS1_TIMER_CTRL0_IE_MODE_MASK) | \
+   (((v) << XS1_TIMER_CTRL0_IE_MODE_SHIFT) & XS1_TIMER_CTRL0_IE_MODE_MASK))
+#define XS1_TIMER_CTRL0_IE_ENABLED_SHIFT 0x2
+#define XS1_TIMER_CTRL0_IE_ENABLED_SIZE 0x1
+#define XS1_TIMER_CTRL0_IE_ENABLED_MASK         \
+  (((1 << XS1_TIMER_CTRL0_IE_ENABLED_SIZE) - 1) \
+   << XS1_TIMER_CTRL0_IE_ENABLED_SHIFT)
+#define XS1_TIMER_CTRL0_IE_ENABLED(x) \
+  (((x)&XS1_TIMER_CTRL0_IE_ENABLED_MASK) >> XS1_TIMER_CTRL0_IE_ENABLED_SHIFT)
+#define XS1_TIMER_CTRL0_IE_ENABLED_SET(x, v)    \
+  (((x) & ~XS1_TIMER_CTRL0_IE_ENABLED_MASK) |   \
+   (((v) << XS1_TIMER_CTRL0_IE_ENABLED_SHIFT) & \
+    XS1_TIMER_CTRL0_IE_ENABLED_MASK))
+#define XS1_TIMER_CTRL0_READY_SHIFT 0x3
+#define XS1_TIMER_CTRL0_READY_SIZE 0x1
+#define XS1_TIMER_CTRL0_READY_MASK \
+  (((1 << XS1_TIMER_CTRL0_READY_SIZE) - 1) << XS1_TIMER_CTRL0_READY_SHIFT)
+#define XS1_TIMER_CTRL0_READY(x) \
+  (((x)&XS1_TIMER_CTRL0_READY_MASK) >> XS1_TIMER_CTRL0_READY_SHIFT)
+#define XS1_TIMER_CTRL0_READY_SET(x, v)  \
+  (((x) & ~XS1_TIMER_CTRL0_READY_MASK) | \
+   (((v) << XS1_TIMER_CTRL0_READY_SHIFT) & XS1_TIMER_CTRL0_READY_MASK))
+#define XS1_TIMER_CTRL0_COND_SHIFT 0x4
+#define XS1_TIMER_CTRL0_COND_SIZE 0x1
+#define XS1_TIMER_CTRL0_COND_MASK \
+  (((1 << XS1_TIMER_CTRL0_COND_SIZE) - 1) << XS1_TIMER_CTRL0_COND_SHIFT)
+#define XS1_TIMER_CTRL0_COND(x) \
+  (((x)&XS1_TIMER_CTRL0_COND_MASK) >> XS1_TIMER_CTRL0_COND_SHIFT)
+#define XS1_TIMER_CTRL0_COND_SET(x, v)  \
+  (((x) & ~XS1_TIMER_CTRL0_COND_MASK) | \
+   (((v) << XS1_TIMER_CTRL0_COND_SHIFT) & XS1_TIMER_CTRL0_COND_MASK))
+#define XS1_TIMER_CTRL0_EV_VALID_SHIFT 0x8
+#define XS1_TIMER_CTRL0_EV_VALID_SIZE 0x1
+#define XS1_TIMER_CTRL0_EV_VALID_MASK \
+  (((1 << XS1_TIMER_CTRL0_EV_VALID_SIZE) - 1) << XS1_TIMER_CTRL0_EV_VALID_SHIFT)
+#define XS1_TIMER_CTRL0_EV_VALID(x) \
+  (((x)&XS1_TIMER_CTRL0_EV_VALID_MASK) >> XS1_TIMER_CTRL0_EV_VALID_SHIFT)
+#define XS1_TIMER_CTRL0_EV_VALID_SET(x, v)  \
+  (((x) & ~XS1_TIMER_CTRL0_EV_VALID_MASK) | \
+   (((v) << XS1_TIMER_CTRL0_EV_VALID_SHIFT) & XS1_TIMER_CTRL0_EV_VALID_MASK))
+#define XS1_TIMER_CTRL0_T_WAITING_SHIFT 0x17
+#define XS1_TIMER_CTRL0_T_WAITING_SIZE 0x1
+#define XS1_TIMER_CTRL0_T_WAITING_MASK         \
+  (((1 << XS1_TIMER_CTRL0_T_WAITING_SIZE) - 1) \
+   << XS1_TIMER_CTRL0_T_WAITING_SHIFT)
+#define XS1_TIMER_CTRL0_T_WAITING(x) \
+  (((x)&XS1_TIMER_CTRL0_T_WAITING_MASK) >> XS1_TIMER_CTRL0_T_WAITING_SHIFT)
+#define XS1_TIMER_CTRL0_T_WAITING_SET(x, v)    \
+  (((x) & ~XS1_TIMER_CTRL0_T_WAITING_MASK) |   \
+   (((v) << XS1_TIMER_CTRL0_T_WAITING_SHIFT) & \
+    XS1_TIMER_CTRL0_T_WAITING_MASK))
+#define XS1_TIMER_CTRL0_T_NUM_SHIFT 0x18
+#define XS1_TIMER_CTRL0_T_NUM_SIZE 0x8
+#define XS1_TIMER_CTRL0_T_NUM_MASK \
+  (((1 << XS1_TIMER_CTRL0_T_NUM_SIZE) - 1) << XS1_TIMER_CTRL0_T_NUM_SHIFT)
+#define XS1_TIMER_CTRL0_T_NUM(x) \
+  (((x)&XS1_TIMER_CTRL0_T_NUM_MASK) >> XS1_TIMER_CTRL0_T_NUM_SHIFT)
+#define XS1_TIMER_CTRL0_T_NUM_SET(x, v)  \
+  (((x) & ~XS1_TIMER_CTRL0_T_NUM_MASK) | \
+   (((v) << XS1_TIMER_CTRL0_T_NUM_SHIFT) & XS1_TIMER_CTRL0_T_NUM_MASK))
+#define XS1_SWMEM_CTRL0_INUSE_SHIFT 0x0
+#define XS1_SWMEM_CTRL0_INUSE_SIZE 0x1
+#define XS1_SWMEM_CTRL0_INUSE_MASK \
+  (((1 << XS1_SWMEM_CTRL0_INUSE_SIZE) - 1) << XS1_SWMEM_CTRL0_INUSE_SHIFT)
+#define XS1_SWMEM_CTRL0_INUSE(x) \
+  (((x)&XS1_SWMEM_CTRL0_INUSE_MASK) >> XS1_SWMEM_CTRL0_INUSE_SHIFT)
+#define XS1_SWMEM_CTRL0_INUSE_SET(x, v)  \
+  (((x) & ~XS1_SWMEM_CTRL0_INUSE_MASK) | \
+   (((v) << XS1_SWMEM_CTRL0_INUSE_SHIFT) & XS1_SWMEM_CTRL0_INUSE_MASK))
+#define XS1_SWMEM_CTRL0_IE_MODE_SHIFT 0x1
+#define XS1_SWMEM_CTRL0_IE_MODE_SIZE 0x1
+#define XS1_SWMEM_CTRL0_IE_MODE_MASK \
+  (((1 << XS1_SWMEM_CTRL0_IE_MODE_SIZE) - 1) << XS1_SWMEM_CTRL0_IE_MODE_SHIFT)
+#define XS1_SWMEM_CTRL0_IE_MODE(x) \
+  (((x)&XS1_SWMEM_CTRL0_IE_MODE_MASK) >> XS1_SWMEM_CTRL0_IE_MODE_SHIFT)
+#define XS1_SWMEM_CTRL0_IE_MODE_SET(x, v)  \
+  (((x) & ~XS1_SWMEM_CTRL0_IE_MODE_MASK) | \
+   (((v) << XS1_SWMEM_CTRL0_IE_MODE_SHIFT) & XS1_SWMEM_CTRL0_IE_MODE_MASK))
+#define XS1_SWMEM_CTRL0_IE_ENABLED_SHIFT 0x2
+#define XS1_SWMEM_CTRL0_IE_ENABLED_SIZE 0x1
+#define XS1_SWMEM_CTRL0_IE_ENABLED_MASK         \
+  (((1 << XS1_SWMEM_CTRL0_IE_ENABLED_SIZE) - 1) \
+   << XS1_SWMEM_CTRL0_IE_ENABLED_SHIFT)
+#define XS1_SWMEM_CTRL0_IE_ENABLED(x) \
+  (((x)&XS1_SWMEM_CTRL0_IE_ENABLED_MASK) >> XS1_SWMEM_CTRL0_IE_ENABLED_SHIFT)
+#define XS1_SWMEM_CTRL0_IE_ENABLED_SET(x, v)    \
+  (((x) & ~XS1_SWMEM_CTRL0_IE_ENABLED_MASK) |   \
+   (((v) << XS1_SWMEM_CTRL0_IE_ENABLED_SHIFT) & \
+    XS1_SWMEM_CTRL0_IE_ENABLED_MASK))
+#define XS1_SWMEM_CTRL0_READY_SHIFT 0x3
+#define XS1_SWMEM_CTRL0_READY_SIZE 0x1
+#define XS1_SWMEM_CTRL0_READY_MASK \
+  (((1 << XS1_SWMEM_CTRL0_READY_SIZE) - 1) << XS1_SWMEM_CTRL0_READY_SHIFT)
+#define XS1_SWMEM_CTRL0_READY(x) \
+  (((x)&XS1_SWMEM_CTRL0_READY_MASK) >> XS1_SWMEM_CTRL0_READY_SHIFT)
+#define XS1_SWMEM_CTRL0_READY_SET(x, v)  \
+  (((x) & ~XS1_SWMEM_CTRL0_READY_MASK) | \
+   (((v) << XS1_SWMEM_CTRL0_READY_SHIFT) & XS1_SWMEM_CTRL0_READY_MASK))
+#define XS1_SWMEM_CTRL0_COND_SHIFT 0x4
+#define XS1_SWMEM_CTRL0_COND_SIZE 0x1
+#define XS1_SWMEM_CTRL0_COND_MASK \
+  (((1 << XS1_SWMEM_CTRL0_COND_SIZE) - 1) << XS1_SWMEM_CTRL0_COND_SHIFT)
+#define XS1_SWMEM_CTRL0_COND(x) \
+  (((x)&XS1_SWMEM_CTRL0_COND_MASK) >> XS1_SWMEM_CTRL0_COND_SHIFT)
+#define XS1_SWMEM_CTRL0_COND_SET(x, v)  \
+  (((x) & ~XS1_SWMEM_CTRL0_COND_MASK) | \
+   (((v) << XS1_SWMEM_CTRL0_COND_SHIFT) & XS1_SWMEM_CTRL0_COND_MASK))
+#define XS1_SWMEM_CTRL0_EV_VALID_SHIFT 0x8
+#define XS1_SWMEM_CTRL0_EV_VALID_SIZE 0x1
+#define XS1_SWMEM_CTRL0_EV_VALID_MASK \
+  (((1 << XS1_SWMEM_CTRL0_EV_VALID_SIZE) - 1) << XS1_SWMEM_CTRL0_EV_VALID_SHIFT)
+#define XS1_SWMEM_CTRL0_EV_VALID(x) \
+  (((x)&XS1_SWMEM_CTRL0_EV_VALID_MASK) >> XS1_SWMEM_CTRL0_EV_VALID_SHIFT)
+#define XS1_SWMEM_CTRL0_EV_VALID_SET(x, v)  \
+  (((x) & ~XS1_SWMEM_CTRL0_EV_VALID_MASK) | \
+   (((v) << XS1_SWMEM_CTRL0_EV_VALID_SHIFT) & XS1_SWMEM_CTRL0_EV_VALID_MASK))
+#define XS1_SWMEM_CTRL0_T_WAITING_SHIFT 0x17
+#define XS1_SWMEM_CTRL0_T_WAITING_SIZE 0x1
+#define XS1_SWMEM_CTRL0_T_WAITING_MASK         \
+  (((1 << XS1_SWMEM_CTRL0_T_WAITING_SIZE) - 1) \
+   << XS1_SWMEM_CTRL0_T_WAITING_SHIFT)
+#define XS1_SWMEM_CTRL0_T_WAITING(x) \
+  (((x)&XS1_SWMEM_CTRL0_T_WAITING_MASK) >> XS1_SWMEM_CTRL0_T_WAITING_SHIFT)
+#define XS1_SWMEM_CTRL0_T_WAITING_SET(x, v)    \
+  (((x) & ~XS1_SWMEM_CTRL0_T_WAITING_MASK) |   \
+   (((v) << XS1_SWMEM_CTRL0_T_WAITING_SHIFT) & \
+    XS1_SWMEM_CTRL0_T_WAITING_MASK))
+#define XS1_SWMEM_CTRL0_T_NUM_SHIFT 0x18
+#define XS1_SWMEM_CTRL0_T_NUM_SIZE 0x8
+#define XS1_SWMEM_CTRL0_T_NUM_MASK \
+  (((1 << XS1_SWMEM_CTRL0_T_NUM_SIZE) - 1) << XS1_SWMEM_CTRL0_T_NUM_SHIFT)
+#define XS1_SWMEM_CTRL0_T_NUM(x) \
+  (((x)&XS1_SWMEM_CTRL0_T_NUM_MASK) >> XS1_SWMEM_CTRL0_T_NUM_SHIFT)
+#define XS1_SWMEM_CTRL0_T_NUM_SET(x, v)  \
+  (((x) & ~XS1_SWMEM_CTRL0_T_NUM_MASK) | \
+   (((v) << XS1_SWMEM_CTRL0_T_NUM_SHIFT) & XS1_SWMEM_CTRL0_T_NUM_MASK))
+#define XS1_OTPA_MOSI_LSB_SHIFT 0x0
+#define XS1_OTPA_MOSI_LSB_SIZE 0x1
+#define XS1_OTPA_MOSI_LSB_MASK \
+  (((1 << XS1_OTPA_MOSI_LSB_SIZE) - 1) << XS1_OTPA_MOSI_LSB_SHIFT)
+#define XS1_OTPA_MOSI_LSB(x) \
+  (((x)&XS1_OTPA_MOSI_LSB_MASK) >> XS1_OTPA_MOSI_LSB_SHIFT)
+#define XS1_OTPA_MOSI_LSB_SET(x, v)  \
+  (((x) & ~XS1_OTPA_MOSI_LSB_MASK) | \
+   (((v) << XS1_OTPA_MOSI_LSB_SHIFT) & XS1_OTPA_MOSI_LSB_MASK))
+#define XS1_OTPA_MOSI_MSB_SHIFT 0x7
+#define XS1_OTPA_MOSI_MSB_SIZE 0x1
+#define XS1_OTPA_MOSI_MSB_MASK \
+  (((1 << XS1_OTPA_MOSI_MSB_SIZE) - 1) << XS1_OTPA_MOSI_MSB_SHIFT)
+#define XS1_OTPA_MOSI_MSB(x) \
+  (((x)&XS1_OTPA_MOSI_MSB_MASK) >> XS1_OTPA_MOSI_MSB_SHIFT)
+#define XS1_OTPA_MOSI_MSB_SET(x, v)  \
+  (((x) & ~XS1_OTPA_MOSI_MSB_MASK) | \
+   (((v) << XS1_OTPA_MOSI_MSB_SHIFT) & XS1_OTPA_MOSI_MSB_MASK))
+#define XS1_OTPA_CLK_IDX_SHIFT 0x8
+#define XS1_OTPA_CLK_IDX_SIZE 0x1
+#define XS1_OTPA_CLK_IDX_MASK \
+  (((1 << XS1_OTPA_CLK_IDX_SIZE) - 1) << XS1_OTPA_CLK_IDX_SHIFT)
+#define XS1_OTPA_CLK_IDX(x) \
+  (((x)&XS1_OTPA_CLK_IDX_MASK) >> XS1_OTPA_CLK_IDX_SHIFT)
+#define XS1_OTPA_CLK_IDX_SET(x, v)  \
+  (((x) & ~XS1_OTPA_CLK_IDX_MASK) | \
+   (((v) << XS1_OTPA_CLK_IDX_SHIFT) & XS1_OTPA_CLK_IDX_MASK))
+#define XS1_OTPA_SP_IDX_SHIFT 0x9
+#define XS1_OTPA_SP_IDX_SIZE 0x1
+#define XS1_OTPA_SP_IDX_MASK \
+  (((1 << XS1_OTPA_SP_IDX_SIZE) - 1) << XS1_OTPA_SP_IDX_SHIFT)
+#define XS1_OTPA_SP_IDX(x) (((x)&XS1_OTPA_SP_IDX_MASK) >> XS1_OTPA_SP_IDX_SHIFT)
+#define XS1_OTPA_SP_IDX_SET(x, v)  \
+  (((x) & ~XS1_OTPA_SP_IDX_MASK) | \
+   (((v) << XS1_OTPA_SP_IDX_SHIFT) & XS1_OTPA_SP_IDX_MASK))
+#define XS1_OTPA_CS_IDX_SHIFT 0xa
+#define XS1_OTPA_CS_IDX_SIZE 0x1
+#define XS1_OTPA_CS_IDX_MASK \
+  (((1 << XS1_OTPA_CS_IDX_SIZE) - 1) << XS1_OTPA_CS_IDX_SHIFT)
+#define XS1_OTPA_CS_IDX(x) (((x)&XS1_OTPA_CS_IDX_MASK) >> XS1_OTPA_CS_IDX_SHIFT)
+#define XS1_OTPA_CS_IDX_SET(x, v)  \
+  (((x) & ~XS1_OTPA_CS_IDX_MASK) | \
+   (((v) << XS1_OTPA_CS_IDX_SHIFT) & XS1_OTPA_CS_IDX_MASK))
+#define XS1_OTPA_CKE_IDX_SHIFT 0xb
+#define XS1_OTPA_CKE_IDX_SIZE 0x1
+#define XS1_OTPA_CKE_IDX_MASK \
+  (((1 << XS1_OTPA_CKE_IDX_SIZE) - 1) << XS1_OTPA_CKE_IDX_SHIFT)
+#define XS1_OTPA_CKE_IDX(x) \
+  (((x)&XS1_OTPA_CKE_IDX_MASK) >> XS1_OTPA_CKE_IDX_SHIFT)
+#define XS1_OTPA_CKE_IDX_SET(x, v)  \
+  (((x) & ~XS1_OTPA_CKE_IDX_MASK) | \
+   (((v) << XS1_OTPA_CKE_IDX_SHIFT) & XS1_OTPA_CKE_IDX_MASK))
+#define XS1_OTPA_DCTRL_IDX_SHIFT 0xc
+#define XS1_OTPA_DCTRL_IDX_SIZE 0x1
+#define XS1_OTPA_DCTRL_IDX_MASK \
+  (((1 << XS1_OTPA_DCTRL_IDX_SIZE) - 1) << XS1_OTPA_DCTRL_IDX_SHIFT)
+#define XS1_OTPA_DCTRL_IDX(x) \
+  (((x)&XS1_OTPA_DCTRL_IDX_MASK) >> XS1_OTPA_DCTRL_IDX_SHIFT)
+#define XS1_OTPA_DCTRL_IDX_SET(x, v)  \
+  (((x) & ~XS1_OTPA_DCTRL_IDX_MASK) | \
+   (((v) << XS1_OTPA_DCTRL_IDX_SHIFT) & XS1_OTPA_DCTRL_IDX_MASK))
+#define XS1_OTPA_PD_IDX_SHIFT 0xd
+#define XS1_OTPA_PD_IDX_SIZE 0x1
+#define XS1_OTPA_PD_IDX_MASK \
+  (((1 << XS1_OTPA_PD_IDX_SIZE) - 1) << XS1_OTPA_PD_IDX_SHIFT)
+#define XS1_OTPA_PD_IDX(x) (((x)&XS1_OTPA_PD_IDX_MASK) >> XS1_OTPA_PD_IDX_SHIFT)
+#define XS1_OTPA_PD_IDX_SET(x, v)  \
+  (((x) & ~XS1_OTPA_PD_IDX_MASK) | \
+   (((v) << XS1_OTPA_PD_IDX_SHIFT) & XS1_OTPA_PD_IDX_MASK))
+#define XS1_OTPA_SEL_IDX_SHIFT 0xe
+#define XS1_OTPA_SEL_IDX_SIZE 0x1
+#define XS1_OTPA_SEL_IDX_MASK \
+  (((1 << XS1_OTPA_SEL_IDX_SIZE) - 1) << XS1_OTPA_SEL_IDX_SHIFT)
+#define XS1_OTPA_SEL_IDX(x) \
+  (((x)&XS1_OTPA_SEL_IDX_MASK) >> XS1_OTPA_SEL_IDX_SHIFT)
+#define XS1_OTPA_SEL_IDX_SET(x, v)  \
+  (((x) & ~XS1_OTPA_SEL_IDX_MASK) | \
+   (((v) << XS1_OTPA_SEL_IDX_SHIFT) & XS1_OTPA_SEL_IDX_MASK))
+#define XS1_OTPA_CK_IDX_SHIFT 0xf
+#define XS1_OTPA_CK_IDX_SIZE 0x1
+#define XS1_OTPA_CK_IDX_MASK \
+  (((1 << XS1_OTPA_CK_IDX_SIZE) - 1) << XS1_OTPA_CK_IDX_SHIFT)
+#define XS1_OTPA_CK_IDX(x) (((x)&XS1_OTPA_CK_IDX_MASK) >> XS1_OTPA_CK_IDX_SHIFT)
+#define XS1_OTPA_CK_IDX_SET(x, v)  \
+  (((x) & ~XS1_OTPA_CK_IDX_MASK) | \
+   (((v) << XS1_OTPA_CK_IDX_SHIFT) & XS1_OTPA_CK_IDX_MASK))
+#define XS1_OTPA_A_LSB_SHIFT 0x10
+#define XS1_OTPA_A_LSB_SIZE 0x1
+#define XS1_OTPA_A_LSB_MASK \
+  (((1 << XS1_OTPA_A_LSB_SIZE) - 1) << XS1_OTPA_A_LSB_SHIFT)
+#define XS1_OTPA_A_LSB(x) (((x)&XS1_OTPA_A_LSB_MASK) >> XS1_OTPA_A_LSB_SHIFT)
+#define XS1_OTPA_A_LSB_SET(x, v)  \
+  (((x) & ~XS1_OTPA_A_LSB_MASK) | \
+   (((v) << XS1_OTPA_A_LSB_SHIFT) & XS1_OTPA_A_LSB_MASK))
+#define XS1_OTPA_A_MSB_SHIFT 0x1a
+#define XS1_OTPA_A_MSB_SIZE 0x1
+#define XS1_OTPA_A_MSB_MASK \
+  (((1 << XS1_OTPA_A_MSB_SIZE) - 1) << XS1_OTPA_A_MSB_SHIFT)
+#define XS1_OTPA_A_MSB(x) (((x)&XS1_OTPA_A_MSB_MASK) >> XS1_OTPA_A_MSB_SHIFT)
+#define XS1_OTPA_A_MSB_SET(x, v)  \
+  (((x) & ~XS1_OTPA_A_MSB_MASK) | \
+   (((v) << XS1_OTPA_A_MSB_SHIFT) & XS1_OTPA_A_MSB_MASK))
+#define XS1_OTPA_RST_IDX_SHIFT 0x1b
+#define XS1_OTPA_RST_IDX_SIZE 0x1
+#define XS1_OTPA_RST_IDX_MASK \
+  (((1 << XS1_OTPA_RST_IDX_SIZE) - 1) << XS1_OTPA_RST_IDX_SHIFT)
+#define XS1_OTPA_RST_IDX(x) \
+  (((x)&XS1_OTPA_RST_IDX_MASK) >> XS1_OTPA_RST_IDX_SHIFT)
+#define XS1_OTPA_RST_IDX_SET(x, v)  \
+  (((x) & ~XS1_OTPA_RST_IDX_MASK) | \
+   (((v) << XS1_OTPA_RST_IDX_SHIFT) & XS1_OTPA_RST_IDX_MASK))
+#define XS1_OTPA_ARB_REQ_IDX_SHIFT 0x1c
+#define XS1_OTPA_ARB_REQ_IDX_SIZE 0x1
+#define XS1_OTPA_ARB_REQ_IDX_MASK \
+  (((1 << XS1_OTPA_ARB_REQ_IDX_SIZE) - 1) << XS1_OTPA_ARB_REQ_IDX_SHIFT)
+#define XS1_OTPA_ARB_REQ_IDX(x) \
+  (((x)&XS1_OTPA_ARB_REQ_IDX_MASK) >> XS1_OTPA_ARB_REQ_IDX_SHIFT)
+#define XS1_OTPA_ARB_REQ_IDX_SET(x, v)  \
+  (((x) & ~XS1_OTPA_ARB_REQ_IDX_MASK) | \
+   (((v) << XS1_OTPA_ARB_REQ_IDX_SHIFT) & XS1_OTPA_ARB_REQ_IDX_MASK))
+#define XS1_OTPA_MUXSEL_LSB_SHIFT 0x1d
+#define XS1_OTPA_MUXSEL_LSB_SIZE 0x1
+#define XS1_OTPA_MUXSEL_LSB_MASK \
+  (((1 << XS1_OTPA_MUXSEL_LSB_SIZE) - 1) << XS1_OTPA_MUXSEL_LSB_SHIFT)
+#define XS1_OTPA_MUXSEL_LSB(x) \
+  (((x)&XS1_OTPA_MUXSEL_LSB_MASK) >> XS1_OTPA_MUXSEL_LSB_SHIFT)
+#define XS1_OTPA_MUXSEL_LSB_SET(x, v)  \
+  (((x) & ~XS1_OTPA_MUXSEL_LSB_MASK) | \
+   (((v) << XS1_OTPA_MUXSEL_LSB_SHIFT) & XS1_OTPA_MUXSEL_LSB_MASK))
+#define XS1_OTPA_MUXSEL_MSB_SHIFT 0x1f
+#define XS1_OTPA_MUXSEL_MSB_SIZE 0x1
+#define XS1_OTPA_MUXSEL_MSB_MASK \
+  (((1 << XS1_OTPA_MUXSEL_MSB_SIZE) - 1) << XS1_OTPA_MUXSEL_MSB_SHIFT)
+#define XS1_OTPA_MUXSEL_MSB(x) \
+  (((x)&XS1_OTPA_MUXSEL_MSB_MASK) >> XS1_OTPA_MUXSEL_MSB_SHIFT)
+#define XS1_OTPA_MUXSEL_MSB_SET(x, v)  \
+  (((x) & ~XS1_OTPA_MUXSEL_MSB_MASK) | \
+   (((v) << XS1_OTPA_MUXSEL_MSB_SHIFT) & XS1_OTPA_MUXSEL_MSB_MASK))
+#define XS1_OTPA_MISO_LSB_SHIFT 0x0
+#define XS1_OTPA_MISO_LSB_SIZE 0x1
+#define XS1_OTPA_MISO_LSB_MASK \
+  (((1 << XS1_OTPA_MISO_LSB_SIZE) - 1) << XS1_OTPA_MISO_LSB_SHIFT)
+#define XS1_OTPA_MISO_LSB(x) \
+  (((x)&XS1_OTPA_MISO_LSB_MASK) >> XS1_OTPA_MISO_LSB_SHIFT)
+#define XS1_OTPA_MISO_LSB_SET(x, v)  \
+  (((x) & ~XS1_OTPA_MISO_LSB_MASK) | \
+   (((v) << XS1_OTPA_MISO_LSB_SHIFT) & XS1_OTPA_MISO_LSB_MASK))
+#define XS1_OTPA_MISO_MSB_SHIFT 0x7
+#define XS1_OTPA_MISO_MSB_SIZE 0x1
+#define XS1_OTPA_MISO_MSB_MASK \
+  (((1 << XS1_OTPA_MISO_MSB_SIZE) - 1) << XS1_OTPA_MISO_MSB_SHIFT)
+#define XS1_OTPA_MISO_MSB(x) \
+  (((x)&XS1_OTPA_MISO_MSB_MASK) >> XS1_OTPA_MISO_MSB_SHIFT)
+#define XS1_OTPA_MISO_MSB_SET(x, v)  \
+  (((x) & ~XS1_OTPA_MISO_MSB_MASK) | \
+   (((v) << XS1_OTPA_MISO_MSB_SHIFT) & XS1_OTPA_MISO_MSB_MASK))
+#define XS1_OTPA_FLAG_IDX_SHIFT 0x8
+#define XS1_OTPA_FLAG_IDX_SIZE 0x1
+#define XS1_OTPA_FLAG_IDX_MASK \
+  (((1 << XS1_OTPA_FLAG_IDX_SIZE) - 1) << XS1_OTPA_FLAG_IDX_SHIFT)
+#define XS1_OTPA_FLAG_IDX(x) \
+  (((x)&XS1_OTPA_FLAG_IDX_MASK) >> XS1_OTPA_FLAG_IDX_SHIFT)
+#define XS1_OTPA_FLAG_IDX_SET(x, v)  \
+  (((x) & ~XS1_OTPA_FLAG_IDX_MASK) | \
+   (((v) << XS1_OTPA_FLAG_IDX_SHIFT) & XS1_OTPA_FLAG_IDX_MASK))
+#define XS1_OTPA_ARB_GNT_IDX_SHIFT 0x9
+#define XS1_OTPA_ARB_GNT_IDX_SIZE 0x1
+#define XS1_OTPA_ARB_GNT_IDX_MASK \
+  (((1 << XS1_OTPA_ARB_GNT_IDX_SIZE) - 1) << XS1_OTPA_ARB_GNT_IDX_SHIFT)
+#define XS1_OTPA_ARB_GNT_IDX(x) \
+  (((x)&XS1_OTPA_ARB_GNT_IDX_MASK) >> XS1_OTPA_ARB_GNT_IDX_SHIFT)
+#define XS1_OTPA_ARB_GNT_IDX_SET(x, v)  \
+  (((x) & ~XS1_OTPA_ARB_GNT_IDX_MASK) | \
+   (((v) << XS1_OTPA_ARB_GNT_IDX_SHIFT) & XS1_OTPA_ARB_GNT_IDX_MASK))
+#define XS1_SYNC_CTRL0_INUSE_SHIFT 0x0
+#define XS1_SYNC_CTRL0_INUSE_SIZE 0x1
+#define XS1_SYNC_CTRL0_INUSE_MASK \
+  (((1 << XS1_SYNC_CTRL0_INUSE_SIZE) - 1) << XS1_SYNC_CTRL0_INUSE_SHIFT)
+#define XS1_SYNC_CTRL0_INUSE(x) \
+  (((x)&XS1_SYNC_CTRL0_INUSE_MASK) >> XS1_SYNC_CTRL0_INUSE_SHIFT)
+#define XS1_SYNC_CTRL0_INUSE_SET(x, v)  \
+  (((x) & ~XS1_SYNC_CTRL0_INUSE_MASK) | \
+   (((v) << XS1_SYNC_CTRL0_INUSE_SHIFT) & XS1_SYNC_CTRL0_INUSE_MASK))
+#define XS1_SYNC_CTRL0_MSYNCED_SHIFT 0x1
+#define XS1_SYNC_CTRL0_MSYNCED_SIZE 0x1
+#define XS1_SYNC_CTRL0_MSYNCED_MASK \
+  (((1 << XS1_SYNC_CTRL0_MSYNCED_SIZE) - 1) << XS1_SYNC_CTRL0_MSYNCED_SHIFT)
+#define XS1_SYNC_CTRL0_MSYNCED(x) \
+  (((x)&XS1_SYNC_CTRL0_MSYNCED_MASK) >> XS1_SYNC_CTRL0_MSYNCED_SHIFT)
+#define XS1_SYNC_CTRL0_MSYNCED_SET(x, v)  \
+  (((x) & ~XS1_SYNC_CTRL0_MSYNCED_MASK) | \
+   (((v) << XS1_SYNC_CTRL0_MSYNCED_SHIFT) & XS1_SYNC_CTRL0_MSYNCED_MASK))
+#define XS1_SYNC_CTRL0_JOIN_SHIFT 0x2
+#define XS1_SYNC_CTRL0_JOIN_SIZE 0x1
+#define XS1_SYNC_CTRL0_JOIN_MASK \
+  (((1 << XS1_SYNC_CTRL0_JOIN_SIZE) - 1) << XS1_SYNC_CTRL0_JOIN_SHIFT)
+#define XS1_SYNC_CTRL0_JOIN(x) \
+  (((x)&XS1_SYNC_CTRL0_JOIN_MASK) >> XS1_SYNC_CTRL0_JOIN_SHIFT)
+#define XS1_SYNC_CTRL0_JOIN_SET(x, v)  \
+  (((x) & ~XS1_SYNC_CTRL0_JOIN_MASK) | \
+   (((v) << XS1_SYNC_CTRL0_JOIN_SHIFT) & XS1_SYNC_CTRL0_JOIN_MASK))
+#define XS1_SYNC_CTRL0_MASTER_SHIFT 0x8
+#define XS1_SYNC_CTRL0_MASTER_SIZE 0x8
+#define XS1_SYNC_CTRL0_MASTER_MASK \
+  (((1 << XS1_SYNC_CTRL0_MASTER_SIZE) - 1) << XS1_SYNC_CTRL0_MASTER_SHIFT)
+#define XS1_SYNC_CTRL0_MASTER(x) \
+  (((x)&XS1_SYNC_CTRL0_MASTER_MASK) >> XS1_SYNC_CTRL0_MASTER_SHIFT)
+#define XS1_SYNC_CTRL0_MASTER_SET(x, v)  \
+  (((x) & ~XS1_SYNC_CTRL0_MASTER_MASK) | \
+   (((v) << XS1_SYNC_CTRL0_MASTER_SHIFT) & XS1_SYNC_CTRL0_MASTER_MASK))
+#define XS1_SYNC_TBV0_SLAVES_SHIFT 0x0
+#define XS1_SYNC_TBV0_SLAVES_SIZE 0x8
+#define XS1_SYNC_TBV0_SLAVES_MASK \
+  (((1 << XS1_SYNC_TBV0_SLAVES_SIZE) - 1) << XS1_SYNC_TBV0_SLAVES_SHIFT)
+#define XS1_SYNC_TBV0_SLAVES(x) \
+  (((x)&XS1_SYNC_TBV0_SLAVES_MASK) >> XS1_SYNC_TBV0_SLAVES_SHIFT)
+#define XS1_SYNC_TBV0_SLAVES_SET(x, v)  \
+  (((x) & ~XS1_SYNC_TBV0_SLAVES_MASK) | \
+   (((v) << XS1_SYNC_TBV0_SLAVES_SHIFT) & XS1_SYNC_TBV0_SLAVES_MASK))
+#define XS1_LOCK_CTRL0_INUSE_SHIFT 0x0
+#define XS1_LOCK_CTRL0_INUSE_SIZE 0x1
+#define XS1_LOCK_CTRL0_INUSE_MASK \
+  (((1 << XS1_LOCK_CTRL0_INUSE_SIZE) - 1) << XS1_LOCK_CTRL0_INUSE_SHIFT)
+#define XS1_LOCK_CTRL0_INUSE(x) \
+  (((x)&XS1_LOCK_CTRL0_INUSE_MASK) >> XS1_LOCK_CTRL0_INUSE_SHIFT)
+#define XS1_LOCK_CTRL0_INUSE_SET(x, v)  \
+  (((x) & ~XS1_LOCK_CTRL0_INUSE_MASK) | \
+   (((v) << XS1_LOCK_CTRL0_INUSE_SHIFT) & XS1_LOCK_CTRL0_INUSE_MASK))
+#define XS1_LOCK_CTRL0_OWNT_V_SHIFT 0x1
+#define XS1_LOCK_CTRL0_OWNT_V_SIZE 0x1
+#define XS1_LOCK_CTRL0_OWNT_V_MASK \
+  (((1 << XS1_LOCK_CTRL0_OWNT_V_SIZE) - 1) << XS1_LOCK_CTRL0_OWNT_V_SHIFT)
+#define XS1_LOCK_CTRL0_OWNT_V(x) \
+  (((x)&XS1_LOCK_CTRL0_OWNT_V_MASK) >> XS1_LOCK_CTRL0_OWNT_V_SHIFT)
+#define XS1_LOCK_CTRL0_OWNT_V_SET(x, v)  \
+  (((x) & ~XS1_LOCK_CTRL0_OWNT_V_MASK) | \
+   (((v) << XS1_LOCK_CTRL0_OWNT_V_SHIFT) & XS1_LOCK_CTRL0_OWNT_V_MASK))
+#define XS1_LOCK_CTRL0_OWNT_SHIFT 0x8
+#define XS1_LOCK_CTRL0_OWNT_SIZE 0x8
+#define XS1_LOCK_CTRL0_OWNT_MASK \
+  (((1 << XS1_LOCK_CTRL0_OWNT_SIZE) - 1) << XS1_LOCK_CTRL0_OWNT_SHIFT)
+#define XS1_LOCK_CTRL0_OWNT(x) \
+  (((x)&XS1_LOCK_CTRL0_OWNT_MASK) >> XS1_LOCK_CTRL0_OWNT_SHIFT)
+#define XS1_LOCK_CTRL0_OWNT_SET(x, v)  \
+  (((x) & ~XS1_LOCK_CTRL0_OWNT_MASK) | \
+   (((v) << XS1_LOCK_CTRL0_OWNT_SHIFT) & XS1_LOCK_CTRL0_OWNT_MASK))
+#define XS1_LOCK_TBV0_WAITING_SHIFT 0x0
+#define XS1_LOCK_TBV0_WAITING_SIZE 0x8
+#define XS1_LOCK_TBV0_WAITING_MASK \
+  (((1 << XS1_LOCK_TBV0_WAITING_SIZE) - 1) << XS1_LOCK_TBV0_WAITING_SHIFT)
+#define XS1_LOCK_TBV0_WAITING(x) \
+  (((x)&XS1_LOCK_TBV0_WAITING_MASK) >> XS1_LOCK_TBV0_WAITING_SHIFT)
+#define XS1_LOCK_TBV0_WAITING_SET(x, v)  \
+  (((x) & ~XS1_LOCK_TBV0_WAITING_MASK) | \
+   (((v) << XS1_LOCK_TBV0_WAITING_SHIFT) & XS1_LOCK_TBV0_WAITING_MASK))
+#define XS1_MMAP_CTRL0_INUSE_SHIFT 0x0
+#define XS1_MMAP_CTRL0_INUSE_SIZE 0x1
+#define XS1_MMAP_CTRL0_INUSE_MASK \
+  (((1 << XS1_MMAP_CTRL0_INUSE_SIZE) - 1) << XS1_MMAP_CTRL0_INUSE_SHIFT)
+#define XS1_MMAP_CTRL0_INUSE(x) \
+  (((x)&XS1_MMAP_CTRL0_INUSE_MASK) >> XS1_MMAP_CTRL0_INUSE_SHIFT)
+#define XS1_MMAP_CTRL0_INUSE_SET(x, v)  \
+  (((x) & ~XS1_MMAP_CTRL0_INUSE_MASK) | \
+   (((v) << XS1_MMAP_CTRL0_INUSE_SHIFT) & XS1_MMAP_CTRL0_INUSE_MASK))
+#define XS1_MMAP_CTRL0_RO_SHIFT 0x1
+#define XS1_MMAP_CTRL0_RO_SIZE 0x1
+#define XS1_MMAP_CTRL0_RO_MASK \
+  (((1 << XS1_MMAP_CTRL0_RO_SIZE) - 1) << XS1_MMAP_CTRL0_RO_SHIFT)
+#define XS1_MMAP_CTRL0_RO(x) \
+  (((x)&XS1_MMAP_CTRL0_RO_MASK) >> XS1_MMAP_CTRL0_RO_SHIFT)
+#define XS1_MMAP_CTRL0_RO_SET(x, v)  \
+  (((x) & ~XS1_MMAP_CTRL0_RO_MASK) | \
+   (((v) << XS1_MMAP_CTRL0_RO_SHIFT) & XS1_MMAP_CTRL0_RO_MASK))
+#define XS1_MMAP_CTRL0_LOCK_SHIFT 0x2
+#define XS1_MMAP_CTRL0_LOCK_SIZE 0x1
+#define XS1_MMAP_CTRL0_LOCK_MASK \
+  (((1 << XS1_MMAP_CTRL0_LOCK_SIZE) - 1) << XS1_MMAP_CTRL0_LOCK_SHIFT)
+#define XS1_MMAP_CTRL0_LOCK(x) \
+  (((x)&XS1_MMAP_CTRL0_LOCK_MASK) >> XS1_MMAP_CTRL0_LOCK_SHIFT)
+#define XS1_MMAP_CTRL0_LOCK_SET(x, v)  \
+  (((x) & ~XS1_MMAP_CTRL0_LOCK_MASK) | \
+   (((v) << XS1_MMAP_CTRL0_LOCK_SHIFT) & XS1_MMAP_CTRL0_LOCK_MASK))
+#define XS1_MMAP_CTRL0_GLOBAL_SHIFT 0x3
+#define XS1_MMAP_CTRL0_GLOBAL_SIZE 0x1
+#define XS1_MMAP_CTRL0_GLOBAL_MASK \
+  (((1 << XS1_MMAP_CTRL0_GLOBAL_SIZE) - 1) << XS1_MMAP_CTRL0_GLOBAL_SHIFT)
+#define XS1_MMAP_CTRL0_GLOBAL(x) \
+  (((x)&XS1_MMAP_CTRL0_GLOBAL_MASK) >> XS1_MMAP_CTRL0_GLOBAL_SHIFT)
+#define XS1_MMAP_CTRL0_GLOBAL_SET(x, v)  \
+  (((x) & ~XS1_MMAP_CTRL0_GLOBAL_MASK) | \
+   (((v) << XS1_MMAP_CTRL0_GLOBAL_SHIFT) & XS1_MMAP_CTRL0_GLOBAL_MASK))
+#define XS1_MMAP_CTRL0_ASID_SHIFT 0x4
+#define XS1_MMAP_CTRL0_ASID_SIZE 0x2
+#define XS1_MMAP_CTRL0_ASID_MASK \
+  (((1 << XS1_MMAP_CTRL0_ASID_SIZE) - 1) << XS1_MMAP_CTRL0_ASID_SHIFT)
+#define XS1_MMAP_CTRL0_ASID(x) \
+  (((x)&XS1_MMAP_CTRL0_ASID_MASK) >> XS1_MMAP_CTRL0_ASID_SHIFT)
+#define XS1_MMAP_CTRL0_ASID_SET(x, v)  \
+  (((x) & ~XS1_MMAP_CTRL0_ASID_MASK) | \
+   (((v) << XS1_MMAP_CTRL0_ASID_SHIFT) & XS1_MMAP_CTRL0_ASID_MASK))
+#define XS1_MMAP_CTRL0_LENGTH_SHIFT 0x6
+#define XS1_MMAP_CTRL0_LENGTH_SIZE 0x2
+#define XS1_MMAP_CTRL0_LENGTH_MASK \
+  (((1 << XS1_MMAP_CTRL0_LENGTH_SIZE) - 1) << XS1_MMAP_CTRL0_LENGTH_SHIFT)
+#define XS1_MMAP_CTRL0_LENGTH(x) \
+  (((x)&XS1_MMAP_CTRL0_LENGTH_MASK) >> XS1_MMAP_CTRL0_LENGTH_SHIFT)
+#define XS1_MMAP_CTRL0_LENGTH_SET(x, v)  \
+  (((x) & ~XS1_MMAP_CTRL0_LENGTH_MASK) | \
+   (((v) << XS1_MMAP_CTRL0_LENGTH_SHIFT) & XS1_MMAP_CTRL0_LENGTH_MASK))
+#define XS1_MMAP_CTRL0_PHY_ADDR_SHIFT 0x8
+#define XS1_MMAP_CTRL0_PHY_ADDR_SIZE 0x18
+#define XS1_MMAP_CTRL0_PHY_ADDR_MASK \
+  (((1 << XS1_MMAP_CTRL0_PHY_ADDR_SIZE) - 1) << XS1_MMAP_CTRL0_PHY_ADDR_SHIFT)
+#define XS1_MMAP_CTRL0_PHY_ADDR(x) \
+  (((x)&XS1_MMAP_CTRL0_PHY_ADDR_MASK) >> XS1_MMAP_CTRL0_PHY_ADDR_SHIFT)
+#define XS1_MMAP_CTRL0_PHY_ADDR_SET(x, v)  \
+  (((x) & ~XS1_MMAP_CTRL0_PHY_ADDR_MASK) | \
+   (((v) << XS1_MMAP_CTRL0_PHY_ADDR_SHIFT) & XS1_MMAP_CTRL0_PHY_ADDR_MASK))
+#define XS1_MMAP_CTRL1_THREADS_EN_SHIFT 0x0
+#define XS1_MMAP_CTRL1_THREADS_EN_SIZE 0x8
+#define XS1_MMAP_CTRL1_THREADS_EN_MASK         \
+  (((1 << XS1_MMAP_CTRL1_THREADS_EN_SIZE) - 1) \
+   << XS1_MMAP_CTRL1_THREADS_EN_SHIFT)
+#define XS1_MMAP_CTRL1_THREADS_EN(x) \
+  (((x)&XS1_MMAP_CTRL1_THREADS_EN_MASK) >> XS1_MMAP_CTRL1_THREADS_EN_SHIFT)
+#define XS1_MMAP_CTRL1_THREADS_EN_SET(x, v)    \
+  (((x) & ~XS1_MMAP_CTRL1_THREADS_EN_MASK) |   \
+   (((v) << XS1_MMAP_CTRL1_THREADS_EN_SHIFT) & \
+    XS1_MMAP_CTRL1_THREADS_EN_MASK))
+#define XS1_MMAP_CTRL1_VIRT_ADDR_SHIFT 0x8
+#define XS1_MMAP_CTRL1_VIRT_ADDR_SIZE 0x18
+#define XS1_MMAP_CTRL1_VIRT_ADDR_MASK \
+  (((1 << XS1_MMAP_CTRL1_VIRT_ADDR_SIZE) - 1) << XS1_MMAP_CTRL1_VIRT_ADDR_SHIFT)
+#define XS1_MMAP_CTRL1_VIRT_ADDR(x) \
+  (((x)&XS1_MMAP_CTRL1_VIRT_ADDR_MASK) >> XS1_MMAP_CTRL1_VIRT_ADDR_SHIFT)
+#define XS1_MMAP_CTRL1_VIRT_ADDR_SET(x, v)  \
+  (((x) & ~XS1_MMAP_CTRL1_VIRT_ADDR_MASK) | \
+   (((v) << XS1_MMAP_CTRL1_VIRT_ADDR_SHIFT) & XS1_MMAP_CTRL1_VIRT_ADDR_MASK))
+#define XS1_CHANEND_CTRL0_INUSE_SHIFT 0x0
+#define XS1_CHANEND_CTRL0_INUSE_SIZE 0x1
+#define XS1_CHANEND_CTRL0_INUSE_MASK \
+  (((1 << XS1_CHANEND_CTRL0_INUSE_SIZE) - 1) << XS1_CHANEND_CTRL0_INUSE_SHIFT)
+#define XS1_CHANEND_CTRL0_INUSE(x) \
+  (((x)&XS1_CHANEND_CTRL0_INUSE_MASK) >> XS1_CHANEND_CTRL0_INUSE_SHIFT)
+#define XS1_CHANEND_CTRL0_INUSE_SET(x, v)  \
+  (((x) & ~XS1_CHANEND_CTRL0_INUSE_MASK) | \
+   (((v) << XS1_CHANEND_CTRL0_INUSE_SHIFT) & XS1_CHANEND_CTRL0_INUSE_MASK))
+#define XS1_CHANEND_CTRL0_IE_MODE_SHIFT 0x1
+#define XS1_CHANEND_CTRL0_IE_MODE_SIZE 0x1
+#define XS1_CHANEND_CTRL0_IE_MODE_MASK         \
+  (((1 << XS1_CHANEND_CTRL0_IE_MODE_SIZE) - 1) \
+   << XS1_CHANEND_CTRL0_IE_MODE_SHIFT)
+#define XS1_CHANEND_CTRL0_IE_MODE(x) \
+  (((x)&XS1_CHANEND_CTRL0_IE_MODE_MASK) >> XS1_CHANEND_CTRL0_IE_MODE_SHIFT)
+#define XS1_CHANEND_CTRL0_IE_MODE_SET(x, v)    \
+  (((x) & ~XS1_CHANEND_CTRL0_IE_MODE_MASK) |   \
+   (((v) << XS1_CHANEND_CTRL0_IE_MODE_SHIFT) & \
+    XS1_CHANEND_CTRL0_IE_MODE_MASK))
+#define XS1_CHANEND_CTRL0_IE_ENABLED_SHIFT 0x2
+#define XS1_CHANEND_CTRL0_IE_ENABLED_SIZE 0x1
+#define XS1_CHANEND_CTRL0_IE_ENABLED_MASK         \
+  (((1 << XS1_CHANEND_CTRL0_IE_ENABLED_SIZE) - 1) \
+   << XS1_CHANEND_CTRL0_IE_ENABLED_SHIFT)
+#define XS1_CHANEND_CTRL0_IE_ENABLED(x)       \
+  (((x)&XS1_CHANEND_CTRL0_IE_ENABLED_MASK) >> \
+   XS1_CHANEND_CTRL0_IE_ENABLED_SHIFT)
+#define XS1_CHANEND_CTRL0_IE_ENABLED_SET(x, v)    \
+  (((x) & ~XS1_CHANEND_CTRL0_IE_ENABLED_MASK) |   \
+   (((v) << XS1_CHANEND_CTRL0_IE_ENABLED_SHIFT) & \
+    XS1_CHANEND_CTRL0_IE_ENABLED_MASK))
+#define XS1_CHANEND_CTRL0_IN_READY_SHIFT 0x4
+#define XS1_CHANEND_CTRL0_IN_READY_SIZE 0x1
+#define XS1_CHANEND_CTRL0_IN_READY_MASK         \
+  (((1 << XS1_CHANEND_CTRL0_IN_READY_SIZE) - 1) \
+   << XS1_CHANEND_CTRL0_IN_READY_SHIFT)
+#define XS1_CHANEND_CTRL0_IN_READY(x) \
+  (((x)&XS1_CHANEND_CTRL0_IN_READY_MASK) >> XS1_CHANEND_CTRL0_IN_READY_SHIFT)
+#define XS1_CHANEND_CTRL0_IN_READY_SET(x, v)    \
+  (((x) & ~XS1_CHANEND_CTRL0_IN_READY_MASK) |   \
+   (((v) << XS1_CHANEND_CTRL0_IN_READY_SHIFT) & \
+    XS1_CHANEND_CTRL0_IN_READY_MASK))
+#define XS1_CHANEND_CTRL0_IN_WAITING_SHIFT 0x5
+#define XS1_CHANEND_CTRL0_IN_WAITING_SIZE 0x1
+#define XS1_CHANEND_CTRL0_IN_WAITING_MASK         \
+  (((1 << XS1_CHANEND_CTRL0_IN_WAITING_SIZE) - 1) \
+   << XS1_CHANEND_CTRL0_IN_WAITING_SHIFT)
+#define XS1_CHANEND_CTRL0_IN_WAITING(x)       \
+  (((x)&XS1_CHANEND_CTRL0_IN_WAITING_MASK) >> \
+   XS1_CHANEND_CTRL0_IN_WAITING_SHIFT)
+#define XS1_CHANEND_CTRL0_IN_WAITING_SET(x, v)    \
+  (((x) & ~XS1_CHANEND_CTRL0_IN_WAITING_MASK) |   \
+   (((v) << XS1_CHANEND_CTRL0_IN_WAITING_SHIFT) & \
+    XS1_CHANEND_CTRL0_IN_WAITING_MASK))
+#define XS1_CHANEND_CTRL0_OUT_READY_SHIFT 0x6
+#define XS1_CHANEND_CTRL0_OUT_READY_SIZE 0x1
+#define XS1_CHANEND_CTRL0_OUT_READY_MASK         \
+  (((1 << XS1_CHANEND_CTRL0_OUT_READY_SIZE) - 1) \
+   << XS1_CHANEND_CTRL0_OUT_READY_SHIFT)
+#define XS1_CHANEND_CTRL0_OUT_READY(x) \
+  (((x)&XS1_CHANEND_CTRL0_OUT_READY_MASK) >> XS1_CHANEND_CTRL0_OUT_READY_SHIFT)
+#define XS1_CHANEND_CTRL0_OUT_READY_SET(x, v)    \
+  (((x) & ~XS1_CHANEND_CTRL0_OUT_READY_MASK) |   \
+   (((v) << XS1_CHANEND_CTRL0_OUT_READY_SHIFT) & \
+    XS1_CHANEND_CTRL0_OUT_READY_MASK))
+#define XS1_CHANEND_CTRL0_OUT_WAITING_SHIFT 0x7
+#define XS1_CHANEND_CTRL0_OUT_WAITING_SIZE 0x1
+#define XS1_CHANEND_CTRL0_OUT_WAITING_MASK         \
+  (((1 << XS1_CHANEND_CTRL0_OUT_WAITING_SIZE) - 1) \
+   << XS1_CHANEND_CTRL0_OUT_WAITING_SHIFT)
+#define XS1_CHANEND_CTRL0_OUT_WAITING(x)       \
+  (((x)&XS1_CHANEND_CTRL0_OUT_WAITING_MASK) >> \
+   XS1_CHANEND_CTRL0_OUT_WAITING_SHIFT)
+#define XS1_CHANEND_CTRL0_OUT_WAITING_SET(x, v)    \
+  (((x) & ~XS1_CHANEND_CTRL0_OUT_WAITING_MASK) |   \
+   (((v) << XS1_CHANEND_CTRL0_OUT_WAITING_SHIFT) & \
+    XS1_CHANEND_CTRL0_OUT_WAITING_MASK))
+#define XS1_CHANEND_CTRL0_EV_VALID_SHIFT 0x8
+#define XS1_CHANEND_CTRL0_EV_VALID_SIZE 0x1
+#define XS1_CHANEND_CTRL0_EV_VALID_MASK         \
+  (((1 << XS1_CHANEND_CTRL0_EV_VALID_SIZE) - 1) \
+   << XS1_CHANEND_CTRL0_EV_VALID_SHIFT)
+#define XS1_CHANEND_CTRL0_EV_VALID(x) \
+  (((x)&XS1_CHANEND_CTRL0_EV_VALID_MASK) >> XS1_CHANEND_CTRL0_EV_VALID_SHIFT)
+#define XS1_CHANEND_CTRL0_EV_VALID_SET(x, v)    \
+  (((x) & ~XS1_CHANEND_CTRL0_EV_VALID_MASK) |   \
+   (((v) << XS1_CHANEND_CTRL0_EV_VALID_SHIFT) & \
+    XS1_CHANEND_CTRL0_EV_VALID_MASK))
+#define XS1_CHANEND_CTRL0_IN_T_NUM_SHIFT 0x10
+#define XS1_CHANEND_CTRL0_IN_T_NUM_SIZE 0x8
+#define XS1_CHANEND_CTRL0_IN_T_NUM_MASK         \
+  (((1 << XS1_CHANEND_CTRL0_IN_T_NUM_SIZE) - 1) \
+   << XS1_CHANEND_CTRL0_IN_T_NUM_SHIFT)
+#define XS1_CHANEND_CTRL0_IN_T_NUM(x) \
+  (((x)&XS1_CHANEND_CTRL0_IN_T_NUM_MASK) >> XS1_CHANEND_CTRL0_IN_T_NUM_SHIFT)
+#define XS1_CHANEND_CTRL0_IN_T_NUM_SET(x, v)    \
+  (((x) & ~XS1_CHANEND_CTRL0_IN_T_NUM_MASK) |   \
+   (((v) << XS1_CHANEND_CTRL0_IN_T_NUM_SHIFT) & \
+    XS1_CHANEND_CTRL0_IN_T_NUM_MASK))
+#define XS1_CHANEND_CTRL0_OUT_T_NUM_SHIFT 0x18
+#define XS1_CHANEND_CTRL0_OUT_T_NUM_SIZE 0x8
+#define XS1_CHANEND_CTRL0_OUT_T_NUM_MASK         \
+  (((1 << XS1_CHANEND_CTRL0_OUT_T_NUM_SIZE) - 1) \
+   << XS1_CHANEND_CTRL0_OUT_T_NUM_SHIFT)
+#define XS1_CHANEND_CTRL0_OUT_T_NUM(x) \
+  (((x)&XS1_CHANEND_CTRL0_OUT_T_NUM_MASK) >> XS1_CHANEND_CTRL0_OUT_T_NUM_SHIFT)
+#define XS1_CHANEND_CTRL0_OUT_T_NUM_SET(x, v)    \
+  (((x) & ~XS1_CHANEND_CTRL0_OUT_T_NUM_MASK) |   \
+   (((v) << XS1_CHANEND_CTRL0_OUT_T_NUM_SHIFT) & \
+    XS1_CHANEND_CTRL0_OUT_T_NUM_MASK))
+#define XS1_CLKBLK_CTRL0_INUSE_SHIFT 0x0
+#define XS1_CLKBLK_CTRL0_INUSE_SIZE 0x1
+#define XS1_CLKBLK_CTRL0_INUSE_MASK \
+  (((1 << XS1_CLKBLK_CTRL0_INUSE_SIZE) - 1) << XS1_CLKBLK_CTRL0_INUSE_SHIFT)
+#define XS1_CLKBLK_CTRL0_INUSE(x) \
+  (((x)&XS1_CLKBLK_CTRL0_INUSE_MASK) >> XS1_CLKBLK_CTRL0_INUSE_SHIFT)
+#define XS1_CLKBLK_CTRL0_INUSE_SET(x, v)  \
+  (((x) & ~XS1_CLKBLK_CTRL0_INUSE_MASK) | \
+   (((v) << XS1_CLKBLK_CTRL0_INUSE_SHIFT) & XS1_CLKBLK_CTRL0_INUSE_MASK))
+#define XS1_CLKBLK_CTRL0_STARTED_SHIFT 0x1
+#define XS1_CLKBLK_CTRL0_STARTED_SIZE 0x1
+#define XS1_CLKBLK_CTRL0_STARTED_MASK \
+  (((1 << XS1_CLKBLK_CTRL0_STARTED_SIZE) - 1) << XS1_CLKBLK_CTRL0_STARTED_SHIFT)
+#define XS1_CLKBLK_CTRL0_STARTED(x) \
+  (((x)&XS1_CLKBLK_CTRL0_STARTED_MASK) >> XS1_CLKBLK_CTRL0_STARTED_SHIFT)
+#define XS1_CLKBLK_CTRL0_STARTED_SET(x, v)  \
+  (((x) & ~XS1_CLKBLK_CTRL0_STARTED_MASK) | \
+   (((v) << XS1_CLKBLK_CTRL0_STARTED_SHIFT) & XS1_CLKBLK_CTRL0_STARTED_MASK))
+#define XS1_CLKBLK_CTRL0_STOPPING_SHIFT 0x2
+#define XS1_CLKBLK_CTRL0_STOPPING_SIZE 0x1
+#define XS1_CLKBLK_CTRL0_STOPPING_MASK         \
+  (((1 << XS1_CLKBLK_CTRL0_STOPPING_SIZE) - 1) \
+   << XS1_CLKBLK_CTRL0_STOPPING_SHIFT)
+#define XS1_CLKBLK_CTRL0_STOPPING(x) \
+  (((x)&XS1_CLKBLK_CTRL0_STOPPING_MASK) >> XS1_CLKBLK_CTRL0_STOPPING_SHIFT)
+#define XS1_CLKBLK_CTRL0_STOPPING_SET(x, v)    \
+  (((x) & ~XS1_CLKBLK_CTRL0_STOPPING_MASK) |   \
+   (((v) << XS1_CLKBLK_CTRL0_STOPPING_SHIFT) & \
+    XS1_CLKBLK_CTRL0_STOPPING_MASK))
+#define XS1_CLKBLK_CTRL0_T_WAITING_SHIFT 0x17
+#define XS1_CLKBLK_CTRL0_T_WAITING_SIZE 0x1
+#define XS1_CLKBLK_CTRL0_T_WAITING_MASK         \
+  (((1 << XS1_CLKBLK_CTRL0_T_WAITING_SIZE) - 1) \
+   << XS1_CLKBLK_CTRL0_T_WAITING_SHIFT)
+#define XS1_CLKBLK_CTRL0_T_WAITING(x) \
+  (((x)&XS1_CLKBLK_CTRL0_T_WAITING_MASK) >> XS1_CLKBLK_CTRL0_T_WAITING_SHIFT)
+#define XS1_CLKBLK_CTRL0_T_WAITING_SET(x, v)    \
+  (((x) & ~XS1_CLKBLK_CTRL0_T_WAITING_MASK) |   \
+   (((v) << XS1_CLKBLK_CTRL0_T_WAITING_SHIFT) & \
+    XS1_CLKBLK_CTRL0_T_WAITING_MASK))
+#define XS1_CLKBLK_CTRL0_T_NUM_SHIFT 0x18
+#define XS1_CLKBLK_CTRL0_T_NUM_SIZE 0x8
+#define XS1_CLKBLK_CTRL0_T_NUM_MASK \
+  (((1 << XS1_CLKBLK_CTRL0_T_NUM_SIZE) - 1) << XS1_CLKBLK_CTRL0_T_NUM_SHIFT)
+#define XS1_CLKBLK_CTRL0_T_NUM(x) \
+  (((x)&XS1_CLKBLK_CTRL0_T_NUM_MASK) >> XS1_CLKBLK_CTRL0_T_NUM_SHIFT)
+#define XS1_CLKBLK_CTRL0_T_NUM_SET(x, v)  \
+  (((x) & ~XS1_CLKBLK_CTRL0_T_NUM_MASK) | \
+   (((v) << XS1_CLKBLK_CTRL0_T_NUM_SHIFT) & XS1_CLKBLK_CTRL0_T_NUM_MASK))
+#define XS1_CLKBLK_CTRL1_FALL_DELAY_SHIFT 0x0
+#define XS1_CLKBLK_CTRL1_FALL_DELAY_SIZE 0x9
+#define XS1_CLKBLK_CTRL1_FALL_DELAY_MASK         \
+  (((1 << XS1_CLKBLK_CTRL1_FALL_DELAY_SIZE) - 1) \
+   << XS1_CLKBLK_CTRL1_FALL_DELAY_SHIFT)
+#define XS1_CLKBLK_CTRL1_FALL_DELAY(x) \
+  (((x)&XS1_CLKBLK_CTRL1_FALL_DELAY_MASK) >> XS1_CLKBLK_CTRL1_FALL_DELAY_SHIFT)
+#define XS1_CLKBLK_CTRL1_FALL_DELAY_SET(x, v)    \
+  (((x) & ~XS1_CLKBLK_CTRL1_FALL_DELAY_MASK) |   \
+   (((v) << XS1_CLKBLK_CTRL1_FALL_DELAY_SHIFT) & \
+    XS1_CLKBLK_CTRL1_FALL_DELAY_MASK))
+#define XS1_CLKBLK_CTRL1_RISE_DELAY_SHIFT 0x10
+#define XS1_CLKBLK_CTRL1_RISE_DELAY_SIZE 0x9
+#define XS1_CLKBLK_CTRL1_RISE_DELAY_MASK         \
+  (((1 << XS1_CLKBLK_CTRL1_RISE_DELAY_SIZE) - 1) \
+   << XS1_CLKBLK_CTRL1_RISE_DELAY_SHIFT)
+#define XS1_CLKBLK_CTRL1_RISE_DELAY(x) \
+  (((x)&XS1_CLKBLK_CTRL1_RISE_DELAY_MASK) >> XS1_CLKBLK_CTRL1_RISE_DELAY_SHIFT)
+#define XS1_CLKBLK_CTRL1_RISE_DELAY_SET(x, v)    \
+  (((x) & ~XS1_CLKBLK_CTRL1_RISE_DELAY_MASK) |   \
+   (((v) << XS1_CLKBLK_CTRL1_RISE_DELAY_SHIFT) & \
+    XS1_CLKBLK_CTRL1_RISE_DELAY_MASK))
+#define XS1_COPROC_CTRL0_INUSE_SHIFT 0x0
+#define XS1_COPROC_CTRL0_INUSE_SIZE 0x1
+#define XS1_COPROC_CTRL0_INUSE_MASK \
+  (((1 << XS1_COPROC_CTRL0_INUSE_SIZE) - 1) << XS1_COPROC_CTRL0_INUSE_SHIFT)
+#define XS1_COPROC_CTRL0_INUSE(x) \
+  (((x)&XS1_COPROC_CTRL0_INUSE_MASK) >> XS1_COPROC_CTRL0_INUSE_SHIFT)
+#define XS1_COPROC_CTRL0_INUSE_SET(x, v)  \
+  (((x) & ~XS1_COPROC_CTRL0_INUSE_MASK) | \
+   (((v) << XS1_COPROC_CTRL0_INUSE_SHIFT) & XS1_COPROC_CTRL0_INUSE_MASK))
+#define XS1_COPROC_CTRL0_OWNT_V_SHIFT 0x1
+#define XS1_COPROC_CTRL0_OWNT_V_SIZE 0x1
+#define XS1_COPROC_CTRL0_OWNT_V_MASK \
+  (((1 << XS1_COPROC_CTRL0_OWNT_V_SIZE) - 1) << XS1_COPROC_CTRL0_OWNT_V_SHIFT)
+#define XS1_COPROC_CTRL0_OWNT_V(x) \
+  (((x)&XS1_COPROC_CTRL0_OWNT_V_MASK) >> XS1_COPROC_CTRL0_OWNT_V_SHIFT)
+#define XS1_COPROC_CTRL0_OWNT_V_SET(x, v)  \
+  (((x) & ~XS1_COPROC_CTRL0_OWNT_V_MASK) | \
+   (((v) << XS1_COPROC_CTRL0_OWNT_V_SHIFT) & XS1_COPROC_CTRL0_OWNT_V_MASK))
+#define XS1_COPROC_CTRL0_OWNT_SHIFT 0x8
+#define XS1_COPROC_CTRL0_OWNT_SIZE 0x8
+#define XS1_COPROC_CTRL0_OWNT_MASK \
+  (((1 << XS1_COPROC_CTRL0_OWNT_SIZE) - 1) << XS1_COPROC_CTRL0_OWNT_SHIFT)
+#define XS1_COPROC_CTRL0_OWNT(x) \
+  (((x)&XS1_COPROC_CTRL0_OWNT_MASK) >> XS1_COPROC_CTRL0_OWNT_SHIFT)
+#define XS1_COPROC_CTRL0_OWNT_SET(x, v)  \
+  (((x) & ~XS1_COPROC_CTRL0_OWNT_MASK) | \
+   (((v) << XS1_COPROC_CTRL0_OWNT_SHIFT) & XS1_COPROC_CTRL0_OWNT_MASK))
+#define XS1_COPROC_TBV0_WAITING_SHIFT 0x0
+#define XS1_COPROC_TBV0_WAITING_SIZE 0x8
+#define XS1_COPROC_TBV0_WAITING_MASK \
+  (((1 << XS1_COPROC_TBV0_WAITING_SIZE) - 1) << XS1_COPROC_TBV0_WAITING_SHIFT)
+#define XS1_COPROC_TBV0_WAITING(x) \
+  (((x)&XS1_COPROC_TBV0_WAITING_MASK) >> XS1_COPROC_TBV0_WAITING_SHIFT)
+#define XS1_COPROC_TBV0_WAITING_SET(x, v)  \
+  (((x) & ~XS1_COPROC_TBV0_WAITING_MASK) | \
+   (((v) << XS1_COPROC_TBV0_WAITING_SHIFT) & XS1_COPROC_TBV0_WAITING_MASK))
+#define XS1_DBG_INT_REQ_DBG_SHIFT 0x0
+#define XS1_DBG_INT_REQ_DBG_SIZE 0x1
+#define XS1_DBG_INT_REQ_DBG_MASK \
+  (((1 << XS1_DBG_INT_REQ_DBG_SIZE) - 1) << XS1_DBG_INT_REQ_DBG_SHIFT)
+#define XS1_DBG_INT_REQ_DBG(x) \
+  (((x)&XS1_DBG_INT_REQ_DBG_MASK) >> XS1_DBG_INT_REQ_DBG_SHIFT)
+#define XS1_DBG_INT_REQ_DBG_SET(x, v)  \
+  (((x) & ~XS1_DBG_INT_REQ_DBG_MASK) | \
+   (((v) << XS1_DBG_INT_REQ_DBG_SHIFT) & XS1_DBG_INT_REQ_DBG_MASK))
+#define XS1_DBG_INT_IN_DBG_SHIFT 0x1
+#define XS1_DBG_INT_IN_DBG_SIZE 0x1
+#define XS1_DBG_INT_IN_DBG_MASK \
+  (((1 << XS1_DBG_INT_IN_DBG_SIZE) - 1) << XS1_DBG_INT_IN_DBG_SHIFT)
+#define XS1_DBG_INT_IN_DBG(x) \
+  (((x)&XS1_DBG_INT_IN_DBG_MASK) >> XS1_DBG_INT_IN_DBG_SHIFT)
+#define XS1_DBG_INT_IN_DBG_SET(x, v)  \
+  (((x) & ~XS1_DBG_INT_IN_DBG_MASK) | \
+   (((v) << XS1_DBG_INT_IN_DBG_SHIFT) & XS1_DBG_INT_IN_DBG_MASK))
+#define XS1_DBG_CTRL_PSWITCH_RO_SHIFT 0x1f
+#define XS1_DBG_CTRL_PSWITCH_RO_SIZE 0x1
+#define XS1_DBG_CTRL_PSWITCH_RO_MASK \
+  (((1 << XS1_DBG_CTRL_PSWITCH_RO_SIZE) - 1) << XS1_DBG_CTRL_PSWITCH_RO_SHIFT)
+#define XS1_DBG_CTRL_PSWITCH_RO(x) \
+  (((x)&XS1_DBG_CTRL_PSWITCH_RO_MASK) >> XS1_DBG_CTRL_PSWITCH_RO_SHIFT)
+#define XS1_DBG_CTRL_PSWITCH_RO_SET(x, v)  \
+  (((x) & ~XS1_DBG_CTRL_PSWITCH_RO_MASK) | \
+   (((v) << XS1_DBG_CTRL_PSWITCH_RO_SHIFT) & XS1_DBG_CTRL_PSWITCH_RO_MASK))
+#define XS1_DEVICE_ID0_VERSION_SHIFT 0x0
+#define XS1_DEVICE_ID0_VERSION_SIZE 0x8
+#define XS1_DEVICE_ID0_VERSION_MASK \
+  (((1 << XS1_DEVICE_ID0_VERSION_SIZE) - 1) << XS1_DEVICE_ID0_VERSION_SHIFT)
+#define XS1_DEVICE_ID0_VERSION(x) \
+  (((x)&XS1_DEVICE_ID0_VERSION_MASK) >> XS1_DEVICE_ID0_VERSION_SHIFT)
+#define XS1_DEVICE_ID0_VERSION_SET(x, v)  \
+  (((x) & ~XS1_DEVICE_ID0_VERSION_MASK) | \
+   (((v) << XS1_DEVICE_ID0_VERSION_SHIFT) & XS1_DEVICE_ID0_VERSION_MASK))
+#define XS1_DEVICE_ID0_REVISION_SHIFT 0x8
+#define XS1_DEVICE_ID0_REVISION_SIZE 0x8
+#define XS1_DEVICE_ID0_REVISION_MASK \
+  (((1 << XS1_DEVICE_ID0_REVISION_SIZE) - 1) << XS1_DEVICE_ID0_REVISION_SHIFT)
+#define XS1_DEVICE_ID0_REVISION(x) \
+  (((x)&XS1_DEVICE_ID0_REVISION_MASK) >> XS1_DEVICE_ID0_REVISION_SHIFT)
+#define XS1_DEVICE_ID0_REVISION_SET(x, v)  \
+  (((x) & ~XS1_DEVICE_ID0_REVISION_MASK) | \
+   (((v) << XS1_DEVICE_ID0_REVISION_SHIFT) & XS1_DEVICE_ID0_REVISION_MASK))
+#define XS1_DEVICE_ID0_NODE_SHIFT 0x10
+#define XS1_DEVICE_ID0_NODE_SIZE 0x8
+#define XS1_DEVICE_ID0_NODE_MASK \
+  (((1 << XS1_DEVICE_ID0_NODE_SIZE) - 1) << XS1_DEVICE_ID0_NODE_SHIFT)
+#define XS1_DEVICE_ID0_NODE(x) \
+  (((x)&XS1_DEVICE_ID0_NODE_MASK) >> XS1_DEVICE_ID0_NODE_SHIFT)
+#define XS1_DEVICE_ID0_NODE_SET(x, v)  \
+  (((x) & ~XS1_DEVICE_ID0_NODE_MASK) | \
+   (((v) << XS1_DEVICE_ID0_NODE_SHIFT) & XS1_DEVICE_ID0_NODE_MASK))
+#define XS1_DEVICE_ID0_PID_SHIFT 0x18
+#define XS1_DEVICE_ID0_PID_SIZE 0x8
+#define XS1_DEVICE_ID0_PID_MASK \
+  (((1 << XS1_DEVICE_ID0_PID_SIZE) - 1) << XS1_DEVICE_ID0_PID_SHIFT)
+#define XS1_DEVICE_ID0_PID(x) \
+  (((x)&XS1_DEVICE_ID0_PID_MASK) >> XS1_DEVICE_ID0_PID_SHIFT)
+#define XS1_DEVICE_ID0_PID_SET(x, v)  \
+  (((x) & ~XS1_DEVICE_ID0_PID_MASK) | \
+   (((v) << XS1_DEVICE_ID0_PID_SHIFT) & XS1_DEVICE_ID0_PID_MASK))
+#define XS1_DEVICE_ID1_NUM_THREADS_SHIFT 0x0
+#define XS1_DEVICE_ID1_NUM_THREADS_SIZE 0x8
+#define XS1_DEVICE_ID1_NUM_THREADS_MASK         \
+  (((1 << XS1_DEVICE_ID1_NUM_THREADS_SIZE) - 1) \
+   << XS1_DEVICE_ID1_NUM_THREADS_SHIFT)
+#define XS1_DEVICE_ID1_NUM_THREADS(x) \
+  (((x)&XS1_DEVICE_ID1_NUM_THREADS_MASK) >> XS1_DEVICE_ID1_NUM_THREADS_SHIFT)
+#define XS1_DEVICE_ID1_NUM_THREADS_SET(x, v)    \
+  (((x) & ~XS1_DEVICE_ID1_NUM_THREADS_MASK) |   \
+   (((v) << XS1_DEVICE_ID1_NUM_THREADS_SHIFT) & \
+    XS1_DEVICE_ID1_NUM_THREADS_MASK))
+#define XS1_DEVICE_ID1_NUM_SYNCS_SHIFT 0x8
+#define XS1_DEVICE_ID1_NUM_SYNCS_SIZE 0x8
+#define XS1_DEVICE_ID1_NUM_SYNCS_MASK \
+  (((1 << XS1_DEVICE_ID1_NUM_SYNCS_SIZE) - 1) << XS1_DEVICE_ID1_NUM_SYNCS_SHIFT)
+#define XS1_DEVICE_ID1_NUM_SYNCS(x) \
+  (((x)&XS1_DEVICE_ID1_NUM_SYNCS_MASK) >> XS1_DEVICE_ID1_NUM_SYNCS_SHIFT)
+#define XS1_DEVICE_ID1_NUM_SYNCS_SET(x, v)  \
+  (((x) & ~XS1_DEVICE_ID1_NUM_SYNCS_MASK) | \
+   (((v) << XS1_DEVICE_ID1_NUM_SYNCS_SHIFT) & XS1_DEVICE_ID1_NUM_SYNCS_MASK))
+#define XS1_DEVICE_ID1_NUM_LOCKS_SHIFT 0x10
+#define XS1_DEVICE_ID1_NUM_LOCKS_SIZE 0x8
+#define XS1_DEVICE_ID1_NUM_LOCKS_MASK \
+  (((1 << XS1_DEVICE_ID1_NUM_LOCKS_SIZE) - 1) << XS1_DEVICE_ID1_NUM_LOCKS_SHIFT)
+#define XS1_DEVICE_ID1_NUM_LOCKS(x) \
+  (((x)&XS1_DEVICE_ID1_NUM_LOCKS_MASK) >> XS1_DEVICE_ID1_NUM_LOCKS_SHIFT)
+#define XS1_DEVICE_ID1_NUM_LOCKS_SET(x, v)  \
+  (((x) & ~XS1_DEVICE_ID1_NUM_LOCKS_MASK) | \
+   (((v) << XS1_DEVICE_ID1_NUM_LOCKS_SHIFT) & XS1_DEVICE_ID1_NUM_LOCKS_MASK))
+#define XS1_DEVICE_ID1_NUM_CHANENDS_SHIFT 0x18
+#define XS1_DEVICE_ID1_NUM_CHANENDS_SIZE 0x8
+#define XS1_DEVICE_ID1_NUM_CHANENDS_MASK         \
+  (((1 << XS1_DEVICE_ID1_NUM_CHANENDS_SIZE) - 1) \
+   << XS1_DEVICE_ID1_NUM_CHANENDS_SHIFT)
+#define XS1_DEVICE_ID1_NUM_CHANENDS(x) \
+  (((x)&XS1_DEVICE_ID1_NUM_CHANENDS_MASK) >> XS1_DEVICE_ID1_NUM_CHANENDS_SHIFT)
+#define XS1_DEVICE_ID1_NUM_CHANENDS_SET(x, v)    \
+  (((x) & ~XS1_DEVICE_ID1_NUM_CHANENDS_MASK) |   \
+   (((v) << XS1_DEVICE_ID1_NUM_CHANENDS_SHIFT) & \
+    XS1_DEVICE_ID1_NUM_CHANENDS_MASK))
+#define XS1_DEVICE_ID2_NUM_TIMERS_SHIFT 0x0
+#define XS1_DEVICE_ID2_NUM_TIMERS_SIZE 0x8
+#define XS1_DEVICE_ID2_NUM_TIMERS_MASK         \
+  (((1 << XS1_DEVICE_ID2_NUM_TIMERS_SIZE) - 1) \
+   << XS1_DEVICE_ID2_NUM_TIMERS_SHIFT)
+#define XS1_DEVICE_ID2_NUM_TIMERS(x) \
+  (((x)&XS1_DEVICE_ID2_NUM_TIMERS_MASK) >> XS1_DEVICE_ID2_NUM_TIMERS_SHIFT)
+#define XS1_DEVICE_ID2_NUM_TIMERS_SET(x, v)    \
+  (((x) & ~XS1_DEVICE_ID2_NUM_TIMERS_MASK) |   \
+   (((v) << XS1_DEVICE_ID2_NUM_TIMERS_SHIFT) & \
+    XS1_DEVICE_ID2_NUM_TIMERS_MASK))
+#define XS1_DEVICE_ID2_NUM_CLKBLKS_SHIFT 0x8
+#define XS1_DEVICE_ID2_NUM_CLKBLKS_SIZE 0x8
+#define XS1_DEVICE_ID2_NUM_CLKBLKS_MASK         \
+  (((1 << XS1_DEVICE_ID2_NUM_CLKBLKS_SIZE) - 1) \
+   << XS1_DEVICE_ID2_NUM_CLKBLKS_SHIFT)
+#define XS1_DEVICE_ID2_NUM_CLKBLKS(x) \
+  (((x)&XS1_DEVICE_ID2_NUM_CLKBLKS_MASK) >> XS1_DEVICE_ID2_NUM_CLKBLKS_SHIFT)
+#define XS1_DEVICE_ID2_NUM_CLKBLKS_SET(x, v)    \
+  (((x) & ~XS1_DEVICE_ID2_NUM_CLKBLKS_MASK) |   \
+   (((v) << XS1_DEVICE_ID2_NUM_CLKBLKS_SHIFT) & \
+    XS1_DEVICE_ID2_NUM_CLKBLKS_MASK))
+#define XS1_JUNK_SHIFT 0x2
+#define XS1_JUNK_SIZE 0x1
+#define XS1_JUNK_MASK (((1 << XS1_JUNK_SIZE) - 1) << XS1_JUNK_SHIFT)
+#define XS1_JUNK(x) (((x)&XS1_JUNK_MASK) >> XS1_JUNK_SHIFT)
+#define XS1_JUNK_SET(x, v) \
+  (((x) & ~XS1_JUNK_MASK) | (((v) << XS1_JUNK_SHIFT) & XS1_JUNK_MASK))
+#define XS1_NETWORK_SHIFT 0x4
+#define XS1_NETWORK_SIZE 0x2
+#define XS1_NETWORK_MASK (((1 << XS1_NETWORK_SIZE) - 1) << XS1_NETWORK_SHIFT)
+#define XS1_NETWORK(x) (((x)&XS1_NETWORK_MASK) >> XS1_NETWORK_SHIFT)
+#define XS1_NETWORK_SET(x, v) \
+  (((x) & ~XS1_NETWORK_MASK) | (((v) << XS1_NETWORK_SHIFT) & XS1_NETWORK_MASK))
+#define XS1_SRC_TARGET_ID_SHIFT 0x10
+#define XS1_SRC_TARGET_ID_SIZE 0x8
+#define XS1_SRC_TARGET_ID_MASK \
+  (((1 << XS1_SRC_TARGET_ID_SIZE) - 1) << XS1_SRC_TARGET_ID_SHIFT)
+#define XS1_SRC_TARGET_ID(x) \
+  (((x)&XS1_SRC_TARGET_ID_MASK) >> XS1_SRC_TARGET_ID_SHIFT)
+#define XS1_SRC_TARGET_ID_SET(x, v)  \
+  (((x) & ~XS1_SRC_TARGET_ID_MASK) | \
+   (((v) << XS1_SRC_TARGET_ID_SHIFT) & XS1_SRC_TARGET_ID_MASK))
+#define XS1_SRC_TARGET_TYPE_SHIFT 0x18
+#define XS1_SRC_TARGET_TYPE_SIZE 0x2
+#define XS1_SRC_TARGET_TYPE_MASK \
+  (((1 << XS1_SRC_TARGET_TYPE_SIZE) - 1) << XS1_SRC_TARGET_TYPE_SHIFT)
+#define XS1_SRC_TARGET_TYPE(x) \
+  (((x)&XS1_SRC_TARGET_TYPE_MASK) >> XS1_SRC_TARGET_TYPE_SHIFT)
+#define XS1_SRC_TARGET_TYPE_SET(x, v)  \
+  (((x) & ~XS1_SRC_TARGET_TYPE_MASK) | \
+   (((v) << XS1_SRC_TARGET_TYPE_SHIFT) & XS1_SRC_TARGET_TYPE_MASK))
+#define XS1_SS_DEVICE_ID0_VERSION_SHIFT 0x0
+#define XS1_SS_DEVICE_ID0_VERSION_SIZE 0x8
+#define XS1_SS_DEVICE_ID0_VERSION_MASK         \
+  (((1 << XS1_SS_DEVICE_ID0_VERSION_SIZE) - 1) \
+   << XS1_SS_DEVICE_ID0_VERSION_SHIFT)
+#define XS1_SS_DEVICE_ID0_VERSION(x) \
+  (((x)&XS1_SS_DEVICE_ID0_VERSION_MASK) >> XS1_SS_DEVICE_ID0_VERSION_SHIFT)
+#define XS1_SS_DEVICE_ID0_VERSION_SET(x, v)    \
+  (((x) & ~XS1_SS_DEVICE_ID0_VERSION_MASK) |   \
+   (((v) << XS1_SS_DEVICE_ID0_VERSION_SHIFT) & \
+    XS1_SS_DEVICE_ID0_VERSION_MASK))
+#define XS1_SS_DEVICE_ID0_REVISION_SHIFT 0x8
+#define XS1_SS_DEVICE_ID0_REVISION_SIZE 0x8
+#define XS1_SS_DEVICE_ID0_REVISION_MASK         \
+  (((1 << XS1_SS_DEVICE_ID0_REVISION_SIZE) - 1) \
+   << XS1_SS_DEVICE_ID0_REVISION_SHIFT)
+#define XS1_SS_DEVICE_ID0_REVISION(x) \
+  (((x)&XS1_SS_DEVICE_ID0_REVISION_MASK) >> XS1_SS_DEVICE_ID0_REVISION_SHIFT)
+#define XS1_SS_DEVICE_ID0_REVISION_SET(x, v)    \
+  (((x) & ~XS1_SS_DEVICE_ID0_REVISION_MASK) |   \
+   (((v) << XS1_SS_DEVICE_ID0_REVISION_SHIFT) & \
+    XS1_SS_DEVICE_ID0_REVISION_MASK))
+#define XS1_SS_DEVICE_ID0_BOOT_CTRL_SHIFT 0x10
+#define XS1_SS_DEVICE_ID0_BOOT_CTRL_SIZE 0x8
+#define XS1_SS_DEVICE_ID0_BOOT_CTRL_MASK         \
+  (((1 << XS1_SS_DEVICE_ID0_BOOT_CTRL_SIZE) - 1) \
+   << XS1_SS_DEVICE_ID0_BOOT_CTRL_SHIFT)
+#define XS1_SS_DEVICE_ID0_BOOT_CTRL(x) \
+  (((x)&XS1_SS_DEVICE_ID0_BOOT_CTRL_MASK) >> XS1_SS_DEVICE_ID0_BOOT_CTRL_SHIFT)
+#define XS1_SS_DEVICE_ID0_BOOT_CTRL_SET(x, v)    \
+  (((x) & ~XS1_SS_DEVICE_ID0_BOOT_CTRL_MASK) |   \
+   (((v) << XS1_SS_DEVICE_ID0_BOOT_CTRL_SHIFT) & \
+    XS1_SS_DEVICE_ID0_BOOT_CTRL_MASK))
+#define XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_SHIFT 0x0
+#define XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_SIZE 0x8
+#define XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_MASK         \
+  (((1 << XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_SIZE) - 1) \
+   << XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_SHIFT)
+#define XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC(x)       \
+  (((x)&XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_MASK) >> \
+   XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_SHIFT)
+#define XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_SET(x, v)    \
+  (((x) & ~XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_MASK) |   \
+   (((v) << XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_SHIFT) & \
+    XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_MASK))
+#define XS1_SS_DEVICE_ID1_NUM_PROCESSORS_SHIFT 0x8
+#define XS1_SS_DEVICE_ID1_NUM_PROCESSORS_SIZE 0x8
+#define XS1_SS_DEVICE_ID1_NUM_PROCESSORS_MASK         \
+  (((1 << XS1_SS_DEVICE_ID1_NUM_PROCESSORS_SIZE) - 1) \
+   << XS1_SS_DEVICE_ID1_NUM_PROCESSORS_SHIFT)
+#define XS1_SS_DEVICE_ID1_NUM_PROCESSORS(x)       \
+  (((x)&XS1_SS_DEVICE_ID1_NUM_PROCESSORS_MASK) >> \
+   XS1_SS_DEVICE_ID1_NUM_PROCESSORS_SHIFT)
+#define XS1_SS_DEVICE_ID1_NUM_PROCESSORS_SET(x, v)    \
+  (((x) & ~XS1_SS_DEVICE_ID1_NUM_PROCESSORS_MASK) |   \
+   (((v) << XS1_SS_DEVICE_ID1_NUM_PROCESSORS_SHIFT) & \
+    XS1_SS_DEVICE_ID1_NUM_PROCESSORS_MASK))
+#define XS1_SS_DEVICE_ID1_NUM_SLINKS_SHIFT 0x10
+#define XS1_SS_DEVICE_ID1_NUM_SLINKS_SIZE 0x8
+#define XS1_SS_DEVICE_ID1_NUM_SLINKS_MASK         \
+  (((1 << XS1_SS_DEVICE_ID1_NUM_SLINKS_SIZE) - 1) \
+   << XS1_SS_DEVICE_ID1_NUM_SLINKS_SHIFT)
+#define XS1_SS_DEVICE_ID1_NUM_SLINKS(x)       \
+  (((x)&XS1_SS_DEVICE_ID1_NUM_SLINKS_MASK) >> \
+   XS1_SS_DEVICE_ID1_NUM_SLINKS_SHIFT)
+#define XS1_SS_DEVICE_ID1_NUM_SLINKS_SET(x, v)    \
+  (((x) & ~XS1_SS_DEVICE_ID1_NUM_SLINKS_MASK) |   \
+   (((v) << XS1_SS_DEVICE_ID1_NUM_SLINKS_SHIFT) & \
+    XS1_SS_DEVICE_ID1_NUM_SLINKS_MASK))
+#define XS1_SS_NODE_CONFIG_HEADERS_SHIFT 0x0
+#define XS1_SS_NODE_CONFIG_HEADERS_SIZE 0x1
+#define XS1_SS_NODE_CONFIG_HEADERS_MASK         \
+  (((1 << XS1_SS_NODE_CONFIG_HEADERS_SIZE) - 1) \
+   << XS1_SS_NODE_CONFIG_HEADERS_SHIFT)
+#define XS1_SS_NODE_CONFIG_HEADERS(x) \
+  (((x)&XS1_SS_NODE_CONFIG_HEADERS_MASK) >> XS1_SS_NODE_CONFIG_HEADERS_SHIFT)
+#define XS1_SS_NODE_CONFIG_HEADERS_SET(x, v)    \
+  (((x) & ~XS1_SS_NODE_CONFIG_HEADERS_MASK) |   \
+   (((v) << XS1_SS_NODE_CONFIG_HEADERS_SHIFT) & \
+    XS1_SS_NODE_CONFIG_HEADERS_MASK))
+#define XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_SHIFT 0x8
+#define XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_SIZE 0x1
+#define XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_MASK         \
+  (((1 << XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_SIZE) - 1) \
+   << XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_SHIFT)
+#define XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG(x)       \
+  (((x)&XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_MASK) >> \
+   XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_SHIFT)
+#define XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_SET(x, v)    \
+  (((x) & ~XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_MASK) |   \
+   (((v) << XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_SHIFT) & \
+    XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_MASK))
+#define XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_SHIFT 0x1f
+#define XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_SIZE 0x1
+#define XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_MASK         \
+  (((1 << XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_SIZE) - 1) \
+   << XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_SHIFT)
+#define XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE(x)       \
+  (((x)&XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_MASK) >> \
+   XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_SHIFT)
+#define XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_SET(x, v)    \
+  (((x) & ~XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_MASK) |   \
+   (((v) << XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_SHIFT) & \
+    XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_MASK))
+#define XS1_SS_NODE_ID_ID_SHIFT 0x0
+#define XS1_SS_NODE_ID_ID_SIZE 0x10
+#define XS1_SS_NODE_ID_ID_MASK \
+  (((1 << XS1_SS_NODE_ID_ID_SIZE) - 1) << XS1_SS_NODE_ID_ID_SHIFT)
+#define XS1_SS_NODE_ID_ID(x) \
+  (((x)&XS1_SS_NODE_ID_ID_MASK) >> XS1_SS_NODE_ID_ID_SHIFT)
+#define XS1_SS_NODE_ID_ID_SET(x, v)  \
+  (((x) & ~XS1_SS_NODE_ID_ID_MASK) | \
+   (((v) << XS1_SS_NODE_ID_ID_SHIFT) & XS1_SS_NODE_ID_ID_MASK))
+#define XS1_SS_PLL_CTL_INPUT_DIVISOR_SHIFT 0x0
+#define XS1_SS_PLL_CTL_INPUT_DIVISOR_SIZE 0x7
+#define XS1_SS_PLL_CTL_INPUT_DIVISOR_MASK         \
+  (((1 << XS1_SS_PLL_CTL_INPUT_DIVISOR_SIZE) - 1) \
+   << XS1_SS_PLL_CTL_INPUT_DIVISOR_SHIFT)
+#define XS1_SS_PLL_CTL_INPUT_DIVISOR(x)       \
+  (((x)&XS1_SS_PLL_CTL_INPUT_DIVISOR_MASK) >> \
+   XS1_SS_PLL_CTL_INPUT_DIVISOR_SHIFT)
+#define XS1_SS_PLL_CTL_INPUT_DIVISOR_SET(x, v)    \
+  (((x) & ~XS1_SS_PLL_CTL_INPUT_DIVISOR_MASK) |   \
+   (((v) << XS1_SS_PLL_CTL_INPUT_DIVISOR_SHIFT) & \
+    XS1_SS_PLL_CTL_INPUT_DIVISOR_MASK))
+#define XS1_SS_PLL_CTL_FEEDBACK_MUL_SHIFT 0x8
+#define XS1_SS_PLL_CTL_FEEDBACK_MUL_SIZE 0xd
+#define XS1_SS_PLL_CTL_FEEDBACK_MUL_MASK         \
+  (((1 << XS1_SS_PLL_CTL_FEEDBACK_MUL_SIZE) - 1) \
+   << XS1_SS_PLL_CTL_FEEDBACK_MUL_SHIFT)
+#define XS1_SS_PLL_CTL_FEEDBACK_MUL(x) \
+  (((x)&XS1_SS_PLL_CTL_FEEDBACK_MUL_MASK) >> XS1_SS_PLL_CTL_FEEDBACK_MUL_SHIFT)
+#define XS1_SS_PLL_CTL_FEEDBACK_MUL_SET(x, v)    \
+  (((x) & ~XS1_SS_PLL_CTL_FEEDBACK_MUL_MASK) |   \
+   (((v) << XS1_SS_PLL_CTL_FEEDBACK_MUL_SHIFT) & \
+    XS1_SS_PLL_CTL_FEEDBACK_MUL_MASK))
+#define XS1_SS_PLL_CTL_POST_DIVISOR_SHIFT 0x17
+#define XS1_SS_PLL_CTL_POST_DIVISOR_SIZE 0x3
+#define XS1_SS_PLL_CTL_POST_DIVISOR_MASK         \
+  (((1 << XS1_SS_PLL_CTL_POST_DIVISOR_SIZE) - 1) \
+   << XS1_SS_PLL_CTL_POST_DIVISOR_SHIFT)
+#define XS1_SS_PLL_CTL_POST_DIVISOR(x) \
+  (((x)&XS1_SS_PLL_CTL_POST_DIVISOR_MASK) >> XS1_SS_PLL_CTL_POST_DIVISOR_SHIFT)
+#define XS1_SS_PLL_CTL_POST_DIVISOR_SET(x, v)    \
+  (((x) & ~XS1_SS_PLL_CTL_POST_DIVISOR_MASK) |   \
+   (((v) << XS1_SS_PLL_CTL_POST_DIVISOR_SHIFT) & \
+    XS1_SS_PLL_CTL_POST_DIVISOR_MASK))
+#define XS1_SS_APP_PLL_ENABLE_SHIFT 0x1b
+#define XS1_SS_APP_PLL_ENABLE_SIZE 0x1
+#define XS1_SS_APP_PLL_ENABLE_MASK \
+  (((1 << XS1_SS_APP_PLL_ENABLE_SIZE) - 1) << XS1_SS_APP_PLL_ENABLE_SHIFT)
+#define XS1_SS_APP_PLL_ENABLE(x) \
+  (((x)&XS1_SS_APP_PLL_ENABLE_MASK) >> XS1_SS_APP_PLL_ENABLE_SHIFT)
+#define XS1_SS_APP_PLL_ENABLE_SET(x, v)  \
+  (((x) & ~XS1_SS_APP_PLL_ENABLE_MASK) | \
+   (((v) << XS1_SS_APP_PLL_ENABLE_SHIFT) & XS1_SS_APP_PLL_ENABLE_MASK))
+#define XS1_SS_FRAC_N_PERIOD_CYC_CNT_SHIFT 0x0
+#define XS1_SS_FRAC_N_PERIOD_CYC_CNT_SIZE 0x8
+#define XS1_SS_FRAC_N_PERIOD_CYC_CNT_MASK         \
+  (((1 << XS1_SS_FRAC_N_PERIOD_CYC_CNT_SIZE) - 1) \
+   << XS1_SS_FRAC_N_PERIOD_CYC_CNT_SHIFT)
+#define XS1_SS_FRAC_N_PERIOD_CYC_CNT(x)       \
+  (((x)&XS1_SS_FRAC_N_PERIOD_CYC_CNT_MASK) >> \
+   XS1_SS_FRAC_N_PERIOD_CYC_CNT_SHIFT)
+#define XS1_SS_FRAC_N_PERIOD_CYC_CNT_SET(x, v)    \
+  (((x) & ~XS1_SS_FRAC_N_PERIOD_CYC_CNT_MASK) |   \
+   (((v) << XS1_SS_FRAC_N_PERIOD_CYC_CNT_SHIFT) & \
+    XS1_SS_FRAC_N_PERIOD_CYC_CNT_MASK))
+#define XS1_SS_FRAC_N_F_HIGH_CYC_CNT_SHIFT 0x8
+#define XS1_SS_FRAC_N_F_HIGH_CYC_CNT_SIZE 0x8
+#define XS1_SS_FRAC_N_F_HIGH_CYC_CNT_MASK         \
+  (((1 << XS1_SS_FRAC_N_F_HIGH_CYC_CNT_SIZE) - 1) \
+   << XS1_SS_FRAC_N_F_HIGH_CYC_CNT_SHIFT)
+#define XS1_SS_FRAC_N_F_HIGH_CYC_CNT(x)       \
+  (((x)&XS1_SS_FRAC_N_F_HIGH_CYC_CNT_MASK) >> \
+   XS1_SS_FRAC_N_F_HIGH_CYC_CNT_SHIFT)
+#define XS1_SS_FRAC_N_F_HIGH_CYC_CNT_SET(x, v)    \
+  (((x) & ~XS1_SS_FRAC_N_F_HIGH_CYC_CNT_MASK) |   \
+   (((v) << XS1_SS_FRAC_N_F_HIGH_CYC_CNT_SHIFT) & \
+    XS1_SS_FRAC_N_F_HIGH_CYC_CNT_MASK))
+#define XS1_SS_FRAC_N_ENABLE_SHIFT 0x1f
+#define XS1_SS_FRAC_N_ENABLE_SIZE 0x1
+#define XS1_SS_FRAC_N_ENABLE_MASK \
+  (((1 << XS1_SS_FRAC_N_ENABLE_SIZE) - 1) << XS1_SS_FRAC_N_ENABLE_SHIFT)
+#define XS1_SS_FRAC_N_ENABLE(x) \
+  (((x)&XS1_SS_FRAC_N_ENABLE_MASK) >> XS1_SS_FRAC_N_ENABLE_SHIFT)
+#define XS1_SS_FRAC_N_ENABLE_SET(x, v)  \
+  (((x) & ~XS1_SS_FRAC_N_ENABLE_MASK) | \
+   (((v) << XS1_SS_FRAC_N_ENABLE_SHIFT) & XS1_SS_FRAC_N_ENABLE_MASK))
+#define XS1_SS_PLL_CTL_NLOCK_SHIFT 0x1e
+#define XS1_SS_PLL_CTL_NRESET_SHIFT 0x1f
+#define XS1_SS_CLK_DIVIDER_CLK_DIV_SHIFT 0x0
+#define XS1_SS_CLK_DIVIDER_CLK_DIV_SIZE 0x10
+#define XS1_SS_CLK_DIVIDER_CLK_DIV_MASK         \
+  (((1 << XS1_SS_CLK_DIVIDER_CLK_DIV_SIZE) - 1) \
+   << XS1_SS_CLK_DIVIDER_CLK_DIV_SHIFT)
+#define XS1_SS_CLK_DIVIDER_CLK_DIV(x) \
+  (((x)&XS1_SS_CLK_DIVIDER_CLK_DIV_MASK) >> XS1_SS_CLK_DIVIDER_CLK_DIV_SHIFT)
+#define XS1_SS_CLK_DIVIDER_CLK_DIV_SET(x, v)    \
+  (((x) & ~XS1_SS_CLK_DIVIDER_CLK_DIV_MASK) |   \
+   (((v) << XS1_SS_CLK_DIVIDER_CLK_DIV_SHIFT) & \
+    XS1_SS_CLK_DIVIDER_CLK_DIV_MASK))
+#define XS1_SS_SSWITCH_REF_CLK_DIV_SHIFT 0x0
+#define XS1_SS_SSWITCH_REF_CLK_DIV_SIZE 0x10
+#define XS1_SS_SSWITCH_REF_CLK_DIV_MASK         \
+  (((1 << XS1_SS_SSWITCH_REF_CLK_DIV_SIZE) - 1) \
+   << XS1_SS_SSWITCH_REF_CLK_DIV_SHIFT)
+#define XS1_SS_SSWITCH_REF_CLK_DIV(x) \
+  (((x)&XS1_SS_SSWITCH_REF_CLK_DIV_MASK) >> XS1_SS_SSWITCH_REF_CLK_DIV_SHIFT)
+#define XS1_SS_SSWITCH_REF_CLK_DIV_SET(x, v)    \
+  (((x) & ~XS1_SS_SSWITCH_REF_CLK_DIV_MASK) |   \
+   (((v) << XS1_SS_SSWITCH_REF_CLK_DIV_SHIFT) & \
+    XS1_SS_SSWITCH_REF_CLK_DIV_MASK))
+#define XS1_DIM0_DIR_SHIFT 0x0
+#define XS1_DIM0_DIR_SIZE 0x4
+#define XS1_DIM0_DIR_MASK (((1 << XS1_DIM0_DIR_SIZE) - 1) << XS1_DIM0_DIR_SHIFT)
+#define XS1_DIM0_DIR(x) (((x)&XS1_DIM0_DIR_MASK) >> XS1_DIM0_DIR_SHIFT)
+#define XS1_DIM0_DIR_SET(x, v)  \
+  (((x) & ~XS1_DIM0_DIR_MASK) | \
+   (((v) << XS1_DIM0_DIR_SHIFT) & XS1_DIM0_DIR_MASK))
+#define XS1_DIM1_DIR_SHIFT 0x4
+#define XS1_DIM1_DIR_SIZE 0x4
+#define XS1_DIM1_DIR_MASK (((1 << XS1_DIM1_DIR_SIZE) - 1) << XS1_DIM1_DIR_SHIFT)
+#define XS1_DIM1_DIR(x) (((x)&XS1_DIM1_DIR_MASK) >> XS1_DIM1_DIR_SHIFT)
+#define XS1_DIM1_DIR_SET(x, v)  \
+  (((x) & ~XS1_DIM1_DIR_MASK) | \
+   (((v) << XS1_DIM1_DIR_SHIFT) & XS1_DIM1_DIR_MASK))
+#define XS1_DIM2_DIR_SHIFT 0x8
+#define XS1_DIM2_DIR_SIZE 0x4
+#define XS1_DIM2_DIR_MASK (((1 << XS1_DIM2_DIR_SIZE) - 1) << XS1_DIM2_DIR_SHIFT)
+#define XS1_DIM2_DIR(x) (((x)&XS1_DIM2_DIR_MASK) >> XS1_DIM2_DIR_SHIFT)
+#define XS1_DIM2_DIR_SET(x, v)  \
+  (((x) & ~XS1_DIM2_DIR_MASK) | \
+   (((v) << XS1_DIM2_DIR_SHIFT) & XS1_DIM2_DIR_MASK))
+#define XS1_DIM3_DIR_SHIFT 0xc
+#define XS1_DIM3_DIR_SIZE 0x4
+#define XS1_DIM3_DIR_MASK (((1 << XS1_DIM3_DIR_SIZE) - 1) << XS1_DIM3_DIR_SHIFT)
+#define XS1_DIM3_DIR(x) (((x)&XS1_DIM3_DIR_MASK) >> XS1_DIM3_DIR_SHIFT)
+#define XS1_DIM3_DIR_SET(x, v)  \
+  (((x) & ~XS1_DIM3_DIR_MASK) | \
+   (((v) << XS1_DIM3_DIR_SHIFT) & XS1_DIM3_DIR_MASK))
+#define XS1_DIM4_DIR_SHIFT 0x10
+#define XS1_DIM4_DIR_SIZE 0x4
+#define XS1_DIM4_DIR_MASK (((1 << XS1_DIM4_DIR_SIZE) - 1) << XS1_DIM4_DIR_SHIFT)
+#define XS1_DIM4_DIR(x) (((x)&XS1_DIM4_DIR_MASK) >> XS1_DIM4_DIR_SHIFT)
+#define XS1_DIM4_DIR_SET(x, v)  \
+  (((x) & ~XS1_DIM4_DIR_MASK) | \
+   (((v) << XS1_DIM4_DIR_SHIFT) & XS1_DIM4_DIR_MASK))
+#define XS1_DIM5_DIR_SHIFT 0x14
+#define XS1_DIM5_DIR_SIZE 0x4
+#define XS1_DIM5_DIR_MASK (((1 << XS1_DIM5_DIR_SIZE) - 1) << XS1_DIM5_DIR_SHIFT)
+#define XS1_DIM5_DIR(x) (((x)&XS1_DIM5_DIR_MASK) >> XS1_DIM5_DIR_SHIFT)
+#define XS1_DIM5_DIR_SET(x, v)  \
+  (((x) & ~XS1_DIM5_DIR_MASK) | \
+   (((v) << XS1_DIM5_DIR_SHIFT) & XS1_DIM5_DIR_MASK))
+#define XS1_DIM6_DIR_SHIFT 0x18
+#define XS1_DIM6_DIR_SIZE 0x4
+#define XS1_DIM6_DIR_MASK (((1 << XS1_DIM6_DIR_SIZE) - 1) << XS1_DIM6_DIR_SHIFT)
+#define XS1_DIM6_DIR(x) (((x)&XS1_DIM6_DIR_MASK) >> XS1_DIM6_DIR_SHIFT)
+#define XS1_DIM6_DIR_SET(x, v)  \
+  (((x) & ~XS1_DIM6_DIR_MASK) | \
+   (((v) << XS1_DIM6_DIR_SHIFT) & XS1_DIM6_DIR_MASK))
+#define XS1_DIM7_DIR_SHIFT 0x1c
+#define XS1_DIM7_DIR_SIZE 0x4
+#define XS1_DIM7_DIR_MASK (((1 << XS1_DIM7_DIR_SIZE) - 1) << XS1_DIM7_DIR_SHIFT)
+#define XS1_DIM7_DIR(x) (((x)&XS1_DIM7_DIR_MASK) >> XS1_DIM7_DIR_SHIFT)
+#define XS1_DIM7_DIR_SET(x, v)  \
+  (((x) & ~XS1_DIM7_DIR_MASK) | \
+   (((v) << XS1_DIM7_DIR_SHIFT) & XS1_DIM7_DIR_MASK))
+#define XS1_DIM8_DIR_SHIFT 0x0
+#define XS1_DIM8_DIR_SIZE 0x4
+#define XS1_DIM8_DIR_MASK (((1 << XS1_DIM8_DIR_SIZE) - 1) << XS1_DIM8_DIR_SHIFT)
+#define XS1_DIM8_DIR(x) (((x)&XS1_DIM8_DIR_MASK) >> XS1_DIM8_DIR_SHIFT)
+#define XS1_DIM8_DIR_SET(x, v)  \
+  (((x) & ~XS1_DIM8_DIR_MASK) | \
+   (((v) << XS1_DIM8_DIR_SHIFT) & XS1_DIM8_DIR_MASK))
+#define XS1_DIM9_DIR_SHIFT 0x4
+#define XS1_DIM9_DIR_SIZE 0x4
+#define XS1_DIM9_DIR_MASK (((1 << XS1_DIM9_DIR_SIZE) - 1) << XS1_DIM9_DIR_SHIFT)
+#define XS1_DIM9_DIR(x) (((x)&XS1_DIM9_DIR_MASK) >> XS1_DIM9_DIR_SHIFT)
+#define XS1_DIM9_DIR_SET(x, v)  \
+  (((x) & ~XS1_DIM9_DIR_MASK) | \
+   (((v) << XS1_DIM9_DIR_SHIFT) & XS1_DIM9_DIR_MASK))
+#define XS1_DIMA_DIR_SHIFT 0x8
+#define XS1_DIMA_DIR_SIZE 0x4
+#define XS1_DIMA_DIR_MASK (((1 << XS1_DIMA_DIR_SIZE) - 1) << XS1_DIMA_DIR_SHIFT)
+#define XS1_DIMA_DIR(x) (((x)&XS1_DIMA_DIR_MASK) >> XS1_DIMA_DIR_SHIFT)
+#define XS1_DIMA_DIR_SET(x, v)  \
+  (((x) & ~XS1_DIMA_DIR_MASK) | \
+   (((v) << XS1_DIMA_DIR_SHIFT) & XS1_DIMA_DIR_MASK))
+#define XS1_DIMB_DIR_SHIFT 0xc
+#define XS1_DIMB_DIR_SIZE 0x4
+#define XS1_DIMB_DIR_MASK (((1 << XS1_DIMB_DIR_SIZE) - 1) << XS1_DIMB_DIR_SHIFT)
+#define XS1_DIMB_DIR(x) (((x)&XS1_DIMB_DIR_MASK) >> XS1_DIMB_DIR_SHIFT)
+#define XS1_DIMB_DIR_SET(x, v)  \
+  (((x) & ~XS1_DIMB_DIR_MASK) | \
+   (((v) << XS1_DIMB_DIR_SHIFT) & XS1_DIMB_DIR_MASK))
+#define XS1_DIMC_DIR_SHIFT 0x10
+#define XS1_DIMC_DIR_SIZE 0x4
+#define XS1_DIMC_DIR_MASK (((1 << XS1_DIMC_DIR_SIZE) - 1) << XS1_DIMC_DIR_SHIFT)
+#define XS1_DIMC_DIR(x) (((x)&XS1_DIMC_DIR_MASK) >> XS1_DIMC_DIR_SHIFT)
+#define XS1_DIMC_DIR_SET(x, v)  \
+  (((x) & ~XS1_DIMC_DIR_MASK) | \
+   (((v) << XS1_DIMC_DIR_SHIFT) & XS1_DIMC_DIR_MASK))
+#define XS1_DIMD_DIR_SHIFT 0x14
+#define XS1_DIMD_DIR_SIZE 0x4
+#define XS1_DIMD_DIR_MASK (((1 << XS1_DIMD_DIR_SIZE) - 1) << XS1_DIMD_DIR_SHIFT)
+#define XS1_DIMD_DIR(x) (((x)&XS1_DIMD_DIR_MASK) >> XS1_DIMD_DIR_SHIFT)
+#define XS1_DIMD_DIR_SET(x, v)  \
+  (((x) & ~XS1_DIMD_DIR_MASK) | \
+   (((v) << XS1_DIMD_DIR_SHIFT) & XS1_DIMD_DIR_MASK))
+#define XS1_DIME_DIR_SHIFT 0x18
+#define XS1_DIME_DIR_SIZE 0x4
+#define XS1_DIME_DIR_MASK (((1 << XS1_DIME_DIR_SIZE) - 1) << XS1_DIME_DIR_SHIFT)
+#define XS1_DIME_DIR(x) (((x)&XS1_DIME_DIR_MASK) >> XS1_DIME_DIR_SHIFT)
+#define XS1_DIME_DIR_SET(x, v)  \
+  (((x) & ~XS1_DIME_DIR_MASK) | \
+   (((v) << XS1_DIME_DIR_SHIFT) & XS1_DIME_DIR_MASK))
+#define XS1_DIMF_DIR_SHIFT 0x1c
+#define XS1_DIMF_DIR_SIZE 0x4
+#define XS1_DIMF_DIR_MASK (((1 << XS1_DIMF_DIR_SIZE) - 1) << XS1_DIMF_DIR_SHIFT)
+#define XS1_DIMF_DIR(x) (((x)&XS1_DIMF_DIR_MASK) >> XS1_DIMF_DIR_SHIFT)
+#define XS1_DIMF_DIR_SET(x, v)  \
+  (((x) & ~XS1_DIMF_DIR_MASK) | \
+   (((v) << XS1_DIMF_DIR_SHIFT) & XS1_DIMF_DIR_MASK))
+#define XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_SHIFT 0x0
+#define XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_SIZE 0x1
+#define XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_MASK         \
+  (((1 << XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_SIZE) - 1) \
+   << XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_SHIFT)
+#define XS1_GLOBAL_DEBUG_ENABLE_INDEBUG(x)       \
+  (((x)&XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_MASK) >> \
+   XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_SHIFT)
+#define XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_SET(x, v)    \
+  (((x) & ~XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_MASK) |   \
+   (((v) << XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_SHIFT) & \
+    XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_MASK))
+#define XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_SHIFT 0x1
+#define XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_SIZE 0x1
+#define XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_MASK         \
+  (((1 << XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_SIZE) - 1) \
+   << XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_SHIFT)
+#define XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ(x)       \
+  (((x)&XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_MASK) >> \
+   XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_SHIFT)
+#define XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_SET(x, v)    \
+  (((x) & ~XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_MASK) |   \
+   (((v) << XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_SHIFT) & \
+    XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_MASK))
+#define XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_SHIFT 0x0
+#define XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_SIZE 0x1
+#define XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_MASK         \
+  (((1 << XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_SIZE) - 1) \
+   << XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_SHIFT)
+#define XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG(x)       \
+  (((x)&XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_MASK) >> \
+   XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_SHIFT)
+#define XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_SET(x, v)    \
+  (((x) & ~XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_MASK) |   \
+   (((v) << XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_SHIFT) & \
+    XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_MASK))
+#define XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_SHIFT 0x1
+#define XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_SIZE 0x1
+#define XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_MASK         \
+  (((1 << XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_SIZE) - 1) \
+   << XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_SHIFT)
+#define XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG(x)       \
+  (((x)&XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_MASK) >> \
+   XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_SHIFT)
+#define XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_SET(x, v)    \
+  (((x) & ~XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_MASK) |   \
+   (((v) << XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_SHIFT) & \
+    XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_MASK))
+#define XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_SHIFT 0x4
+#define XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_SIZE 0x1
+#define XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_MASK         \
+  (((1 << XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_SIZE) - 1) \
+   << XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_SHIFT)
+#define XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG(x)       \
+  (((x)&XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_MASK) >> \
+   XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_SHIFT)
+#define XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_SET(x, v)    \
+  (((x) & ~XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_MASK) |   \
+   (((v) << XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_SHIFT) & \
+    XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_MASK))
+#define XS1_LINK_SRC_INUSE_SHIFT 0x0
+#define XS1_LINK_SRC_INUSE_SIZE 0x1
+#define XS1_LINK_SRC_INUSE_MASK \
+  (((1 << XS1_LINK_SRC_INUSE_SIZE) - 1) << XS1_LINK_SRC_INUSE_SHIFT)
+#define XS1_LINK_SRC_INUSE(x) \
+  (((x)&XS1_LINK_SRC_INUSE_MASK) >> XS1_LINK_SRC_INUSE_SHIFT)
+#define XS1_LINK_SRC_INUSE_SET(x, v)  \
+  (((x) & ~XS1_LINK_SRC_INUSE_MASK) | \
+   (((v) << XS1_LINK_SRC_INUSE_SHIFT) & XS1_LINK_SRC_INUSE_MASK))
+#define XS1_LINK_DST_INUSE_SHIFT 0x1
+#define XS1_LINK_DST_INUSE_SIZE 0x1
+#define XS1_LINK_DST_INUSE_MASK \
+  (((1 << XS1_LINK_DST_INUSE_SIZE) - 1) << XS1_LINK_DST_INUSE_SHIFT)
+#define XS1_LINK_DST_INUSE(x) \
+  (((x)&XS1_LINK_DST_INUSE_MASK) >> XS1_LINK_DST_INUSE_SHIFT)
+#define XS1_LINK_DST_INUSE_SET(x, v)  \
+  (((x) & ~XS1_LINK_DST_INUSE_MASK) | \
+   (((v) << XS1_LINK_DST_INUSE_SHIFT) & XS1_LINK_DST_INUSE_MASK))
+#define XS1_LINK_JUNK_SHIFT 0x2
+#define XS1_LINK_JUNK_SIZE 0x1
+#define XS1_LINK_JUNK_MASK \
+  (((1 << XS1_LINK_JUNK_SIZE) - 1) << XS1_LINK_JUNK_SHIFT)
+#define XS1_LINK_JUNK(x) (((x)&XS1_LINK_JUNK_MASK) >> XS1_LINK_JUNK_SHIFT)
+#define XS1_LINK_JUNK_SET(x, v)  \
+  (((x) & ~XS1_LINK_JUNK_MASK) | \
+   (((v) << XS1_LINK_JUNK_SHIFT) & XS1_LINK_JUNK_MASK))
+#define XS1_LINK_NETWORK_SHIFT 0x4
+#define XS1_LINK_NETWORK_SIZE 0x2
+#define XS1_LINK_NETWORK_MASK \
+  (((1 << XS1_LINK_NETWORK_SIZE) - 1) << XS1_LINK_NETWORK_SHIFT)
+#define XS1_LINK_NETWORK(x) \
+  (((x)&XS1_LINK_NETWORK_MASK) >> XS1_LINK_NETWORK_SHIFT)
+#define XS1_LINK_NETWORK_SET(x, v)  \
+  (((x) & ~XS1_LINK_NETWORK_MASK) | \
+   (((v) << XS1_LINK_NETWORK_SHIFT) & XS1_LINK_NETWORK_MASK))
+#define XS1_LINK_DIRECTION_SHIFT 0x8
+#define XS1_LINK_DIRECTION_SIZE 0x4
+#define XS1_LINK_DIRECTION_MASK \
+  (((1 << XS1_LINK_DIRECTION_SIZE) - 1) << XS1_LINK_DIRECTION_SHIFT)
+#define XS1_LINK_DIRECTION(x) \
+  (((x)&XS1_LINK_DIRECTION_MASK) >> XS1_LINK_DIRECTION_SHIFT)
+#define XS1_LINK_DIRECTION_SET(x, v)  \
+  (((x) & ~XS1_LINK_DIRECTION_MASK) | \
+   (((v) << XS1_LINK_DIRECTION_SHIFT) & XS1_LINK_DIRECTION_MASK))
+#define XS1_XLINK_INTER_TOKEN_DELAY_SHIFT 0x0
+#define XS1_XLINK_INTER_TOKEN_DELAY_SIZE 0xb
+#define XS1_XLINK_INTER_TOKEN_DELAY_MASK         \
+  (((1 << XS1_XLINK_INTER_TOKEN_DELAY_SIZE) - 1) \
+   << XS1_XLINK_INTER_TOKEN_DELAY_SHIFT)
+#define XS1_XLINK_INTER_TOKEN_DELAY(x) \
+  (((x)&XS1_XLINK_INTER_TOKEN_DELAY_MASK) >> XS1_XLINK_INTER_TOKEN_DELAY_SHIFT)
+#define XS1_XLINK_INTER_TOKEN_DELAY_SET(x, v)    \
+  (((x) & ~XS1_XLINK_INTER_TOKEN_DELAY_MASK) |   \
+   (((v) << XS1_XLINK_INTER_TOKEN_DELAY_SHIFT) & \
+    XS1_XLINK_INTER_TOKEN_DELAY_MASK))
+#define XS1_XLINK_INTRA_TOKEN_DELAY_SHIFT 0xb
+#define XS1_XLINK_INTRA_TOKEN_DELAY_SIZE 0xb
+#define XS1_XLINK_INTRA_TOKEN_DELAY_MASK         \
+  (((1 << XS1_XLINK_INTRA_TOKEN_DELAY_SIZE) - 1) \
+   << XS1_XLINK_INTRA_TOKEN_DELAY_SHIFT)
+#define XS1_XLINK_INTRA_TOKEN_DELAY(x) \
+  (((x)&XS1_XLINK_INTRA_TOKEN_DELAY_MASK) >> XS1_XLINK_INTRA_TOKEN_DELAY_SHIFT)
+#define XS1_XLINK_INTRA_TOKEN_DELAY_SET(x, v)    \
+  (((x) & ~XS1_XLINK_INTRA_TOKEN_DELAY_MASK) |   \
+   (((v) << XS1_XLINK_INTRA_TOKEN_DELAY_SHIFT) & \
+    XS1_XLINK_INTRA_TOKEN_DELAY_MASK))
+#define XS1_XLINK_RX_RESET_SHIFT 0x17
+#define XS1_XLINK_RX_RESET_SIZE 0x1
+#define XS1_XLINK_RX_RESET_MASK \
+  (((1 << XS1_XLINK_RX_RESET_SIZE) - 1) << XS1_XLINK_RX_RESET_SHIFT)
+#define XS1_XLINK_RX_RESET(x) \
+  (((x)&XS1_XLINK_RX_RESET_MASK) >> XS1_XLINK_RX_RESET_SHIFT)
+#define XS1_XLINK_RX_RESET_SET(x, v)  \
+  (((x) & ~XS1_XLINK_RX_RESET_MASK) | \
+   (((v) << XS1_XLINK_RX_RESET_SHIFT) & XS1_XLINK_RX_RESET_MASK))
+#define XS1_XLINK_HELLO_SHIFT 0x18
+#define XS1_XLINK_HELLO_SIZE 0x1
+#define XS1_XLINK_HELLO_MASK \
+  (((1 << XS1_XLINK_HELLO_SIZE) - 1) << XS1_XLINK_HELLO_SHIFT)
+#define XS1_XLINK_HELLO(x) (((x)&XS1_XLINK_HELLO_MASK) >> XS1_XLINK_HELLO_SHIFT)
+#define XS1_XLINK_HELLO_SET(x, v)  \
+  (((x) & ~XS1_XLINK_HELLO_MASK) | \
+   (((v) << XS1_XLINK_HELLO_SHIFT) & XS1_XLINK_HELLO_MASK))
+#define XS1_TX_CREDIT_SHIFT 0x19
+#define XS1_TX_CREDIT_SIZE 0x1
+#define XS1_TX_CREDIT_MASK \
+  (((1 << XS1_TX_CREDIT_SIZE) - 1) << XS1_TX_CREDIT_SHIFT)
+#define XS1_TX_CREDIT(x) (((x)&XS1_TX_CREDIT_MASK) >> XS1_TX_CREDIT_SHIFT)
+#define XS1_TX_CREDIT_SET(x, v)  \
+  (((x) & ~XS1_TX_CREDIT_MASK) | \
+   (((v) << XS1_TX_CREDIT_SHIFT) & XS1_TX_CREDIT_MASK))
+#define XS1_RX_CREDIT_SHIFT 0x1a
+#define XS1_RX_CREDIT_SIZE 0x1
+#define XS1_RX_CREDIT_MASK \
+  (((1 << XS1_RX_CREDIT_SIZE) - 1) << XS1_RX_CREDIT_SHIFT)
+#define XS1_RX_CREDIT(x) (((x)&XS1_RX_CREDIT_MASK) >> XS1_RX_CREDIT_SHIFT)
+#define XS1_RX_CREDIT_SET(x, v)  \
+  (((x) & ~XS1_RX_CREDIT_MASK) | \
+   (((v) << XS1_RX_CREDIT_SHIFT) & XS1_RX_CREDIT_MASK))
+#define XS1_XLINK_RX_ERROR_SHIFT 0x1b
+#define XS1_XLINK_RX_ERROR_SIZE 0x1
+#define XS1_XLINK_RX_ERROR_MASK \
+  (((1 << XS1_XLINK_RX_ERROR_SIZE) - 1) << XS1_XLINK_RX_ERROR_SHIFT)
+#define XS1_XLINK_RX_ERROR(x) \
+  (((x)&XS1_XLINK_RX_ERROR_MASK) >> XS1_XLINK_RX_ERROR_SHIFT)
+#define XS1_XLINK_RX_ERROR_SET(x, v)  \
+  (((x) & ~XS1_XLINK_RX_ERROR_MASK) | \
+   (((v) << XS1_XLINK_RX_ERROR_SHIFT) & XS1_XLINK_RX_ERROR_MASK))
+#define XS1_XLINK_WIDE_SHIFT 0x1e
+#define XS1_XLINK_WIDE_SIZE 0x1
+#define XS1_XLINK_WIDE_MASK \
+  (((1 << XS1_XLINK_WIDE_SIZE) - 1) << XS1_XLINK_WIDE_SHIFT)
+#define XS1_XLINK_WIDE(x) (((x)&XS1_XLINK_WIDE_MASK) >> XS1_XLINK_WIDE_SHIFT)
+#define XS1_XLINK_WIDE_SET(x, v)  \
+  (((x) & ~XS1_XLINK_WIDE_MASK) | \
+   (((v) << XS1_XLINK_WIDE_SHIFT) & XS1_XLINK_WIDE_MASK))
+#define XS1_XLINK_ENABLE_SHIFT 0x1f
+#define XS1_XLINK_ENABLE_SIZE 0x1
+#define XS1_XLINK_ENABLE_MASK \
+  (((1 << XS1_XLINK_ENABLE_SIZE) - 1) << XS1_XLINK_ENABLE_SHIFT)
+#define XS1_XLINK_ENABLE(x) \
+  (((x)&XS1_XLINK_ENABLE_MASK) >> XS1_XLINK_ENABLE_SHIFT)
+#define XS1_XLINK_ENABLE_SET(x, v)  \
+  (((x) & ~XS1_XLINK_ENABLE_MASK) | \
+   (((v) << XS1_XLINK_ENABLE_SHIFT) & XS1_XLINK_ENABLE_MASK))
+#define XS1_XSTATIC_DEST_CHAN_END_SHIFT 0x0
+#define XS1_XSTATIC_DEST_CHAN_END_SIZE 0x5
+#define XS1_XSTATIC_DEST_CHAN_END_MASK         \
+  (((1 << XS1_XSTATIC_DEST_CHAN_END_SIZE) - 1) \
+   << XS1_XSTATIC_DEST_CHAN_END_SHIFT)
+#define XS1_XSTATIC_DEST_CHAN_END(x) \
+  (((x)&XS1_XSTATIC_DEST_CHAN_END_MASK) >> XS1_XSTATIC_DEST_CHAN_END_SHIFT)
+#define XS1_XSTATIC_DEST_CHAN_END_SET(x, v)    \
+  (((x) & ~XS1_XSTATIC_DEST_CHAN_END_MASK) |   \
+   (((v) << XS1_XSTATIC_DEST_CHAN_END_SHIFT) & \
+    XS1_XSTATIC_DEST_CHAN_END_MASK))
+#define XS1_XSTATIC_ENABLE_SHIFT 0x1f
+#define XS1_XSTATIC_ENABLE_SIZE 0x1
+#define XS1_XSTATIC_ENABLE_MASK \
+  (((1 << XS1_XSTATIC_ENABLE_SIZE) - 1) << XS1_XSTATIC_ENABLE_SHIFT)
+#define XS1_XSTATIC_ENABLE(x) \
+  (((x)&XS1_XSTATIC_ENABLE_MASK) >> XS1_XSTATIC_ENABLE_SHIFT)
+#define XS1_XSTATIC_ENABLE_SET(x, v)  \
+  (((x) & ~XS1_XSTATIC_ENABLE_MASK) | \
+   (((v) << XS1_XSTATIC_ENABLE_SHIFT) & XS1_XSTATIC_ENABLE_MASK))
+#define XS1_SSCTRL_PSCTRL_CORE_NUM_SHIFT 0x8
+#define XS1_SSCTRL_PSCTRL_CORE_NUM_SIZE 0x8
+#define XS1_SSCTRL_PSCTRL_CORE_NUM_MASK         \
+  (((1 << XS1_SSCTRL_PSCTRL_CORE_NUM_SIZE) - 1) \
+   << XS1_SSCTRL_PSCTRL_CORE_NUM_SHIFT)
+#define XS1_SSCTRL_PSCTRL_CORE_NUM(x) \
+  (((x)&XS1_SSCTRL_PSCTRL_CORE_NUM_MASK) >> XS1_SSCTRL_PSCTRL_CORE_NUM_SHIFT)
+#define XS1_SSCTRL_PSCTRL_CORE_NUM_SET(x, v)    \
+  (((x) & ~XS1_SSCTRL_PSCTRL_CORE_NUM_MASK) |   \
+   (((v) << XS1_SSCTRL_PSCTRL_CORE_NUM_SHIFT) & \
+    XS1_SSCTRL_PSCTRL_CORE_NUM_MASK))
+#define XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_SHIFT 0x0
+#define XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_SIZE 0x2
+#define XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_MASK         \
+  (((1 << XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_SIZE) - 1) \
+   << XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_SHIFT)
+#define XS1_USB_PHY_CFG0_UTMI_XCVRSELECT(x)       \
+  (((x)&XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_MASK) >> \
+   XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_SHIFT)
+#define XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_SET(x, v)    \
+  (((x) & ~XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_MASK) |   \
+   (((v) << XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_SHIFT) & \
+    XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_MASK))
+#define XS1_USB_PHY_CFG0_UTMI_TERMSELECT_SHIFT 0x2
+#define XS1_USB_PHY_CFG0_UTMI_TERMSELECT_SIZE 0x1
+#define XS1_USB_PHY_CFG0_UTMI_TERMSELECT_MASK         \
+  (((1 << XS1_USB_PHY_CFG0_UTMI_TERMSELECT_SIZE) - 1) \
+   << XS1_USB_PHY_CFG0_UTMI_TERMSELECT_SHIFT)
+#define XS1_USB_PHY_CFG0_UTMI_TERMSELECT(x)       \
+  (((x)&XS1_USB_PHY_CFG0_UTMI_TERMSELECT_MASK) >> \
+   XS1_USB_PHY_CFG0_UTMI_TERMSELECT_SHIFT)
+#define XS1_USB_PHY_CFG0_UTMI_TERMSELECT_SET(x, v)    \
+  (((x) & ~XS1_USB_PHY_CFG0_UTMI_TERMSELECT_MASK) |   \
+   (((v) << XS1_USB_PHY_CFG0_UTMI_TERMSELECT_SHIFT) & \
+    XS1_USB_PHY_CFG0_UTMI_TERMSELECT_MASK))
+#define XS1_USB_PHY_CFG0_UTMI_OPMODE_SHIFT 0x3
+#define XS1_USB_PHY_CFG0_UTMI_OPMODE_SIZE 0x2
+#define XS1_USB_PHY_CFG0_UTMI_OPMODE_MASK         \
+  (((1 << XS1_USB_PHY_CFG0_UTMI_OPMODE_SIZE) - 1) \
+   << XS1_USB_PHY_CFG0_UTMI_OPMODE_SHIFT)
+#define XS1_USB_PHY_CFG0_UTMI_OPMODE(x)       \
+  (((x)&XS1_USB_PHY_CFG0_UTMI_OPMODE_MASK) >> \
+   XS1_USB_PHY_CFG0_UTMI_OPMODE_SHIFT)
+#define XS1_USB_PHY_CFG0_UTMI_OPMODE_SET(x, v)    \
+  (((x) & ~XS1_USB_PHY_CFG0_UTMI_OPMODE_MASK) |   \
+   (((v) << XS1_USB_PHY_CFG0_UTMI_OPMODE_SHIFT) & \
+    XS1_USB_PHY_CFG0_UTMI_OPMODE_MASK))
+#define XS1_USB_PHY_CFG0_UTMI_SUSPENDM_SHIFT 0x5
+#define XS1_USB_PHY_CFG0_UTMI_SUSPENDM_SIZE 0x1
+#define XS1_USB_PHY_CFG0_UTMI_SUSPENDM_MASK         \
+  (((1 << XS1_USB_PHY_CFG0_UTMI_SUSPENDM_SIZE) - 1) \
+   << XS1_USB_PHY_CFG0_UTMI_SUSPENDM_SHIFT)
+#define XS1_USB_PHY_CFG0_UTMI_SUSPENDM(x)       \
+  (((x)&XS1_USB_PHY_CFG0_UTMI_SUSPENDM_MASK) >> \
+   XS1_USB_PHY_CFG0_UTMI_SUSPENDM_SHIFT)
+#define XS1_USB_PHY_CFG0_UTMI_SUSPENDM_SET(x, v)    \
+  (((x) & ~XS1_USB_PHY_CFG0_UTMI_SUSPENDM_MASK) |   \
+   (((v) << XS1_USB_PHY_CFG0_UTMI_SUSPENDM_SHIFT) & \
+    XS1_USB_PHY_CFG0_UTMI_SUSPENDM_MASK))
+#define XS1_USB_PHY_CFG0_DPPULLDOWN_SHIFT 0x6
+#define XS1_USB_PHY_CFG0_DPPULLDOWN_SIZE 0x1
+#define XS1_USB_PHY_CFG0_DPPULLDOWN_MASK         \
+  (((1 << XS1_USB_PHY_CFG0_DPPULLDOWN_SIZE) - 1) \
+   << XS1_USB_PHY_CFG0_DPPULLDOWN_SHIFT)
+#define XS1_USB_PHY_CFG0_DPPULLDOWN(x) \
+  (((x)&XS1_USB_PHY_CFG0_DPPULLDOWN_MASK) >> XS1_USB_PHY_CFG0_DPPULLDOWN_SHIFT)
+#define XS1_USB_PHY_CFG0_DPPULLDOWN_SET(x, v)    \
+  (((x) & ~XS1_USB_PHY_CFG0_DPPULLDOWN_MASK) |   \
+   (((v) << XS1_USB_PHY_CFG0_DPPULLDOWN_SHIFT) & \
+    XS1_USB_PHY_CFG0_DPPULLDOWN_MASK))
+#define XS1_USB_PHY_CFG0_DMPULLDOWN_SHIFT 0x7
+#define XS1_USB_PHY_CFG0_DMPULLDOWN_SIZE 0x1
+#define XS1_USB_PHY_CFG0_DMPULLDOWN_MASK         \
+  (((1 << XS1_USB_PHY_CFG0_DMPULLDOWN_SIZE) - 1) \
+   << XS1_USB_PHY_CFG0_DMPULLDOWN_SHIFT)
+#define XS1_USB_PHY_CFG0_DMPULLDOWN(x) \
+  (((x)&XS1_USB_PHY_CFG0_DMPULLDOWN_MASK) >> XS1_USB_PHY_CFG0_DMPULLDOWN_SHIFT)
+#define XS1_USB_PHY_CFG0_DMPULLDOWN_SET(x, v)    \
+  (((x) & ~XS1_USB_PHY_CFG0_DMPULLDOWN_MASK) |   \
+   (((v) << XS1_USB_PHY_CFG0_DMPULLDOWN_SHIFT) & \
+    XS1_USB_PHY_CFG0_DMPULLDOWN_MASK))
+#define XS1_USB_PHY_CFG0_TXBITSTUFF_EN_SHIFT 0x8
+#define XS1_USB_PHY_CFG0_TXBITSTUFF_EN_SIZE 0x1
+#define XS1_USB_PHY_CFG0_TXBITSTUFF_EN_MASK         \
+  (((1 << XS1_USB_PHY_CFG0_TXBITSTUFF_EN_SIZE) - 1) \
+   << XS1_USB_PHY_CFG0_TXBITSTUFF_EN_SHIFT)
+#define XS1_USB_PHY_CFG0_TXBITSTUFF_EN(x)       \
+  (((x)&XS1_USB_PHY_CFG0_TXBITSTUFF_EN_MASK) >> \
+   XS1_USB_PHY_CFG0_TXBITSTUFF_EN_SHIFT)
+#define XS1_USB_PHY_CFG0_TXBITSTUFF_EN_SET(x, v)    \
+  (((x) & ~XS1_USB_PHY_CFG0_TXBITSTUFF_EN_MASK) |   \
+   (((v) << XS1_USB_PHY_CFG0_TXBITSTUFF_EN_SHIFT) & \
+    XS1_USB_PHY_CFG0_TXBITSTUFF_EN_MASK))
+#define XS1_USB_PHY_CFG0_PLL_EN_SHIFT 0x9
+#define XS1_USB_PHY_CFG0_PLL_EN_SIZE 0x1
+#define XS1_USB_PHY_CFG0_PLL_EN_MASK \
+  (((1 << XS1_USB_PHY_CFG0_PLL_EN_SIZE) - 1) << XS1_USB_PHY_CFG0_PLL_EN_SHIFT)
+#define XS1_USB_PHY_CFG0_PLL_EN(x) \
+  (((x)&XS1_USB_PHY_CFG0_PLL_EN_MASK) >> XS1_USB_PHY_CFG0_PLL_EN_SHIFT)
+#define XS1_USB_PHY_CFG0_PLL_EN_SET(x, v)  \
+  (((x) & ~XS1_USB_PHY_CFG0_PLL_EN_MASK) | \
+   (((v) << XS1_USB_PHY_CFG0_PLL_EN_SHIFT) & XS1_USB_PHY_CFG0_PLL_EN_MASK))
+#define XS1_USB_PHY_CFG0_LPM_ALIVE_SHIFT 0xa
+#define XS1_USB_PHY_CFG0_LPM_ALIVE_SIZE 0x1
+#define XS1_USB_PHY_CFG0_LPM_ALIVE_MASK         \
+  (((1 << XS1_USB_PHY_CFG0_LPM_ALIVE_SIZE) - 1) \
+   << XS1_USB_PHY_CFG0_LPM_ALIVE_SHIFT)
+#define XS1_USB_PHY_CFG0_LPM_ALIVE(x) \
+  (((x)&XS1_USB_PHY_CFG0_LPM_ALIVE_MASK) >> XS1_USB_PHY_CFG0_LPM_ALIVE_SHIFT)
+#define XS1_USB_PHY_CFG0_LPM_ALIVE_SET(x, v)    \
+  (((x) & ~XS1_USB_PHY_CFG0_LPM_ALIVE_MASK) |   \
+   (((v) << XS1_USB_PHY_CFG0_LPM_ALIVE_SHIFT) & \
+    XS1_USB_PHY_CFG0_LPM_ALIVE_MASK))
+#define XS1_USB_PHY_CFG0_IDPAD_EN_SHIFT 0xb
+#define XS1_USB_PHY_CFG0_IDPAD_EN_SIZE 0x1
+#define XS1_USB_PHY_CFG0_IDPAD_EN_MASK         \
+  (((1 << XS1_USB_PHY_CFG0_IDPAD_EN_SIZE) - 1) \
+   << XS1_USB_PHY_CFG0_IDPAD_EN_SHIFT)
+#define XS1_USB_PHY_CFG0_IDPAD_EN(x) \
+  (((x)&XS1_USB_PHY_CFG0_IDPAD_EN_MASK) >> XS1_USB_PHY_CFG0_IDPAD_EN_SHIFT)
+#define XS1_USB_PHY_CFG0_IDPAD_EN_SET(x, v)    \
+  (((x) & ~XS1_USB_PHY_CFG0_IDPAD_EN_MASK) |   \
+   (((v) << XS1_USB_PHY_CFG0_IDPAD_EN_SHIFT) & \
+    XS1_USB_PHY_CFG0_IDPAD_EN_MASK))
+#define XS1_USB_PHY_CFG0_XTLSEL_SHIFT 0xc
+#define XS1_USB_PHY_CFG0_XTLSEL_SIZE 0x3
+#define XS1_USB_PHY_CFG0_XTLSEL_MASK \
+  (((1 << XS1_USB_PHY_CFG0_XTLSEL_SIZE) - 1) << XS1_USB_PHY_CFG0_XTLSEL_SHIFT)
+#define XS1_USB_PHY_CFG0_XTLSEL(x) \
+  (((x)&XS1_USB_PHY_CFG0_XTLSEL_MASK) >> XS1_USB_PHY_CFG0_XTLSEL_SHIFT)
+#define XS1_USB_PHY_CFG0_XTLSEL_SET(x, v)  \
+  (((x) & ~XS1_USB_PHY_CFG0_XTLSEL_MASK) | \
+   (((v) << XS1_USB_PHY_CFG0_XTLSEL_SHIFT) & XS1_USB_PHY_CFG0_XTLSEL_MASK))
+#define XS1_USB_PHY_CFG2_PONRST_SHIFT 0x0
+#define XS1_USB_PHY_CFG2_PONRST_SIZE 0x1
+#define XS1_USB_PHY_CFG2_PONRST_MASK \
+  (((1 << XS1_USB_PHY_CFG2_PONRST_SIZE) - 1) << XS1_USB_PHY_CFG2_PONRST_SHIFT)
+#define XS1_USB_PHY_CFG2_PONRST(x) \
+  (((x)&XS1_USB_PHY_CFG2_PONRST_MASK) >> XS1_USB_PHY_CFG2_PONRST_SHIFT)
+#define XS1_USB_PHY_CFG2_PONRST_SET(x, v)  \
+  (((x) & ~XS1_USB_PHY_CFG2_PONRST_MASK) | \
+   (((v) << XS1_USB_PHY_CFG2_PONRST_SHIFT) & XS1_USB_PHY_CFG2_PONRST_MASK))
+#define XS1_USB_PHY_CFG2_UTMI_RESET_SHIFT 0x1
+#define XS1_USB_PHY_CFG2_UTMI_RESET_SIZE 0x1
+#define XS1_USB_PHY_CFG2_UTMI_RESET_MASK         \
+  (((1 << XS1_USB_PHY_CFG2_UTMI_RESET_SIZE) - 1) \
+   << XS1_USB_PHY_CFG2_UTMI_RESET_SHIFT)
+#define XS1_USB_PHY_CFG2_UTMI_RESET(x) \
+  (((x)&XS1_USB_PHY_CFG2_UTMI_RESET_MASK) >> XS1_USB_PHY_CFG2_UTMI_RESET_SHIFT)
+#define XS1_USB_PHY_CFG2_UTMI_RESET_SET(x, v)    \
+  (((x) & ~XS1_USB_PHY_CFG2_UTMI_RESET_MASK) |   \
+   (((v) << XS1_USB_PHY_CFG2_UTMI_RESET_SHIFT) & \
+    XS1_USB_PHY_CFG2_UTMI_RESET_MASK))
+#define XS1_USB_PHY_CFG3_VCONTROL_SHIFT 0x0
+#define XS1_USB_PHY_CFG3_VCONTROL_SIZE 0x4
+#define XS1_USB_PHY_CFG3_VCONTROL_MASK         \
+  (((1 << XS1_USB_PHY_CFG3_VCONTROL_SIZE) - 1) \
+   << XS1_USB_PHY_CFG3_VCONTROL_SHIFT)
+#define XS1_USB_PHY_CFG3_VCONTROL(x) \
+  (((x)&XS1_USB_PHY_CFG3_VCONTROL_MASK) >> XS1_USB_PHY_CFG3_VCONTROL_SHIFT)
+#define XS1_USB_PHY_CFG3_VCONTROL_SET(x, v)    \
+  (((x) & ~XS1_USB_PHY_CFG3_VCONTROL_MASK) |   \
+   (((v) << XS1_USB_PHY_CFG3_VCONTROL_SHIFT) & \
+    XS1_USB_PHY_CFG3_VCONTROL_MASK))
+#define XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_SHIFT 0x4
+#define XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_SIZE 0x1
+#define XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_MASK         \
+  (((1 << XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_SIZE) - 1) \
+   << XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_SHIFT)
+#define XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE(x)       \
+  (((x)&XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_MASK) >> \
+   XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_SHIFT)
+#define XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_SET(x, v)    \
+  (((x) & ~XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_MASK) |   \
+   (((v) << XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_SHIFT) & \
+    XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_MASK))
+#define XS1_USB_PHY_CFG3_LS_EN_SHIFT 0x5
+#define XS1_USB_PHY_CFG3_LS_EN_SIZE 0x1
+#define XS1_USB_PHY_CFG3_LS_EN_MASK \
+  (((1 << XS1_USB_PHY_CFG3_LS_EN_SIZE) - 1) << XS1_USB_PHY_CFG3_LS_EN_SHIFT)
+#define XS1_USB_PHY_CFG3_LS_EN(x) \
+  (((x)&XS1_USB_PHY_CFG3_LS_EN_MASK) >> XS1_USB_PHY_CFG3_LS_EN_SHIFT)
+#define XS1_USB_PHY_CFG3_LS_EN_SET(x, v)  \
+  (((x) & ~XS1_USB_PHY_CFG3_LS_EN_MASK) | \
+   (((v) << XS1_USB_PHY_CFG3_LS_EN_SHIFT) & XS1_USB_PHY_CFG3_LS_EN_MASK))
+#define XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_SHIFT 0x6
+#define XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_SIZE 0x1
+#define XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_MASK         \
+  (((1 << XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_SIZE) - 1) \
+   << XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_SHIFT)
+#define XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM(x)       \
+  (((x)&XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_MASK) >> \
+   XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_SHIFT)
+#define XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_SET(x, v)    \
+  (((x) & ~XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_MASK) |   \
+   (((v) << XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_SHIFT) & \
+    XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_MASK))
+#define XS1_USB_PHY_CFG3_HS_BIST_MODE_SHIFT 0x7
+#define XS1_USB_PHY_CFG3_HS_BIST_MODE_SIZE 0x1
+#define XS1_USB_PHY_CFG3_HS_BIST_MODE_MASK         \
+  (((1 << XS1_USB_PHY_CFG3_HS_BIST_MODE_SIZE) - 1) \
+   << XS1_USB_PHY_CFG3_HS_BIST_MODE_SHIFT)
+#define XS1_USB_PHY_CFG3_HS_BIST_MODE(x)       \
+  (((x)&XS1_USB_PHY_CFG3_HS_BIST_MODE_MASK) >> \
+   XS1_USB_PHY_CFG3_HS_BIST_MODE_SHIFT)
+#define XS1_USB_PHY_CFG3_HS_BIST_MODE_SET(x, v)    \
+  (((x) & ~XS1_USB_PHY_CFG3_HS_BIST_MODE_MASK) |   \
+   (((v) << XS1_USB_PHY_CFG3_HS_BIST_MODE_SHIFT) & \
+    XS1_USB_PHY_CFG3_HS_BIST_MODE_MASK))
+#define XS1_USB_SHIM_CFG_AND_RXV_RXA_SHIFT 0x0
+#define XS1_USB_SHIM_CFG_AND_RXV_RXA_SIZE 0x1
+#define XS1_USB_SHIM_CFG_AND_RXV_RXA_MASK         \
+  (((1 << XS1_USB_SHIM_CFG_AND_RXV_RXA_SIZE) - 1) \
+   << XS1_USB_SHIM_CFG_AND_RXV_RXA_SHIFT)
+#define XS1_USB_SHIM_CFG_AND_RXV_RXA(x)       \
+  (((x)&XS1_USB_SHIM_CFG_AND_RXV_RXA_MASK) >> \
+   XS1_USB_SHIM_CFG_AND_RXV_RXA_SHIFT)
+#define XS1_USB_SHIM_CFG_AND_RXV_RXA_SET(x, v)    \
+  (((x) & ~XS1_USB_SHIM_CFG_AND_RXV_RXA_MASK) |   \
+   (((v) << XS1_USB_SHIM_CFG_AND_RXV_RXA_SHIFT) & \
+    XS1_USB_SHIM_CFG_AND_RXV_RXA_MASK))
+#define XS1_USB_SHIM_CFG_FLAG_MODE_SHIFT 0x1
+#define XS1_USB_SHIM_CFG_FLAG_MODE_SIZE 0x1
+#define XS1_USB_SHIM_CFG_FLAG_MODE_MASK         \
+  (((1 << XS1_USB_SHIM_CFG_FLAG_MODE_SIZE) - 1) \
+   << XS1_USB_SHIM_CFG_FLAG_MODE_SHIFT)
+#define XS1_USB_SHIM_CFG_FLAG_MODE(x) \
+  (((x)&XS1_USB_SHIM_CFG_FLAG_MODE_MASK) >> XS1_USB_SHIM_CFG_FLAG_MODE_SHIFT)
+#define XS1_USB_SHIM_CFG_FLAG_MODE_SET(x, v)    \
+  (((x) & ~XS1_USB_SHIM_CFG_FLAG_MODE_MASK) |   \
+   (((v) << XS1_USB_SHIM_CFG_FLAG_MODE_SHIFT) & \
+    XS1_USB_SHIM_CFG_FLAG_MODE_MASK))
+#define XS1_WATCHDOG_COUNT_ENABLE_SHIFT 0x0
+#define XS1_WATCHDOG_COUNT_ENABLE_SIZE 0x1
+#define XS1_WATCHDOG_COUNT_ENABLE_MASK         \
+  (((1 << XS1_WATCHDOG_COUNT_ENABLE_SIZE) - 1) \
+   << XS1_WATCHDOG_COUNT_ENABLE_SHIFT)
+#define XS1_WATCHDOG_COUNT_ENABLE(x) \
+  (((x)&XS1_WATCHDOG_COUNT_ENABLE_MASK) >> XS1_WATCHDOG_COUNT_ENABLE_SHIFT)
+#define XS1_WATCHDOG_COUNT_ENABLE_SET(x, v)    \
+  (((x) & ~XS1_WATCHDOG_COUNT_ENABLE_MASK) |   \
+   (((v) << XS1_WATCHDOG_COUNT_ENABLE_SHIFT) & \
+    XS1_WATCHDOG_COUNT_ENABLE_MASK))
+#define XS1_WATCHDOG_TRIGGER_ENABLE_SHIFT 0x1
+#define XS1_WATCHDOG_TRIGGER_ENABLE_SIZE 0x1
+#define XS1_WATCHDOG_TRIGGER_ENABLE_MASK         \
+  (((1 << XS1_WATCHDOG_TRIGGER_ENABLE_SIZE) - 1) \
+   << XS1_WATCHDOG_TRIGGER_ENABLE_SHIFT)
+#define XS1_WATCHDOG_TRIGGER_ENABLE(x) \
+  (((x)&XS1_WATCHDOG_TRIGGER_ENABLE_MASK) >> XS1_WATCHDOG_TRIGGER_ENABLE_SHIFT)
+#define XS1_WATCHDOG_TRIGGER_ENABLE_SET(x, v)    \
+  (((x) & ~XS1_WATCHDOG_TRIGGER_ENABLE_MASK) |   \
+   (((v) << XS1_WATCHDOG_TRIGGER_ENABLE_SHIFT) & \
+    XS1_WATCHDOG_TRIGGER_ENABLE_MASK))
+#define XS1_WATCHDOG_PRESCALER_VALUE_SHIFT 0x0
+#define XS1_WATCHDOG_PRESCALER_VALUE_SIZE 0x10
+#define XS1_WATCHDOG_PRESCALER_VALUE_MASK         \
+  (((1 << XS1_WATCHDOG_PRESCALER_VALUE_SIZE) - 1) \
+   << XS1_WATCHDOG_PRESCALER_VALUE_SHIFT)
+#define XS1_WATCHDOG_PRESCALER_VALUE(x)       \
+  (((x)&XS1_WATCHDOG_PRESCALER_VALUE_MASK) >> \
+   XS1_WATCHDOG_PRESCALER_VALUE_SHIFT)
+#define XS1_WATCHDOG_PRESCALER_VALUE_SET(x, v)    \
+  (((x) & ~XS1_WATCHDOG_PRESCALER_VALUE_MASK) |   \
+   (((v) << XS1_WATCHDOG_PRESCALER_VALUE_SHIFT) & \
+    XS1_WATCHDOG_PRESCALER_VALUE_MASK))
+#define XS1_WATCHDOG_PRESCALER_WRAP_VALUE_SHIFT 0x0
+#define XS1_WATCHDOG_PRESCALER_WRAP_VALUE_SIZE 0x10
+#define XS1_WATCHDOG_PRESCALER_WRAP_VALUE_MASK         \
+  (((1 << XS1_WATCHDOG_PRESCALER_WRAP_VALUE_SIZE) - 1) \
+   << XS1_WATCHDOG_PRESCALER_WRAP_VALUE_SHIFT)
+#define XS1_WATCHDOG_PRESCALER_WRAP_VALUE(x)       \
+  (((x)&XS1_WATCHDOG_PRESCALER_WRAP_VALUE_MASK) >> \
+   XS1_WATCHDOG_PRESCALER_WRAP_VALUE_SHIFT)
+#define XS1_WATCHDOG_PRESCALER_WRAP_VALUE_SET(x, v)    \
+  (((x) & ~XS1_WATCHDOG_PRESCALER_WRAP_VALUE_MASK) |   \
+   (((v) << XS1_WATCHDOG_PRESCALER_WRAP_VALUE_SHIFT) & \
+    XS1_WATCHDOG_PRESCALER_WRAP_VALUE_MASK))
+#define XS1_WATCHDOG_COUNT_VALUE_SHIFT 0x0
+#define XS1_WATCHDOG_COUNT_VALUE_SIZE 0xc
+#define XS1_WATCHDOG_COUNT_VALUE_MASK \
+  (((1 << XS1_WATCHDOG_COUNT_VALUE_SIZE) - 1) << XS1_WATCHDOG_COUNT_VALUE_SHIFT)
+#define XS1_WATCHDOG_COUNT_VALUE(x) \
+  (((x)&XS1_WATCHDOG_COUNT_VALUE_MASK) >> XS1_WATCHDOG_COUNT_VALUE_SHIFT)
+#define XS1_WATCHDOG_COUNT_VALUE_SET(x, v)  \
+  (((x) & ~XS1_WATCHDOG_COUNT_VALUE_MASK) | \
+   (((v) << XS1_WATCHDOG_COUNT_VALUE_SHIFT) & XS1_WATCHDOG_COUNT_VALUE_MASK))
+#define XS1_WATCHDOG_HAS_TRIGGERED_SHIFT 0x0
+#define XS1_WATCHDOG_HAS_TRIGGERED_SIZE 0x1
+#define XS1_WATCHDOG_HAS_TRIGGERED_MASK         \
+  (((1 << XS1_WATCHDOG_HAS_TRIGGERED_SIZE) - 1) \
+   << XS1_WATCHDOG_HAS_TRIGGERED_SHIFT)
+#define XS1_WATCHDOG_HAS_TRIGGERED(x) \
+  (((x)&XS1_WATCHDOG_HAS_TRIGGERED_MASK) >> XS1_WATCHDOG_HAS_TRIGGERED_SHIFT)
+#define XS1_WATCHDOG_HAS_TRIGGERED_SET(x, v)    \
+  (((x) & ~XS1_WATCHDOG_HAS_TRIGGERED_MASK) |   \
+   (((v) << XS1_WATCHDOG_HAS_TRIGGERED_SHIFT) & \
+    XS1_WATCHDOG_HAS_TRIGGERED_MASK))
+#define XS1_MIPI_STATUS0_OSC_CLK_ACT_SHIFT 0x0
+#define XS1_MIPI_STATUS0_OSC_CLK_ACT_SIZE 0x1
+#define XS1_MIPI_STATUS0_OSC_CLK_ACT_MASK         \
+  (((1 << XS1_MIPI_STATUS0_OSC_CLK_ACT_SIZE) - 1) \
+   << XS1_MIPI_STATUS0_OSC_CLK_ACT_SHIFT)
+#define XS1_MIPI_STATUS0_OSC_CLK_ACT(x)       \
+  (((x)&XS1_MIPI_STATUS0_OSC_CLK_ACT_MASK) >> \
+   XS1_MIPI_STATUS0_OSC_CLK_ACT_SHIFT)
+#define XS1_MIPI_STATUS0_OSC_CLK_ACT_SET(x, v)    \
+  (((x) & ~XS1_MIPI_STATUS0_OSC_CLK_ACT_MASK) |   \
+   (((v) << XS1_MIPI_STATUS0_OSC_CLK_ACT_SHIFT) & \
+    XS1_MIPI_STATUS0_OSC_CLK_ACT_MASK))
+#define XS1_MIPI_STATUS0_OSC_CLK_READY_SHIFT 0x1
+#define XS1_MIPI_STATUS0_OSC_CLK_READY_SIZE 0x1
+#define XS1_MIPI_STATUS0_OSC_CLK_READY_MASK         \
+  (((1 << XS1_MIPI_STATUS0_OSC_CLK_READY_SIZE) - 1) \
+   << XS1_MIPI_STATUS0_OSC_CLK_READY_SHIFT)
+#define XS1_MIPI_STATUS0_OSC_CLK_READY(x)       \
+  (((x)&XS1_MIPI_STATUS0_OSC_CLK_READY_MASK) >> \
+   XS1_MIPI_STATUS0_OSC_CLK_READY_SHIFT)
+#define XS1_MIPI_STATUS0_OSC_CLK_READY_SET(x, v)    \
+  (((x) & ~XS1_MIPI_STATUS0_OSC_CLK_READY_MASK) |   \
+   (((v) << XS1_MIPI_STATUS0_OSC_CLK_READY_SHIFT) & \
+    XS1_MIPI_STATUS0_OSC_CLK_READY_MASK))
+#define XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_SHIFT 0x2
+#define XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_SIZE 0x1
+#define XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_MASK         \
+  (((1 << XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_SIZE) - 1) \
+   << XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_SHIFT)
+#define XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G(x)       \
+  (((x)&XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_MASK) >> \
+   XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_SHIFT)
+#define XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_SET(x, v)    \
+  (((x) & ~XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_MASK) |   \
+   (((v) << XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_SHIFT) & \
+    XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_MASK))
+#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_SHIFT 0x3
+#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_SIZE 0x1
+#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_MASK         \
+  (((1 << XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_SIZE) - 1) \
+   << XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_SHIFT)
+#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN0(x)       \
+  (((x)&XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_MASK) >> \
+   XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_SHIFT)
+#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_SET(x, v)    \
+  (((x) & ~XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_MASK) |   \
+   (((v) << XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_SHIFT) & \
+    XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_MASK))
+#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_SHIFT 0x4
+#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_SIZE 0x1
+#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_MASK         \
+  (((1 << XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_SIZE) - 1) \
+   << XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_SHIFT)
+#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN1(x)       \
+  (((x)&XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_MASK) >> \
+   XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_SHIFT)
+#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_SET(x, v)    \
+  (((x) & ~XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_MASK) |   \
+   (((v) << XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_SHIFT) & \
+    XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_MASK))
+#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_SHIFT 0x5
+#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_SIZE 0x1
+#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_MASK         \
+  (((1 << XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_SIZE) - 1) \
+   << XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_SHIFT)
+#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN2(x)       \
+  (((x)&XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_MASK) >> \
+   XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_SHIFT)
+#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_SET(x, v)    \
+  (((x) & ~XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_MASK) |   \
+   (((v) << XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_SHIFT) & \
+    XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_MASK))
+#define XS1_MIPI_STATUS0_STOPSTATE_CLK_SHIFT 0xc
+#define XS1_MIPI_STATUS0_STOPSTATE_CLK_SIZE 0x1
+#define XS1_MIPI_STATUS0_STOPSTATE_CLK_MASK         \
+  (((1 << XS1_MIPI_STATUS0_STOPSTATE_CLK_SIZE) - 1) \
+   << XS1_MIPI_STATUS0_STOPSTATE_CLK_SHIFT)
+#define XS1_MIPI_STATUS0_STOPSTATE_CLK(x)       \
+  (((x)&XS1_MIPI_STATUS0_STOPSTATE_CLK_MASK) >> \
+   XS1_MIPI_STATUS0_STOPSTATE_CLK_SHIFT)
+#define XS1_MIPI_STATUS0_STOPSTATE_CLK_SET(x, v)    \
+  (((x) & ~XS1_MIPI_STATUS0_STOPSTATE_CLK_MASK) |   \
+   (((v) << XS1_MIPI_STATUS0_STOPSTATE_CLK_SHIFT) & \
+    XS1_MIPI_STATUS0_STOPSTATE_CLK_MASK))
+#define XS1_MIPI_STATUS0_STOPSTATE_LAN0_SHIFT 0xd
+#define XS1_MIPI_STATUS0_STOPSTATE_LAN0_SIZE 0x1
+#define XS1_MIPI_STATUS0_STOPSTATE_LAN0_MASK         \
+  (((1 << XS1_MIPI_STATUS0_STOPSTATE_LAN0_SIZE) - 1) \
+   << XS1_MIPI_STATUS0_STOPSTATE_LAN0_SHIFT)
+#define XS1_MIPI_STATUS0_STOPSTATE_LAN0(x)       \
+  (((x)&XS1_MIPI_STATUS0_STOPSTATE_LAN0_MASK) >> \
+   XS1_MIPI_STATUS0_STOPSTATE_LAN0_SHIFT)
+#define XS1_MIPI_STATUS0_STOPSTATE_LAN0_SET(x, v)    \
+  (((x) & ~XS1_MIPI_STATUS0_STOPSTATE_LAN0_MASK) |   \
+   (((v) << XS1_MIPI_STATUS0_STOPSTATE_LAN0_SHIFT) & \
+    XS1_MIPI_STATUS0_STOPSTATE_LAN0_MASK))
+#define XS1_MIPI_STATUS0_STOPSTATE_LAN1_SHIFT 0xe
+#define XS1_MIPI_STATUS0_STOPSTATE_LAN1_SIZE 0x1
+#define XS1_MIPI_STATUS0_STOPSTATE_LAN1_MASK         \
+  (((1 << XS1_MIPI_STATUS0_STOPSTATE_LAN1_SIZE) - 1) \
+   << XS1_MIPI_STATUS0_STOPSTATE_LAN1_SHIFT)
+#define XS1_MIPI_STATUS0_STOPSTATE_LAN1(x)       \
+  (((x)&XS1_MIPI_STATUS0_STOPSTATE_LAN1_MASK) >> \
+   XS1_MIPI_STATUS0_STOPSTATE_LAN1_SHIFT)
+#define XS1_MIPI_STATUS0_STOPSTATE_LAN1_SET(x, v)    \
+  (((x) & ~XS1_MIPI_STATUS0_STOPSTATE_LAN1_MASK) |   \
+   (((v) << XS1_MIPI_STATUS0_STOPSTATE_LAN1_SHIFT) & \
+    XS1_MIPI_STATUS0_STOPSTATE_LAN1_MASK))
+#define XS1_MIPI_SHIM_STATUS_REG_SHIFT 0x0
+#define XS1_MIPI_SHIM_STATUS_REG_SIZE 0x1
+#define XS1_MIPI_SHIM_STATUS_REG_MASK \
+  (((1 << XS1_MIPI_SHIM_STATUS_REG_SIZE) - 1) << XS1_MIPI_SHIM_STATUS_REG_SHIFT)
+#define XS1_MIPI_SHIM_STATUS_REG(x) \
+  (((x)&XS1_MIPI_SHIM_STATUS_REG_MASK) >> XS1_MIPI_SHIM_STATUS_REG_SHIFT)
+#define XS1_MIPI_SHIM_STATUS_REG_SET(x, v)  \
+  (((x) & ~XS1_MIPI_SHIM_STATUS_REG_MASK) | \
+   (((v) << XS1_MIPI_SHIM_STATUS_REG_SHIFT) & XS1_MIPI_SHIM_STATUS_REG_MASK))
+#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_SHIFT 0x0
+#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_SIZE 0x1
+#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_MASK         \
+  (((1 << XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_SIZE) - 1) \
+   << XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_SHIFT)
+#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN(x)       \
+  (((x)&XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_MASK) >> \
+   XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_SHIFT)
+#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_SET(x, v)    \
+  (((x) & ~XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_MASK) |   \
+   (((v) << XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_SHIFT) & \
+    XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_MASK))
+#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_SHIFT 0x8
+#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_SIZE 0x8
+#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_MASK         \
+  (((1 << XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_SIZE) - 1) \
+   << XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_SHIFT)
+#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE(x)       \
+  (((x)&XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_MASK) >> \
+   XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_SHIFT)
+#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_SET(x, v)    \
+  (((x) & ~XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_MASK) |   \
+   (((v) << XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_SHIFT) & \
+    XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_MASK))
+#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_SHIFT 0x10
+#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_SIZE 0x6
+#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_MASK         \
+  (((1 << XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_SIZE) - 1) \
+   << XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_SHIFT)
+#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE(x)       \
+  (((x)&XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_MASK) >> \
+   XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_SHIFT)
+#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_SET(x, v)    \
+  (((x) & ~XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_MASK) |   \
+   (((v) << XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_SHIFT) & \
+    XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_MASK))
+#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_SHIFT 0x19
+#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_SIZE 0x1
+#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_MASK         \
+  (((1 << XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_SIZE) - 1) \
+   << XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_SHIFT)
+#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT(x)       \
+  (((x)&XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_MASK) >> \
+   XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_SHIFT)
+#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_SET(x, v)    \
+  (((x) & ~XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_MASK) |   \
+   (((v) << XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_SHIFT) & \
+    XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_MASK))
+#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG_SHIFT 0x1a
+#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG_SIZE 0x1
+#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG_MASK         \
+  (((1 << XS1_MIPI_SHIM_CFG0_SEL_DEBUG_SIZE) - 1) \
+   << XS1_MIPI_SHIM_CFG0_SEL_DEBUG_SHIFT)
+#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG(x)       \
+  (((x)&XS1_MIPI_SHIM_CFG0_SEL_DEBUG_MASK) >> \
+   XS1_MIPI_SHIM_CFG0_SEL_DEBUG_SHIFT)
+#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG_SET(x, v)    \
+  (((x) & ~XS1_MIPI_SHIM_CFG0_SEL_DEBUG_MASK) |   \
+   (((v) << XS1_MIPI_SHIM_CFG0_SEL_DEBUG_SHIFT) & \
+    XS1_MIPI_SHIM_CFG0_SEL_DEBUG_MASK))
+#define XS1_LPDDR_PE_TREFI_CNT_SHIFT 0x0
+#define XS1_LPDDR_PE_TREFI_CNT_SIZE 0xb
+#define XS1_LPDDR_PE_TREFI_CNT_MASK \
+  (((1 << XS1_LPDDR_PE_TREFI_CNT_SIZE) - 1) << XS1_LPDDR_PE_TREFI_CNT_SHIFT)
+#define XS1_LPDDR_PE_TREFI_CNT(x) \
+  (((x)&XS1_LPDDR_PE_TREFI_CNT_MASK) >> XS1_LPDDR_PE_TREFI_CNT_SHIFT)
+#define XS1_LPDDR_PE_TREFI_CNT_SET(x, v)  \
+  (((x) & ~XS1_LPDDR_PE_TREFI_CNT_MASK) | \
+   (((v) << XS1_LPDDR_PE_TREFI_CNT_SHIFT) & XS1_LPDDR_PE_TREFI_CNT_MASK))
+#define XS1_LPDDR_PE_TRAS_CNT_SHIFT 0xb
+#define XS1_LPDDR_PE_TRAS_CNT_SIZE 0x4
+#define XS1_LPDDR_PE_TRAS_CNT_MASK \
+  (((1 << XS1_LPDDR_PE_TRAS_CNT_SIZE) - 1) << XS1_LPDDR_PE_TRAS_CNT_SHIFT)
+#define XS1_LPDDR_PE_TRAS_CNT(x) \
+  (((x)&XS1_LPDDR_PE_TRAS_CNT_MASK) >> XS1_LPDDR_PE_TRAS_CNT_SHIFT)
+#define XS1_LPDDR_PE_TRAS_CNT_SET(x, v)  \
+  (((x) & ~XS1_LPDDR_PE_TRAS_CNT_MASK) | \
+   (((v) << XS1_LPDDR_PE_TRAS_CNT_SHIFT) & XS1_LPDDR_PE_TRAS_CNT_MASK))
+#define XS1_LPDDR_PE_TXSR_CNT_SHIFT 0xf
+#define XS1_LPDDR_PE_TXSR_CNT_SIZE 0x6
+#define XS1_LPDDR_PE_TXSR_CNT_MASK \
+  (((1 << XS1_LPDDR_PE_TXSR_CNT_SIZE) - 1) << XS1_LPDDR_PE_TXSR_CNT_SHIFT)
+#define XS1_LPDDR_PE_TXSR_CNT(x) \
+  (((x)&XS1_LPDDR_PE_TXSR_CNT_MASK) >> XS1_LPDDR_PE_TXSR_CNT_SHIFT)
+#define XS1_LPDDR_PE_TXSR_CNT_SET(x, v)  \
+  (((x) & ~XS1_LPDDR_PE_TXSR_CNT_MASK) | \
+   (((v) << XS1_LPDDR_PE_TXSR_CNT_SHIFT) & XS1_LPDDR_PE_TXSR_CNT_MASK))
+#define XS1_LPDDR_PE_TWR_CNT_SHIFT 0x15
+#define XS1_LPDDR_PE_TWR_CNT_SIZE 0x3
+#define XS1_LPDDR_PE_TWR_CNT_MASK \
+  (((1 << XS1_LPDDR_PE_TWR_CNT_SIZE) - 1) << XS1_LPDDR_PE_TWR_CNT_SHIFT)
+#define XS1_LPDDR_PE_TWR_CNT(x) \
+  (((x)&XS1_LPDDR_PE_TWR_CNT_MASK) >> XS1_LPDDR_PE_TWR_CNT_SHIFT)
+#define XS1_LPDDR_PE_TWR_CNT_SET(x, v)  \
+  (((x) & ~XS1_LPDDR_PE_TWR_CNT_MASK) | \
+   (((v) << XS1_LPDDR_PE_TWR_CNT_SHIFT) & XS1_LPDDR_PE_TWR_CNT_MASK))
+#define XS1_LPDDR_PE_TRC_CNT_SHIFT 0x0
+#define XS1_LPDDR_PE_TRC_CNT_SIZE 0x4
+#define XS1_LPDDR_PE_TRC_CNT_MASK \
+  (((1 << XS1_LPDDR_PE_TRC_CNT_SIZE) - 1) << XS1_LPDDR_PE_TRC_CNT_SHIFT)
+#define XS1_LPDDR_PE_TRC_CNT(x) \
+  (((x)&XS1_LPDDR_PE_TRC_CNT_MASK) >> XS1_LPDDR_PE_TRC_CNT_SHIFT)
+#define XS1_LPDDR_PE_TRC_CNT_SET(x, v)  \
+  (((x) & ~XS1_LPDDR_PE_TRC_CNT_MASK) | \
+   (((v) << XS1_LPDDR_PE_TRC_CNT_SHIFT) & XS1_LPDDR_PE_TRC_CNT_MASK))
+#define XS1_LPDDR_PE_TRCD_CNT_SHIFT 0x4
+#define XS1_LPDDR_PE_TRCD_CNT_SIZE 0x3
+#define XS1_LPDDR_PE_TRCD_CNT_MASK \
+  (((1 << XS1_LPDDR_PE_TRCD_CNT_SIZE) - 1) << XS1_LPDDR_PE_TRCD_CNT_SHIFT)
+#define XS1_LPDDR_PE_TRCD_CNT(x) \
+  (((x)&XS1_LPDDR_PE_TRCD_CNT_MASK) >> XS1_LPDDR_PE_TRCD_CNT_SHIFT)
+#define XS1_LPDDR_PE_TRCD_CNT_SET(x, v)  \
+  (((x) & ~XS1_LPDDR_PE_TRCD_CNT_MASK) | \
+   (((v) << XS1_LPDDR_PE_TRCD_CNT_SHIFT) & XS1_LPDDR_PE_TRCD_CNT_MASK))
+#define XS1_LPDDR_PE_TRP_CNT_SHIFT 0x7
+#define XS1_LPDDR_PE_TRP_CNT_SIZE 0x3
+#define XS1_LPDDR_PE_TRP_CNT_MASK \
+  (((1 << XS1_LPDDR_PE_TRP_CNT_SIZE) - 1) << XS1_LPDDR_PE_TRP_CNT_SHIFT)
+#define XS1_LPDDR_PE_TRP_CNT(x) \
+  (((x)&XS1_LPDDR_PE_TRP_CNT_MASK) >> XS1_LPDDR_PE_TRP_CNT_SHIFT)
+#define XS1_LPDDR_PE_TRP_CNT_SET(x, v)  \
+  (((x) & ~XS1_LPDDR_PE_TRP_CNT_MASK) | \
+   (((v) << XS1_LPDDR_PE_TRP_CNT_SHIFT) & XS1_LPDDR_PE_TRP_CNT_MASK))
+#define XS1_LPDDR_PE_TRFC_CNT_SHIFT 0xa
+#define XS1_LPDDR_PE_TRFC_CNT_SIZE 0x5
+#define XS1_LPDDR_PE_TRFC_CNT_MASK \
+  (((1 << XS1_LPDDR_PE_TRFC_CNT_SIZE) - 1) << XS1_LPDDR_PE_TRFC_CNT_SHIFT)
+#define XS1_LPDDR_PE_TRFC_CNT(x) \
+  (((x)&XS1_LPDDR_PE_TRFC_CNT_MASK) >> XS1_LPDDR_PE_TRFC_CNT_SHIFT)
+#define XS1_LPDDR_PE_TRFC_CNT_SET(x, v)  \
+  (((x) & ~XS1_LPDDR_PE_TRFC_CNT_MASK) | \
+   (((v) << XS1_LPDDR_PE_TRFC_CNT_SHIFT) & XS1_LPDDR_PE_TRFC_CNT_MASK))
+#define XS1_LPDDR_PE_TRRD_CNT_SHIFT 0xf
+#define XS1_LPDDR_PE_TRRD_CNT_SIZE 0x2
+#define XS1_LPDDR_PE_TRRD_CNT_MASK \
+  (((1 << XS1_LPDDR_PE_TRRD_CNT_SIZE) - 1) << XS1_LPDDR_PE_TRRD_CNT_SHIFT)
+#define XS1_LPDDR_PE_TRRD_CNT(x) \
+  (((x)&XS1_LPDDR_PE_TRRD_CNT_MASK) >> XS1_LPDDR_PE_TRRD_CNT_SHIFT)
+#define XS1_LPDDR_PE_TRRD_CNT_SET(x, v)  \
+  (((x) & ~XS1_LPDDR_PE_TRRD_CNT_MASK) | \
+   (((v) << XS1_LPDDR_PE_TRRD_CNT_SHIFT) & XS1_LPDDR_PE_TRRD_CNT_MASK))
+#define XS1_LPDDR_PE_EN_256M_DEV_SIZE_SHIFT 0x11
+#define XS1_LPDDR_PE_EN_256M_DEV_SIZE_SIZE 0x1
+#define XS1_LPDDR_PE_EN_256M_DEV_SIZE_MASK         \
+  (((1 << XS1_LPDDR_PE_EN_256M_DEV_SIZE_SIZE) - 1) \
+   << XS1_LPDDR_PE_EN_256M_DEV_SIZE_SHIFT)
+#define XS1_LPDDR_PE_EN_256M_DEV_SIZE(x)       \
+  (((x)&XS1_LPDDR_PE_EN_256M_DEV_SIZE_MASK) >> \
+   XS1_LPDDR_PE_EN_256M_DEV_SIZE_SHIFT)
+#define XS1_LPDDR_PE_EN_256M_DEV_SIZE_SET(x, v)    \
+  (((x) & ~XS1_LPDDR_PE_EN_256M_DEV_SIZE_MASK) |   \
+   (((v) << XS1_LPDDR_PE_EN_256M_DEV_SIZE_SHIFT) & \
+    XS1_LPDDR_PE_EN_256M_DEV_SIZE_MASK))
+#define XS1_DEVICE_ID0_VERSION_VALUE 0x0
+#define XS1_DEVICE_ID0_REVISION_VALUE 0x4
+#define XS1_PS_DBG_HANDLER XS1_PS_DBG_SCRATCH_0
+#define XS1_PS_DBG_COMMAND XS1_PS_DBG_SCRATCH_1
+#define XS1_PS_DBG_ARG0_REG XS1_PS_DBG_SCRATCH_2
+#define XS1_PS_DBG_ARG1_REG XS1_PS_DBG_SCRATCH_3
+#define XS1_PS_DBG_ARG2_REG XS1_PS_DBG_SCRATCH_4
+#define XS1_PS_DBG_ARG3_REG XS1_PS_DBG_SCRATCH_5
+#define XS1_PS_DBG_ARG4_REG XS1_PS_DBG_SCRATCH_6
+#define XS1_PS_DBG_ARG5_REG XS1_PS_DBG_SCRATCH_7
+#define XS1_PSWITCH_DBG_HANDLER_NUM XS1_PSWITCH_DBG_SCRATCH_0_NUM
+#define XS1_PSWITCH_DBG_COMMAND_NUM XS1_PSWITCH_DBG_SCRATCH_1_NUM
+#define XS1_PSWITCH_DBG_ARG0_NUM XS1_PSWITCH_DBG_SCRATCH_2_NUM
+#define XS1_PSWITCH_DBG_ARG1_NUM XS1_PSWITCH_DBG_SCRATCH_3_NUM
+#define XS1_PSWITCH_DBG_ARG2_NUM XS1_PSWITCH_DBG_SCRATCH_4_NUM
+#define XS1_PSWITCH_DBG_ARG3_NUM XS1_PSWITCH_DBG_SCRATCH_5_NUM
+#define XS1_PSWITCH_DBG_ARG4_NUM XS1_PSWITCH_DBG_SCRATCH_6_NUM
+#define XS1_PSWITCH_DBG_ARG5_NUM XS1_PSWITCH_DBG_SCRATCH_7_NUM
+#define XS1_XMOS_PHY_CONF_WIDTH 0x3
+#define XS1_USB_PHY_VCONTROL_SETUP_LENGTH 0x6
+#define XS1_USB_PHY_ENTER_BIST_LENGTH 0x40
+#define XS1_USB_PHY_CLKCNT_WIDTH 0x4
+#define XS1_USB_BISTGO_CTR_WIDTH 0x4
+#define XS1_USB_TESTGO_CTR_WIDTH 0x4
+#define XS1_USB_TESTGO_PULSE_LENGTH 0x8
+#define XS1_USB_BISTGO_PULSE_LENGTH 0x8
+#define XS1_CRC5_RESULT_WIDTH 0x5
+#define XS1_MS_NIBBLE "7:4"
+#define XS1_LS_NIBBLE "3:0"
+#endif /* _xs3a_registers_h_ */