xmos-ai-tools 1.3.2.dev80__py3-none-macosx_10_15_universal2.whl
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- xmos_ai_tools/__init__.py +7 -0
- xmos_ai_tools/io_server/__init__.py +151 -0
- xmos_ai_tools/runtime/__init__.py +0 -0
- xmos_ai_tools/runtime/buildfiles/aitoolslib.cmake +13 -0
- xmos_ai_tools/runtime/buildfiles/aitoolslib.make +8 -0
- xmos_ai_tools/runtime/include/flash_server.h +74 -0
- xmos_ai_tools/runtime/include/flatbuffers/allocator.h +68 -0
- xmos_ai_tools/runtime/include/flatbuffers/array.h +243 -0
- xmos_ai_tools/runtime/include/flatbuffers/base.h +474 -0
- xmos_ai_tools/runtime/include/flatbuffers/bfbs_generator.h +43 -0
- xmos_ai_tools/runtime/include/flatbuffers/buffer.h +142 -0
- xmos_ai_tools/runtime/include/flatbuffers/buffer_ref.h +53 -0
- xmos_ai_tools/runtime/include/flatbuffers/code_generators.h +235 -0
- xmos_ai_tools/runtime/include/flatbuffers/default_allocator.h +64 -0
- xmos_ai_tools/runtime/include/flatbuffers/detached_buffer.h +114 -0
- xmos_ai_tools/runtime/include/flatbuffers/flatbuffer_builder.h +1197 -0
- xmos_ai_tools/runtime/include/flatbuffers/flatbuffers.h +270 -0
- xmos_ai_tools/runtime/include/flatbuffers/flatc.h +111 -0
- xmos_ai_tools/runtime/include/flatbuffers/flexbuffers.h +1897 -0
- xmos_ai_tools/runtime/include/flatbuffers/grpc.h +300 -0
- xmos_ai_tools/runtime/include/flatbuffers/hash.h +127 -0
- xmos_ai_tools/runtime/include/flatbuffers/idl.h +1232 -0
- xmos_ai_tools/runtime/include/flatbuffers/minireflect.h +419 -0
- xmos_ai_tools/runtime/include/flatbuffers/pch/flatc_pch.h +39 -0
- xmos_ai_tools/runtime/include/flatbuffers/pch/pch.h +38 -0
- xmos_ai_tools/runtime/include/flatbuffers/reflection.h +502 -0
- xmos_ai_tools/runtime/include/flatbuffers/reflection_generated.h +1449 -0
- xmos_ai_tools/runtime/include/flatbuffers/registry.h +128 -0
- xmos_ai_tools/runtime/include/flatbuffers/stl_emulation.h +509 -0
- xmos_ai_tools/runtime/include/flatbuffers/string.h +64 -0
- xmos_ai_tools/runtime/include/flatbuffers/struct.h +53 -0
- xmos_ai_tools/runtime/include/flatbuffers/table.h +168 -0
- xmos_ai_tools/runtime/include/flatbuffers/util.h +690 -0
- xmos_ai_tools/runtime/include/flatbuffers/vector.h +370 -0
- xmos_ai_tools/runtime/include/flatbuffers/vector_downward.h +271 -0
- xmos_ai_tools/runtime/include/flatbuffers/verifier.h +283 -0
- xmos_ai_tools/runtime/include/ioserver.h +44 -0
- xmos_ai_tools/runtime/include/lib_nn/api/TransposeConv.h +24 -0
- xmos_ai_tools/runtime/include/lib_nn/api/add_int16.h +27 -0
- xmos_ai_tools/runtime/include/lib_nn/api/add_int16_transform.h +42 -0
- xmos_ai_tools/runtime/include/lib_nn/api/dequantize_int16.h +22 -0
- xmos_ai_tools/runtime/include/lib_nn/api/dequantize_int16_transform.h +34 -0
- xmos_ai_tools/runtime/include/lib_nn/api/expand_8_to_16.h +8 -0
- xmos_ai_tools/runtime/include/lib_nn/api/multiply_int16.h +42 -0
- xmos_ai_tools/runtime/include/lib_nn/api/multiply_int16_transform.h +71 -0
- xmos_ai_tools/runtime/include/lib_nn/api/nn_api.h +15 -0
- xmos_ai_tools/runtime/include/lib_nn/api/nn_bin_types.h +14 -0
- xmos_ai_tools/runtime/include/lib_nn/api/nn_config.h +287 -0
- xmos_ai_tools/runtime/include/lib_nn/api/nn_conv2d_structs.h +72 -0
- xmos_ai_tools/runtime/include/lib_nn/api/nn_image.h +26 -0
- xmos_ai_tools/runtime/include/lib_nn/api/nn_layers.h +303 -0
- xmos_ai_tools/runtime/include/lib_nn/api/nn_op_helper.h +132 -0
- xmos_ai_tools/runtime/include/lib_nn/api/nn_op_utils.h +150 -0
- xmos_ai_tools/runtime/include/lib_nn/api/nn_operator.h +18 -0
- xmos_ai_tools/runtime/include/lib_nn/api/nn_pooling.h +551 -0
- xmos_ai_tools/runtime/include/lib_nn/api/nn_types.h +83 -0
- xmos_ai_tools/runtime/include/lib_nn/api/nn_window_params.h +55 -0
- xmos_ai_tools/runtime/include/lib_nn/api/output_transform_fn_int16.h +54 -0
- xmos_ai_tools/runtime/include/lib_nn/api/output_transform_fn_int16_kernel_transform.h +37 -0
- xmos_ai_tools/runtime/include/lib_nn/api/output_transform_fn_int16_mappings.h +13 -0
- xmos_ai_tools/runtime/include/lib_nn/api/quadratic_approximation.h +82 -0
- xmos_ai_tools/runtime/include/lib_nn/api/quadratic_interpolation.h +23 -0
- xmos_ai_tools/runtime/include/lib_nn/api/quantize_int16.h +22 -0
- xmos_ai_tools/runtime/include/lib_nn/api/quantize_int16_transform.h +33 -0
- xmos_ai_tools/runtime/include/lib_nn/api/version.h +13 -0
- xmos_ai_tools/runtime/include/lib_nn/api/vpu_memmove_word_aligned.h +15 -0
- xmos_ai_tools/runtime/include/lib_nn/api/vpu_memset_256.h +55 -0
- xmos_ai_tools/runtime/include/lib_nn/api/vpu_sim.h +118 -0
- xmos_ai_tools/runtime/include/lib_nn/api/xs3_vpu.h +216 -0
- xmos_ai_tools/runtime/include/lib_nn/api/xs3a_registers.h +2869 -0
- xmos_ai_tools/runtime/include/lib_nn/src/asm/asm_constants.h +41 -0
- xmos_ai_tools/runtime/include/lib_nn/src/asm/window_op_plan.h +25 -0
- xmos_ai_tools/runtime/include/lib_tflite_micro/api/fast_flash.h +47 -0
- xmos_ai_tools/runtime/include/lib_tflite_micro/api/inference_engine.h +218 -0
- xmos_ai_tools/runtime/include/lib_tflite_micro/api/memory_parallel_transport.h +52 -0
- xmos_ai_tools/runtime/include/lib_tflite_micro/api/version.h +13 -0
- xmos_ai_tools/runtime/include/lib_tflite_micro/api/xcore_config.h +17 -0
- xmos_ai_tools/runtime/include/lib_tflite_micro/api/xcore_device_memory.h +62 -0
- xmos_ai_tools/runtime/include/lib_tflite_micro/api/xcore_shared_config.h +31 -0
- xmos_ai_tools/runtime/include/lib_tflite_micro/src/tflite-xcore-kernels/conv2d_float.h +155 -0
- xmos_ai_tools/runtime/include/lib_tflite_micro/src/tflite-xcore-kernels/xcore_common.h +19 -0
- xmos_ai_tools/runtime/include/lib_tflite_micro/src/tflite-xcore-kernels/xcore_custom_options.h +28 -0
- xmos_ai_tools/runtime/include/lib_tflite_micro/src/tflite-xcore-kernels/xcore_error_reporter.h +32 -0
- xmos_ai_tools/runtime/include/lib_tflite_micro/src/tflite-xcore-kernels/xcore_interpreter.h +49 -0
- xmos_ai_tools/runtime/include/lib_tflite_micro/src/tflite-xcore-kernels/xcore_ops.h +71 -0
- xmos_ai_tools/runtime/include/lib_tflite_micro/src/tflite-xcore-kernels/xcore_profiler.h +49 -0
- xmos_ai_tools/runtime/include/lib_tflite_micro/src/tflite-xcore-kernels/xcore_utils.h +160 -0
- xmos_ai_tools/runtime/include/lib_tflite_micro/src/thread_call.h +119 -0
- xmos_ai_tools/runtime/include/lib_xud/lib_xud/api/legacy/usb_defs.h +4 -0
- xmos_ai_tools/runtime/include/lib_xud/lib_xud/api/legacy/usb_device.h +4 -0
- xmos_ai_tools/runtime/include/lib_xud/lib_xud/api/legacy/usb_std_descriptors.h +4 -0
- xmos_ai_tools/runtime/include/lib_xud/lib_xud/api/legacy/usb_std_requests.h +4 -0
- xmos_ai_tools/runtime/include/lib_xud/lib_xud/api/xud.h +518 -0
- xmos_ai_tools/runtime/include/lib_xud/lib_xud/api/xud_conf_default.h +11 -0
- xmos_ai_tools/runtime/include/lib_xud/lib_xud/api/xud_device.h +87 -0
- xmos_ai_tools/runtime/include/lib_xud/lib_xud/api/xud_std_descriptors.h +191 -0
- xmos_ai_tools/runtime/include/lib_xud/lib_xud/api/xud_std_requests.h +120 -0
- xmos_ai_tools/runtime/include/lib_xud/lib_xud/src/user/XUD_USB_Defines.h +70 -0
- xmos_ai_tools/runtime/include/lib_xud/lib_xud/src/user/class/hid.h +23 -0
- xmos_ai_tools/runtime/include/lib_xud/lib_xud/src/user/class/usbaudio10.h +30 -0
- xmos_ai_tools/runtime/include/lib_xud/lib_xud/src/user/class/usbaudio20.h +357 -0
- xmos_ai_tools/runtime/include/lib_xud/lib_xud/src/user/class/usbaudiocommon.h +168 -0
- xmos_ai_tools/runtime/include/signal/micro/kernels/delay_flexbuffers_generated_data.h +25 -0
- xmos_ai_tools/runtime/include/signal/micro/kernels/energy_flexbuffers_generated_data.h +28 -0
- xmos_ai_tools/runtime/include/signal/micro/kernels/fft_flexbuffers_generated_data.h +37 -0
- xmos_ai_tools/runtime/include/signal/micro/kernels/filter_bank_flexbuffers_generated_data.h +25 -0
- xmos_ai_tools/runtime/include/signal/micro/kernels/filter_bank_log_flexbuffers_generated_data.h +27 -0
- xmos_ai_tools/runtime/include/signal/micro/kernels/filter_bank_spectral_subtraction_flexbuffers_generated_data.h +26 -0
- xmos_ai_tools/runtime/include/signal/micro/kernels/framer_flexbuffers_generated_data.h +25 -0
- xmos_ai_tools/runtime/include/signal/micro/kernels/irfft.h +31 -0
- xmos_ai_tools/runtime/include/signal/micro/kernels/overlap_add_flexbuffers_generated_data.h +25 -0
- xmos_ai_tools/runtime/include/signal/micro/kernels/pcan_flexbuffers_generated_data.h +7 -0
- xmos_ai_tools/runtime/include/signal/micro/kernels/rfft.h +31 -0
- xmos_ai_tools/runtime/include/signal/micro/kernels/stacker_flexbuffers_generated_data.h +25 -0
- xmos_ai_tools/runtime/include/signal/micro/kernels/window_flexbuffers_generated_data.h +25 -0
- xmos_ai_tools/runtime/include/signal/src/circular_buffer.h +118 -0
- xmos_ai_tools/runtime/include/signal/src/complex.h +29 -0
- xmos_ai_tools/runtime/include/signal/src/energy.h +38 -0
- xmos_ai_tools/runtime/include/signal/src/fft_auto_scale.h +35 -0
- xmos_ai_tools/runtime/include/signal/src/filter_bank.h +69 -0
- xmos_ai_tools/runtime/include/signal/src/filter_bank_log.h +38 -0
- xmos_ai_tools/runtime/include/signal/src/filter_bank_spectral_subtraction.h +73 -0
- xmos_ai_tools/runtime/include/signal/src/filter_bank_square_root.h +34 -0
- xmos_ai_tools/runtime/include/signal/src/irfft.h +84 -0
- xmos_ai_tools/runtime/include/signal/src/kiss_fft_wrappers/kiss_fft_common.h +49 -0
- xmos_ai_tools/runtime/include/signal/src/kiss_fft_wrappers/kiss_fft_float.h +31 -0
- xmos_ai_tools/runtime/include/signal/src/kiss_fft_wrappers/kiss_fft_int16.h +30 -0
- xmos_ai_tools/runtime/include/signal/src/kiss_fft_wrappers/kiss_fft_int32.h +31 -0
- xmos_ai_tools/runtime/include/signal/src/log.h +30 -0
- xmos_ai_tools/runtime/include/signal/src/max_abs.h +31 -0
- xmos_ai_tools/runtime/include/signal/src/msb.h +32 -0
- xmos_ai_tools/runtime/include/signal/src/overlap_add.h +46 -0
- xmos_ai_tools/runtime/include/signal/src/pcan_argc_fixed.h +41 -0
- xmos_ai_tools/runtime/include/signal/src/rfft.h +85 -0
- xmos_ai_tools/runtime/include/signal/src/square_root.h +32 -0
- xmos_ai_tools/runtime/include/signal/src/window.h +31 -0
- xmos_ai_tools/runtime/include/signal/testdata/fft_test_data.h +48 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/array.h +156 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/builtin_op_data.h +22 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/builtin_ops.h +241 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/c/builtin_op_data.h +20 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/c/c_api_types.h +26 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/c/common.h +30 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/context_util.h +54 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/core/api/error_reporter.h +72 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/core/api/flatbuffer_conversions.h +440 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/core/api/tensor_utils.h +28 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/core/c/builtin_op_data.h +626 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/core/c/c_api_types.h +178 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/core/c/common.h +1496 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/core/macros.h +78 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/bits.h +102 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/fft.h +50 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/fft_io.h +34 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/fft_util.h +34 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/filterbank.h +63 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/filterbank_io.h +35 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/filterbank_util.h +50 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/frontend.h +64 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/frontend_io.h +31 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/frontend_util.h +52 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/kiss_fft_common.h +48 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/kiss_fft_int16.h +33 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/log_lut.h +40 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/log_scale.h +39 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/log_scale_io.h +33 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/log_scale_util.h +45 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/noise_reduction.h +46 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/noise_reduction_io.h +36 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/noise_reduction_util.h +50 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/pcan_gain_control.h +47 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/pcan_gain_control_util.h +57 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/window.h +49 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/window_io.h +34 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/experimental/microfrontend/lib/window_util.h +45 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/common.h +1358 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/compatibility.h +122 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/cppmath.h +40 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/max.h +35 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/min.h +35 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/optimized/neon_check.h +20 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/portable_tensor.h +141 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/portable_tensor_utils.h +623 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/quantization_util.h +292 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/add.h +561 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/add_n.h +86 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/arg_min_max.h +88 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/batch_matmul.h +275 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/batch_to_space_nd.h +101 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/binary_function.h +91 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/broadcast_args.h +56 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/broadcast_to.h +97 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/ceil.h +37 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/comparisons.h +271 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/concatenation.h +141 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/conv.h +289 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/cumsum.h +175 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/depth_to_space.h +79 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/depthwiseconv_float.h +100 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/depthwiseconv_uint8.h +319 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/dequantize.h +78 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/div.h +247 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/elu.h +37 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/exp.h +38 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/fill.h +38 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/floor.h +39 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/floor_div.h +35 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/floor_mod.h +44 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/fully_connected.h +323 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/hard_swish.h +168 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/integer_ops/add.h +250 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/integer_ops/conv.h +241 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/integer_ops/depthwise_conv.h +291 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/integer_ops/fully_connected.h +126 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/integer_ops/l2normalization.h +67 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/integer_ops/logistic.h +121 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/integer_ops/mean.h +18 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/integer_ops/mul.h +194 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/integer_ops/pooling.h +264 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/integer_ops/tanh.h +117 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/integer_ops/transpose_conv.h +224 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/l2normalization.h +90 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/leaky_relu.h +69 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/log_softmax.h +256 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/logistic.h +132 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/lstm_cell.h +422 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/maximum_minimum.h +64 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/mul.h +267 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/neg.h +37 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/pad.h +169 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/pooling.h +303 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/portable_tensor_utils.h +333 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/portable_tensor_utils_impl.h +244 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/prelu.h +111 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/process_broadcast_shapes.h +140 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/quantize.h +89 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/reduce.h +491 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/requantize.h +70 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/resize_bilinear.h +233 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/resize_nearest_neighbor.h +102 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/round.h +51 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/select.h +151 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/slice.h +80 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/softmax.h +233 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/space_to_batch_nd.h +109 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/space_to_depth.h +80 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/strided_slice.h +147 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/sub.h +465 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/tanh.h +129 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/transpose.h +203 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/reference/transpose_conv.h +225 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/runtime_shape.h +168 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/strided_slice_logic.h +278 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/tensor_ctypes.h +42 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/internal/types.h +1096 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/kernel_util.h +341 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/op_macros.h +49 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/kernels/padding.h +115 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/arena_allocator/ibuffer_allocator.h +100 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/arena_allocator/non_persistent_arena_buffer_allocator.h +104 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/arena_allocator/persistent_arena_buffer_allocator.h +58 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/arena_allocator/recording_single_arena_buffer_allocator.h +63 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/arena_allocator/single_arena_buffer_allocator.h +144 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/benchmarks/micro_benchmark.h +95 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/compatibility.h +32 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/cortex_m_generic/debug_log_callback.h +49 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/debug_log.h +38 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/examples/micro_speech/micro_model_settings.h +37 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/examples/network_tester/expected_output_data.h +47 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/examples/network_tester/input_data.h +108 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/examples/network_tester/network_model.h +166 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/examples/person_detection/detection_responder.h +32 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/examples/person_detection/image_provider.h +38 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/examples/person_detection/main_functions.h +37 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/examples/person_detection/model_settings.h +35 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/fake_micro_context.h +70 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/flatbuffer_utils.h +65 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/activation_utils.h +57 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/activations.h +64 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/add.h +78 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/arc_mli/mli_function_specializations.h +141 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/arc_mli/mli_interface.h +75 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/arc_mli/mli_slicers.h +56 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/arc_mli/mli_tf_utils.h +310 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/arc_mli/scratch_buf_mgr.h +145 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/arc_mli/scratch_buffers.h +78 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/ceva/ceva_common.h +24 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/ceva/ceva_tflm_lib.h +613 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/ceva/mcps_macros.h +115 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/ceva/types.h +1286 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/circular_buffer.h +45 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/circular_buffer_flexbuffers_generated_data.h +22 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/conv.h +117 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/conv_test.h +94 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/depthwise_conv.h +80 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/dequantize.h +38 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/detection_postprocess_flexbuffers_generated_data.h +25 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/ethosu.h +28 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/fully_connected.h +112 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/hard_swish.h +30 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/kernel_runner.h +86 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/kernel_util.h +150 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/leaky_relu.h +43 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/logical.h +35 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/logistic.h +42 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/lstm_eval.h +541 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/lstm_eval_test.h +817 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/lstm_shared.h +150 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/micro_ops.h +158 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/micro_tensor_utils.h +56 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/mul.h +74 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/pad.h +27 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/pooling.h +142 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/prelu.h +39 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/quantize.h +37 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/reduce.h +65 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/reshape.h +26 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/softmax.h +67 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/strided_slice.h +40 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/sub.h +60 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/svdf.h +100 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/testdata/conv_test_data.h +37 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/testdata/lstm_test_data.h +579 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/unidirectional_sequence_lstm.h +47 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/xtensa/hifimini/fixedpoint_utils.h +139 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/xtensa/lstm_eval.h +216 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/xtensa/lstm_shared.h +78 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/xtensa/xtensa.h +38 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/xtensa/xtensa_add.h +48 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/xtensa/xtensa_conv.h +89 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/xtensa/xtensa_depthwise_conv.h +74 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/xtensa/xtensa_fully_connected.h +78 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/xtensa/xtensa_pad.h +49 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/xtensa/xtensa_pooling.h +76 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/xtensa/xtensa_reduce.h +47 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/xtensa/xtensa_reshape.h +44 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/xtensa/xtensa_softmax.h +58 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/xtensa/xtensa_svdf.h +39 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/memory_helpers.h +64 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/memory_planner/greedy_memory_planner.h +170 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/memory_planner/linear_memory_planner.h +53 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/memory_planner/memory_plan_struct.h +73 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/memory_planner/micro_memory_planner.h +95 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/memory_planner/non_persistent_buffer_planner_shim.h +133 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/micro_allocation_info.h +138 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/micro_allocator.h +351 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/micro_arena_constants.h +28 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/micro_common.h +38 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/micro_context.h +176 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/micro_graph.h +79 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/micro_interpreter.h +189 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/micro_interpreter_context.h +125 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/micro_interpreter_graph.h +110 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/micro_log.h +42 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/micro_mutable_op_resolver.h +708 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/micro_op_resolver.h +62 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/micro_profiler.h +140 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/micro_profiler_interface.h +38 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/micro_resource_variable.h +89 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/micro_time.h +36 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/micro_utils.h +162 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/mock_micro_graph.h +60 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/python/interpreter/src/python_ops_resolver.h +21 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/python/tflite_size/src/flatbuffer_size.h +30 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/python/tflite_size/src/flatbuffer_size_wrapper.h +33 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/recording_micro_allocator.h +125 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/recording_micro_interpreter.h +69 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/system_setup.h +27 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/test_helper_custom_ops.h +49 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/test_helpers.h +334 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/testing/micro_test.h +267 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/testing/test_conv_model.h +23 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/tflite_bridge/flatbuffer_conversions_bridge.h +45 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/tflite_bridge/micro_error_reporter.h +36 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/tools/benchmarking/log_utils.h +273 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/tools/benchmarking/metrics.h +41 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/micro/tools/benchmarking/op_resolver.h +127 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/portable_type_to_tflitetype.h +75 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/schema/schema_generated.h +24644 -0
- xmos_ai_tools/runtime/include/tensorflow/lite/schema/schema_utils.h +33 -0
- xmos_ai_tools/runtime/include/tile_ram_server.h +38 -0
- xmos_ai_tools/runtime/lib/libhost_xtflitemicro.a +0 -0
- xmos_ai_tools/runtime/lib/libxtflitemicro.a +0 -0
- xmos_ai_tools/xformer/__init__.py +60 -0
- xmos_ai_tools/xformer/flash.py +190 -0
- xmos_ai_tools/xinterpreters/__init__.py +1 -0
- xmos_ai_tools/xinterpreters/exceptions.py +38 -0
- xmos_ai_tools/xinterpreters/host_interpreter.py +652 -0
- xmos_ai_tools/xinterpreters/libs/macos/xtflm_python.1.0.1.dylib +0 -0
- xmos_ai_tools/xinterpreters/libs/macos/xtflm_python.dylib +0 -0
- xmos_ai_tools-1.3.2.dev80.data/data/bin/xcore-opt +0 -0
- xmos_ai_tools-1.3.2.dev80.dist-info/METADATA +33 -0
- xmos_ai_tools-1.3.2.dev80.dist-info/RECORD +395 -0
- xmos_ai_tools-1.3.2.dev80.dist-info/WHEEL +5 -0
- xmos_ai_tools-1.3.2.dev80.dist-info/top_level.txt +1 -0
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/*
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* Copyright XMOS - (c) 2007 - 2018
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* AUTOGENERATED - DO NOT EDIT
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* by lib_xmosutils/Scripts/CreateXS1.pl
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*/
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#ifndef _xs3a_registers_h_
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#define _xs3a_registers_h_
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#define XS1_PS_RAM_BASE 0xb
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#define XS1_PS_VECTOR_BASE 0x10b
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#define XS1_PS_XCORE_CTRL0 0x20b
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#define XS1_PS_BOOT_CONFIG 0x30b
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#define XS1_PS_BOOT_STATUS 0x40b
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#define XS1_PS_SECURITY_CONFIG 0x50b
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#define XS1_PS_RING_OSC_CTRL 0x60b
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#define XS1_PS_RING_OSC_DATA0 0x70b
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#define XS1_PS_RING_OSC_DATA1 0x80b
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#define XS1_PS_RING_OSC_DATA2 0x90b
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#define XS1_PS_RING_OSC_DATA3 0xa0b
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#define XS1_PS_UNAVAILABLE_RESOURCE 0xb0b
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#define XS1_PS_RAM_SIZE 0xc0b
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#define XS1_PS_ROM_RMA 0xf0b
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#define XS1_PS_DBG_SSR 0x100b
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#define XS1_PS_DBG_SPC 0x110b
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#define XS1_PS_DBG_SSP 0x120b
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#define XS1_PS_DBG_T_NUM_NUM 0x13
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#define XS1_PS_DBG_T_NUM 0x130b
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#define XS1_PS_DBG_T_REG 0x140b
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#define XS1_PS_DBG_TYPE 0x150b
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#define XS1_PS_DBG_DATA 0x160b
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#define XS1_PS_DBG_RUN_CTRL 0x180b
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#define XS1_PS_DBG_SCRATCH_0 0x200b
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#define XS1_PS_DBG_SCRATCH_1 0x210b
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#define XS1_PS_DBG_SCRATCH_2 0x220b
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#define XS1_PS_DBG_SCRATCH_3 0x230b
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#define XS1_PS_DBG_SCRATCH_4 0x240b
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#define XS1_PS_DBG_SCRATCH_5 0x250b
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#define XS1_PS_DBG_SCRATCH_6 0x260b
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#define XS1_PS_DBG_SCRATCH_7 0x270b
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#define XS1_PS_DBG_IBREAK_ADDR_0 0x300b
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#define XS1_NUM_PS_DBG_IBREAK_ADDR 0x4
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#define XS1_PS_DBG_IBREAK_ADDR_1 0x310b
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#define XS1_PS_DBG_IBREAK_ADDR_2 0x320b
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#define XS1_PS_DBG_IBREAK_ADDR_3 0x330b
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#define XS1_PS_DBG_IBREAK_CTRL_0 0x400b
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#define XS1_NUM_PS_DBG_IBREAK_CTRL 0x4
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#define XS1_PS_DBG_IBREAK_CTRL_1 0x410b
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#define XS1_PS_DBG_IBREAK_CTRL_2 0x420b
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#define XS1_PS_DBG_IBREAK_CTRL_3 0x430b
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#define XS1_PS_DBG_DWATCH_ADDR1_0 0x500b
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#define XS1_NUM_PS_DBG_DWATCH_ADDR1 0x4
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#define XS1_PS_DBG_DWATCH_ADDR1_1 0x510b
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#define XS1_PS_DBG_DWATCH_ADDR1_2 0x520b
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#define XS1_PS_DBG_DWATCH_ADDR1_3 0x530b
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#define XS1_PS_DBG_DWATCH_ADDR2_0 0x600b
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#define XS1_NUM_PS_DBG_DWATCH_ADDR2 0x4
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#define XS1_PS_DBG_DWATCH_ADDR2_1 0x610b
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#define XS1_PS_DBG_DWATCH_ADDR2_2 0x620b
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#define XS1_PS_DBG_DWATCH_ADDR2_3 0x630b
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#define XS1_PS_DBG_DWATCH_CTRL_0 0x700b
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#define XS1_NUM_PS_DBG_DWATCH_CTRL 0x4
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#define XS1_PS_DBG_DWATCH_CTRL_1 0x710b
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#define XS1_PS_DBG_RWATCH_ADDR1_0 0x800b
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#define XS1_PS_DBG_RWATCH_ADDR2_1 0x910b
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#define XS1_PS_DBG_RWATCH_ADDR2_2 0x920b
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#define XS1_PS_DBG_RWATCH_ADDR2_3 0x930b
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#define XS1_PS_DBG_RWATCH_CTRL_0 0x9c0b
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#define XS1_NUM_PS_DBG_RWATCH_CTRL 0x4
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#define XS1_PS_DBG_RWATCH_CTRL_1 0x9d0b
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#define XS1_PS_DBG_RWATCH_CTRL_2 0x9e0b
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#define XS1_PS_DBG_RWATCH_CTRL_3 0x9f0b
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#define XS1_PS_CACHE_MISS_CNT 0xa00b
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#define XS1_PS_CACHE_ACCESS_CNT 0xa10b
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#define XS1_SSWITCH_DEVICE_ID0_NUM 0x0
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#define XS1_SSWITCH_DEVICE_ID1_NUM 0x1
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#define XS1_SSWITCH_DEVICE_ID2_NUM 0x2
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#define XS1_SSWITCH_DEVICE_ID3_NUM 0x3
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#define XS1_SSWITCH_NODE_CONFIG_NUM 0x4
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|
+
#define XS1_SSWITCH_NODE_ID_NUM 0x5
|
90
|
+
#define XS1_SSWITCH_PLL_CTL_NUM 0x6
|
91
|
+
#define XS1_SSWITCH_CLK_DIVIDER_NUM 0x7
|
92
|
+
#define XS1_SSWITCH_REF_CLK_DIVIDER_NUM 0x8
|
93
|
+
#define XS1_SSWITCH_JTAG_DEVICE_ID_NUM 0x9
|
94
|
+
#define XS1_SSWITCH_JTAG_USERCODE_NUM 0xa
|
95
|
+
#define XS1_SSWITCH_DDR_CLK_DIVIDER_NUM 0xb
|
96
|
+
#define XS1_SSWITCH_DIMENSION_DIRECTION0_NUM 0xc
|
97
|
+
#define XS1_SSWITCH_DIMENSION_DIRECTION1_NUM 0xd
|
98
|
+
#define XS1_SSWITCH_SS_APP_CLK_DIVIDER_NUM 0xe
|
99
|
+
#define XS1_SSWITCH_SS_APP_PLL_CTL_NUM 0xf
|
100
|
+
#define XS1_SSWITCH_XCORE0_GLOBAL_DEBUG_CONFIG_NUM 0x10
|
101
|
+
#define XS1_SSWITCH_XCORE1_GLOBAL_DEBUG_CONFIG_NUM 0x11
|
102
|
+
#define XS1_SSWITCH_SS_APP_PLL_FRAC_N_DIVIDER_NUM 0x12
|
103
|
+
#define XS1_SSWITCH_MIPI_CLK_DIVIDER_NUM 0x14
|
104
|
+
#define XS1_SSWITCH_MIPI_CFG_CLK_DIVIDER_NUM 0x15
|
105
|
+
#define XS1_SSWITCH_GLOBAL_DEBUG_SOURCE_NUM 0x1f
|
106
|
+
#define XS1_SSWITCH_SLINK_0_NUM 0x20
|
107
|
+
#define XS1_NUM_SSWITCH_SLINK 0x9
|
108
|
+
#define XS1_SSWITCH_SLINK_1_NUM 0x21
|
109
|
+
#define XS1_SSWITCH_SLINK_2_NUM 0x22
|
110
|
+
#define XS1_SSWITCH_SLINK_3_NUM 0x23
|
111
|
+
#define XS1_SSWITCH_SLINK_4_NUM 0x24
|
112
|
+
#define XS1_SSWITCH_SLINK_5_NUM 0x25
|
113
|
+
#define XS1_SSWITCH_SLINK_6_NUM 0x26
|
114
|
+
#define XS1_SSWITCH_SLINK_7_NUM 0x27
|
115
|
+
#define XS1_SSWITCH_SLINK_8_NUM 0x28
|
116
|
+
#define XS1_SSWITCH_PLINK_0_NUM 0x40
|
117
|
+
#define XS1_NUM_SSWITCH_PLINK 0x8
|
118
|
+
#define XS1_SSWITCH_PLINK_1_NUM 0x41
|
119
|
+
#define XS1_SSWITCH_PLINK_2_NUM 0x42
|
120
|
+
#define XS1_SSWITCH_PLINK_3_NUM 0x43
|
121
|
+
#define XS1_SSWITCH_PLINK_4_NUM 0x44
|
122
|
+
#define XS1_SSWITCH_PLINK_5_NUM 0x45
|
123
|
+
#define XS1_SSWITCH_PLINK_6_NUM 0x46
|
124
|
+
#define XS1_SSWITCH_PLINK_7_NUM 0x47
|
125
|
+
#define XS1_SSWITCH_XLINK_0_NUM 0x80
|
126
|
+
#define XS1_NUM_SSWITCH_XLINK 0x9
|
127
|
+
#define XS1_SSWITCH_XLINK_1_NUM 0x81
|
128
|
+
#define XS1_SSWITCH_XLINK_2_NUM 0x82
|
129
|
+
#define XS1_SSWITCH_XLINK_3_NUM 0x83
|
130
|
+
#define XS1_SSWITCH_XLINK_4_NUM 0x84
|
131
|
+
#define XS1_SSWITCH_XLINK_5_NUM 0x85
|
132
|
+
#define XS1_SSWITCH_XLINK_6_NUM 0x86
|
133
|
+
#define XS1_SSWITCH_XLINK_7_NUM 0x87
|
134
|
+
#define XS1_SSWITCH_XLINK_8_NUM 0x88
|
135
|
+
#define XS1_SSWITCH_XSTATIC_0_NUM 0xa0
|
136
|
+
#define XS1_NUM_SSWITCH_XSTATIC 0x8
|
137
|
+
#define XS1_SSWITCH_XSTATIC_1_NUM 0xa1
|
138
|
+
#define XS1_SSWITCH_XSTATIC_2_NUM 0xa2
|
139
|
+
#define XS1_SSWITCH_XSTATIC_3_NUM 0xa3
|
140
|
+
#define XS1_SSWITCH_XSTATIC_4_NUM 0xa4
|
141
|
+
#define XS1_SSWITCH_XSTATIC_5_NUM 0xa5
|
142
|
+
#define XS1_SSWITCH_XSTATIC_6_NUM 0xa6
|
143
|
+
#define XS1_SSWITCH_XSTATIC_7_NUM 0xa7
|
144
|
+
#define XS1_SSWITCH_USB_XCFGI_REG0_NUM 0xf000
|
145
|
+
#define XS1_SSWITCH_USB_XCFGI_REG1_NUM 0xf001
|
146
|
+
#define XS1_SSWITCH_USB_XCFGI_REG2_NUM 0xf002
|
147
|
+
#define XS1_SSWITCH_USB_XCFG_COARSE_TUNE_NUM 0xf003
|
148
|
+
#define XS1_SSWITCH_USB_XCFG_FINE_TUNE_NUM 0xf004
|
149
|
+
#define XS1_SSWITCH_USB_XCFG_LOCK_RANGE_MAX_NUM 0xf005
|
150
|
+
#define XS1_SSWITCH_USB_XCFG_LOCK_RANGE_MIN_NUM 0xf006
|
151
|
+
#define XS1_SSWITCH_USB_PHY_CFG0_NUM 0xf008
|
152
|
+
#define XS1_SSWITCH_USB_PHY_CFG1_NUM 0xf009
|
153
|
+
#define XS1_SSWITCH_USB_PHY_CFG2_NUM 0xf00a
|
154
|
+
#define XS1_SSWITCH_USB_PHY_CFG3_NUM 0xf00b
|
155
|
+
#define XS1_SSWITCH_USB_SHIM_CFG_NUM 0xf00c
|
156
|
+
#define XS1_SSWITCH_USB_PHY_XCFGO_REG0_NUM 0xf010
|
157
|
+
#define XS1_SSWITCH_USB_PHY_STATUS_NUM 0xf011
|
158
|
+
#define XS1_SSWITCH_WATCHDOG_CFG_NUM 0xf020
|
159
|
+
#define XS1_SSWITCH_WATCHDOG_PRESCALER_NUM 0xf021
|
160
|
+
#define XS1_SSWITCH_WATCHDOG_PRESCALER_WRAP_NUM 0xf022
|
161
|
+
#define XS1_SSWITCH_WATCHDOG_COUNT_NUM 0xf023
|
162
|
+
#define XS1_SSWITCH_WATCHDOG_STATUS_NUM 0xf024
|
163
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG0_NUM 0xe000
|
164
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG1_NUM 0xe001
|
165
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG2_NUM 0xe002
|
166
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG3_NUM 0xe003
|
167
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG4_NUM 0xe004
|
168
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG5_NUM 0xe005
|
169
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG6_NUM 0xe006
|
170
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG7_NUM 0xe007
|
171
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG8_NUM 0xe008
|
172
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG9_NUM 0xe009
|
173
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG10_NUM 0xe00a
|
174
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG11_NUM 0xe00b
|
175
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG12_NUM 0xe00c
|
176
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG13_NUM 0xe00d
|
177
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG14_NUM 0xe00e
|
178
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG15_NUM 0xe00f
|
179
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG16_NUM 0xe010
|
180
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG17_NUM 0xe011
|
181
|
+
#define XS1_SSWITCH_MIPI_XCFGI_REG18_NUM 0xe012
|
182
|
+
#define XS1_SSWITCH_MIPI_STATUS0_NUM 0xe013
|
183
|
+
#define XS1_SSWITCH_MIPI_SHIM_STATUS_NUM 0xe014
|
184
|
+
#define XS1_SSWITCH_MIPI_DPHY_CFG0_NUM 0xe018
|
185
|
+
#define XS1_SSWITCH_MIPI_DPHY_CFG1_NUM 0xe019
|
186
|
+
#define XS1_SSWITCH_MIPI_DPHY_CFG2_NUM 0xe01a
|
187
|
+
#define XS1_SSWITCH_MIPI_DPHY_CFG3_NUM 0xe01b
|
188
|
+
#define XS1_SSWITCH_MIPI_DPHY_CFG4_NUM 0xe01c
|
189
|
+
#define XS1_SSWITCH_MIPI_DPHY_CFG5_NUM 0xe01d
|
190
|
+
#define XS1_SSWITCH_MIPI_SHIM_CFG0_NUM 0xe01f
|
191
|
+
#define XS1_SSWITCH_MIPI_XCFGO_REG0_NUM 0xe020
|
192
|
+
#define XS1_SSWITCH_MIPI_XCFGO_REG1_NUM 0xe021
|
193
|
+
#define XS1_SSWITCH_MIPI_XCFGO_REG2_NUM 0xe022
|
194
|
+
#define XS1_SSWITCH_LPDDR_IID_ENABLE_NUM 0xc000
|
195
|
+
#define XS1_SSWITCH_LPDDR_IID_0_7_NUM 0xc001
|
196
|
+
#define XS1_SSWITCH_LPDDR_IID_8_15_NUM 0xc002
|
197
|
+
#define XS1_SSWITCH_LPDDR_QUEUE_CONT_NUM 0xc003
|
198
|
+
#define XS1_SSWITCH_LPDDR_RO_COMMAND_QUEUE_PRIORITY_NUM 0xc008
|
199
|
+
#define XS1_SSWITCH_LPDDR_RW_COMMAND_QUEUE_PRIORITY_NUM 0xc009
|
200
|
+
#define XS1_SSWITCH_LPDDR_ARBITRATION_TIMEOUT_NUM 0xc00a
|
201
|
+
#define XS1_SSWITCH_LPDDR_ARBITRATION_MTG_COMMAND_NUM 0xc010
|
202
|
+
#define XS1_SSWITCH_LPDDR_DLL_CONTROL_NUM 0xc014
|
203
|
+
#define XS1_SSWITCH_LPDDR_DLL_MEASUREMENT_STATUS_NUM 0xc015
|
204
|
+
#define XS1_SSWITCH_LPDDR_DLL_MANUAL_CONTROL_NUM 0xc016
|
205
|
+
#define XS1_SSWITCH_LPDDR_DLL_PHY_CALIBRATION_DATA_NUM 0xc017
|
206
|
+
#define XS1_SSWITCH_LPDDR_PHY_CONTROL_NUM 0xc01d
|
207
|
+
#define XS1_SSWITCH_LPDDR_LMR_OPCODE_NUM 0xc01e
|
208
|
+
#define XS1_SSWITCH_LPDDR_EMR_OPCODE_NUM 0xc01f
|
209
|
+
#define XS1_SSWITCH_LPDDR_PROTOCOL_ENGINE_CONF_0_NUM 0xc020
|
210
|
+
#define XS1_SSWITCH_LPDDR_PROTOCOL_ENGINE_CONF_1_NUM 0xc021
|
211
|
+
#define XS1_SSWITCH_LPDDR_PROTOCOL_ENGINE_STATUS_NUM 0xc022
|
212
|
+
#define XS1_SSWITCH_PADCTRL_CLK_NUM 0xd000
|
213
|
+
#define XS1_SSWITCH_PADCTRL_CKE_NUM 0xd001
|
214
|
+
#define XS1_SSWITCH_PADCTRL_CS_N_NUM 0xd002
|
215
|
+
#define XS1_SSWITCH_PADCTRL_WE_N_NUM 0xd003
|
216
|
+
#define XS1_SSWITCH_PADCTRL_CAS_N_NUM 0xd004
|
217
|
+
#define XS1_SSWITCH_PADCTRL_RAS_N_NUM 0xd005
|
218
|
+
#define XS1_SSWITCH_PADCTRL_ADDR_NUM 0xd006
|
219
|
+
#define XS1_SSWITCH_PADCTRL_BA_NUM 0xd007
|
220
|
+
#define XS1_SSWITCH_PADCTRL_DQ_NUM 0xd008
|
221
|
+
#define XS1_SSWITCH_PADCTRL_DQS_NUM 0xd009
|
222
|
+
#define XS1_SSWITCH_PADCTRL_DM_NUM 0xd00a
|
223
|
+
#define XS1_PSWITCH_DEVICE_ID0_NUM 0x0
|
224
|
+
#define XS1_PSWITCH_DEVICE_ID1_NUM 0x1
|
225
|
+
#define XS1_PSWITCH_DEVICE_ID2_NUM 0x2
|
226
|
+
#define XS1_PSWITCH_DEVICE_ID3_NUM 0x3
|
227
|
+
#define XS1_PSWITCH_DBG_CTRL_NUM 0x4
|
228
|
+
#define XS1_PSWITCH_DBG_INT_NUM 0x5
|
229
|
+
#define XS1_PSWITCH_PLL_CLK_DIVIDER_NUM 0x6
|
230
|
+
#define XS1_PSWITCH_SECU_CONFIG_NUM 0x7
|
231
|
+
#define XS1_PSWITCH_DBG_SCRATCH_0_NUM 0x20
|
232
|
+
#define XS1_NUM_PSWITCH_DBG_SCRATCH 0x8
|
233
|
+
#define XS1_PSWITCH_DBG_SCRATCH_1_NUM 0x21
|
234
|
+
#define XS1_PSWITCH_DBG_SCRATCH_2_NUM 0x22
|
235
|
+
#define XS1_PSWITCH_DBG_SCRATCH_3_NUM 0x23
|
236
|
+
#define XS1_PSWITCH_DBG_SCRATCH_4_NUM 0x24
|
237
|
+
#define XS1_PSWITCH_DBG_SCRATCH_5_NUM 0x25
|
238
|
+
#define XS1_PSWITCH_DBG_SCRATCH_6_NUM 0x26
|
239
|
+
#define XS1_PSWITCH_DBG_SCRATCH_7_NUM 0x27
|
240
|
+
#define XS1_PSWITCH_T0_PC_NUM 0x40
|
241
|
+
#define XS1_PSWITCH_T1_PC_NUM 0x41
|
242
|
+
#define XS1_PSWITCH_T2_PC_NUM 0x42
|
243
|
+
#define XS1_PSWITCH_T3_PC_NUM 0x43
|
244
|
+
#define XS1_PSWITCH_T4_PC_NUM 0x44
|
245
|
+
#define XS1_PSWITCH_T5_PC_NUM 0x45
|
246
|
+
#define XS1_PSWITCH_T6_PC_NUM 0x46
|
247
|
+
#define XS1_PSWITCH_T7_PC_NUM 0x47
|
248
|
+
#define XS1_PSWITCH_T0_SR_NUM 0x60
|
249
|
+
#define XS1_PSWITCH_T1_SR_NUM 0x61
|
250
|
+
#define XS1_PSWITCH_T2_SR_NUM 0x62
|
251
|
+
#define XS1_PSWITCH_T3_SR_NUM 0x63
|
252
|
+
#define XS1_PSWITCH_T4_SR_NUM 0x64
|
253
|
+
#define XS1_PSWITCH_T5_SR_NUM 0x65
|
254
|
+
#define XS1_PSWITCH_T6_SR_NUM 0x66
|
255
|
+
#define XS1_PSWITCH_T7_SR_NUM 0x67
|
256
|
+
#define XS1_ID_ID_SHIFT 0x0
|
257
|
+
#define XS1_ID_ID_SIZE 0x6
|
258
|
+
#define XS1_ID_ID_MASK (((1 << XS1_ID_ID_SIZE) - 1) << XS1_ID_ID_SHIFT)
|
259
|
+
#define XS1_ID_ID(x) (((x)&XS1_ID_ID_MASK) >> XS1_ID_ID_SHIFT)
|
260
|
+
#define XS1_ID_ID_SET(x, v) \
|
261
|
+
(((x) & ~XS1_ID_ID_MASK) | (((v) << XS1_ID_ID_SHIFT) & XS1_ID_ID_MASK))
|
262
|
+
#define XS1_EXCEPTION_TYPE_SHIFT 0x0
|
263
|
+
#define XS1_EXCEPTION_TYPE_SIZE 0x5
|
264
|
+
#define XS1_EXCEPTION_TYPE_MASK \
|
265
|
+
(((1 << XS1_EXCEPTION_TYPE_SIZE) - 1) << XS1_EXCEPTION_TYPE_SHIFT)
|
266
|
+
#define XS1_EXCEPTION_TYPE(x) \
|
267
|
+
(((x)&XS1_EXCEPTION_TYPE_MASK) >> XS1_EXCEPTION_TYPE_SHIFT)
|
268
|
+
#define XS1_EXCEPTION_TYPE_SET(x, v) \
|
269
|
+
(((x) & ~XS1_EXCEPTION_TYPE_MASK) | \
|
270
|
+
(((v) << XS1_EXCEPTION_TYPE_SHIFT) & XS1_EXCEPTION_TYPE_MASK))
|
271
|
+
#define XS1_DBG_T_NUM_NUM_SHIFT 0x0
|
272
|
+
#define XS1_DBG_T_NUM_NUM_SIZE 0x8
|
273
|
+
#define XS1_DBG_T_NUM_NUM_MASK \
|
274
|
+
(((1 << XS1_DBG_T_NUM_NUM_SIZE) - 1) << XS1_DBG_T_NUM_NUM_SHIFT)
|
275
|
+
#define XS1_DBG_T_NUM_NUM(x) \
|
276
|
+
(((x)&XS1_DBG_T_NUM_NUM_MASK) >> XS1_DBG_T_NUM_NUM_SHIFT)
|
277
|
+
#define XS1_DBG_T_NUM_NUM_SET(x, v) \
|
278
|
+
(((x) & ~XS1_DBG_T_NUM_NUM_MASK) | \
|
279
|
+
(((v) << XS1_DBG_T_NUM_NUM_SHIFT) & XS1_DBG_T_NUM_NUM_MASK))
|
280
|
+
#define XS1_DBG_T_REG_REG_SHIFT 0x0
|
281
|
+
#define XS1_DBG_T_REG_REG_SIZE 0x5
|
282
|
+
#define XS1_DBG_T_REG_REG_MASK \
|
283
|
+
(((1 << XS1_DBG_T_REG_REG_SIZE) - 1) << XS1_DBG_T_REG_REG_SHIFT)
|
284
|
+
#define XS1_DBG_T_REG_REG(x) \
|
285
|
+
(((x)&XS1_DBG_T_REG_REG_MASK) >> XS1_DBG_T_REG_REG_SHIFT)
|
286
|
+
#define XS1_DBG_T_REG_REG_SET(x, v) \
|
287
|
+
(((x) & ~XS1_DBG_T_REG_REG_MASK) | \
|
288
|
+
(((v) << XS1_DBG_T_REG_REG_SHIFT) & XS1_DBG_T_REG_REG_MASK))
|
289
|
+
#define XS1_BRK_ENABLE_SHIFT 0x0
|
290
|
+
#define XS1_BRK_ENABLE_SIZE 0x1
|
291
|
+
#define XS1_BRK_ENABLE_MASK \
|
292
|
+
(((1 << XS1_BRK_ENABLE_SIZE) - 1) << XS1_BRK_ENABLE_SHIFT)
|
293
|
+
#define XS1_BRK_ENABLE(x) (((x)&XS1_BRK_ENABLE_MASK) >> XS1_BRK_ENABLE_SHIFT)
|
294
|
+
#define XS1_BRK_ENABLE_SET(x, v) \
|
295
|
+
(((x) & ~XS1_BRK_ENABLE_MASK) | \
|
296
|
+
(((v) << XS1_BRK_ENABLE_SHIFT) & XS1_BRK_ENABLE_MASK))
|
297
|
+
#define XS1_ALL_BITS_SHIFT 0x0
|
298
|
+
#define XS1_ALL_BITS_SIZE 0x20
|
299
|
+
#define XS1_ALL_BITS_MASK (((1 << XS1_ALL_BITS_SIZE) - 1) << XS1_ALL_BITS_SHIFT)
|
300
|
+
#define XS1_ALL_BITS(x) (((x)&XS1_ALL_BITS_MASK) >> XS1_ALL_BITS_SHIFT)
|
301
|
+
#define XS1_ALL_BITS_SET(x, v) \
|
302
|
+
(((x) & ~XS1_ALL_BITS_MASK) | \
|
303
|
+
(((v) << XS1_ALL_BITS_SHIFT) & XS1_ALL_BITS_MASK))
|
304
|
+
#define XS1_KEP_ADDRESS_BITS_SHIFT 0x7
|
305
|
+
#define XS1_KEP_ADDRESS_BITS_SIZE 0x19
|
306
|
+
#define XS1_KEP_ADDRESS_BITS_MASK \
|
307
|
+
(((1 << XS1_KEP_ADDRESS_BITS_SIZE) - 1) << XS1_KEP_ADDRESS_BITS_SHIFT)
|
308
|
+
#define XS1_KEP_ADDRESS_BITS(x) \
|
309
|
+
(((x)&XS1_KEP_ADDRESS_BITS_MASK) >> XS1_KEP_ADDRESS_BITS_SHIFT)
|
310
|
+
#define XS1_KEP_ADDRESS_BITS_SET(x, v) \
|
311
|
+
(((x) & ~XS1_KEP_ADDRESS_BITS_MASK) | \
|
312
|
+
(((v) << XS1_KEP_ADDRESS_BITS_SHIFT) & XS1_KEP_ADDRESS_BITS_MASK))
|
313
|
+
#define XS1_WORD_ADDRESS_BITS_SHIFT 0x2
|
314
|
+
#define XS1_WORD_ADDRESS_BITS_SIZE 0x1e
|
315
|
+
#define XS1_WORD_ADDRESS_BITS_MASK \
|
316
|
+
(((1 << XS1_WORD_ADDRESS_BITS_SIZE) - 1) << XS1_WORD_ADDRESS_BITS_SHIFT)
|
317
|
+
#define XS1_WORD_ADDRESS_BITS(x) \
|
318
|
+
(((x)&XS1_WORD_ADDRESS_BITS_MASK) >> XS1_WORD_ADDRESS_BITS_SHIFT)
|
319
|
+
#define XS1_WORD_ADDRESS_BITS_SET(x, v) \
|
320
|
+
(((x) & ~XS1_WORD_ADDRESS_BITS_MASK) | \
|
321
|
+
(((v) << XS1_WORD_ADDRESS_BITS_SHIFT) & XS1_WORD_ADDRESS_BITS_MASK))
|
322
|
+
#define XS1_VECTOR_BASE_SHIFT 0x13
|
323
|
+
#define XS1_VECTOR_BASE_SIZE 0xd
|
324
|
+
#define XS1_VECTOR_BASE_MASK \
|
325
|
+
(((1 << XS1_VECTOR_BASE_SIZE) - 1) << XS1_VECTOR_BASE_SHIFT)
|
326
|
+
#define XS1_VECTOR_BASE(x) (((x)&XS1_VECTOR_BASE_MASK) >> XS1_VECTOR_BASE_SHIFT)
|
327
|
+
#define XS1_VECTOR_BASE_SET(x, v) \
|
328
|
+
(((x) & ~XS1_VECTOR_BASE_MASK) | \
|
329
|
+
(((v) << XS1_VECTOR_BASE_SHIFT) & XS1_VECTOR_BASE_MASK))
|
330
|
+
#define XS1_IBRK_CONDITION_SHIFT 0x1
|
331
|
+
#define XS1_IBRK_CONDITION_SIZE 0x1
|
332
|
+
#define XS1_IBRK_CONDITION_MASK \
|
333
|
+
(((1 << XS1_IBRK_CONDITION_SIZE) - 1) << XS1_IBRK_CONDITION_SHIFT)
|
334
|
+
#define XS1_IBRK_CONDITION(x) \
|
335
|
+
(((x)&XS1_IBRK_CONDITION_MASK) >> XS1_IBRK_CONDITION_SHIFT)
|
336
|
+
#define XS1_IBRK_CONDITION_SET(x, v) \
|
337
|
+
(((x) & ~XS1_IBRK_CONDITION_MASK) | \
|
338
|
+
(((v) << XS1_IBRK_CONDITION_SHIFT) & XS1_IBRK_CONDITION_MASK))
|
339
|
+
#define XS1_DBRK_CONDITION_SHIFT 0x1
|
340
|
+
#define XS1_DBRK_CONDITION_SIZE 0x1
|
341
|
+
#define XS1_DBRK_CONDITION_MASK \
|
342
|
+
(((1 << XS1_DBRK_CONDITION_SIZE) - 1) << XS1_DBRK_CONDITION_SHIFT)
|
343
|
+
#define XS1_DBRK_CONDITION(x) \
|
344
|
+
(((x)&XS1_DBRK_CONDITION_MASK) >> XS1_DBRK_CONDITION_SHIFT)
|
345
|
+
#define XS1_DBRK_CONDITION_SET(x, v) \
|
346
|
+
(((x) & ~XS1_DBRK_CONDITION_MASK) | \
|
347
|
+
(((v) << XS1_DBRK_CONDITION_SHIFT) & XS1_DBRK_CONDITION_MASK))
|
348
|
+
#define XS1_RBRK_CONDITION_SHIFT 0x1
|
349
|
+
#define XS1_RBRK_CONDITION_SIZE 0x1
|
350
|
+
#define XS1_RBRK_CONDITION_MASK \
|
351
|
+
(((1 << XS1_RBRK_CONDITION_SIZE) - 1) << XS1_RBRK_CONDITION_SHIFT)
|
352
|
+
#define XS1_RBRK_CONDITION(x) \
|
353
|
+
(((x)&XS1_RBRK_CONDITION_MASK) >> XS1_RBRK_CONDITION_SHIFT)
|
354
|
+
#define XS1_RBRK_CONDITION_SET(x, v) \
|
355
|
+
(((x) & ~XS1_RBRK_CONDITION_MASK) | \
|
356
|
+
(((v) << XS1_RBRK_CONDITION_SHIFT) & XS1_RBRK_CONDITION_MASK))
|
357
|
+
#define XS1_BRK_LOAD_SHIFT 0x2
|
358
|
+
#define XS1_BRK_LOAD_SIZE 0x1
|
359
|
+
#define XS1_BRK_LOAD_MASK (((1 << XS1_BRK_LOAD_SIZE) - 1) << XS1_BRK_LOAD_SHIFT)
|
360
|
+
#define XS1_BRK_LOAD(x) (((x)&XS1_BRK_LOAD_MASK) >> XS1_BRK_LOAD_SHIFT)
|
361
|
+
#define XS1_BRK_LOAD_SET(x, v) \
|
362
|
+
(((x) & ~XS1_BRK_LOAD_MASK) | \
|
363
|
+
(((v) << XS1_BRK_LOAD_SHIFT) & XS1_BRK_LOAD_MASK))
|
364
|
+
#define XS1_BRK_THREADS_SHIFT 0x10
|
365
|
+
#define XS1_BRK_THREADS_SIZE 0x8
|
366
|
+
#define XS1_BRK_THREADS_MASK \
|
367
|
+
(((1 << XS1_BRK_THREADS_SIZE) - 1) << XS1_BRK_THREADS_SHIFT)
|
368
|
+
#define XS1_BRK_THREADS(x) (((x)&XS1_BRK_THREADS_MASK) >> XS1_BRK_THREADS_SHIFT)
|
369
|
+
#define XS1_BRK_THREADS_SET(x, v) \
|
370
|
+
(((x) & ~XS1_BRK_THREADS_MASK) | \
|
371
|
+
(((v) << XS1_BRK_THREADS_SHIFT) & XS1_BRK_THREADS_MASK))
|
372
|
+
#define XS1_DBG_TYPE_CAUSE_SHIFT 0x0
|
373
|
+
#define XS1_DBG_TYPE_CAUSE_SIZE 0x3
|
374
|
+
#define XS1_DBG_TYPE_CAUSE_MASK \
|
375
|
+
(((1 << XS1_DBG_TYPE_CAUSE_SIZE) - 1) << XS1_DBG_TYPE_CAUSE_SHIFT)
|
376
|
+
#define XS1_DBG_TYPE_CAUSE(x) \
|
377
|
+
(((x)&XS1_DBG_TYPE_CAUSE_MASK) >> XS1_DBG_TYPE_CAUSE_SHIFT)
|
378
|
+
#define XS1_DBG_TYPE_CAUSE_SET(x, v) \
|
379
|
+
(((x) & ~XS1_DBG_TYPE_CAUSE_MASK) | \
|
380
|
+
(((v) << XS1_DBG_TYPE_CAUSE_SHIFT) & XS1_DBG_TYPE_CAUSE_MASK))
|
381
|
+
#define XS1_DBG_TYPE_T_NUM_SHIFT 0x8
|
382
|
+
#define XS1_DBG_TYPE_T_NUM_SIZE 0x8
|
383
|
+
#define XS1_DBG_TYPE_T_NUM_MASK \
|
384
|
+
(((1 << XS1_DBG_TYPE_T_NUM_SIZE) - 1) << XS1_DBG_TYPE_T_NUM_SHIFT)
|
385
|
+
#define XS1_DBG_TYPE_T_NUM(x) \
|
386
|
+
(((x)&XS1_DBG_TYPE_T_NUM_MASK) >> XS1_DBG_TYPE_T_NUM_SHIFT)
|
387
|
+
#define XS1_DBG_TYPE_T_NUM_SET(x, v) \
|
388
|
+
(((x) & ~XS1_DBG_TYPE_T_NUM_MASK) | \
|
389
|
+
(((v) << XS1_DBG_TYPE_T_NUM_SHIFT) & XS1_DBG_TYPE_T_NUM_MASK))
|
390
|
+
#define XS1_DBG_TYPE_HW_NUM_SHIFT 0x10
|
391
|
+
#define XS1_DBG_TYPE_HW_NUM_SIZE 0x2
|
392
|
+
#define XS1_DBG_TYPE_HW_NUM_MASK \
|
393
|
+
(((1 << XS1_DBG_TYPE_HW_NUM_SIZE) - 1) << XS1_DBG_TYPE_HW_NUM_SHIFT)
|
394
|
+
#define XS1_DBG_TYPE_HW_NUM(x) \
|
395
|
+
(((x)&XS1_DBG_TYPE_HW_NUM_MASK) >> XS1_DBG_TYPE_HW_NUM_SHIFT)
|
396
|
+
#define XS1_DBG_TYPE_HW_NUM_SET(x, v) \
|
397
|
+
(((x) & ~XS1_DBG_TYPE_HW_NUM_MASK) | \
|
398
|
+
(((v) << XS1_DBG_TYPE_HW_NUM_SHIFT) & XS1_DBG_TYPE_HW_NUM_MASK))
|
399
|
+
#define XS1_DBG_RUN_CTRL_STOP_SHIFT 0x0
|
400
|
+
#define XS1_DBG_RUN_CTRL_STOP_SIZE 0x8
|
401
|
+
#define XS1_DBG_RUN_CTRL_STOP_MASK \
|
402
|
+
(((1 << XS1_DBG_RUN_CTRL_STOP_SIZE) - 1) << XS1_DBG_RUN_CTRL_STOP_SHIFT)
|
403
|
+
#define XS1_DBG_RUN_CTRL_STOP(x) \
|
404
|
+
(((x)&XS1_DBG_RUN_CTRL_STOP_MASK) >> XS1_DBG_RUN_CTRL_STOP_SHIFT)
|
405
|
+
#define XS1_DBG_RUN_CTRL_STOP_SET(x, v) \
|
406
|
+
(((x) & ~XS1_DBG_RUN_CTRL_STOP_MASK) | \
|
407
|
+
(((v) << XS1_DBG_RUN_CTRL_STOP_SHIFT) & XS1_DBG_RUN_CTRL_STOP_MASK))
|
408
|
+
#define XS1_XCORE_CTRL0_USB_ENABLE_SHIFT 0x1
|
409
|
+
#define XS1_XCORE_CTRL0_USB_ENABLE_SIZE 0x1
|
410
|
+
#define XS1_XCORE_CTRL0_USB_ENABLE_MASK \
|
411
|
+
(((1 << XS1_XCORE_CTRL0_USB_ENABLE_SIZE) - 1) \
|
412
|
+
<< XS1_XCORE_CTRL0_USB_ENABLE_SHIFT)
|
413
|
+
#define XS1_XCORE_CTRL0_USB_ENABLE(x) \
|
414
|
+
(((x)&XS1_XCORE_CTRL0_USB_ENABLE_MASK) >> XS1_XCORE_CTRL0_USB_ENABLE_SHIFT)
|
415
|
+
#define XS1_XCORE_CTRL0_USB_ENABLE_SET(x, v) \
|
416
|
+
(((x) & ~XS1_XCORE_CTRL0_USB_ENABLE_MASK) | \
|
417
|
+
(((v) << XS1_XCORE_CTRL0_USB_ENABLE_SHIFT) & \
|
418
|
+
XS1_XCORE_CTRL0_USB_ENABLE_MASK))
|
419
|
+
#define XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SHIFT 0x4
|
420
|
+
#define XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SIZE 0x1
|
421
|
+
#define XS1_XCORE_CTRL0_CLK_DIVIDER_EN_MASK \
|
422
|
+
(((1 << XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SIZE) - 1) \
|
423
|
+
<< XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SHIFT)
|
424
|
+
#define XS1_XCORE_CTRL0_CLK_DIVIDER_EN(x) \
|
425
|
+
(((x)&XS1_XCORE_CTRL0_CLK_DIVIDER_EN_MASK) >> \
|
426
|
+
XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SHIFT)
|
427
|
+
#define XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SET(x, v) \
|
428
|
+
(((x) & ~XS1_XCORE_CTRL0_CLK_DIVIDER_EN_MASK) | \
|
429
|
+
(((v) << XS1_XCORE_CTRL0_CLK_DIVIDER_EN_SHIFT) & \
|
430
|
+
XS1_XCORE_CTRL0_CLK_DIVIDER_EN_MASK))
|
431
|
+
#define XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SHIFT 0x5
|
432
|
+
#define XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SIZE 0x1
|
433
|
+
#define XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_MASK \
|
434
|
+
(((1 << XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SIZE) - 1) \
|
435
|
+
<< XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SHIFT)
|
436
|
+
#define XS1_XCORE_CTRL0_CLK_DIVIDER_DYN(x) \
|
437
|
+
(((x)&XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_MASK) >> \
|
438
|
+
XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SHIFT)
|
439
|
+
#define XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SET(x, v) \
|
440
|
+
(((x) & ~XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_MASK) | \
|
441
|
+
(((v) << XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_SHIFT) & \
|
442
|
+
XS1_XCORE_CTRL0_CLK_DIVIDER_DYN_MASK))
|
443
|
+
#define XS1_BOOT_CONFIG_SECURE_BOOT_SHIFT 0x8
|
444
|
+
#define XS1_BOOT_CONFIG_SECURE_BOOT_SIZE 0x1
|
445
|
+
#define XS1_BOOT_CONFIG_SECURE_BOOT_MASK \
|
446
|
+
(((1 << XS1_BOOT_CONFIG_SECURE_BOOT_SIZE) - 1) \
|
447
|
+
<< XS1_BOOT_CONFIG_SECURE_BOOT_SHIFT)
|
448
|
+
#define XS1_BOOT_CONFIG_SECURE_BOOT(x) \
|
449
|
+
(((x)&XS1_BOOT_CONFIG_SECURE_BOOT_MASK) >> XS1_BOOT_CONFIG_SECURE_BOOT_SHIFT)
|
450
|
+
#define XS1_BOOT_CONFIG_SECURE_BOOT_SET(x, v) \
|
451
|
+
(((x) & ~XS1_BOOT_CONFIG_SECURE_BOOT_MASK) | \
|
452
|
+
(((v) << XS1_BOOT_CONFIG_SECURE_BOOT_SHIFT) & \
|
453
|
+
XS1_BOOT_CONFIG_SECURE_BOOT_MASK))
|
454
|
+
#define XS1_BOOT_CONFIG_PROCESSOR_SHIFT 0x10
|
455
|
+
#define XS1_BOOT_CONFIG_PROCESSOR_SIZE 0x8
|
456
|
+
#define XS1_BOOT_CONFIG_PROCESSOR_MASK \
|
457
|
+
(((1 << XS1_BOOT_CONFIG_PROCESSOR_SIZE) - 1) \
|
458
|
+
<< XS1_BOOT_CONFIG_PROCESSOR_SHIFT)
|
459
|
+
#define XS1_BOOT_CONFIG_PROCESSOR(x) \
|
460
|
+
(((x)&XS1_BOOT_CONFIG_PROCESSOR_MASK) >> XS1_BOOT_CONFIG_PROCESSOR_SHIFT)
|
461
|
+
#define XS1_BOOT_CONFIG_PROCESSOR_SET(x, v) \
|
462
|
+
(((x) & ~XS1_BOOT_CONFIG_PROCESSOR_MASK) | \
|
463
|
+
(((v) << XS1_BOOT_CONFIG_PROCESSOR_SHIFT) & \
|
464
|
+
XS1_BOOT_CONFIG_PROCESSOR_MASK))
|
465
|
+
#define XS1_BOOT_STATUS_LEDS_SHIFT 0x0
|
466
|
+
#define XS1_BOOT_STATUS_LEDS_SIZE 0x4
|
467
|
+
#define XS1_BOOT_STATUS_LEDS_MASK \
|
468
|
+
(((1 << XS1_BOOT_STATUS_LEDS_SIZE) - 1) << XS1_BOOT_STATUS_LEDS_SHIFT)
|
469
|
+
#define XS1_BOOT_STATUS_LEDS(x) \
|
470
|
+
(((x)&XS1_BOOT_STATUS_LEDS_MASK) >> XS1_BOOT_STATUS_LEDS_SHIFT)
|
471
|
+
#define XS1_BOOT_STATUS_LEDS_SET(x, v) \
|
472
|
+
(((x) & ~XS1_BOOT_STATUS_LEDS_MASK) | \
|
473
|
+
(((v) << XS1_BOOT_STATUS_LEDS_SHIFT) & XS1_BOOT_STATUS_LEDS_MASK))
|
474
|
+
#define XS1_BOOT_STATUS_BITS_SHIFT 0x4
|
475
|
+
#define XS1_BOOT_STATUS_BITS_SIZE 0x1c
|
476
|
+
#define XS1_BOOT_STATUS_BITS_MASK \
|
477
|
+
(((1 << XS1_BOOT_STATUS_BITS_SIZE) - 1) << XS1_BOOT_STATUS_BITS_SHIFT)
|
478
|
+
#define XS1_BOOT_STATUS_BITS(x) \
|
479
|
+
(((x)&XS1_BOOT_STATUS_BITS_MASK) >> XS1_BOOT_STATUS_BITS_SHIFT)
|
480
|
+
#define XS1_BOOT_STATUS_BITS_SET(x, v) \
|
481
|
+
(((x) & ~XS1_BOOT_STATUS_BITS_MASK) | \
|
482
|
+
(((v) << XS1_BOOT_STATUS_BITS_SHIFT) & XS1_BOOT_STATUS_BITS_MASK))
|
483
|
+
#define XS1_RING_OSC_PERPH_ENABLE_SHIFT 0x0
|
484
|
+
#define XS1_RING_OSC_PERPH_ENABLE_SIZE 0x1
|
485
|
+
#define XS1_RING_OSC_PERPH_ENABLE_MASK \
|
486
|
+
(((1 << XS1_RING_OSC_PERPH_ENABLE_SIZE) - 1) \
|
487
|
+
<< XS1_RING_OSC_PERPH_ENABLE_SHIFT)
|
488
|
+
#define XS1_RING_OSC_PERPH_ENABLE(x) \
|
489
|
+
(((x)&XS1_RING_OSC_PERPH_ENABLE_MASK) >> XS1_RING_OSC_PERPH_ENABLE_SHIFT)
|
490
|
+
#define XS1_RING_OSC_PERPH_ENABLE_SET(x, v) \
|
491
|
+
(((x) & ~XS1_RING_OSC_PERPH_ENABLE_MASK) | \
|
492
|
+
(((v) << XS1_RING_OSC_PERPH_ENABLE_SHIFT) & \
|
493
|
+
XS1_RING_OSC_PERPH_ENABLE_MASK))
|
494
|
+
#define XS1_RING_OSC_CORE_ENABLE_SHIFT 0x1
|
495
|
+
#define XS1_RING_OSC_CORE_ENABLE_SIZE 0x1
|
496
|
+
#define XS1_RING_OSC_CORE_ENABLE_MASK \
|
497
|
+
(((1 << XS1_RING_OSC_CORE_ENABLE_SIZE) - 1) << XS1_RING_OSC_CORE_ENABLE_SHIFT)
|
498
|
+
#define XS1_RING_OSC_CORE_ENABLE(x) \
|
499
|
+
(((x)&XS1_RING_OSC_CORE_ENABLE_MASK) >> XS1_RING_OSC_CORE_ENABLE_SHIFT)
|
500
|
+
#define XS1_RING_OSC_CORE_ENABLE_SET(x, v) \
|
501
|
+
(((x) & ~XS1_RING_OSC_CORE_ENABLE_MASK) | \
|
502
|
+
(((v) << XS1_RING_OSC_CORE_ENABLE_SHIFT) & XS1_RING_OSC_CORE_ENABLE_MASK))
|
503
|
+
#define XS1_RING_OSC_DATA_SHIFT 0x0
|
504
|
+
#define XS1_RING_OSC_DATA_SIZE 0x10
|
505
|
+
#define XS1_RING_OSC_DATA_MASK \
|
506
|
+
(((1 << XS1_RING_OSC_DATA_SIZE) - 1) << XS1_RING_OSC_DATA_SHIFT)
|
507
|
+
#define XS1_RING_OSC_DATA(x) \
|
508
|
+
(((x)&XS1_RING_OSC_DATA_MASK) >> XS1_RING_OSC_DATA_SHIFT)
|
509
|
+
#define XS1_RING_OSC_DATA_SET(x, v) \
|
510
|
+
(((x) & ~XS1_RING_OSC_DATA_MASK) | \
|
511
|
+
(((v) << XS1_RING_OSC_DATA_SHIFT) & XS1_RING_OSC_DATA_MASK))
|
512
|
+
#define XS1_PLL_CLK_DIVIDER_SHIFT 0x0
|
513
|
+
#define XS1_PLL_CLK_DIVIDER_SIZE 0x10
|
514
|
+
#define XS1_PLL_CLK_DIVIDER_MASK \
|
515
|
+
(((1 << XS1_PLL_CLK_DIVIDER_SIZE) - 1) << XS1_PLL_CLK_DIVIDER_SHIFT)
|
516
|
+
#define XS1_PLL_CLK_DIVIDER(x) \
|
517
|
+
(((x)&XS1_PLL_CLK_DIVIDER_MASK) >> XS1_PLL_CLK_DIVIDER_SHIFT)
|
518
|
+
#define XS1_PLL_CLK_DIVIDER_SET(x, v) \
|
519
|
+
(((x) & ~XS1_PLL_CLK_DIVIDER_MASK) | \
|
520
|
+
(((v) << XS1_PLL_CLK_DIVIDER_SHIFT) & XS1_PLL_CLK_DIVIDER_MASK))
|
521
|
+
#define XS1_PLL_CLK_DISABLE_SHIFT 0x1f
|
522
|
+
#define XS1_PLL_CLK_DISABLE_SIZE 0x1
|
523
|
+
#define XS1_PLL_CLK_DISABLE_MASK \
|
524
|
+
(((1 << XS1_PLL_CLK_DISABLE_SIZE) - 1) << XS1_PLL_CLK_DISABLE_SHIFT)
|
525
|
+
#define XS1_PLL_CLK_DISABLE(x) \
|
526
|
+
(((x)&XS1_PLL_CLK_DISABLE_MASK) >> XS1_PLL_CLK_DISABLE_SHIFT)
|
527
|
+
#define XS1_PLL_CLK_DISABLE_SET(x, v) \
|
528
|
+
(((x) & ~XS1_PLL_CLK_DISABLE_MASK) | \
|
529
|
+
(((v) << XS1_PLL_CLK_DISABLE_SHIFT) & XS1_PLL_CLK_DISABLE_MASK))
|
530
|
+
#define XS1_THREAD_CTRL0_INUSE_SHIFT 0x0
|
531
|
+
#define XS1_THREAD_CTRL0_INUSE_SIZE 0x1
|
532
|
+
#define XS1_THREAD_CTRL0_INUSE_MASK \
|
533
|
+
(((1 << XS1_THREAD_CTRL0_INUSE_SIZE) - 1) << XS1_THREAD_CTRL0_INUSE_SHIFT)
|
534
|
+
#define XS1_THREAD_CTRL0_INUSE(x) \
|
535
|
+
(((x)&XS1_THREAD_CTRL0_INUSE_MASK) >> XS1_THREAD_CTRL0_INUSE_SHIFT)
|
536
|
+
#define XS1_THREAD_CTRL0_INUSE_SET(x, v) \
|
537
|
+
(((x) & ~XS1_THREAD_CTRL0_INUSE_MASK) | \
|
538
|
+
(((v) << XS1_THREAD_CTRL0_INUSE_SHIFT) & XS1_THREAD_CTRL0_INUSE_MASK))
|
539
|
+
#define XS1_THREAD_CTRL0_MSYNC_SHIFT 0x1
|
540
|
+
#define XS1_THREAD_CTRL0_MSYNC_SIZE 0x1
|
541
|
+
#define XS1_THREAD_CTRL0_MSYNC_MASK \
|
542
|
+
(((1 << XS1_THREAD_CTRL0_MSYNC_SIZE) - 1) << XS1_THREAD_CTRL0_MSYNC_SHIFT)
|
543
|
+
#define XS1_THREAD_CTRL0_MSYNC(x) \
|
544
|
+
(((x)&XS1_THREAD_CTRL0_MSYNC_MASK) >> XS1_THREAD_CTRL0_MSYNC_SHIFT)
|
545
|
+
#define XS1_THREAD_CTRL0_MSYNC_SET(x, v) \
|
546
|
+
(((x) & ~XS1_THREAD_CTRL0_MSYNC_MASK) | \
|
547
|
+
(((v) << XS1_THREAD_CTRL0_MSYNC_SHIFT) & XS1_THREAD_CTRL0_MSYNC_MASK))
|
548
|
+
#define XS1_THREAD_CTRL0_SSYNC_SHIFT 0x2
|
549
|
+
#define XS1_THREAD_CTRL0_SSYNC_SIZE 0x1
|
550
|
+
#define XS1_THREAD_CTRL0_SSYNC_MASK \
|
551
|
+
(((1 << XS1_THREAD_CTRL0_SSYNC_SIZE) - 1) << XS1_THREAD_CTRL0_SSYNC_SHIFT)
|
552
|
+
#define XS1_THREAD_CTRL0_SSYNC(x) \
|
553
|
+
(((x)&XS1_THREAD_CTRL0_SSYNC_MASK) >> XS1_THREAD_CTRL0_SSYNC_SHIFT)
|
554
|
+
#define XS1_THREAD_CTRL0_SSYNC_SET(x, v) \
|
555
|
+
(((x) & ~XS1_THREAD_CTRL0_SSYNC_MASK) | \
|
556
|
+
(((v) << XS1_THREAD_CTRL0_SSYNC_SHIFT) & XS1_THREAD_CTRL0_SSYNC_MASK))
|
557
|
+
#define XS1_THREAD_CTRL0_MASTER_SHIFT 0x8
|
558
|
+
#define XS1_THREAD_CTRL0_MASTER_SIZE 0x8
|
559
|
+
#define XS1_THREAD_CTRL0_MASTER_MASK \
|
560
|
+
(((1 << XS1_THREAD_CTRL0_MASTER_SIZE) - 1) << XS1_THREAD_CTRL0_MASTER_SHIFT)
|
561
|
+
#define XS1_THREAD_CTRL0_MASTER(x) \
|
562
|
+
(((x)&XS1_THREAD_CTRL0_MASTER_MASK) >> XS1_THREAD_CTRL0_MASTER_SHIFT)
|
563
|
+
#define XS1_THREAD_CTRL0_MASTER_SET(x, v) \
|
564
|
+
(((x) & ~XS1_THREAD_CTRL0_MASTER_MASK) | \
|
565
|
+
(((v) << XS1_THREAD_CTRL0_MASTER_SHIFT) & XS1_THREAD_CTRL0_MASTER_MASK))
|
566
|
+
#define XS1_PORT_CTRL0_INUSE_SHIFT 0x0
|
567
|
+
#define XS1_PORT_CTRL0_INUSE_SIZE 0x1
|
568
|
+
#define XS1_PORT_CTRL0_INUSE_MASK \
|
569
|
+
(((1 << XS1_PORT_CTRL0_INUSE_SIZE) - 1) << XS1_PORT_CTRL0_INUSE_SHIFT)
|
570
|
+
#define XS1_PORT_CTRL0_INUSE(x) \
|
571
|
+
(((x)&XS1_PORT_CTRL0_INUSE_MASK) >> XS1_PORT_CTRL0_INUSE_SHIFT)
|
572
|
+
#define XS1_PORT_CTRL0_INUSE_SET(x, v) \
|
573
|
+
(((x) & ~XS1_PORT_CTRL0_INUSE_MASK) | \
|
574
|
+
(((v) << XS1_PORT_CTRL0_INUSE_SHIFT) & XS1_PORT_CTRL0_INUSE_MASK))
|
575
|
+
#define XS1_PORT_CTRL0_IE_MODE_SHIFT 0x1
|
576
|
+
#define XS1_PORT_CTRL0_IE_MODE_SIZE 0x1
|
577
|
+
#define XS1_PORT_CTRL0_IE_MODE_MASK \
|
578
|
+
(((1 << XS1_PORT_CTRL0_IE_MODE_SIZE) - 1) << XS1_PORT_CTRL0_IE_MODE_SHIFT)
|
579
|
+
#define XS1_PORT_CTRL0_IE_MODE(x) \
|
580
|
+
(((x)&XS1_PORT_CTRL0_IE_MODE_MASK) >> XS1_PORT_CTRL0_IE_MODE_SHIFT)
|
581
|
+
#define XS1_PORT_CTRL0_IE_MODE_SET(x, v) \
|
582
|
+
(((x) & ~XS1_PORT_CTRL0_IE_MODE_MASK) | \
|
583
|
+
(((v) << XS1_PORT_CTRL0_IE_MODE_SHIFT) & XS1_PORT_CTRL0_IE_MODE_MASK))
|
584
|
+
#define XS1_PORT_CTRL0_IE_ENABLED_SHIFT 0x2
|
585
|
+
#define XS1_PORT_CTRL0_IE_ENABLED_SIZE 0x1
|
586
|
+
#define XS1_PORT_CTRL0_IE_ENABLED_MASK \
|
587
|
+
(((1 << XS1_PORT_CTRL0_IE_ENABLED_SIZE) - 1) \
|
588
|
+
<< XS1_PORT_CTRL0_IE_ENABLED_SHIFT)
|
589
|
+
#define XS1_PORT_CTRL0_IE_ENABLED(x) \
|
590
|
+
(((x)&XS1_PORT_CTRL0_IE_ENABLED_MASK) >> XS1_PORT_CTRL0_IE_ENABLED_SHIFT)
|
591
|
+
#define XS1_PORT_CTRL0_IE_ENABLED_SET(x, v) \
|
592
|
+
(((x) & ~XS1_PORT_CTRL0_IE_ENABLED_MASK) | \
|
593
|
+
(((v) << XS1_PORT_CTRL0_IE_ENABLED_SHIFT) & \
|
594
|
+
XS1_PORT_CTRL0_IE_ENABLED_MASK))
|
595
|
+
#define XS1_PORT_CTRL0_DIRECTION_SHIFT 0x3
|
596
|
+
#define XS1_PORT_CTRL0_DIRECTION_SIZE 0x1
|
597
|
+
#define XS1_PORT_CTRL0_DIRECTION_MASK \
|
598
|
+
(((1 << XS1_PORT_CTRL0_DIRECTION_SIZE) - 1) << XS1_PORT_CTRL0_DIRECTION_SHIFT)
|
599
|
+
#define XS1_PORT_CTRL0_DIRECTION(x) \
|
600
|
+
(((x)&XS1_PORT_CTRL0_DIRECTION_MASK) >> XS1_PORT_CTRL0_DIRECTION_SHIFT)
|
601
|
+
#define XS1_PORT_CTRL0_DIRECTION_SET(x, v) \
|
602
|
+
(((x) & ~XS1_PORT_CTRL0_DIRECTION_MASK) | \
|
603
|
+
(((v) << XS1_PORT_CTRL0_DIRECTION_SHIFT) & XS1_PORT_CTRL0_DIRECTION_MASK))
|
604
|
+
#define XS1_PORT_CTRL0_COND_SHIFT 0x4
|
605
|
+
#define XS1_PORT_CTRL0_COND_SIZE 0x4
|
606
|
+
#define XS1_PORT_CTRL0_COND_MASK \
|
607
|
+
(((1 << XS1_PORT_CTRL0_COND_SIZE) - 1) << XS1_PORT_CTRL0_COND_SHIFT)
|
608
|
+
#define XS1_PORT_CTRL0_COND(x) \
|
609
|
+
(((x)&XS1_PORT_CTRL0_COND_MASK) >> XS1_PORT_CTRL0_COND_SHIFT)
|
610
|
+
#define XS1_PORT_CTRL0_COND_SET(x, v) \
|
611
|
+
(((x) & ~XS1_PORT_CTRL0_COND_MASK) | \
|
612
|
+
(((v) << XS1_PORT_CTRL0_COND_SHIFT) & XS1_PORT_CTRL0_COND_MASK))
|
613
|
+
#define XS1_PORT_CTRL0_MASTER_SLAVE_SHIFT 0x8
|
614
|
+
#define XS1_PORT_CTRL0_MASTER_SLAVE_SIZE 0x1
|
615
|
+
#define XS1_PORT_CTRL0_MASTER_SLAVE_MASK \
|
616
|
+
(((1 << XS1_PORT_CTRL0_MASTER_SLAVE_SIZE) - 1) \
|
617
|
+
<< XS1_PORT_CTRL0_MASTER_SLAVE_SHIFT)
|
618
|
+
#define XS1_PORT_CTRL0_MASTER_SLAVE(x) \
|
619
|
+
(((x)&XS1_PORT_CTRL0_MASTER_SLAVE_MASK) >> XS1_PORT_CTRL0_MASTER_SLAVE_SHIFT)
|
620
|
+
#define XS1_PORT_CTRL0_MASTER_SLAVE_SET(x, v) \
|
621
|
+
(((x) & ~XS1_PORT_CTRL0_MASTER_SLAVE_MASK) | \
|
622
|
+
(((v) << XS1_PORT_CTRL0_MASTER_SLAVE_SHIFT) & \
|
623
|
+
XS1_PORT_CTRL0_MASTER_SLAVE_MASK))
|
624
|
+
#define XS1_PORT_CTRL0_BUFFERS_SHIFT 0x9
|
625
|
+
#define XS1_PORT_CTRL0_BUFFERS_SIZE 0x1
|
626
|
+
#define XS1_PORT_CTRL0_BUFFERS_MASK \
|
627
|
+
(((1 << XS1_PORT_CTRL0_BUFFERS_SIZE) - 1) << XS1_PORT_CTRL0_BUFFERS_SHIFT)
|
628
|
+
#define XS1_PORT_CTRL0_BUFFERS(x) \
|
629
|
+
(((x)&XS1_PORT_CTRL0_BUFFERS_MASK) >> XS1_PORT_CTRL0_BUFFERS_SHIFT)
|
630
|
+
#define XS1_PORT_CTRL0_BUFFERS_SET(x, v) \
|
631
|
+
(((x) & ~XS1_PORT_CTRL0_BUFFERS_MASK) | \
|
632
|
+
(((v) << XS1_PORT_CTRL0_BUFFERS_SHIFT) & XS1_PORT_CTRL0_BUFFERS_MASK))
|
633
|
+
#define XS1_PORT_CTRL0_READY_MODE_SHIFT 0xa
|
634
|
+
#define XS1_PORT_CTRL0_READY_MODE_SIZE 0x2
|
635
|
+
#define XS1_PORT_CTRL0_READY_MODE_MASK \
|
636
|
+
(((1 << XS1_PORT_CTRL0_READY_MODE_SIZE) - 1) \
|
637
|
+
<< XS1_PORT_CTRL0_READY_MODE_SHIFT)
|
638
|
+
#define XS1_PORT_CTRL0_READY_MODE(x) \
|
639
|
+
(((x)&XS1_PORT_CTRL0_READY_MODE_MASK) >> XS1_PORT_CTRL0_READY_MODE_SHIFT)
|
640
|
+
#define XS1_PORT_CTRL0_READY_MODE_SET(x, v) \
|
641
|
+
(((x) & ~XS1_PORT_CTRL0_READY_MODE_MASK) | \
|
642
|
+
(((v) << XS1_PORT_CTRL0_READY_MODE_SHIFT) & \
|
643
|
+
XS1_PORT_CTRL0_READY_MODE_MASK))
|
644
|
+
#define XS1_PORT_CTRL0_PORT_TYPE_SHIFT 0xc
|
645
|
+
#define XS1_PORT_CTRL0_PORT_TYPE_SIZE 0x2
|
646
|
+
#define XS1_PORT_CTRL0_PORT_TYPE_MASK \
|
647
|
+
(((1 << XS1_PORT_CTRL0_PORT_TYPE_SIZE) - 1) << XS1_PORT_CTRL0_PORT_TYPE_SHIFT)
|
648
|
+
#define XS1_PORT_CTRL0_PORT_TYPE(x) \
|
649
|
+
(((x)&XS1_PORT_CTRL0_PORT_TYPE_MASK) >> XS1_PORT_CTRL0_PORT_TYPE_SHIFT)
|
650
|
+
#define XS1_PORT_CTRL0_PORT_TYPE_SET(x, v) \
|
651
|
+
(((x) & ~XS1_PORT_CTRL0_PORT_TYPE_MASK) | \
|
652
|
+
(((v) << XS1_PORT_CTRL0_PORT_TYPE_SHIFT) & XS1_PORT_CTRL0_PORT_TYPE_MASK))
|
653
|
+
#define XS1_PORT_CTRL0_INVERT_SHIFT 0xe
|
654
|
+
#define XS1_PORT_CTRL0_INVERT_SIZE 0x1
|
655
|
+
#define XS1_PORT_CTRL0_INVERT_MASK \
|
656
|
+
(((1 << XS1_PORT_CTRL0_INVERT_SIZE) - 1) << XS1_PORT_CTRL0_INVERT_SHIFT)
|
657
|
+
#define XS1_PORT_CTRL0_INVERT(x) \
|
658
|
+
(((x)&XS1_PORT_CTRL0_INVERT_MASK) >> XS1_PORT_CTRL0_INVERT_SHIFT)
|
659
|
+
#define XS1_PORT_CTRL0_INVERT_SET(x, v) \
|
660
|
+
(((x) & ~XS1_PORT_CTRL0_INVERT_MASK) | \
|
661
|
+
(((v) << XS1_PORT_CTRL0_INVERT_SHIFT) & XS1_PORT_CTRL0_INVERT_MASK))
|
662
|
+
#define XS1_PORT_CTRL0_SDELAY_SHIFT 0xf
|
663
|
+
#define XS1_PORT_CTRL0_SDELAY_SIZE 0x1
|
664
|
+
#define XS1_PORT_CTRL0_SDELAY_MASK \
|
665
|
+
(((1 << XS1_PORT_CTRL0_SDELAY_SIZE) - 1) << XS1_PORT_CTRL0_SDELAY_SHIFT)
|
666
|
+
#define XS1_PORT_CTRL0_SDELAY(x) \
|
667
|
+
(((x)&XS1_PORT_CTRL0_SDELAY_MASK) >> XS1_PORT_CTRL0_SDELAY_SHIFT)
|
668
|
+
#define XS1_PORT_CTRL0_SDELAY_SET(x, v) \
|
669
|
+
(((x) & ~XS1_PORT_CTRL0_SDELAY_MASK) | \
|
670
|
+
(((v) << XS1_PORT_CTRL0_SDELAY_SHIFT) & XS1_PORT_CTRL0_SDELAY_MASK))
|
671
|
+
#define XS1_PORT_CTRL0_EV_VALID_SHIFT 0x16
|
672
|
+
#define XS1_PORT_CTRL0_EV_VALID_SIZE 0x1
|
673
|
+
#define XS1_PORT_CTRL0_EV_VALID_MASK \
|
674
|
+
(((1 << XS1_PORT_CTRL0_EV_VALID_SIZE) - 1) << XS1_PORT_CTRL0_EV_VALID_SHIFT)
|
675
|
+
#define XS1_PORT_CTRL0_EV_VALID(x) \
|
676
|
+
(((x)&XS1_PORT_CTRL0_EV_VALID_MASK) >> XS1_PORT_CTRL0_EV_VALID_SHIFT)
|
677
|
+
#define XS1_PORT_CTRL0_EV_VALID_SET(x, v) \
|
678
|
+
(((x) & ~XS1_PORT_CTRL0_EV_VALID_MASK) | \
|
679
|
+
(((v) << XS1_PORT_CTRL0_EV_VALID_SHIFT) & XS1_PORT_CTRL0_EV_VALID_MASK))
|
680
|
+
#define XS1_PORT_CTRL0_T_WAITING_SHIFT 0x17
|
681
|
+
#define XS1_PORT_CTRL0_T_WAITING_SIZE 0x1
|
682
|
+
#define XS1_PORT_CTRL0_T_WAITING_MASK \
|
683
|
+
(((1 << XS1_PORT_CTRL0_T_WAITING_SIZE) - 1) << XS1_PORT_CTRL0_T_WAITING_SHIFT)
|
684
|
+
#define XS1_PORT_CTRL0_T_WAITING(x) \
|
685
|
+
(((x)&XS1_PORT_CTRL0_T_WAITING_MASK) >> XS1_PORT_CTRL0_T_WAITING_SHIFT)
|
686
|
+
#define XS1_PORT_CTRL0_T_WAITING_SET(x, v) \
|
687
|
+
(((x) & ~XS1_PORT_CTRL0_T_WAITING_MASK) | \
|
688
|
+
(((v) << XS1_PORT_CTRL0_T_WAITING_SHIFT) & XS1_PORT_CTRL0_T_WAITING_MASK))
|
689
|
+
#define XS1_PORT_CTRL0_T_NUM_SHIFT 0x18
|
690
|
+
#define XS1_PORT_CTRL0_T_NUM_SIZE 0x8
|
691
|
+
#define XS1_PORT_CTRL0_T_NUM_MASK \
|
692
|
+
(((1 << XS1_PORT_CTRL0_T_NUM_SIZE) - 1) << XS1_PORT_CTRL0_T_NUM_SHIFT)
|
693
|
+
#define XS1_PORT_CTRL0_T_NUM(x) \
|
694
|
+
(((x)&XS1_PORT_CTRL0_T_NUM_MASK) >> XS1_PORT_CTRL0_T_NUM_SHIFT)
|
695
|
+
#define XS1_PORT_CTRL0_T_NUM_SET(x, v) \
|
696
|
+
(((x) & ~XS1_PORT_CTRL0_T_NUM_MASK) | \
|
697
|
+
(((v) << XS1_PORT_CTRL0_T_NUM_SHIFT) & XS1_PORT_CTRL0_T_NUM_MASK))
|
698
|
+
#define XS1_PORT_CTRL1_DRIVE_SHIFT 0x0
|
699
|
+
#define XS1_PORT_CTRL1_DRIVE_SIZE 0x8
|
700
|
+
#define XS1_PORT_CTRL1_DRIVE_MASK \
|
701
|
+
(((1 << XS1_PORT_CTRL1_DRIVE_SIZE) - 1) << XS1_PORT_CTRL1_DRIVE_SHIFT)
|
702
|
+
#define XS1_PORT_CTRL1_DRIVE(x) \
|
703
|
+
(((x)&XS1_PORT_CTRL1_DRIVE_MASK) >> XS1_PORT_CTRL1_DRIVE_SHIFT)
|
704
|
+
#define XS1_PORT_CTRL1_DRIVE_SET(x, v) \
|
705
|
+
(((x) & ~XS1_PORT_CTRL1_DRIVE_MASK) | \
|
706
|
+
(((v) << XS1_PORT_CTRL1_DRIVE_SHIFT) & XS1_PORT_CTRL1_DRIVE_MASK))
|
707
|
+
#define XS1_PORT_CTRL1_TWIDTH_SHIFT 0x8
|
708
|
+
#define XS1_PORT_CTRL1_TWIDTH_SIZE 0x8
|
709
|
+
#define XS1_PORT_CTRL1_TWIDTH_MASK \
|
710
|
+
(((1 << XS1_PORT_CTRL1_TWIDTH_SIZE) - 1) << XS1_PORT_CTRL1_TWIDTH_SHIFT)
|
711
|
+
#define XS1_PORT_CTRL1_TWIDTH(x) \
|
712
|
+
(((x)&XS1_PORT_CTRL1_TWIDTH_MASK) >> XS1_PORT_CTRL1_TWIDTH_SHIFT)
|
713
|
+
#define XS1_PORT_CTRL1_TWIDTH_SET(x, v) \
|
714
|
+
(((x) & ~XS1_PORT_CTRL1_TWIDTH_MASK) | \
|
715
|
+
(((v) << XS1_PORT_CTRL1_TWIDTH_SHIFT) & XS1_PORT_CTRL1_TWIDTH_MASK))
|
716
|
+
#define XS1_PORT_CTRL1_SREG_COUNT_SHIFT 0x10
|
717
|
+
#define XS1_PORT_CTRL1_SREG_COUNT_SIZE 0x8
|
718
|
+
#define XS1_PORT_CTRL1_SREG_COUNT_MASK \
|
719
|
+
(((1 << XS1_PORT_CTRL1_SREG_COUNT_SIZE) - 1) \
|
720
|
+
<< XS1_PORT_CTRL1_SREG_COUNT_SHIFT)
|
721
|
+
#define XS1_PORT_CTRL1_SREG_COUNT(x) \
|
722
|
+
(((x)&XS1_PORT_CTRL1_SREG_COUNT_MASK) >> XS1_PORT_CTRL1_SREG_COUNT_SHIFT)
|
723
|
+
#define XS1_PORT_CTRL1_SREG_COUNT_SET(x, v) \
|
724
|
+
(((x) & ~XS1_PORT_CTRL1_SREG_COUNT_MASK) | \
|
725
|
+
(((v) << XS1_PORT_CTRL1_SREG_COUNT_SHIFT) & \
|
726
|
+
XS1_PORT_CTRL1_SREG_COUNT_MASK))
|
727
|
+
#define XS1_PORT_CTRL1_TREG_FULL_SHIFT 0x18
|
728
|
+
#define XS1_PORT_CTRL1_TREG_FULL_SIZE 0x1
|
729
|
+
#define XS1_PORT_CTRL1_TREG_FULL_MASK \
|
730
|
+
(((1 << XS1_PORT_CTRL1_TREG_FULL_SIZE) - 1) << XS1_PORT_CTRL1_TREG_FULL_SHIFT)
|
731
|
+
#define XS1_PORT_CTRL1_TREG_FULL(x) \
|
732
|
+
(((x)&XS1_PORT_CTRL1_TREG_FULL_MASK) >> XS1_PORT_CTRL1_TREG_FULL_SHIFT)
|
733
|
+
#define XS1_PORT_CTRL1_TREG_FULL_SET(x, v) \
|
734
|
+
(((x) & ~XS1_PORT_CTRL1_TREG_FULL_MASK) | \
|
735
|
+
(((v) << XS1_PORT_CTRL1_TREG_FULL_SHIFT) & XS1_PORT_CTRL1_TREG_FULL_MASK))
|
736
|
+
#define XS1_PORT_CTRL1_CHANGE_DIR_SHIFT 0x19
|
737
|
+
#define XS1_PORT_CTRL1_CHANGE_DIR_SIZE 0x1
|
738
|
+
#define XS1_PORT_CTRL1_CHANGE_DIR_MASK \
|
739
|
+
(((1 << XS1_PORT_CTRL1_CHANGE_DIR_SIZE) - 1) \
|
740
|
+
<< XS1_PORT_CTRL1_CHANGE_DIR_SHIFT)
|
741
|
+
#define XS1_PORT_CTRL1_CHANGE_DIR(x) \
|
742
|
+
(((x)&XS1_PORT_CTRL1_CHANGE_DIR_MASK) >> XS1_PORT_CTRL1_CHANGE_DIR_SHIFT)
|
743
|
+
#define XS1_PORT_CTRL1_CHANGE_DIR_SET(x, v) \
|
744
|
+
(((x) & ~XS1_PORT_CTRL1_CHANGE_DIR_MASK) | \
|
745
|
+
(((v) << XS1_PORT_CTRL1_CHANGE_DIR_SHIFT) & \
|
746
|
+
XS1_PORT_CTRL1_CHANGE_DIR_MASK))
|
747
|
+
#define XS1_PORT_CTRL1_SYNCR_SHIFT 0x1a
|
748
|
+
#define XS1_PORT_CTRL1_SYNCR_SIZE 0x1
|
749
|
+
#define XS1_PORT_CTRL1_SYNCR_MASK \
|
750
|
+
(((1 << XS1_PORT_CTRL1_SYNCR_SIZE) - 1) << XS1_PORT_CTRL1_SYNCR_SHIFT)
|
751
|
+
#define XS1_PORT_CTRL1_SYNCR(x) \
|
752
|
+
(((x)&XS1_PORT_CTRL1_SYNCR_MASK) >> XS1_PORT_CTRL1_SYNCR_SHIFT)
|
753
|
+
#define XS1_PORT_CTRL1_SYNCR_SET(x, v) \
|
754
|
+
(((x) & ~XS1_PORT_CTRL1_SYNCR_MASK) | \
|
755
|
+
(((v) << XS1_PORT_CTRL1_SYNCR_SHIFT) & XS1_PORT_CTRL1_SYNCR_MASK))
|
756
|
+
#define XS1_PORT_CTRL1_INST_COMMITTED_SHIFT 0x1b
|
757
|
+
#define XS1_PORT_CTRL1_INST_COMMITTED_SIZE 0x1
|
758
|
+
#define XS1_PORT_CTRL1_INST_COMMITTED_MASK \
|
759
|
+
(((1 << XS1_PORT_CTRL1_INST_COMMITTED_SIZE) - 1) \
|
760
|
+
<< XS1_PORT_CTRL1_INST_COMMITTED_SHIFT)
|
761
|
+
#define XS1_PORT_CTRL1_INST_COMMITTED(x) \
|
762
|
+
(((x)&XS1_PORT_CTRL1_INST_COMMITTED_MASK) >> \
|
763
|
+
XS1_PORT_CTRL1_INST_COMMITTED_SHIFT)
|
764
|
+
#define XS1_PORT_CTRL1_INST_COMMITTED_SET(x, v) \
|
765
|
+
(((x) & ~XS1_PORT_CTRL1_INST_COMMITTED_MASK) | \
|
766
|
+
(((v) << XS1_PORT_CTRL1_INST_COMMITTED_SHIFT) & \
|
767
|
+
XS1_PORT_CTRL1_INST_COMMITTED_MASK))
|
768
|
+
#define XS1_PORT_CTRL1_HOLD_DATA_SHIFT 0x1c
|
769
|
+
#define XS1_PORT_CTRL1_HOLD_DATA_SIZE 0x1
|
770
|
+
#define XS1_PORT_CTRL1_HOLD_DATA_MASK \
|
771
|
+
(((1 << XS1_PORT_CTRL1_HOLD_DATA_SIZE) - 1) << XS1_PORT_CTRL1_HOLD_DATA_SHIFT)
|
772
|
+
#define XS1_PORT_CTRL1_HOLD_DATA(x) \
|
773
|
+
(((x)&XS1_PORT_CTRL1_HOLD_DATA_MASK) >> XS1_PORT_CTRL1_HOLD_DATA_SHIFT)
|
774
|
+
#define XS1_PORT_CTRL1_HOLD_DATA_SET(x, v) \
|
775
|
+
(((x) & ~XS1_PORT_CTRL1_HOLD_DATA_MASK) | \
|
776
|
+
(((v) << XS1_PORT_CTRL1_HOLD_DATA_SHIFT) & XS1_PORT_CTRL1_HOLD_DATA_MASK))
|
777
|
+
#define XS1_PORT_CTRL1_WAIT_FOR_TIME_SHIFT 0x1d
|
778
|
+
#define XS1_PORT_CTRL1_WAIT_FOR_TIME_SIZE 0x1
|
779
|
+
#define XS1_PORT_CTRL1_WAIT_FOR_TIME_MASK \
|
780
|
+
(((1 << XS1_PORT_CTRL1_WAIT_FOR_TIME_SIZE) - 1) \
|
781
|
+
<< XS1_PORT_CTRL1_WAIT_FOR_TIME_SHIFT)
|
782
|
+
#define XS1_PORT_CTRL1_WAIT_FOR_TIME(x) \
|
783
|
+
(((x)&XS1_PORT_CTRL1_WAIT_FOR_TIME_MASK) >> \
|
784
|
+
XS1_PORT_CTRL1_WAIT_FOR_TIME_SHIFT)
|
785
|
+
#define XS1_PORT_CTRL1_WAIT_FOR_TIME_SET(x, v) \
|
786
|
+
(((x) & ~XS1_PORT_CTRL1_WAIT_FOR_TIME_MASK) | \
|
787
|
+
(((v) << XS1_PORT_CTRL1_WAIT_FOR_TIME_SHIFT) & \
|
788
|
+
XS1_PORT_CTRL1_WAIT_FOR_TIME_MASK))
|
789
|
+
#define XS1_PORT_CTRL1_TIMEMET_SHIFT 0x1e
|
790
|
+
#define XS1_PORT_CTRL1_TIMEMET_SIZE 0x1
|
791
|
+
#define XS1_PORT_CTRL1_TIMEMET_MASK \
|
792
|
+
(((1 << XS1_PORT_CTRL1_TIMEMET_SIZE) - 1) << XS1_PORT_CTRL1_TIMEMET_SHIFT)
|
793
|
+
#define XS1_PORT_CTRL1_TIMEMET(x) \
|
794
|
+
(((x)&XS1_PORT_CTRL1_TIMEMET_MASK) >> XS1_PORT_CTRL1_TIMEMET_SHIFT)
|
795
|
+
#define XS1_PORT_CTRL1_TIMEMET_SET(x, v) \
|
796
|
+
(((x) & ~XS1_PORT_CTRL1_TIMEMET_MASK) | \
|
797
|
+
(((v) << XS1_PORT_CTRL1_TIMEMET_SHIFT) & XS1_PORT_CTRL1_TIMEMET_MASK))
|
798
|
+
#define XS1_PORT_CTRL1_ENDIN_SHIFT 0x1f
|
799
|
+
#define XS1_PORT_CTRL1_ENDIN_SIZE 0x1
|
800
|
+
#define XS1_PORT_CTRL1_ENDIN_MASK \
|
801
|
+
(((1 << XS1_PORT_CTRL1_ENDIN_SIZE) - 1) << XS1_PORT_CTRL1_ENDIN_SHIFT)
|
802
|
+
#define XS1_PORT_CTRL1_ENDIN(x) \
|
803
|
+
(((x)&XS1_PORT_CTRL1_ENDIN_MASK) >> XS1_PORT_CTRL1_ENDIN_SHIFT)
|
804
|
+
#define XS1_PORT_CTRL1_ENDIN_SET(x, v) \
|
805
|
+
(((x) & ~XS1_PORT_CTRL1_ENDIN_MASK) | \
|
806
|
+
(((v) << XS1_PORT_CTRL1_ENDIN_SHIFT) & XS1_PORT_CTRL1_ENDIN_MASK))
|
807
|
+
#define XS1_PORT_CTRL2_TIME_SHIFT 0x0
|
808
|
+
#define XS1_PORT_CTRL2_TIME_SIZE 0x10
|
809
|
+
#define XS1_PORT_CTRL2_TIME_MASK \
|
810
|
+
(((1 << XS1_PORT_CTRL2_TIME_SIZE) - 1) << XS1_PORT_CTRL2_TIME_SHIFT)
|
811
|
+
#define XS1_PORT_CTRL2_TIME(x) \
|
812
|
+
(((x)&XS1_PORT_CTRL2_TIME_MASK) >> XS1_PORT_CTRL2_TIME_SHIFT)
|
813
|
+
#define XS1_PORT_CTRL2_TIME_SET(x, v) \
|
814
|
+
(((x) & ~XS1_PORT_CTRL2_TIME_MASK) | \
|
815
|
+
(((v) << XS1_PORT_CTRL2_TIME_SHIFT) & XS1_PORT_CTRL2_TIME_MASK))
|
816
|
+
#define XS1_PORT_CTRL2_PIN_DELAY_SHIFT 0x10
|
817
|
+
#define XS1_PORT_CTRL2_PIN_DELAY_SIZE 0x3
|
818
|
+
#define XS1_PORT_CTRL2_PIN_DELAY_MASK \
|
819
|
+
(((1 << XS1_PORT_CTRL2_PIN_DELAY_SIZE) - 1) << XS1_PORT_CTRL2_PIN_DELAY_SHIFT)
|
820
|
+
#define XS1_PORT_CTRL2_PIN_DELAY(x) \
|
821
|
+
(((x)&XS1_PORT_CTRL2_PIN_DELAY_MASK) >> XS1_PORT_CTRL2_PIN_DELAY_SHIFT)
|
822
|
+
#define XS1_PORT_CTRL2_PIN_DELAY_SET(x, v) \
|
823
|
+
(((x) & ~XS1_PORT_CTRL2_PIN_DELAY_MASK) | \
|
824
|
+
(((v) << XS1_PORT_CTRL2_PIN_DELAY_SHIFT) & XS1_PORT_CTRL2_PIN_DELAY_MASK))
|
825
|
+
#define XS1_PORT_PAD_CTRL_OEN_SHIFT 0x0
|
826
|
+
#define XS1_PORT_PAD_CTRL_OEN_SIZE 0x1
|
827
|
+
#define XS1_PORT_PAD_CTRL_OEN_MASK \
|
828
|
+
(((1 << XS1_PORT_PAD_CTRL_OEN_SIZE) - 1) << XS1_PORT_PAD_CTRL_OEN_SHIFT)
|
829
|
+
#define XS1_PORT_PAD_CTRL_OEN(x) \
|
830
|
+
(((x)&XS1_PORT_PAD_CTRL_OEN_MASK) >> XS1_PORT_PAD_CTRL_OEN_SHIFT)
|
831
|
+
#define XS1_PORT_PAD_CTRL_OEN_SET(x, v) \
|
832
|
+
(((x) & ~XS1_PORT_PAD_CTRL_OEN_MASK) | \
|
833
|
+
(((v) << XS1_PORT_PAD_CTRL_OEN_SHIFT) & XS1_PORT_PAD_CTRL_OEN_MASK))
|
834
|
+
#define XS1_PORT_PAD_CTRL_REN_SHIFT 0x1
|
835
|
+
#define XS1_PORT_PAD_CTRL_REN_SIZE 0x1
|
836
|
+
#define XS1_PORT_PAD_CTRL_REN_MASK \
|
837
|
+
(((1 << XS1_PORT_PAD_CTRL_REN_SIZE) - 1) << XS1_PORT_PAD_CTRL_REN_SHIFT)
|
838
|
+
#define XS1_PORT_PAD_CTRL_REN(x) \
|
839
|
+
(((x)&XS1_PORT_PAD_CTRL_REN_MASK) >> XS1_PORT_PAD_CTRL_REN_SHIFT)
|
840
|
+
#define XS1_PORT_PAD_CTRL_REN_SET(x, v) \
|
841
|
+
(((x) & ~XS1_PORT_PAD_CTRL_REN_MASK) | \
|
842
|
+
(((v) << XS1_PORT_PAD_CTRL_REN_SHIFT) & XS1_PORT_PAD_CTRL_REN_MASK))
|
843
|
+
#define XS1_PORT_PAD_CTRL_P_SHIFT 0x2
|
844
|
+
#define XS1_PORT_PAD_CTRL_P_SIZE 0x2
|
845
|
+
#define XS1_PORT_PAD_CTRL_P_MASK \
|
846
|
+
(((1 << XS1_PORT_PAD_CTRL_P_SIZE) - 1) << XS1_PORT_PAD_CTRL_P_SHIFT)
|
847
|
+
#define XS1_PORT_PAD_CTRL_P(x) \
|
848
|
+
(((x)&XS1_PORT_PAD_CTRL_P_MASK) >> XS1_PORT_PAD_CTRL_P_SHIFT)
|
849
|
+
#define XS1_PORT_PAD_CTRL_P_SET(x, v) \
|
850
|
+
(((x) & ~XS1_PORT_PAD_CTRL_P_MASK) | \
|
851
|
+
(((v) << XS1_PORT_PAD_CTRL_P_SHIFT) & XS1_PORT_PAD_CTRL_P_MASK))
|
852
|
+
#define XS1_PORT_PAD_CTRL_E_SHIFT 0x4
|
853
|
+
#define XS1_PORT_PAD_CTRL_E_SIZE 0x2
|
854
|
+
#define XS1_PORT_PAD_CTRL_E_MASK \
|
855
|
+
(((1 << XS1_PORT_PAD_CTRL_E_SIZE) - 1) << XS1_PORT_PAD_CTRL_E_SHIFT)
|
856
|
+
#define XS1_PORT_PAD_CTRL_E(x) \
|
857
|
+
(((x)&XS1_PORT_PAD_CTRL_E_MASK) >> XS1_PORT_PAD_CTRL_E_SHIFT)
|
858
|
+
#define XS1_PORT_PAD_CTRL_E_SET(x, v) \
|
859
|
+
(((x) & ~XS1_PORT_PAD_CTRL_E_MASK) | \
|
860
|
+
(((v) << XS1_PORT_PAD_CTRL_E_SHIFT) & XS1_PORT_PAD_CTRL_E_MASK))
|
861
|
+
#define XS1_PORT_PAD_CTRL_SR_SHIFT 0x6
|
862
|
+
#define XS1_PORT_PAD_CTRL_SR_SIZE 0x1
|
863
|
+
#define XS1_PORT_PAD_CTRL_SR_MASK \
|
864
|
+
(((1 << XS1_PORT_PAD_CTRL_SR_SIZE) - 1) << XS1_PORT_PAD_CTRL_SR_SHIFT)
|
865
|
+
#define XS1_PORT_PAD_CTRL_SR(x) \
|
866
|
+
(((x)&XS1_PORT_PAD_CTRL_SR_MASK) >> XS1_PORT_PAD_CTRL_SR_SHIFT)
|
867
|
+
#define XS1_PORT_PAD_CTRL_SR_SET(x, v) \
|
868
|
+
(((x) & ~XS1_PORT_PAD_CTRL_SR_MASK) | \
|
869
|
+
(((v) << XS1_PORT_PAD_CTRL_SR_SHIFT) & XS1_PORT_PAD_CTRL_SR_MASK))
|
870
|
+
#define XS1_PORT_PAD_CTRL_SMT_SHIFT 0x7
|
871
|
+
#define XS1_PORT_PAD_CTRL_SMT_SIZE 0x1
|
872
|
+
#define XS1_PORT_PAD_CTRL_SMT_MASK \
|
873
|
+
(((1 << XS1_PORT_PAD_CTRL_SMT_SIZE) - 1) << XS1_PORT_PAD_CTRL_SMT_SHIFT)
|
874
|
+
#define XS1_PORT_PAD_CTRL_SMT(x) \
|
875
|
+
(((x)&XS1_PORT_PAD_CTRL_SMT_MASK) >> XS1_PORT_PAD_CTRL_SMT_SHIFT)
|
876
|
+
#define XS1_PORT_PAD_CTRL_SMT_SET(x, v) \
|
877
|
+
(((x) & ~XS1_PORT_PAD_CTRL_SMT_MASK) | \
|
878
|
+
(((v) << XS1_PORT_PAD_CTRL_SMT_SHIFT) & XS1_PORT_PAD_CTRL_SMT_MASK))
|
879
|
+
#define XS1_TIMER_CTRL0_INUSE_SHIFT 0x0
|
880
|
+
#define XS1_TIMER_CTRL0_INUSE_SIZE 0x1
|
881
|
+
#define XS1_TIMER_CTRL0_INUSE_MASK \
|
882
|
+
(((1 << XS1_TIMER_CTRL0_INUSE_SIZE) - 1) << XS1_TIMER_CTRL0_INUSE_SHIFT)
|
883
|
+
#define XS1_TIMER_CTRL0_INUSE(x) \
|
884
|
+
(((x)&XS1_TIMER_CTRL0_INUSE_MASK) >> XS1_TIMER_CTRL0_INUSE_SHIFT)
|
885
|
+
#define XS1_TIMER_CTRL0_INUSE_SET(x, v) \
|
886
|
+
(((x) & ~XS1_TIMER_CTRL0_INUSE_MASK) | \
|
887
|
+
(((v) << XS1_TIMER_CTRL0_INUSE_SHIFT) & XS1_TIMER_CTRL0_INUSE_MASK))
|
888
|
+
#define XS1_TIMER_CTRL0_IE_MODE_SHIFT 0x1
|
889
|
+
#define XS1_TIMER_CTRL0_IE_MODE_SIZE 0x1
|
890
|
+
#define XS1_TIMER_CTRL0_IE_MODE_MASK \
|
891
|
+
(((1 << XS1_TIMER_CTRL0_IE_MODE_SIZE) - 1) << XS1_TIMER_CTRL0_IE_MODE_SHIFT)
|
892
|
+
#define XS1_TIMER_CTRL0_IE_MODE(x) \
|
893
|
+
(((x)&XS1_TIMER_CTRL0_IE_MODE_MASK) >> XS1_TIMER_CTRL0_IE_MODE_SHIFT)
|
894
|
+
#define XS1_TIMER_CTRL0_IE_MODE_SET(x, v) \
|
895
|
+
(((x) & ~XS1_TIMER_CTRL0_IE_MODE_MASK) | \
|
896
|
+
(((v) << XS1_TIMER_CTRL0_IE_MODE_SHIFT) & XS1_TIMER_CTRL0_IE_MODE_MASK))
|
897
|
+
#define XS1_TIMER_CTRL0_IE_ENABLED_SHIFT 0x2
|
898
|
+
#define XS1_TIMER_CTRL0_IE_ENABLED_SIZE 0x1
|
899
|
+
#define XS1_TIMER_CTRL0_IE_ENABLED_MASK \
|
900
|
+
(((1 << XS1_TIMER_CTRL0_IE_ENABLED_SIZE) - 1) \
|
901
|
+
<< XS1_TIMER_CTRL0_IE_ENABLED_SHIFT)
|
902
|
+
#define XS1_TIMER_CTRL0_IE_ENABLED(x) \
|
903
|
+
(((x)&XS1_TIMER_CTRL0_IE_ENABLED_MASK) >> XS1_TIMER_CTRL0_IE_ENABLED_SHIFT)
|
904
|
+
#define XS1_TIMER_CTRL0_IE_ENABLED_SET(x, v) \
|
905
|
+
(((x) & ~XS1_TIMER_CTRL0_IE_ENABLED_MASK) | \
|
906
|
+
(((v) << XS1_TIMER_CTRL0_IE_ENABLED_SHIFT) & \
|
907
|
+
XS1_TIMER_CTRL0_IE_ENABLED_MASK))
|
908
|
+
#define XS1_TIMER_CTRL0_READY_SHIFT 0x3
|
909
|
+
#define XS1_TIMER_CTRL0_READY_SIZE 0x1
|
910
|
+
#define XS1_TIMER_CTRL0_READY_MASK \
|
911
|
+
(((1 << XS1_TIMER_CTRL0_READY_SIZE) - 1) << XS1_TIMER_CTRL0_READY_SHIFT)
|
912
|
+
#define XS1_TIMER_CTRL0_READY(x) \
|
913
|
+
(((x)&XS1_TIMER_CTRL0_READY_MASK) >> XS1_TIMER_CTRL0_READY_SHIFT)
|
914
|
+
#define XS1_TIMER_CTRL0_READY_SET(x, v) \
|
915
|
+
(((x) & ~XS1_TIMER_CTRL0_READY_MASK) | \
|
916
|
+
(((v) << XS1_TIMER_CTRL0_READY_SHIFT) & XS1_TIMER_CTRL0_READY_MASK))
|
917
|
+
#define XS1_TIMER_CTRL0_COND_SHIFT 0x4
|
918
|
+
#define XS1_TIMER_CTRL0_COND_SIZE 0x1
|
919
|
+
#define XS1_TIMER_CTRL0_COND_MASK \
|
920
|
+
(((1 << XS1_TIMER_CTRL0_COND_SIZE) - 1) << XS1_TIMER_CTRL0_COND_SHIFT)
|
921
|
+
#define XS1_TIMER_CTRL0_COND(x) \
|
922
|
+
(((x)&XS1_TIMER_CTRL0_COND_MASK) >> XS1_TIMER_CTRL0_COND_SHIFT)
|
923
|
+
#define XS1_TIMER_CTRL0_COND_SET(x, v) \
|
924
|
+
(((x) & ~XS1_TIMER_CTRL0_COND_MASK) | \
|
925
|
+
(((v) << XS1_TIMER_CTRL0_COND_SHIFT) & XS1_TIMER_CTRL0_COND_MASK))
|
926
|
+
#define XS1_TIMER_CTRL0_EV_VALID_SHIFT 0x8
|
927
|
+
#define XS1_TIMER_CTRL0_EV_VALID_SIZE 0x1
|
928
|
+
#define XS1_TIMER_CTRL0_EV_VALID_MASK \
|
929
|
+
(((1 << XS1_TIMER_CTRL0_EV_VALID_SIZE) - 1) << XS1_TIMER_CTRL0_EV_VALID_SHIFT)
|
930
|
+
#define XS1_TIMER_CTRL0_EV_VALID(x) \
|
931
|
+
(((x)&XS1_TIMER_CTRL0_EV_VALID_MASK) >> XS1_TIMER_CTRL0_EV_VALID_SHIFT)
|
932
|
+
#define XS1_TIMER_CTRL0_EV_VALID_SET(x, v) \
|
933
|
+
(((x) & ~XS1_TIMER_CTRL0_EV_VALID_MASK) | \
|
934
|
+
(((v) << XS1_TIMER_CTRL0_EV_VALID_SHIFT) & XS1_TIMER_CTRL0_EV_VALID_MASK))
|
935
|
+
#define XS1_TIMER_CTRL0_T_WAITING_SHIFT 0x17
|
936
|
+
#define XS1_TIMER_CTRL0_T_WAITING_SIZE 0x1
|
937
|
+
#define XS1_TIMER_CTRL0_T_WAITING_MASK \
|
938
|
+
(((1 << XS1_TIMER_CTRL0_T_WAITING_SIZE) - 1) \
|
939
|
+
<< XS1_TIMER_CTRL0_T_WAITING_SHIFT)
|
940
|
+
#define XS1_TIMER_CTRL0_T_WAITING(x) \
|
941
|
+
(((x)&XS1_TIMER_CTRL0_T_WAITING_MASK) >> XS1_TIMER_CTRL0_T_WAITING_SHIFT)
|
942
|
+
#define XS1_TIMER_CTRL0_T_WAITING_SET(x, v) \
|
943
|
+
(((x) & ~XS1_TIMER_CTRL0_T_WAITING_MASK) | \
|
944
|
+
(((v) << XS1_TIMER_CTRL0_T_WAITING_SHIFT) & \
|
945
|
+
XS1_TIMER_CTRL0_T_WAITING_MASK))
|
946
|
+
#define XS1_TIMER_CTRL0_T_NUM_SHIFT 0x18
|
947
|
+
#define XS1_TIMER_CTRL0_T_NUM_SIZE 0x8
|
948
|
+
#define XS1_TIMER_CTRL0_T_NUM_MASK \
|
949
|
+
(((1 << XS1_TIMER_CTRL0_T_NUM_SIZE) - 1) << XS1_TIMER_CTRL0_T_NUM_SHIFT)
|
950
|
+
#define XS1_TIMER_CTRL0_T_NUM(x) \
|
951
|
+
(((x)&XS1_TIMER_CTRL0_T_NUM_MASK) >> XS1_TIMER_CTRL0_T_NUM_SHIFT)
|
952
|
+
#define XS1_TIMER_CTRL0_T_NUM_SET(x, v) \
|
953
|
+
(((x) & ~XS1_TIMER_CTRL0_T_NUM_MASK) | \
|
954
|
+
(((v) << XS1_TIMER_CTRL0_T_NUM_SHIFT) & XS1_TIMER_CTRL0_T_NUM_MASK))
|
955
|
+
#define XS1_SWMEM_CTRL0_INUSE_SHIFT 0x0
|
956
|
+
#define XS1_SWMEM_CTRL0_INUSE_SIZE 0x1
|
957
|
+
#define XS1_SWMEM_CTRL0_INUSE_MASK \
|
958
|
+
(((1 << XS1_SWMEM_CTRL0_INUSE_SIZE) - 1) << XS1_SWMEM_CTRL0_INUSE_SHIFT)
|
959
|
+
#define XS1_SWMEM_CTRL0_INUSE(x) \
|
960
|
+
(((x)&XS1_SWMEM_CTRL0_INUSE_MASK) >> XS1_SWMEM_CTRL0_INUSE_SHIFT)
|
961
|
+
#define XS1_SWMEM_CTRL0_INUSE_SET(x, v) \
|
962
|
+
(((x) & ~XS1_SWMEM_CTRL0_INUSE_MASK) | \
|
963
|
+
(((v) << XS1_SWMEM_CTRL0_INUSE_SHIFT) & XS1_SWMEM_CTRL0_INUSE_MASK))
|
964
|
+
#define XS1_SWMEM_CTRL0_IE_MODE_SHIFT 0x1
|
965
|
+
#define XS1_SWMEM_CTRL0_IE_MODE_SIZE 0x1
|
966
|
+
#define XS1_SWMEM_CTRL0_IE_MODE_MASK \
|
967
|
+
(((1 << XS1_SWMEM_CTRL0_IE_MODE_SIZE) - 1) << XS1_SWMEM_CTRL0_IE_MODE_SHIFT)
|
968
|
+
#define XS1_SWMEM_CTRL0_IE_MODE(x) \
|
969
|
+
(((x)&XS1_SWMEM_CTRL0_IE_MODE_MASK) >> XS1_SWMEM_CTRL0_IE_MODE_SHIFT)
|
970
|
+
#define XS1_SWMEM_CTRL0_IE_MODE_SET(x, v) \
|
971
|
+
(((x) & ~XS1_SWMEM_CTRL0_IE_MODE_MASK) | \
|
972
|
+
(((v) << XS1_SWMEM_CTRL0_IE_MODE_SHIFT) & XS1_SWMEM_CTRL0_IE_MODE_MASK))
|
973
|
+
#define XS1_SWMEM_CTRL0_IE_ENABLED_SHIFT 0x2
|
974
|
+
#define XS1_SWMEM_CTRL0_IE_ENABLED_SIZE 0x1
|
975
|
+
#define XS1_SWMEM_CTRL0_IE_ENABLED_MASK \
|
976
|
+
(((1 << XS1_SWMEM_CTRL0_IE_ENABLED_SIZE) - 1) \
|
977
|
+
<< XS1_SWMEM_CTRL0_IE_ENABLED_SHIFT)
|
978
|
+
#define XS1_SWMEM_CTRL0_IE_ENABLED(x) \
|
979
|
+
(((x)&XS1_SWMEM_CTRL0_IE_ENABLED_MASK) >> XS1_SWMEM_CTRL0_IE_ENABLED_SHIFT)
|
980
|
+
#define XS1_SWMEM_CTRL0_IE_ENABLED_SET(x, v) \
|
981
|
+
(((x) & ~XS1_SWMEM_CTRL0_IE_ENABLED_MASK) | \
|
982
|
+
(((v) << XS1_SWMEM_CTRL0_IE_ENABLED_SHIFT) & \
|
983
|
+
XS1_SWMEM_CTRL0_IE_ENABLED_MASK))
|
984
|
+
#define XS1_SWMEM_CTRL0_READY_SHIFT 0x3
|
985
|
+
#define XS1_SWMEM_CTRL0_READY_SIZE 0x1
|
986
|
+
#define XS1_SWMEM_CTRL0_READY_MASK \
|
987
|
+
(((1 << XS1_SWMEM_CTRL0_READY_SIZE) - 1) << XS1_SWMEM_CTRL0_READY_SHIFT)
|
988
|
+
#define XS1_SWMEM_CTRL0_READY(x) \
|
989
|
+
(((x)&XS1_SWMEM_CTRL0_READY_MASK) >> XS1_SWMEM_CTRL0_READY_SHIFT)
|
990
|
+
#define XS1_SWMEM_CTRL0_READY_SET(x, v) \
|
991
|
+
(((x) & ~XS1_SWMEM_CTRL0_READY_MASK) | \
|
992
|
+
(((v) << XS1_SWMEM_CTRL0_READY_SHIFT) & XS1_SWMEM_CTRL0_READY_MASK))
|
993
|
+
#define XS1_SWMEM_CTRL0_COND_SHIFT 0x4
|
994
|
+
#define XS1_SWMEM_CTRL0_COND_SIZE 0x1
|
995
|
+
#define XS1_SWMEM_CTRL0_COND_MASK \
|
996
|
+
(((1 << XS1_SWMEM_CTRL0_COND_SIZE) - 1) << XS1_SWMEM_CTRL0_COND_SHIFT)
|
997
|
+
#define XS1_SWMEM_CTRL0_COND(x) \
|
998
|
+
(((x)&XS1_SWMEM_CTRL0_COND_MASK) >> XS1_SWMEM_CTRL0_COND_SHIFT)
|
999
|
+
#define XS1_SWMEM_CTRL0_COND_SET(x, v) \
|
1000
|
+
(((x) & ~XS1_SWMEM_CTRL0_COND_MASK) | \
|
1001
|
+
(((v) << XS1_SWMEM_CTRL0_COND_SHIFT) & XS1_SWMEM_CTRL0_COND_MASK))
|
1002
|
+
#define XS1_SWMEM_CTRL0_EV_VALID_SHIFT 0x8
|
1003
|
+
#define XS1_SWMEM_CTRL0_EV_VALID_SIZE 0x1
|
1004
|
+
#define XS1_SWMEM_CTRL0_EV_VALID_MASK \
|
1005
|
+
(((1 << XS1_SWMEM_CTRL0_EV_VALID_SIZE) - 1) << XS1_SWMEM_CTRL0_EV_VALID_SHIFT)
|
1006
|
+
#define XS1_SWMEM_CTRL0_EV_VALID(x) \
|
1007
|
+
(((x)&XS1_SWMEM_CTRL0_EV_VALID_MASK) >> XS1_SWMEM_CTRL0_EV_VALID_SHIFT)
|
1008
|
+
#define XS1_SWMEM_CTRL0_EV_VALID_SET(x, v) \
|
1009
|
+
(((x) & ~XS1_SWMEM_CTRL0_EV_VALID_MASK) | \
|
1010
|
+
(((v) << XS1_SWMEM_CTRL0_EV_VALID_SHIFT) & XS1_SWMEM_CTRL0_EV_VALID_MASK))
|
1011
|
+
#define XS1_SWMEM_CTRL0_T_WAITING_SHIFT 0x17
|
1012
|
+
#define XS1_SWMEM_CTRL0_T_WAITING_SIZE 0x1
|
1013
|
+
#define XS1_SWMEM_CTRL0_T_WAITING_MASK \
|
1014
|
+
(((1 << XS1_SWMEM_CTRL0_T_WAITING_SIZE) - 1) \
|
1015
|
+
<< XS1_SWMEM_CTRL0_T_WAITING_SHIFT)
|
1016
|
+
#define XS1_SWMEM_CTRL0_T_WAITING(x) \
|
1017
|
+
(((x)&XS1_SWMEM_CTRL0_T_WAITING_MASK) >> XS1_SWMEM_CTRL0_T_WAITING_SHIFT)
|
1018
|
+
#define XS1_SWMEM_CTRL0_T_WAITING_SET(x, v) \
|
1019
|
+
(((x) & ~XS1_SWMEM_CTRL0_T_WAITING_MASK) | \
|
1020
|
+
(((v) << XS1_SWMEM_CTRL0_T_WAITING_SHIFT) & \
|
1021
|
+
XS1_SWMEM_CTRL0_T_WAITING_MASK))
|
1022
|
+
#define XS1_SWMEM_CTRL0_T_NUM_SHIFT 0x18
|
1023
|
+
#define XS1_SWMEM_CTRL0_T_NUM_SIZE 0x8
|
1024
|
+
#define XS1_SWMEM_CTRL0_T_NUM_MASK \
|
1025
|
+
(((1 << XS1_SWMEM_CTRL0_T_NUM_SIZE) - 1) << XS1_SWMEM_CTRL0_T_NUM_SHIFT)
|
1026
|
+
#define XS1_SWMEM_CTRL0_T_NUM(x) \
|
1027
|
+
(((x)&XS1_SWMEM_CTRL0_T_NUM_MASK) >> XS1_SWMEM_CTRL0_T_NUM_SHIFT)
|
1028
|
+
#define XS1_SWMEM_CTRL0_T_NUM_SET(x, v) \
|
1029
|
+
(((x) & ~XS1_SWMEM_CTRL0_T_NUM_MASK) | \
|
1030
|
+
(((v) << XS1_SWMEM_CTRL0_T_NUM_SHIFT) & XS1_SWMEM_CTRL0_T_NUM_MASK))
|
1031
|
+
#define XS1_OTPA_MOSI_LSB_SHIFT 0x0
|
1032
|
+
#define XS1_OTPA_MOSI_LSB_SIZE 0x1
|
1033
|
+
#define XS1_OTPA_MOSI_LSB_MASK \
|
1034
|
+
(((1 << XS1_OTPA_MOSI_LSB_SIZE) - 1) << XS1_OTPA_MOSI_LSB_SHIFT)
|
1035
|
+
#define XS1_OTPA_MOSI_LSB(x) \
|
1036
|
+
(((x)&XS1_OTPA_MOSI_LSB_MASK) >> XS1_OTPA_MOSI_LSB_SHIFT)
|
1037
|
+
#define XS1_OTPA_MOSI_LSB_SET(x, v) \
|
1038
|
+
(((x) & ~XS1_OTPA_MOSI_LSB_MASK) | \
|
1039
|
+
(((v) << XS1_OTPA_MOSI_LSB_SHIFT) & XS1_OTPA_MOSI_LSB_MASK))
|
1040
|
+
#define XS1_OTPA_MOSI_MSB_SHIFT 0x7
|
1041
|
+
#define XS1_OTPA_MOSI_MSB_SIZE 0x1
|
1042
|
+
#define XS1_OTPA_MOSI_MSB_MASK \
|
1043
|
+
(((1 << XS1_OTPA_MOSI_MSB_SIZE) - 1) << XS1_OTPA_MOSI_MSB_SHIFT)
|
1044
|
+
#define XS1_OTPA_MOSI_MSB(x) \
|
1045
|
+
(((x)&XS1_OTPA_MOSI_MSB_MASK) >> XS1_OTPA_MOSI_MSB_SHIFT)
|
1046
|
+
#define XS1_OTPA_MOSI_MSB_SET(x, v) \
|
1047
|
+
(((x) & ~XS1_OTPA_MOSI_MSB_MASK) | \
|
1048
|
+
(((v) << XS1_OTPA_MOSI_MSB_SHIFT) & XS1_OTPA_MOSI_MSB_MASK))
|
1049
|
+
#define XS1_OTPA_CLK_IDX_SHIFT 0x8
|
1050
|
+
#define XS1_OTPA_CLK_IDX_SIZE 0x1
|
1051
|
+
#define XS1_OTPA_CLK_IDX_MASK \
|
1052
|
+
(((1 << XS1_OTPA_CLK_IDX_SIZE) - 1) << XS1_OTPA_CLK_IDX_SHIFT)
|
1053
|
+
#define XS1_OTPA_CLK_IDX(x) \
|
1054
|
+
(((x)&XS1_OTPA_CLK_IDX_MASK) >> XS1_OTPA_CLK_IDX_SHIFT)
|
1055
|
+
#define XS1_OTPA_CLK_IDX_SET(x, v) \
|
1056
|
+
(((x) & ~XS1_OTPA_CLK_IDX_MASK) | \
|
1057
|
+
(((v) << XS1_OTPA_CLK_IDX_SHIFT) & XS1_OTPA_CLK_IDX_MASK))
|
1058
|
+
#define XS1_OTPA_SP_IDX_SHIFT 0x9
|
1059
|
+
#define XS1_OTPA_SP_IDX_SIZE 0x1
|
1060
|
+
#define XS1_OTPA_SP_IDX_MASK \
|
1061
|
+
(((1 << XS1_OTPA_SP_IDX_SIZE) - 1) << XS1_OTPA_SP_IDX_SHIFT)
|
1062
|
+
#define XS1_OTPA_SP_IDX(x) (((x)&XS1_OTPA_SP_IDX_MASK) >> XS1_OTPA_SP_IDX_SHIFT)
|
1063
|
+
#define XS1_OTPA_SP_IDX_SET(x, v) \
|
1064
|
+
(((x) & ~XS1_OTPA_SP_IDX_MASK) | \
|
1065
|
+
(((v) << XS1_OTPA_SP_IDX_SHIFT) & XS1_OTPA_SP_IDX_MASK))
|
1066
|
+
#define XS1_OTPA_CS_IDX_SHIFT 0xa
|
1067
|
+
#define XS1_OTPA_CS_IDX_SIZE 0x1
|
1068
|
+
#define XS1_OTPA_CS_IDX_MASK \
|
1069
|
+
(((1 << XS1_OTPA_CS_IDX_SIZE) - 1) << XS1_OTPA_CS_IDX_SHIFT)
|
1070
|
+
#define XS1_OTPA_CS_IDX(x) (((x)&XS1_OTPA_CS_IDX_MASK) >> XS1_OTPA_CS_IDX_SHIFT)
|
1071
|
+
#define XS1_OTPA_CS_IDX_SET(x, v) \
|
1072
|
+
(((x) & ~XS1_OTPA_CS_IDX_MASK) | \
|
1073
|
+
(((v) << XS1_OTPA_CS_IDX_SHIFT) & XS1_OTPA_CS_IDX_MASK))
|
1074
|
+
#define XS1_OTPA_CKE_IDX_SHIFT 0xb
|
1075
|
+
#define XS1_OTPA_CKE_IDX_SIZE 0x1
|
1076
|
+
#define XS1_OTPA_CKE_IDX_MASK \
|
1077
|
+
(((1 << XS1_OTPA_CKE_IDX_SIZE) - 1) << XS1_OTPA_CKE_IDX_SHIFT)
|
1078
|
+
#define XS1_OTPA_CKE_IDX(x) \
|
1079
|
+
(((x)&XS1_OTPA_CKE_IDX_MASK) >> XS1_OTPA_CKE_IDX_SHIFT)
|
1080
|
+
#define XS1_OTPA_CKE_IDX_SET(x, v) \
|
1081
|
+
(((x) & ~XS1_OTPA_CKE_IDX_MASK) | \
|
1082
|
+
(((v) << XS1_OTPA_CKE_IDX_SHIFT) & XS1_OTPA_CKE_IDX_MASK))
|
1083
|
+
#define XS1_OTPA_DCTRL_IDX_SHIFT 0xc
|
1084
|
+
#define XS1_OTPA_DCTRL_IDX_SIZE 0x1
|
1085
|
+
#define XS1_OTPA_DCTRL_IDX_MASK \
|
1086
|
+
(((1 << XS1_OTPA_DCTRL_IDX_SIZE) - 1) << XS1_OTPA_DCTRL_IDX_SHIFT)
|
1087
|
+
#define XS1_OTPA_DCTRL_IDX(x) \
|
1088
|
+
(((x)&XS1_OTPA_DCTRL_IDX_MASK) >> XS1_OTPA_DCTRL_IDX_SHIFT)
|
1089
|
+
#define XS1_OTPA_DCTRL_IDX_SET(x, v) \
|
1090
|
+
(((x) & ~XS1_OTPA_DCTRL_IDX_MASK) | \
|
1091
|
+
(((v) << XS1_OTPA_DCTRL_IDX_SHIFT) & XS1_OTPA_DCTRL_IDX_MASK))
|
1092
|
+
#define XS1_OTPA_PD_IDX_SHIFT 0xd
|
1093
|
+
#define XS1_OTPA_PD_IDX_SIZE 0x1
|
1094
|
+
#define XS1_OTPA_PD_IDX_MASK \
|
1095
|
+
(((1 << XS1_OTPA_PD_IDX_SIZE) - 1) << XS1_OTPA_PD_IDX_SHIFT)
|
1096
|
+
#define XS1_OTPA_PD_IDX(x) (((x)&XS1_OTPA_PD_IDX_MASK) >> XS1_OTPA_PD_IDX_SHIFT)
|
1097
|
+
#define XS1_OTPA_PD_IDX_SET(x, v) \
|
1098
|
+
(((x) & ~XS1_OTPA_PD_IDX_MASK) | \
|
1099
|
+
(((v) << XS1_OTPA_PD_IDX_SHIFT) & XS1_OTPA_PD_IDX_MASK))
|
1100
|
+
#define XS1_OTPA_SEL_IDX_SHIFT 0xe
|
1101
|
+
#define XS1_OTPA_SEL_IDX_SIZE 0x1
|
1102
|
+
#define XS1_OTPA_SEL_IDX_MASK \
|
1103
|
+
(((1 << XS1_OTPA_SEL_IDX_SIZE) - 1) << XS1_OTPA_SEL_IDX_SHIFT)
|
1104
|
+
#define XS1_OTPA_SEL_IDX(x) \
|
1105
|
+
(((x)&XS1_OTPA_SEL_IDX_MASK) >> XS1_OTPA_SEL_IDX_SHIFT)
|
1106
|
+
#define XS1_OTPA_SEL_IDX_SET(x, v) \
|
1107
|
+
(((x) & ~XS1_OTPA_SEL_IDX_MASK) | \
|
1108
|
+
(((v) << XS1_OTPA_SEL_IDX_SHIFT) & XS1_OTPA_SEL_IDX_MASK))
|
1109
|
+
#define XS1_OTPA_CK_IDX_SHIFT 0xf
|
1110
|
+
#define XS1_OTPA_CK_IDX_SIZE 0x1
|
1111
|
+
#define XS1_OTPA_CK_IDX_MASK \
|
1112
|
+
(((1 << XS1_OTPA_CK_IDX_SIZE) - 1) << XS1_OTPA_CK_IDX_SHIFT)
|
1113
|
+
#define XS1_OTPA_CK_IDX(x) (((x)&XS1_OTPA_CK_IDX_MASK) >> XS1_OTPA_CK_IDX_SHIFT)
|
1114
|
+
#define XS1_OTPA_CK_IDX_SET(x, v) \
|
1115
|
+
(((x) & ~XS1_OTPA_CK_IDX_MASK) | \
|
1116
|
+
(((v) << XS1_OTPA_CK_IDX_SHIFT) & XS1_OTPA_CK_IDX_MASK))
|
1117
|
+
#define XS1_OTPA_A_LSB_SHIFT 0x10
|
1118
|
+
#define XS1_OTPA_A_LSB_SIZE 0x1
|
1119
|
+
#define XS1_OTPA_A_LSB_MASK \
|
1120
|
+
(((1 << XS1_OTPA_A_LSB_SIZE) - 1) << XS1_OTPA_A_LSB_SHIFT)
|
1121
|
+
#define XS1_OTPA_A_LSB(x) (((x)&XS1_OTPA_A_LSB_MASK) >> XS1_OTPA_A_LSB_SHIFT)
|
1122
|
+
#define XS1_OTPA_A_LSB_SET(x, v) \
|
1123
|
+
(((x) & ~XS1_OTPA_A_LSB_MASK) | \
|
1124
|
+
(((v) << XS1_OTPA_A_LSB_SHIFT) & XS1_OTPA_A_LSB_MASK))
|
1125
|
+
#define XS1_OTPA_A_MSB_SHIFT 0x1a
|
1126
|
+
#define XS1_OTPA_A_MSB_SIZE 0x1
|
1127
|
+
#define XS1_OTPA_A_MSB_MASK \
|
1128
|
+
(((1 << XS1_OTPA_A_MSB_SIZE) - 1) << XS1_OTPA_A_MSB_SHIFT)
|
1129
|
+
#define XS1_OTPA_A_MSB(x) (((x)&XS1_OTPA_A_MSB_MASK) >> XS1_OTPA_A_MSB_SHIFT)
|
1130
|
+
#define XS1_OTPA_A_MSB_SET(x, v) \
|
1131
|
+
(((x) & ~XS1_OTPA_A_MSB_MASK) | \
|
1132
|
+
(((v) << XS1_OTPA_A_MSB_SHIFT) & XS1_OTPA_A_MSB_MASK))
|
1133
|
+
#define XS1_OTPA_RST_IDX_SHIFT 0x1b
|
1134
|
+
#define XS1_OTPA_RST_IDX_SIZE 0x1
|
1135
|
+
#define XS1_OTPA_RST_IDX_MASK \
|
1136
|
+
(((1 << XS1_OTPA_RST_IDX_SIZE) - 1) << XS1_OTPA_RST_IDX_SHIFT)
|
1137
|
+
#define XS1_OTPA_RST_IDX(x) \
|
1138
|
+
(((x)&XS1_OTPA_RST_IDX_MASK) >> XS1_OTPA_RST_IDX_SHIFT)
|
1139
|
+
#define XS1_OTPA_RST_IDX_SET(x, v) \
|
1140
|
+
(((x) & ~XS1_OTPA_RST_IDX_MASK) | \
|
1141
|
+
(((v) << XS1_OTPA_RST_IDX_SHIFT) & XS1_OTPA_RST_IDX_MASK))
|
1142
|
+
#define XS1_OTPA_ARB_REQ_IDX_SHIFT 0x1c
|
1143
|
+
#define XS1_OTPA_ARB_REQ_IDX_SIZE 0x1
|
1144
|
+
#define XS1_OTPA_ARB_REQ_IDX_MASK \
|
1145
|
+
(((1 << XS1_OTPA_ARB_REQ_IDX_SIZE) - 1) << XS1_OTPA_ARB_REQ_IDX_SHIFT)
|
1146
|
+
#define XS1_OTPA_ARB_REQ_IDX(x) \
|
1147
|
+
(((x)&XS1_OTPA_ARB_REQ_IDX_MASK) >> XS1_OTPA_ARB_REQ_IDX_SHIFT)
|
1148
|
+
#define XS1_OTPA_ARB_REQ_IDX_SET(x, v) \
|
1149
|
+
(((x) & ~XS1_OTPA_ARB_REQ_IDX_MASK) | \
|
1150
|
+
(((v) << XS1_OTPA_ARB_REQ_IDX_SHIFT) & XS1_OTPA_ARB_REQ_IDX_MASK))
|
1151
|
+
#define XS1_OTPA_MUXSEL_LSB_SHIFT 0x1d
|
1152
|
+
#define XS1_OTPA_MUXSEL_LSB_SIZE 0x1
|
1153
|
+
#define XS1_OTPA_MUXSEL_LSB_MASK \
|
1154
|
+
(((1 << XS1_OTPA_MUXSEL_LSB_SIZE) - 1) << XS1_OTPA_MUXSEL_LSB_SHIFT)
|
1155
|
+
#define XS1_OTPA_MUXSEL_LSB(x) \
|
1156
|
+
(((x)&XS1_OTPA_MUXSEL_LSB_MASK) >> XS1_OTPA_MUXSEL_LSB_SHIFT)
|
1157
|
+
#define XS1_OTPA_MUXSEL_LSB_SET(x, v) \
|
1158
|
+
(((x) & ~XS1_OTPA_MUXSEL_LSB_MASK) | \
|
1159
|
+
(((v) << XS1_OTPA_MUXSEL_LSB_SHIFT) & XS1_OTPA_MUXSEL_LSB_MASK))
|
1160
|
+
#define XS1_OTPA_MUXSEL_MSB_SHIFT 0x1f
|
1161
|
+
#define XS1_OTPA_MUXSEL_MSB_SIZE 0x1
|
1162
|
+
#define XS1_OTPA_MUXSEL_MSB_MASK \
|
1163
|
+
(((1 << XS1_OTPA_MUXSEL_MSB_SIZE) - 1) << XS1_OTPA_MUXSEL_MSB_SHIFT)
|
1164
|
+
#define XS1_OTPA_MUXSEL_MSB(x) \
|
1165
|
+
(((x)&XS1_OTPA_MUXSEL_MSB_MASK) >> XS1_OTPA_MUXSEL_MSB_SHIFT)
|
1166
|
+
#define XS1_OTPA_MUXSEL_MSB_SET(x, v) \
|
1167
|
+
(((x) & ~XS1_OTPA_MUXSEL_MSB_MASK) | \
|
1168
|
+
(((v) << XS1_OTPA_MUXSEL_MSB_SHIFT) & XS1_OTPA_MUXSEL_MSB_MASK))
|
1169
|
+
#define XS1_OTPA_MISO_LSB_SHIFT 0x0
|
1170
|
+
#define XS1_OTPA_MISO_LSB_SIZE 0x1
|
1171
|
+
#define XS1_OTPA_MISO_LSB_MASK \
|
1172
|
+
(((1 << XS1_OTPA_MISO_LSB_SIZE) - 1) << XS1_OTPA_MISO_LSB_SHIFT)
|
1173
|
+
#define XS1_OTPA_MISO_LSB(x) \
|
1174
|
+
(((x)&XS1_OTPA_MISO_LSB_MASK) >> XS1_OTPA_MISO_LSB_SHIFT)
|
1175
|
+
#define XS1_OTPA_MISO_LSB_SET(x, v) \
|
1176
|
+
(((x) & ~XS1_OTPA_MISO_LSB_MASK) | \
|
1177
|
+
(((v) << XS1_OTPA_MISO_LSB_SHIFT) & XS1_OTPA_MISO_LSB_MASK))
|
1178
|
+
#define XS1_OTPA_MISO_MSB_SHIFT 0x7
|
1179
|
+
#define XS1_OTPA_MISO_MSB_SIZE 0x1
|
1180
|
+
#define XS1_OTPA_MISO_MSB_MASK \
|
1181
|
+
(((1 << XS1_OTPA_MISO_MSB_SIZE) - 1) << XS1_OTPA_MISO_MSB_SHIFT)
|
1182
|
+
#define XS1_OTPA_MISO_MSB(x) \
|
1183
|
+
(((x)&XS1_OTPA_MISO_MSB_MASK) >> XS1_OTPA_MISO_MSB_SHIFT)
|
1184
|
+
#define XS1_OTPA_MISO_MSB_SET(x, v) \
|
1185
|
+
(((x) & ~XS1_OTPA_MISO_MSB_MASK) | \
|
1186
|
+
(((v) << XS1_OTPA_MISO_MSB_SHIFT) & XS1_OTPA_MISO_MSB_MASK))
|
1187
|
+
#define XS1_OTPA_FLAG_IDX_SHIFT 0x8
|
1188
|
+
#define XS1_OTPA_FLAG_IDX_SIZE 0x1
|
1189
|
+
#define XS1_OTPA_FLAG_IDX_MASK \
|
1190
|
+
(((1 << XS1_OTPA_FLAG_IDX_SIZE) - 1) << XS1_OTPA_FLAG_IDX_SHIFT)
|
1191
|
+
#define XS1_OTPA_FLAG_IDX(x) \
|
1192
|
+
(((x)&XS1_OTPA_FLAG_IDX_MASK) >> XS1_OTPA_FLAG_IDX_SHIFT)
|
1193
|
+
#define XS1_OTPA_FLAG_IDX_SET(x, v) \
|
1194
|
+
(((x) & ~XS1_OTPA_FLAG_IDX_MASK) | \
|
1195
|
+
(((v) << XS1_OTPA_FLAG_IDX_SHIFT) & XS1_OTPA_FLAG_IDX_MASK))
|
1196
|
+
#define XS1_OTPA_ARB_GNT_IDX_SHIFT 0x9
|
1197
|
+
#define XS1_OTPA_ARB_GNT_IDX_SIZE 0x1
|
1198
|
+
#define XS1_OTPA_ARB_GNT_IDX_MASK \
|
1199
|
+
(((1 << XS1_OTPA_ARB_GNT_IDX_SIZE) - 1) << XS1_OTPA_ARB_GNT_IDX_SHIFT)
|
1200
|
+
#define XS1_OTPA_ARB_GNT_IDX(x) \
|
1201
|
+
(((x)&XS1_OTPA_ARB_GNT_IDX_MASK) >> XS1_OTPA_ARB_GNT_IDX_SHIFT)
|
1202
|
+
#define XS1_OTPA_ARB_GNT_IDX_SET(x, v) \
|
1203
|
+
(((x) & ~XS1_OTPA_ARB_GNT_IDX_MASK) | \
|
1204
|
+
(((v) << XS1_OTPA_ARB_GNT_IDX_SHIFT) & XS1_OTPA_ARB_GNT_IDX_MASK))
|
1205
|
+
#define XS1_SYNC_CTRL0_INUSE_SHIFT 0x0
|
1206
|
+
#define XS1_SYNC_CTRL0_INUSE_SIZE 0x1
|
1207
|
+
#define XS1_SYNC_CTRL0_INUSE_MASK \
|
1208
|
+
(((1 << XS1_SYNC_CTRL0_INUSE_SIZE) - 1) << XS1_SYNC_CTRL0_INUSE_SHIFT)
|
1209
|
+
#define XS1_SYNC_CTRL0_INUSE(x) \
|
1210
|
+
(((x)&XS1_SYNC_CTRL0_INUSE_MASK) >> XS1_SYNC_CTRL0_INUSE_SHIFT)
|
1211
|
+
#define XS1_SYNC_CTRL0_INUSE_SET(x, v) \
|
1212
|
+
(((x) & ~XS1_SYNC_CTRL0_INUSE_MASK) | \
|
1213
|
+
(((v) << XS1_SYNC_CTRL0_INUSE_SHIFT) & XS1_SYNC_CTRL0_INUSE_MASK))
|
1214
|
+
#define XS1_SYNC_CTRL0_MSYNCED_SHIFT 0x1
|
1215
|
+
#define XS1_SYNC_CTRL0_MSYNCED_SIZE 0x1
|
1216
|
+
#define XS1_SYNC_CTRL0_MSYNCED_MASK \
|
1217
|
+
(((1 << XS1_SYNC_CTRL0_MSYNCED_SIZE) - 1) << XS1_SYNC_CTRL0_MSYNCED_SHIFT)
|
1218
|
+
#define XS1_SYNC_CTRL0_MSYNCED(x) \
|
1219
|
+
(((x)&XS1_SYNC_CTRL0_MSYNCED_MASK) >> XS1_SYNC_CTRL0_MSYNCED_SHIFT)
|
1220
|
+
#define XS1_SYNC_CTRL0_MSYNCED_SET(x, v) \
|
1221
|
+
(((x) & ~XS1_SYNC_CTRL0_MSYNCED_MASK) | \
|
1222
|
+
(((v) << XS1_SYNC_CTRL0_MSYNCED_SHIFT) & XS1_SYNC_CTRL0_MSYNCED_MASK))
|
1223
|
+
#define XS1_SYNC_CTRL0_JOIN_SHIFT 0x2
|
1224
|
+
#define XS1_SYNC_CTRL0_JOIN_SIZE 0x1
|
1225
|
+
#define XS1_SYNC_CTRL0_JOIN_MASK \
|
1226
|
+
(((1 << XS1_SYNC_CTRL0_JOIN_SIZE) - 1) << XS1_SYNC_CTRL0_JOIN_SHIFT)
|
1227
|
+
#define XS1_SYNC_CTRL0_JOIN(x) \
|
1228
|
+
(((x)&XS1_SYNC_CTRL0_JOIN_MASK) >> XS1_SYNC_CTRL0_JOIN_SHIFT)
|
1229
|
+
#define XS1_SYNC_CTRL0_JOIN_SET(x, v) \
|
1230
|
+
(((x) & ~XS1_SYNC_CTRL0_JOIN_MASK) | \
|
1231
|
+
(((v) << XS1_SYNC_CTRL0_JOIN_SHIFT) & XS1_SYNC_CTRL0_JOIN_MASK))
|
1232
|
+
#define XS1_SYNC_CTRL0_MASTER_SHIFT 0x8
|
1233
|
+
#define XS1_SYNC_CTRL0_MASTER_SIZE 0x8
|
1234
|
+
#define XS1_SYNC_CTRL0_MASTER_MASK \
|
1235
|
+
(((1 << XS1_SYNC_CTRL0_MASTER_SIZE) - 1) << XS1_SYNC_CTRL0_MASTER_SHIFT)
|
1236
|
+
#define XS1_SYNC_CTRL0_MASTER(x) \
|
1237
|
+
(((x)&XS1_SYNC_CTRL0_MASTER_MASK) >> XS1_SYNC_CTRL0_MASTER_SHIFT)
|
1238
|
+
#define XS1_SYNC_CTRL0_MASTER_SET(x, v) \
|
1239
|
+
(((x) & ~XS1_SYNC_CTRL0_MASTER_MASK) | \
|
1240
|
+
(((v) << XS1_SYNC_CTRL0_MASTER_SHIFT) & XS1_SYNC_CTRL0_MASTER_MASK))
|
1241
|
+
#define XS1_SYNC_TBV0_SLAVES_SHIFT 0x0
|
1242
|
+
#define XS1_SYNC_TBV0_SLAVES_SIZE 0x8
|
1243
|
+
#define XS1_SYNC_TBV0_SLAVES_MASK \
|
1244
|
+
(((1 << XS1_SYNC_TBV0_SLAVES_SIZE) - 1) << XS1_SYNC_TBV0_SLAVES_SHIFT)
|
1245
|
+
#define XS1_SYNC_TBV0_SLAVES(x) \
|
1246
|
+
(((x)&XS1_SYNC_TBV0_SLAVES_MASK) >> XS1_SYNC_TBV0_SLAVES_SHIFT)
|
1247
|
+
#define XS1_SYNC_TBV0_SLAVES_SET(x, v) \
|
1248
|
+
(((x) & ~XS1_SYNC_TBV0_SLAVES_MASK) | \
|
1249
|
+
(((v) << XS1_SYNC_TBV0_SLAVES_SHIFT) & XS1_SYNC_TBV0_SLAVES_MASK))
|
1250
|
+
#define XS1_LOCK_CTRL0_INUSE_SHIFT 0x0
|
1251
|
+
#define XS1_LOCK_CTRL0_INUSE_SIZE 0x1
|
1252
|
+
#define XS1_LOCK_CTRL0_INUSE_MASK \
|
1253
|
+
(((1 << XS1_LOCK_CTRL0_INUSE_SIZE) - 1) << XS1_LOCK_CTRL0_INUSE_SHIFT)
|
1254
|
+
#define XS1_LOCK_CTRL0_INUSE(x) \
|
1255
|
+
(((x)&XS1_LOCK_CTRL0_INUSE_MASK) >> XS1_LOCK_CTRL0_INUSE_SHIFT)
|
1256
|
+
#define XS1_LOCK_CTRL0_INUSE_SET(x, v) \
|
1257
|
+
(((x) & ~XS1_LOCK_CTRL0_INUSE_MASK) | \
|
1258
|
+
(((v) << XS1_LOCK_CTRL0_INUSE_SHIFT) & XS1_LOCK_CTRL0_INUSE_MASK))
|
1259
|
+
#define XS1_LOCK_CTRL0_OWNT_V_SHIFT 0x1
|
1260
|
+
#define XS1_LOCK_CTRL0_OWNT_V_SIZE 0x1
|
1261
|
+
#define XS1_LOCK_CTRL0_OWNT_V_MASK \
|
1262
|
+
(((1 << XS1_LOCK_CTRL0_OWNT_V_SIZE) - 1) << XS1_LOCK_CTRL0_OWNT_V_SHIFT)
|
1263
|
+
#define XS1_LOCK_CTRL0_OWNT_V(x) \
|
1264
|
+
(((x)&XS1_LOCK_CTRL0_OWNT_V_MASK) >> XS1_LOCK_CTRL0_OWNT_V_SHIFT)
|
1265
|
+
#define XS1_LOCK_CTRL0_OWNT_V_SET(x, v) \
|
1266
|
+
(((x) & ~XS1_LOCK_CTRL0_OWNT_V_MASK) | \
|
1267
|
+
(((v) << XS1_LOCK_CTRL0_OWNT_V_SHIFT) & XS1_LOCK_CTRL0_OWNT_V_MASK))
|
1268
|
+
#define XS1_LOCK_CTRL0_OWNT_SHIFT 0x8
|
1269
|
+
#define XS1_LOCK_CTRL0_OWNT_SIZE 0x8
|
1270
|
+
#define XS1_LOCK_CTRL0_OWNT_MASK \
|
1271
|
+
(((1 << XS1_LOCK_CTRL0_OWNT_SIZE) - 1) << XS1_LOCK_CTRL0_OWNT_SHIFT)
|
1272
|
+
#define XS1_LOCK_CTRL0_OWNT(x) \
|
1273
|
+
(((x)&XS1_LOCK_CTRL0_OWNT_MASK) >> XS1_LOCK_CTRL0_OWNT_SHIFT)
|
1274
|
+
#define XS1_LOCK_CTRL0_OWNT_SET(x, v) \
|
1275
|
+
(((x) & ~XS1_LOCK_CTRL0_OWNT_MASK) | \
|
1276
|
+
(((v) << XS1_LOCK_CTRL0_OWNT_SHIFT) & XS1_LOCK_CTRL0_OWNT_MASK))
|
1277
|
+
#define XS1_LOCK_TBV0_WAITING_SHIFT 0x0
|
1278
|
+
#define XS1_LOCK_TBV0_WAITING_SIZE 0x8
|
1279
|
+
#define XS1_LOCK_TBV0_WAITING_MASK \
|
1280
|
+
(((1 << XS1_LOCK_TBV0_WAITING_SIZE) - 1) << XS1_LOCK_TBV0_WAITING_SHIFT)
|
1281
|
+
#define XS1_LOCK_TBV0_WAITING(x) \
|
1282
|
+
(((x)&XS1_LOCK_TBV0_WAITING_MASK) >> XS1_LOCK_TBV0_WAITING_SHIFT)
|
1283
|
+
#define XS1_LOCK_TBV0_WAITING_SET(x, v) \
|
1284
|
+
(((x) & ~XS1_LOCK_TBV0_WAITING_MASK) | \
|
1285
|
+
(((v) << XS1_LOCK_TBV0_WAITING_SHIFT) & XS1_LOCK_TBV0_WAITING_MASK))
|
1286
|
+
#define XS1_MMAP_CTRL0_INUSE_SHIFT 0x0
|
1287
|
+
#define XS1_MMAP_CTRL0_INUSE_SIZE 0x1
|
1288
|
+
#define XS1_MMAP_CTRL0_INUSE_MASK \
|
1289
|
+
(((1 << XS1_MMAP_CTRL0_INUSE_SIZE) - 1) << XS1_MMAP_CTRL0_INUSE_SHIFT)
|
1290
|
+
#define XS1_MMAP_CTRL0_INUSE(x) \
|
1291
|
+
(((x)&XS1_MMAP_CTRL0_INUSE_MASK) >> XS1_MMAP_CTRL0_INUSE_SHIFT)
|
1292
|
+
#define XS1_MMAP_CTRL0_INUSE_SET(x, v) \
|
1293
|
+
(((x) & ~XS1_MMAP_CTRL0_INUSE_MASK) | \
|
1294
|
+
(((v) << XS1_MMAP_CTRL0_INUSE_SHIFT) & XS1_MMAP_CTRL0_INUSE_MASK))
|
1295
|
+
#define XS1_MMAP_CTRL0_RO_SHIFT 0x1
|
1296
|
+
#define XS1_MMAP_CTRL0_RO_SIZE 0x1
|
1297
|
+
#define XS1_MMAP_CTRL0_RO_MASK \
|
1298
|
+
(((1 << XS1_MMAP_CTRL0_RO_SIZE) - 1) << XS1_MMAP_CTRL0_RO_SHIFT)
|
1299
|
+
#define XS1_MMAP_CTRL0_RO(x) \
|
1300
|
+
(((x)&XS1_MMAP_CTRL0_RO_MASK) >> XS1_MMAP_CTRL0_RO_SHIFT)
|
1301
|
+
#define XS1_MMAP_CTRL0_RO_SET(x, v) \
|
1302
|
+
(((x) & ~XS1_MMAP_CTRL0_RO_MASK) | \
|
1303
|
+
(((v) << XS1_MMAP_CTRL0_RO_SHIFT) & XS1_MMAP_CTRL0_RO_MASK))
|
1304
|
+
#define XS1_MMAP_CTRL0_LOCK_SHIFT 0x2
|
1305
|
+
#define XS1_MMAP_CTRL0_LOCK_SIZE 0x1
|
1306
|
+
#define XS1_MMAP_CTRL0_LOCK_MASK \
|
1307
|
+
(((1 << XS1_MMAP_CTRL0_LOCK_SIZE) - 1) << XS1_MMAP_CTRL0_LOCK_SHIFT)
|
1308
|
+
#define XS1_MMAP_CTRL0_LOCK(x) \
|
1309
|
+
(((x)&XS1_MMAP_CTRL0_LOCK_MASK) >> XS1_MMAP_CTRL0_LOCK_SHIFT)
|
1310
|
+
#define XS1_MMAP_CTRL0_LOCK_SET(x, v) \
|
1311
|
+
(((x) & ~XS1_MMAP_CTRL0_LOCK_MASK) | \
|
1312
|
+
(((v) << XS1_MMAP_CTRL0_LOCK_SHIFT) & XS1_MMAP_CTRL0_LOCK_MASK))
|
1313
|
+
#define XS1_MMAP_CTRL0_GLOBAL_SHIFT 0x3
|
1314
|
+
#define XS1_MMAP_CTRL0_GLOBAL_SIZE 0x1
|
1315
|
+
#define XS1_MMAP_CTRL0_GLOBAL_MASK \
|
1316
|
+
(((1 << XS1_MMAP_CTRL0_GLOBAL_SIZE) - 1) << XS1_MMAP_CTRL0_GLOBAL_SHIFT)
|
1317
|
+
#define XS1_MMAP_CTRL0_GLOBAL(x) \
|
1318
|
+
(((x)&XS1_MMAP_CTRL0_GLOBAL_MASK) >> XS1_MMAP_CTRL0_GLOBAL_SHIFT)
|
1319
|
+
#define XS1_MMAP_CTRL0_GLOBAL_SET(x, v) \
|
1320
|
+
(((x) & ~XS1_MMAP_CTRL0_GLOBAL_MASK) | \
|
1321
|
+
(((v) << XS1_MMAP_CTRL0_GLOBAL_SHIFT) & XS1_MMAP_CTRL0_GLOBAL_MASK))
|
1322
|
+
#define XS1_MMAP_CTRL0_ASID_SHIFT 0x4
|
1323
|
+
#define XS1_MMAP_CTRL0_ASID_SIZE 0x2
|
1324
|
+
#define XS1_MMAP_CTRL0_ASID_MASK \
|
1325
|
+
(((1 << XS1_MMAP_CTRL0_ASID_SIZE) - 1) << XS1_MMAP_CTRL0_ASID_SHIFT)
|
1326
|
+
#define XS1_MMAP_CTRL0_ASID(x) \
|
1327
|
+
(((x)&XS1_MMAP_CTRL0_ASID_MASK) >> XS1_MMAP_CTRL0_ASID_SHIFT)
|
1328
|
+
#define XS1_MMAP_CTRL0_ASID_SET(x, v) \
|
1329
|
+
(((x) & ~XS1_MMAP_CTRL0_ASID_MASK) | \
|
1330
|
+
(((v) << XS1_MMAP_CTRL0_ASID_SHIFT) & XS1_MMAP_CTRL0_ASID_MASK))
|
1331
|
+
#define XS1_MMAP_CTRL0_LENGTH_SHIFT 0x6
|
1332
|
+
#define XS1_MMAP_CTRL0_LENGTH_SIZE 0x2
|
1333
|
+
#define XS1_MMAP_CTRL0_LENGTH_MASK \
|
1334
|
+
(((1 << XS1_MMAP_CTRL0_LENGTH_SIZE) - 1) << XS1_MMAP_CTRL0_LENGTH_SHIFT)
|
1335
|
+
#define XS1_MMAP_CTRL0_LENGTH(x) \
|
1336
|
+
(((x)&XS1_MMAP_CTRL0_LENGTH_MASK) >> XS1_MMAP_CTRL0_LENGTH_SHIFT)
|
1337
|
+
#define XS1_MMAP_CTRL0_LENGTH_SET(x, v) \
|
1338
|
+
(((x) & ~XS1_MMAP_CTRL0_LENGTH_MASK) | \
|
1339
|
+
(((v) << XS1_MMAP_CTRL0_LENGTH_SHIFT) & XS1_MMAP_CTRL0_LENGTH_MASK))
|
1340
|
+
#define XS1_MMAP_CTRL0_PHY_ADDR_SHIFT 0x8
|
1341
|
+
#define XS1_MMAP_CTRL0_PHY_ADDR_SIZE 0x18
|
1342
|
+
#define XS1_MMAP_CTRL0_PHY_ADDR_MASK \
|
1343
|
+
(((1 << XS1_MMAP_CTRL0_PHY_ADDR_SIZE) - 1) << XS1_MMAP_CTRL0_PHY_ADDR_SHIFT)
|
1344
|
+
#define XS1_MMAP_CTRL0_PHY_ADDR(x) \
|
1345
|
+
(((x)&XS1_MMAP_CTRL0_PHY_ADDR_MASK) >> XS1_MMAP_CTRL0_PHY_ADDR_SHIFT)
|
1346
|
+
#define XS1_MMAP_CTRL0_PHY_ADDR_SET(x, v) \
|
1347
|
+
(((x) & ~XS1_MMAP_CTRL0_PHY_ADDR_MASK) | \
|
1348
|
+
(((v) << XS1_MMAP_CTRL0_PHY_ADDR_SHIFT) & XS1_MMAP_CTRL0_PHY_ADDR_MASK))
|
1349
|
+
#define XS1_MMAP_CTRL1_THREADS_EN_SHIFT 0x0
|
1350
|
+
#define XS1_MMAP_CTRL1_THREADS_EN_SIZE 0x8
|
1351
|
+
#define XS1_MMAP_CTRL1_THREADS_EN_MASK \
|
1352
|
+
(((1 << XS1_MMAP_CTRL1_THREADS_EN_SIZE) - 1) \
|
1353
|
+
<< XS1_MMAP_CTRL1_THREADS_EN_SHIFT)
|
1354
|
+
#define XS1_MMAP_CTRL1_THREADS_EN(x) \
|
1355
|
+
(((x)&XS1_MMAP_CTRL1_THREADS_EN_MASK) >> XS1_MMAP_CTRL1_THREADS_EN_SHIFT)
|
1356
|
+
#define XS1_MMAP_CTRL1_THREADS_EN_SET(x, v) \
|
1357
|
+
(((x) & ~XS1_MMAP_CTRL1_THREADS_EN_MASK) | \
|
1358
|
+
(((v) << XS1_MMAP_CTRL1_THREADS_EN_SHIFT) & \
|
1359
|
+
XS1_MMAP_CTRL1_THREADS_EN_MASK))
|
1360
|
+
#define XS1_MMAP_CTRL1_VIRT_ADDR_SHIFT 0x8
|
1361
|
+
#define XS1_MMAP_CTRL1_VIRT_ADDR_SIZE 0x18
|
1362
|
+
#define XS1_MMAP_CTRL1_VIRT_ADDR_MASK \
|
1363
|
+
(((1 << XS1_MMAP_CTRL1_VIRT_ADDR_SIZE) - 1) << XS1_MMAP_CTRL1_VIRT_ADDR_SHIFT)
|
1364
|
+
#define XS1_MMAP_CTRL1_VIRT_ADDR(x) \
|
1365
|
+
(((x)&XS1_MMAP_CTRL1_VIRT_ADDR_MASK) >> XS1_MMAP_CTRL1_VIRT_ADDR_SHIFT)
|
1366
|
+
#define XS1_MMAP_CTRL1_VIRT_ADDR_SET(x, v) \
|
1367
|
+
(((x) & ~XS1_MMAP_CTRL1_VIRT_ADDR_MASK) | \
|
1368
|
+
(((v) << XS1_MMAP_CTRL1_VIRT_ADDR_SHIFT) & XS1_MMAP_CTRL1_VIRT_ADDR_MASK))
|
1369
|
+
#define XS1_CHANEND_CTRL0_INUSE_SHIFT 0x0
|
1370
|
+
#define XS1_CHANEND_CTRL0_INUSE_SIZE 0x1
|
1371
|
+
#define XS1_CHANEND_CTRL0_INUSE_MASK \
|
1372
|
+
(((1 << XS1_CHANEND_CTRL0_INUSE_SIZE) - 1) << XS1_CHANEND_CTRL0_INUSE_SHIFT)
|
1373
|
+
#define XS1_CHANEND_CTRL0_INUSE(x) \
|
1374
|
+
(((x)&XS1_CHANEND_CTRL0_INUSE_MASK) >> XS1_CHANEND_CTRL0_INUSE_SHIFT)
|
1375
|
+
#define XS1_CHANEND_CTRL0_INUSE_SET(x, v) \
|
1376
|
+
(((x) & ~XS1_CHANEND_CTRL0_INUSE_MASK) | \
|
1377
|
+
(((v) << XS1_CHANEND_CTRL0_INUSE_SHIFT) & XS1_CHANEND_CTRL0_INUSE_MASK))
|
1378
|
+
#define XS1_CHANEND_CTRL0_IE_MODE_SHIFT 0x1
|
1379
|
+
#define XS1_CHANEND_CTRL0_IE_MODE_SIZE 0x1
|
1380
|
+
#define XS1_CHANEND_CTRL0_IE_MODE_MASK \
|
1381
|
+
(((1 << XS1_CHANEND_CTRL0_IE_MODE_SIZE) - 1) \
|
1382
|
+
<< XS1_CHANEND_CTRL0_IE_MODE_SHIFT)
|
1383
|
+
#define XS1_CHANEND_CTRL0_IE_MODE(x) \
|
1384
|
+
(((x)&XS1_CHANEND_CTRL0_IE_MODE_MASK) >> XS1_CHANEND_CTRL0_IE_MODE_SHIFT)
|
1385
|
+
#define XS1_CHANEND_CTRL0_IE_MODE_SET(x, v) \
|
1386
|
+
(((x) & ~XS1_CHANEND_CTRL0_IE_MODE_MASK) | \
|
1387
|
+
(((v) << XS1_CHANEND_CTRL0_IE_MODE_SHIFT) & \
|
1388
|
+
XS1_CHANEND_CTRL0_IE_MODE_MASK))
|
1389
|
+
#define XS1_CHANEND_CTRL0_IE_ENABLED_SHIFT 0x2
|
1390
|
+
#define XS1_CHANEND_CTRL0_IE_ENABLED_SIZE 0x1
|
1391
|
+
#define XS1_CHANEND_CTRL0_IE_ENABLED_MASK \
|
1392
|
+
(((1 << XS1_CHANEND_CTRL0_IE_ENABLED_SIZE) - 1) \
|
1393
|
+
<< XS1_CHANEND_CTRL0_IE_ENABLED_SHIFT)
|
1394
|
+
#define XS1_CHANEND_CTRL0_IE_ENABLED(x) \
|
1395
|
+
(((x)&XS1_CHANEND_CTRL0_IE_ENABLED_MASK) >> \
|
1396
|
+
XS1_CHANEND_CTRL0_IE_ENABLED_SHIFT)
|
1397
|
+
#define XS1_CHANEND_CTRL0_IE_ENABLED_SET(x, v) \
|
1398
|
+
(((x) & ~XS1_CHANEND_CTRL0_IE_ENABLED_MASK) | \
|
1399
|
+
(((v) << XS1_CHANEND_CTRL0_IE_ENABLED_SHIFT) & \
|
1400
|
+
XS1_CHANEND_CTRL0_IE_ENABLED_MASK))
|
1401
|
+
#define XS1_CHANEND_CTRL0_IN_READY_SHIFT 0x4
|
1402
|
+
#define XS1_CHANEND_CTRL0_IN_READY_SIZE 0x1
|
1403
|
+
#define XS1_CHANEND_CTRL0_IN_READY_MASK \
|
1404
|
+
(((1 << XS1_CHANEND_CTRL0_IN_READY_SIZE) - 1) \
|
1405
|
+
<< XS1_CHANEND_CTRL0_IN_READY_SHIFT)
|
1406
|
+
#define XS1_CHANEND_CTRL0_IN_READY(x) \
|
1407
|
+
(((x)&XS1_CHANEND_CTRL0_IN_READY_MASK) >> XS1_CHANEND_CTRL0_IN_READY_SHIFT)
|
1408
|
+
#define XS1_CHANEND_CTRL0_IN_READY_SET(x, v) \
|
1409
|
+
(((x) & ~XS1_CHANEND_CTRL0_IN_READY_MASK) | \
|
1410
|
+
(((v) << XS1_CHANEND_CTRL0_IN_READY_SHIFT) & \
|
1411
|
+
XS1_CHANEND_CTRL0_IN_READY_MASK))
|
1412
|
+
#define XS1_CHANEND_CTRL0_IN_WAITING_SHIFT 0x5
|
1413
|
+
#define XS1_CHANEND_CTRL0_IN_WAITING_SIZE 0x1
|
1414
|
+
#define XS1_CHANEND_CTRL0_IN_WAITING_MASK \
|
1415
|
+
(((1 << XS1_CHANEND_CTRL0_IN_WAITING_SIZE) - 1) \
|
1416
|
+
<< XS1_CHANEND_CTRL0_IN_WAITING_SHIFT)
|
1417
|
+
#define XS1_CHANEND_CTRL0_IN_WAITING(x) \
|
1418
|
+
(((x)&XS1_CHANEND_CTRL0_IN_WAITING_MASK) >> \
|
1419
|
+
XS1_CHANEND_CTRL0_IN_WAITING_SHIFT)
|
1420
|
+
#define XS1_CHANEND_CTRL0_IN_WAITING_SET(x, v) \
|
1421
|
+
(((x) & ~XS1_CHANEND_CTRL0_IN_WAITING_MASK) | \
|
1422
|
+
(((v) << XS1_CHANEND_CTRL0_IN_WAITING_SHIFT) & \
|
1423
|
+
XS1_CHANEND_CTRL0_IN_WAITING_MASK))
|
1424
|
+
#define XS1_CHANEND_CTRL0_OUT_READY_SHIFT 0x6
|
1425
|
+
#define XS1_CHANEND_CTRL0_OUT_READY_SIZE 0x1
|
1426
|
+
#define XS1_CHANEND_CTRL0_OUT_READY_MASK \
|
1427
|
+
(((1 << XS1_CHANEND_CTRL0_OUT_READY_SIZE) - 1) \
|
1428
|
+
<< XS1_CHANEND_CTRL0_OUT_READY_SHIFT)
|
1429
|
+
#define XS1_CHANEND_CTRL0_OUT_READY(x) \
|
1430
|
+
(((x)&XS1_CHANEND_CTRL0_OUT_READY_MASK) >> XS1_CHANEND_CTRL0_OUT_READY_SHIFT)
|
1431
|
+
#define XS1_CHANEND_CTRL0_OUT_READY_SET(x, v) \
|
1432
|
+
(((x) & ~XS1_CHANEND_CTRL0_OUT_READY_MASK) | \
|
1433
|
+
(((v) << XS1_CHANEND_CTRL0_OUT_READY_SHIFT) & \
|
1434
|
+
XS1_CHANEND_CTRL0_OUT_READY_MASK))
|
1435
|
+
#define XS1_CHANEND_CTRL0_OUT_WAITING_SHIFT 0x7
|
1436
|
+
#define XS1_CHANEND_CTRL0_OUT_WAITING_SIZE 0x1
|
1437
|
+
#define XS1_CHANEND_CTRL0_OUT_WAITING_MASK \
|
1438
|
+
(((1 << XS1_CHANEND_CTRL0_OUT_WAITING_SIZE) - 1) \
|
1439
|
+
<< XS1_CHANEND_CTRL0_OUT_WAITING_SHIFT)
|
1440
|
+
#define XS1_CHANEND_CTRL0_OUT_WAITING(x) \
|
1441
|
+
(((x)&XS1_CHANEND_CTRL0_OUT_WAITING_MASK) >> \
|
1442
|
+
XS1_CHANEND_CTRL0_OUT_WAITING_SHIFT)
|
1443
|
+
#define XS1_CHANEND_CTRL0_OUT_WAITING_SET(x, v) \
|
1444
|
+
(((x) & ~XS1_CHANEND_CTRL0_OUT_WAITING_MASK) | \
|
1445
|
+
(((v) << XS1_CHANEND_CTRL0_OUT_WAITING_SHIFT) & \
|
1446
|
+
XS1_CHANEND_CTRL0_OUT_WAITING_MASK))
|
1447
|
+
#define XS1_CHANEND_CTRL0_EV_VALID_SHIFT 0x8
|
1448
|
+
#define XS1_CHANEND_CTRL0_EV_VALID_SIZE 0x1
|
1449
|
+
#define XS1_CHANEND_CTRL0_EV_VALID_MASK \
|
1450
|
+
(((1 << XS1_CHANEND_CTRL0_EV_VALID_SIZE) - 1) \
|
1451
|
+
<< XS1_CHANEND_CTRL0_EV_VALID_SHIFT)
|
1452
|
+
#define XS1_CHANEND_CTRL0_EV_VALID(x) \
|
1453
|
+
(((x)&XS1_CHANEND_CTRL0_EV_VALID_MASK) >> XS1_CHANEND_CTRL0_EV_VALID_SHIFT)
|
1454
|
+
#define XS1_CHANEND_CTRL0_EV_VALID_SET(x, v) \
|
1455
|
+
(((x) & ~XS1_CHANEND_CTRL0_EV_VALID_MASK) | \
|
1456
|
+
(((v) << XS1_CHANEND_CTRL0_EV_VALID_SHIFT) & \
|
1457
|
+
XS1_CHANEND_CTRL0_EV_VALID_MASK))
|
1458
|
+
#define XS1_CHANEND_CTRL0_IN_T_NUM_SHIFT 0x10
|
1459
|
+
#define XS1_CHANEND_CTRL0_IN_T_NUM_SIZE 0x8
|
1460
|
+
#define XS1_CHANEND_CTRL0_IN_T_NUM_MASK \
|
1461
|
+
(((1 << XS1_CHANEND_CTRL0_IN_T_NUM_SIZE) - 1) \
|
1462
|
+
<< XS1_CHANEND_CTRL0_IN_T_NUM_SHIFT)
|
1463
|
+
#define XS1_CHANEND_CTRL0_IN_T_NUM(x) \
|
1464
|
+
(((x)&XS1_CHANEND_CTRL0_IN_T_NUM_MASK) >> XS1_CHANEND_CTRL0_IN_T_NUM_SHIFT)
|
1465
|
+
#define XS1_CHANEND_CTRL0_IN_T_NUM_SET(x, v) \
|
1466
|
+
(((x) & ~XS1_CHANEND_CTRL0_IN_T_NUM_MASK) | \
|
1467
|
+
(((v) << XS1_CHANEND_CTRL0_IN_T_NUM_SHIFT) & \
|
1468
|
+
XS1_CHANEND_CTRL0_IN_T_NUM_MASK))
|
1469
|
+
#define XS1_CHANEND_CTRL0_OUT_T_NUM_SHIFT 0x18
|
1470
|
+
#define XS1_CHANEND_CTRL0_OUT_T_NUM_SIZE 0x8
|
1471
|
+
#define XS1_CHANEND_CTRL0_OUT_T_NUM_MASK \
|
1472
|
+
(((1 << XS1_CHANEND_CTRL0_OUT_T_NUM_SIZE) - 1) \
|
1473
|
+
<< XS1_CHANEND_CTRL0_OUT_T_NUM_SHIFT)
|
1474
|
+
#define XS1_CHANEND_CTRL0_OUT_T_NUM(x) \
|
1475
|
+
(((x)&XS1_CHANEND_CTRL0_OUT_T_NUM_MASK) >> XS1_CHANEND_CTRL0_OUT_T_NUM_SHIFT)
|
1476
|
+
#define XS1_CHANEND_CTRL0_OUT_T_NUM_SET(x, v) \
|
1477
|
+
(((x) & ~XS1_CHANEND_CTRL0_OUT_T_NUM_MASK) | \
|
1478
|
+
(((v) << XS1_CHANEND_CTRL0_OUT_T_NUM_SHIFT) & \
|
1479
|
+
XS1_CHANEND_CTRL0_OUT_T_NUM_MASK))
|
1480
|
+
#define XS1_CLKBLK_CTRL0_INUSE_SHIFT 0x0
|
1481
|
+
#define XS1_CLKBLK_CTRL0_INUSE_SIZE 0x1
|
1482
|
+
#define XS1_CLKBLK_CTRL0_INUSE_MASK \
|
1483
|
+
(((1 << XS1_CLKBLK_CTRL0_INUSE_SIZE) - 1) << XS1_CLKBLK_CTRL0_INUSE_SHIFT)
|
1484
|
+
#define XS1_CLKBLK_CTRL0_INUSE(x) \
|
1485
|
+
(((x)&XS1_CLKBLK_CTRL0_INUSE_MASK) >> XS1_CLKBLK_CTRL0_INUSE_SHIFT)
|
1486
|
+
#define XS1_CLKBLK_CTRL0_INUSE_SET(x, v) \
|
1487
|
+
(((x) & ~XS1_CLKBLK_CTRL0_INUSE_MASK) | \
|
1488
|
+
(((v) << XS1_CLKBLK_CTRL0_INUSE_SHIFT) & XS1_CLKBLK_CTRL0_INUSE_MASK))
|
1489
|
+
#define XS1_CLKBLK_CTRL0_STARTED_SHIFT 0x1
|
1490
|
+
#define XS1_CLKBLK_CTRL0_STARTED_SIZE 0x1
|
1491
|
+
#define XS1_CLKBLK_CTRL0_STARTED_MASK \
|
1492
|
+
(((1 << XS1_CLKBLK_CTRL0_STARTED_SIZE) - 1) << XS1_CLKBLK_CTRL0_STARTED_SHIFT)
|
1493
|
+
#define XS1_CLKBLK_CTRL0_STARTED(x) \
|
1494
|
+
(((x)&XS1_CLKBLK_CTRL0_STARTED_MASK) >> XS1_CLKBLK_CTRL0_STARTED_SHIFT)
|
1495
|
+
#define XS1_CLKBLK_CTRL0_STARTED_SET(x, v) \
|
1496
|
+
(((x) & ~XS1_CLKBLK_CTRL0_STARTED_MASK) | \
|
1497
|
+
(((v) << XS1_CLKBLK_CTRL0_STARTED_SHIFT) & XS1_CLKBLK_CTRL0_STARTED_MASK))
|
1498
|
+
#define XS1_CLKBLK_CTRL0_STOPPING_SHIFT 0x2
|
1499
|
+
#define XS1_CLKBLK_CTRL0_STOPPING_SIZE 0x1
|
1500
|
+
#define XS1_CLKBLK_CTRL0_STOPPING_MASK \
|
1501
|
+
(((1 << XS1_CLKBLK_CTRL0_STOPPING_SIZE) - 1) \
|
1502
|
+
<< XS1_CLKBLK_CTRL0_STOPPING_SHIFT)
|
1503
|
+
#define XS1_CLKBLK_CTRL0_STOPPING(x) \
|
1504
|
+
(((x)&XS1_CLKBLK_CTRL0_STOPPING_MASK) >> XS1_CLKBLK_CTRL0_STOPPING_SHIFT)
|
1505
|
+
#define XS1_CLKBLK_CTRL0_STOPPING_SET(x, v) \
|
1506
|
+
(((x) & ~XS1_CLKBLK_CTRL0_STOPPING_MASK) | \
|
1507
|
+
(((v) << XS1_CLKBLK_CTRL0_STOPPING_SHIFT) & \
|
1508
|
+
XS1_CLKBLK_CTRL0_STOPPING_MASK))
|
1509
|
+
#define XS1_CLKBLK_CTRL0_T_WAITING_SHIFT 0x17
|
1510
|
+
#define XS1_CLKBLK_CTRL0_T_WAITING_SIZE 0x1
|
1511
|
+
#define XS1_CLKBLK_CTRL0_T_WAITING_MASK \
|
1512
|
+
(((1 << XS1_CLKBLK_CTRL0_T_WAITING_SIZE) - 1) \
|
1513
|
+
<< XS1_CLKBLK_CTRL0_T_WAITING_SHIFT)
|
1514
|
+
#define XS1_CLKBLK_CTRL0_T_WAITING(x) \
|
1515
|
+
(((x)&XS1_CLKBLK_CTRL0_T_WAITING_MASK) >> XS1_CLKBLK_CTRL0_T_WAITING_SHIFT)
|
1516
|
+
#define XS1_CLKBLK_CTRL0_T_WAITING_SET(x, v) \
|
1517
|
+
(((x) & ~XS1_CLKBLK_CTRL0_T_WAITING_MASK) | \
|
1518
|
+
(((v) << XS1_CLKBLK_CTRL0_T_WAITING_SHIFT) & \
|
1519
|
+
XS1_CLKBLK_CTRL0_T_WAITING_MASK))
|
1520
|
+
#define XS1_CLKBLK_CTRL0_T_NUM_SHIFT 0x18
|
1521
|
+
#define XS1_CLKBLK_CTRL0_T_NUM_SIZE 0x8
|
1522
|
+
#define XS1_CLKBLK_CTRL0_T_NUM_MASK \
|
1523
|
+
(((1 << XS1_CLKBLK_CTRL0_T_NUM_SIZE) - 1) << XS1_CLKBLK_CTRL0_T_NUM_SHIFT)
|
1524
|
+
#define XS1_CLKBLK_CTRL0_T_NUM(x) \
|
1525
|
+
(((x)&XS1_CLKBLK_CTRL0_T_NUM_MASK) >> XS1_CLKBLK_CTRL0_T_NUM_SHIFT)
|
1526
|
+
#define XS1_CLKBLK_CTRL0_T_NUM_SET(x, v) \
|
1527
|
+
(((x) & ~XS1_CLKBLK_CTRL0_T_NUM_MASK) | \
|
1528
|
+
(((v) << XS1_CLKBLK_CTRL0_T_NUM_SHIFT) & XS1_CLKBLK_CTRL0_T_NUM_MASK))
|
1529
|
+
#define XS1_CLKBLK_CTRL1_FALL_DELAY_SHIFT 0x0
|
1530
|
+
#define XS1_CLKBLK_CTRL1_FALL_DELAY_SIZE 0x9
|
1531
|
+
#define XS1_CLKBLK_CTRL1_FALL_DELAY_MASK \
|
1532
|
+
(((1 << XS1_CLKBLK_CTRL1_FALL_DELAY_SIZE) - 1) \
|
1533
|
+
<< XS1_CLKBLK_CTRL1_FALL_DELAY_SHIFT)
|
1534
|
+
#define XS1_CLKBLK_CTRL1_FALL_DELAY(x) \
|
1535
|
+
(((x)&XS1_CLKBLK_CTRL1_FALL_DELAY_MASK) >> XS1_CLKBLK_CTRL1_FALL_DELAY_SHIFT)
|
1536
|
+
#define XS1_CLKBLK_CTRL1_FALL_DELAY_SET(x, v) \
|
1537
|
+
(((x) & ~XS1_CLKBLK_CTRL1_FALL_DELAY_MASK) | \
|
1538
|
+
(((v) << XS1_CLKBLK_CTRL1_FALL_DELAY_SHIFT) & \
|
1539
|
+
XS1_CLKBLK_CTRL1_FALL_DELAY_MASK))
|
1540
|
+
#define XS1_CLKBLK_CTRL1_RISE_DELAY_SHIFT 0x10
|
1541
|
+
#define XS1_CLKBLK_CTRL1_RISE_DELAY_SIZE 0x9
|
1542
|
+
#define XS1_CLKBLK_CTRL1_RISE_DELAY_MASK \
|
1543
|
+
(((1 << XS1_CLKBLK_CTRL1_RISE_DELAY_SIZE) - 1) \
|
1544
|
+
<< XS1_CLKBLK_CTRL1_RISE_DELAY_SHIFT)
|
1545
|
+
#define XS1_CLKBLK_CTRL1_RISE_DELAY(x) \
|
1546
|
+
(((x)&XS1_CLKBLK_CTRL1_RISE_DELAY_MASK) >> XS1_CLKBLK_CTRL1_RISE_DELAY_SHIFT)
|
1547
|
+
#define XS1_CLKBLK_CTRL1_RISE_DELAY_SET(x, v) \
|
1548
|
+
(((x) & ~XS1_CLKBLK_CTRL1_RISE_DELAY_MASK) | \
|
1549
|
+
(((v) << XS1_CLKBLK_CTRL1_RISE_DELAY_SHIFT) & \
|
1550
|
+
XS1_CLKBLK_CTRL1_RISE_DELAY_MASK))
|
1551
|
+
#define XS1_COPROC_CTRL0_INUSE_SHIFT 0x0
|
1552
|
+
#define XS1_COPROC_CTRL0_INUSE_SIZE 0x1
|
1553
|
+
#define XS1_COPROC_CTRL0_INUSE_MASK \
|
1554
|
+
(((1 << XS1_COPROC_CTRL0_INUSE_SIZE) - 1) << XS1_COPROC_CTRL0_INUSE_SHIFT)
|
1555
|
+
#define XS1_COPROC_CTRL0_INUSE(x) \
|
1556
|
+
(((x)&XS1_COPROC_CTRL0_INUSE_MASK) >> XS1_COPROC_CTRL0_INUSE_SHIFT)
|
1557
|
+
#define XS1_COPROC_CTRL0_INUSE_SET(x, v) \
|
1558
|
+
(((x) & ~XS1_COPROC_CTRL0_INUSE_MASK) | \
|
1559
|
+
(((v) << XS1_COPROC_CTRL0_INUSE_SHIFT) & XS1_COPROC_CTRL0_INUSE_MASK))
|
1560
|
+
#define XS1_COPROC_CTRL0_OWNT_V_SHIFT 0x1
|
1561
|
+
#define XS1_COPROC_CTRL0_OWNT_V_SIZE 0x1
|
1562
|
+
#define XS1_COPROC_CTRL0_OWNT_V_MASK \
|
1563
|
+
(((1 << XS1_COPROC_CTRL0_OWNT_V_SIZE) - 1) << XS1_COPROC_CTRL0_OWNT_V_SHIFT)
|
1564
|
+
#define XS1_COPROC_CTRL0_OWNT_V(x) \
|
1565
|
+
(((x)&XS1_COPROC_CTRL0_OWNT_V_MASK) >> XS1_COPROC_CTRL0_OWNT_V_SHIFT)
|
1566
|
+
#define XS1_COPROC_CTRL0_OWNT_V_SET(x, v) \
|
1567
|
+
(((x) & ~XS1_COPROC_CTRL0_OWNT_V_MASK) | \
|
1568
|
+
(((v) << XS1_COPROC_CTRL0_OWNT_V_SHIFT) & XS1_COPROC_CTRL0_OWNT_V_MASK))
|
1569
|
+
#define XS1_COPROC_CTRL0_OWNT_SHIFT 0x8
|
1570
|
+
#define XS1_COPROC_CTRL0_OWNT_SIZE 0x8
|
1571
|
+
#define XS1_COPROC_CTRL0_OWNT_MASK \
|
1572
|
+
(((1 << XS1_COPROC_CTRL0_OWNT_SIZE) - 1) << XS1_COPROC_CTRL0_OWNT_SHIFT)
|
1573
|
+
#define XS1_COPROC_CTRL0_OWNT(x) \
|
1574
|
+
(((x)&XS1_COPROC_CTRL0_OWNT_MASK) >> XS1_COPROC_CTRL0_OWNT_SHIFT)
|
1575
|
+
#define XS1_COPROC_CTRL0_OWNT_SET(x, v) \
|
1576
|
+
(((x) & ~XS1_COPROC_CTRL0_OWNT_MASK) | \
|
1577
|
+
(((v) << XS1_COPROC_CTRL0_OWNT_SHIFT) & XS1_COPROC_CTRL0_OWNT_MASK))
|
1578
|
+
#define XS1_COPROC_TBV0_WAITING_SHIFT 0x0
|
1579
|
+
#define XS1_COPROC_TBV0_WAITING_SIZE 0x8
|
1580
|
+
#define XS1_COPROC_TBV0_WAITING_MASK \
|
1581
|
+
(((1 << XS1_COPROC_TBV0_WAITING_SIZE) - 1) << XS1_COPROC_TBV0_WAITING_SHIFT)
|
1582
|
+
#define XS1_COPROC_TBV0_WAITING(x) \
|
1583
|
+
(((x)&XS1_COPROC_TBV0_WAITING_MASK) >> XS1_COPROC_TBV0_WAITING_SHIFT)
|
1584
|
+
#define XS1_COPROC_TBV0_WAITING_SET(x, v) \
|
1585
|
+
(((x) & ~XS1_COPROC_TBV0_WAITING_MASK) | \
|
1586
|
+
(((v) << XS1_COPROC_TBV0_WAITING_SHIFT) & XS1_COPROC_TBV0_WAITING_MASK))
|
1587
|
+
#define XS1_DBG_INT_REQ_DBG_SHIFT 0x0
|
1588
|
+
#define XS1_DBG_INT_REQ_DBG_SIZE 0x1
|
1589
|
+
#define XS1_DBG_INT_REQ_DBG_MASK \
|
1590
|
+
(((1 << XS1_DBG_INT_REQ_DBG_SIZE) - 1) << XS1_DBG_INT_REQ_DBG_SHIFT)
|
1591
|
+
#define XS1_DBG_INT_REQ_DBG(x) \
|
1592
|
+
(((x)&XS1_DBG_INT_REQ_DBG_MASK) >> XS1_DBG_INT_REQ_DBG_SHIFT)
|
1593
|
+
#define XS1_DBG_INT_REQ_DBG_SET(x, v) \
|
1594
|
+
(((x) & ~XS1_DBG_INT_REQ_DBG_MASK) | \
|
1595
|
+
(((v) << XS1_DBG_INT_REQ_DBG_SHIFT) & XS1_DBG_INT_REQ_DBG_MASK))
|
1596
|
+
#define XS1_DBG_INT_IN_DBG_SHIFT 0x1
|
1597
|
+
#define XS1_DBG_INT_IN_DBG_SIZE 0x1
|
1598
|
+
#define XS1_DBG_INT_IN_DBG_MASK \
|
1599
|
+
(((1 << XS1_DBG_INT_IN_DBG_SIZE) - 1) << XS1_DBG_INT_IN_DBG_SHIFT)
|
1600
|
+
#define XS1_DBG_INT_IN_DBG(x) \
|
1601
|
+
(((x)&XS1_DBG_INT_IN_DBG_MASK) >> XS1_DBG_INT_IN_DBG_SHIFT)
|
1602
|
+
#define XS1_DBG_INT_IN_DBG_SET(x, v) \
|
1603
|
+
(((x) & ~XS1_DBG_INT_IN_DBG_MASK) | \
|
1604
|
+
(((v) << XS1_DBG_INT_IN_DBG_SHIFT) & XS1_DBG_INT_IN_DBG_MASK))
|
1605
|
+
#define XS1_DBG_CTRL_PSWITCH_RO_SHIFT 0x1f
|
1606
|
+
#define XS1_DBG_CTRL_PSWITCH_RO_SIZE 0x1
|
1607
|
+
#define XS1_DBG_CTRL_PSWITCH_RO_MASK \
|
1608
|
+
(((1 << XS1_DBG_CTRL_PSWITCH_RO_SIZE) - 1) << XS1_DBG_CTRL_PSWITCH_RO_SHIFT)
|
1609
|
+
#define XS1_DBG_CTRL_PSWITCH_RO(x) \
|
1610
|
+
(((x)&XS1_DBG_CTRL_PSWITCH_RO_MASK) >> XS1_DBG_CTRL_PSWITCH_RO_SHIFT)
|
1611
|
+
#define XS1_DBG_CTRL_PSWITCH_RO_SET(x, v) \
|
1612
|
+
(((x) & ~XS1_DBG_CTRL_PSWITCH_RO_MASK) | \
|
1613
|
+
(((v) << XS1_DBG_CTRL_PSWITCH_RO_SHIFT) & XS1_DBG_CTRL_PSWITCH_RO_MASK))
|
1614
|
+
#define XS1_DEVICE_ID0_VERSION_SHIFT 0x0
|
1615
|
+
#define XS1_DEVICE_ID0_VERSION_SIZE 0x8
|
1616
|
+
#define XS1_DEVICE_ID0_VERSION_MASK \
|
1617
|
+
(((1 << XS1_DEVICE_ID0_VERSION_SIZE) - 1) << XS1_DEVICE_ID0_VERSION_SHIFT)
|
1618
|
+
#define XS1_DEVICE_ID0_VERSION(x) \
|
1619
|
+
(((x)&XS1_DEVICE_ID0_VERSION_MASK) >> XS1_DEVICE_ID0_VERSION_SHIFT)
|
1620
|
+
#define XS1_DEVICE_ID0_VERSION_SET(x, v) \
|
1621
|
+
(((x) & ~XS1_DEVICE_ID0_VERSION_MASK) | \
|
1622
|
+
(((v) << XS1_DEVICE_ID0_VERSION_SHIFT) & XS1_DEVICE_ID0_VERSION_MASK))
|
1623
|
+
#define XS1_DEVICE_ID0_REVISION_SHIFT 0x8
|
1624
|
+
#define XS1_DEVICE_ID0_REVISION_SIZE 0x8
|
1625
|
+
#define XS1_DEVICE_ID0_REVISION_MASK \
|
1626
|
+
(((1 << XS1_DEVICE_ID0_REVISION_SIZE) - 1) << XS1_DEVICE_ID0_REVISION_SHIFT)
|
1627
|
+
#define XS1_DEVICE_ID0_REVISION(x) \
|
1628
|
+
(((x)&XS1_DEVICE_ID0_REVISION_MASK) >> XS1_DEVICE_ID0_REVISION_SHIFT)
|
1629
|
+
#define XS1_DEVICE_ID0_REVISION_SET(x, v) \
|
1630
|
+
(((x) & ~XS1_DEVICE_ID0_REVISION_MASK) | \
|
1631
|
+
(((v) << XS1_DEVICE_ID0_REVISION_SHIFT) & XS1_DEVICE_ID0_REVISION_MASK))
|
1632
|
+
#define XS1_DEVICE_ID0_NODE_SHIFT 0x10
|
1633
|
+
#define XS1_DEVICE_ID0_NODE_SIZE 0x8
|
1634
|
+
#define XS1_DEVICE_ID0_NODE_MASK \
|
1635
|
+
(((1 << XS1_DEVICE_ID0_NODE_SIZE) - 1) << XS1_DEVICE_ID0_NODE_SHIFT)
|
1636
|
+
#define XS1_DEVICE_ID0_NODE(x) \
|
1637
|
+
(((x)&XS1_DEVICE_ID0_NODE_MASK) >> XS1_DEVICE_ID0_NODE_SHIFT)
|
1638
|
+
#define XS1_DEVICE_ID0_NODE_SET(x, v) \
|
1639
|
+
(((x) & ~XS1_DEVICE_ID0_NODE_MASK) | \
|
1640
|
+
(((v) << XS1_DEVICE_ID0_NODE_SHIFT) & XS1_DEVICE_ID0_NODE_MASK))
|
1641
|
+
#define XS1_DEVICE_ID0_PID_SHIFT 0x18
|
1642
|
+
#define XS1_DEVICE_ID0_PID_SIZE 0x8
|
1643
|
+
#define XS1_DEVICE_ID0_PID_MASK \
|
1644
|
+
(((1 << XS1_DEVICE_ID0_PID_SIZE) - 1) << XS1_DEVICE_ID0_PID_SHIFT)
|
1645
|
+
#define XS1_DEVICE_ID0_PID(x) \
|
1646
|
+
(((x)&XS1_DEVICE_ID0_PID_MASK) >> XS1_DEVICE_ID0_PID_SHIFT)
|
1647
|
+
#define XS1_DEVICE_ID0_PID_SET(x, v) \
|
1648
|
+
(((x) & ~XS1_DEVICE_ID0_PID_MASK) | \
|
1649
|
+
(((v) << XS1_DEVICE_ID0_PID_SHIFT) & XS1_DEVICE_ID0_PID_MASK))
|
1650
|
+
#define XS1_DEVICE_ID1_NUM_THREADS_SHIFT 0x0
|
1651
|
+
#define XS1_DEVICE_ID1_NUM_THREADS_SIZE 0x8
|
1652
|
+
#define XS1_DEVICE_ID1_NUM_THREADS_MASK \
|
1653
|
+
(((1 << XS1_DEVICE_ID1_NUM_THREADS_SIZE) - 1) \
|
1654
|
+
<< XS1_DEVICE_ID1_NUM_THREADS_SHIFT)
|
1655
|
+
#define XS1_DEVICE_ID1_NUM_THREADS(x) \
|
1656
|
+
(((x)&XS1_DEVICE_ID1_NUM_THREADS_MASK) >> XS1_DEVICE_ID1_NUM_THREADS_SHIFT)
|
1657
|
+
#define XS1_DEVICE_ID1_NUM_THREADS_SET(x, v) \
|
1658
|
+
(((x) & ~XS1_DEVICE_ID1_NUM_THREADS_MASK) | \
|
1659
|
+
(((v) << XS1_DEVICE_ID1_NUM_THREADS_SHIFT) & \
|
1660
|
+
XS1_DEVICE_ID1_NUM_THREADS_MASK))
|
1661
|
+
#define XS1_DEVICE_ID1_NUM_SYNCS_SHIFT 0x8
|
1662
|
+
#define XS1_DEVICE_ID1_NUM_SYNCS_SIZE 0x8
|
1663
|
+
#define XS1_DEVICE_ID1_NUM_SYNCS_MASK \
|
1664
|
+
(((1 << XS1_DEVICE_ID1_NUM_SYNCS_SIZE) - 1) << XS1_DEVICE_ID1_NUM_SYNCS_SHIFT)
|
1665
|
+
#define XS1_DEVICE_ID1_NUM_SYNCS(x) \
|
1666
|
+
(((x)&XS1_DEVICE_ID1_NUM_SYNCS_MASK) >> XS1_DEVICE_ID1_NUM_SYNCS_SHIFT)
|
1667
|
+
#define XS1_DEVICE_ID1_NUM_SYNCS_SET(x, v) \
|
1668
|
+
(((x) & ~XS1_DEVICE_ID1_NUM_SYNCS_MASK) | \
|
1669
|
+
(((v) << XS1_DEVICE_ID1_NUM_SYNCS_SHIFT) & XS1_DEVICE_ID1_NUM_SYNCS_MASK))
|
1670
|
+
#define XS1_DEVICE_ID1_NUM_LOCKS_SHIFT 0x10
|
1671
|
+
#define XS1_DEVICE_ID1_NUM_LOCKS_SIZE 0x8
|
1672
|
+
#define XS1_DEVICE_ID1_NUM_LOCKS_MASK \
|
1673
|
+
(((1 << XS1_DEVICE_ID1_NUM_LOCKS_SIZE) - 1) << XS1_DEVICE_ID1_NUM_LOCKS_SHIFT)
|
1674
|
+
#define XS1_DEVICE_ID1_NUM_LOCKS(x) \
|
1675
|
+
(((x)&XS1_DEVICE_ID1_NUM_LOCKS_MASK) >> XS1_DEVICE_ID1_NUM_LOCKS_SHIFT)
|
1676
|
+
#define XS1_DEVICE_ID1_NUM_LOCKS_SET(x, v) \
|
1677
|
+
(((x) & ~XS1_DEVICE_ID1_NUM_LOCKS_MASK) | \
|
1678
|
+
(((v) << XS1_DEVICE_ID1_NUM_LOCKS_SHIFT) & XS1_DEVICE_ID1_NUM_LOCKS_MASK))
|
1679
|
+
#define XS1_DEVICE_ID1_NUM_CHANENDS_SHIFT 0x18
|
1680
|
+
#define XS1_DEVICE_ID1_NUM_CHANENDS_SIZE 0x8
|
1681
|
+
#define XS1_DEVICE_ID1_NUM_CHANENDS_MASK \
|
1682
|
+
(((1 << XS1_DEVICE_ID1_NUM_CHANENDS_SIZE) - 1) \
|
1683
|
+
<< XS1_DEVICE_ID1_NUM_CHANENDS_SHIFT)
|
1684
|
+
#define XS1_DEVICE_ID1_NUM_CHANENDS(x) \
|
1685
|
+
(((x)&XS1_DEVICE_ID1_NUM_CHANENDS_MASK) >> XS1_DEVICE_ID1_NUM_CHANENDS_SHIFT)
|
1686
|
+
#define XS1_DEVICE_ID1_NUM_CHANENDS_SET(x, v) \
|
1687
|
+
(((x) & ~XS1_DEVICE_ID1_NUM_CHANENDS_MASK) | \
|
1688
|
+
(((v) << XS1_DEVICE_ID1_NUM_CHANENDS_SHIFT) & \
|
1689
|
+
XS1_DEVICE_ID1_NUM_CHANENDS_MASK))
|
1690
|
+
#define XS1_DEVICE_ID2_NUM_TIMERS_SHIFT 0x0
|
1691
|
+
#define XS1_DEVICE_ID2_NUM_TIMERS_SIZE 0x8
|
1692
|
+
#define XS1_DEVICE_ID2_NUM_TIMERS_MASK \
|
1693
|
+
(((1 << XS1_DEVICE_ID2_NUM_TIMERS_SIZE) - 1) \
|
1694
|
+
<< XS1_DEVICE_ID2_NUM_TIMERS_SHIFT)
|
1695
|
+
#define XS1_DEVICE_ID2_NUM_TIMERS(x) \
|
1696
|
+
(((x)&XS1_DEVICE_ID2_NUM_TIMERS_MASK) >> XS1_DEVICE_ID2_NUM_TIMERS_SHIFT)
|
1697
|
+
#define XS1_DEVICE_ID2_NUM_TIMERS_SET(x, v) \
|
1698
|
+
(((x) & ~XS1_DEVICE_ID2_NUM_TIMERS_MASK) | \
|
1699
|
+
(((v) << XS1_DEVICE_ID2_NUM_TIMERS_SHIFT) & \
|
1700
|
+
XS1_DEVICE_ID2_NUM_TIMERS_MASK))
|
1701
|
+
#define XS1_DEVICE_ID2_NUM_CLKBLKS_SHIFT 0x8
|
1702
|
+
#define XS1_DEVICE_ID2_NUM_CLKBLKS_SIZE 0x8
|
1703
|
+
#define XS1_DEVICE_ID2_NUM_CLKBLKS_MASK \
|
1704
|
+
(((1 << XS1_DEVICE_ID2_NUM_CLKBLKS_SIZE) - 1) \
|
1705
|
+
<< XS1_DEVICE_ID2_NUM_CLKBLKS_SHIFT)
|
1706
|
+
#define XS1_DEVICE_ID2_NUM_CLKBLKS(x) \
|
1707
|
+
(((x)&XS1_DEVICE_ID2_NUM_CLKBLKS_MASK) >> XS1_DEVICE_ID2_NUM_CLKBLKS_SHIFT)
|
1708
|
+
#define XS1_DEVICE_ID2_NUM_CLKBLKS_SET(x, v) \
|
1709
|
+
(((x) & ~XS1_DEVICE_ID2_NUM_CLKBLKS_MASK) | \
|
1710
|
+
(((v) << XS1_DEVICE_ID2_NUM_CLKBLKS_SHIFT) & \
|
1711
|
+
XS1_DEVICE_ID2_NUM_CLKBLKS_MASK))
|
1712
|
+
#define XS1_JUNK_SHIFT 0x2
|
1713
|
+
#define XS1_JUNK_SIZE 0x1
|
1714
|
+
#define XS1_JUNK_MASK (((1 << XS1_JUNK_SIZE) - 1) << XS1_JUNK_SHIFT)
|
1715
|
+
#define XS1_JUNK(x) (((x)&XS1_JUNK_MASK) >> XS1_JUNK_SHIFT)
|
1716
|
+
#define XS1_JUNK_SET(x, v) \
|
1717
|
+
(((x) & ~XS1_JUNK_MASK) | (((v) << XS1_JUNK_SHIFT) & XS1_JUNK_MASK))
|
1718
|
+
#define XS1_NETWORK_SHIFT 0x4
|
1719
|
+
#define XS1_NETWORK_SIZE 0x2
|
1720
|
+
#define XS1_NETWORK_MASK (((1 << XS1_NETWORK_SIZE) - 1) << XS1_NETWORK_SHIFT)
|
1721
|
+
#define XS1_NETWORK(x) (((x)&XS1_NETWORK_MASK) >> XS1_NETWORK_SHIFT)
|
1722
|
+
#define XS1_NETWORK_SET(x, v) \
|
1723
|
+
(((x) & ~XS1_NETWORK_MASK) | (((v) << XS1_NETWORK_SHIFT) & XS1_NETWORK_MASK))
|
1724
|
+
#define XS1_SRC_TARGET_ID_SHIFT 0x10
|
1725
|
+
#define XS1_SRC_TARGET_ID_SIZE 0x8
|
1726
|
+
#define XS1_SRC_TARGET_ID_MASK \
|
1727
|
+
(((1 << XS1_SRC_TARGET_ID_SIZE) - 1) << XS1_SRC_TARGET_ID_SHIFT)
|
1728
|
+
#define XS1_SRC_TARGET_ID(x) \
|
1729
|
+
(((x)&XS1_SRC_TARGET_ID_MASK) >> XS1_SRC_TARGET_ID_SHIFT)
|
1730
|
+
#define XS1_SRC_TARGET_ID_SET(x, v) \
|
1731
|
+
(((x) & ~XS1_SRC_TARGET_ID_MASK) | \
|
1732
|
+
(((v) << XS1_SRC_TARGET_ID_SHIFT) & XS1_SRC_TARGET_ID_MASK))
|
1733
|
+
#define XS1_SRC_TARGET_TYPE_SHIFT 0x18
|
1734
|
+
#define XS1_SRC_TARGET_TYPE_SIZE 0x2
|
1735
|
+
#define XS1_SRC_TARGET_TYPE_MASK \
|
1736
|
+
(((1 << XS1_SRC_TARGET_TYPE_SIZE) - 1) << XS1_SRC_TARGET_TYPE_SHIFT)
|
1737
|
+
#define XS1_SRC_TARGET_TYPE(x) \
|
1738
|
+
(((x)&XS1_SRC_TARGET_TYPE_MASK) >> XS1_SRC_TARGET_TYPE_SHIFT)
|
1739
|
+
#define XS1_SRC_TARGET_TYPE_SET(x, v) \
|
1740
|
+
(((x) & ~XS1_SRC_TARGET_TYPE_MASK) | \
|
1741
|
+
(((v) << XS1_SRC_TARGET_TYPE_SHIFT) & XS1_SRC_TARGET_TYPE_MASK))
|
1742
|
+
#define XS1_SS_DEVICE_ID0_VERSION_SHIFT 0x0
|
1743
|
+
#define XS1_SS_DEVICE_ID0_VERSION_SIZE 0x8
|
1744
|
+
#define XS1_SS_DEVICE_ID0_VERSION_MASK \
|
1745
|
+
(((1 << XS1_SS_DEVICE_ID0_VERSION_SIZE) - 1) \
|
1746
|
+
<< XS1_SS_DEVICE_ID0_VERSION_SHIFT)
|
1747
|
+
#define XS1_SS_DEVICE_ID0_VERSION(x) \
|
1748
|
+
(((x)&XS1_SS_DEVICE_ID0_VERSION_MASK) >> XS1_SS_DEVICE_ID0_VERSION_SHIFT)
|
1749
|
+
#define XS1_SS_DEVICE_ID0_VERSION_SET(x, v) \
|
1750
|
+
(((x) & ~XS1_SS_DEVICE_ID0_VERSION_MASK) | \
|
1751
|
+
(((v) << XS1_SS_DEVICE_ID0_VERSION_SHIFT) & \
|
1752
|
+
XS1_SS_DEVICE_ID0_VERSION_MASK))
|
1753
|
+
#define XS1_SS_DEVICE_ID0_REVISION_SHIFT 0x8
|
1754
|
+
#define XS1_SS_DEVICE_ID0_REVISION_SIZE 0x8
|
1755
|
+
#define XS1_SS_DEVICE_ID0_REVISION_MASK \
|
1756
|
+
(((1 << XS1_SS_DEVICE_ID0_REVISION_SIZE) - 1) \
|
1757
|
+
<< XS1_SS_DEVICE_ID0_REVISION_SHIFT)
|
1758
|
+
#define XS1_SS_DEVICE_ID0_REVISION(x) \
|
1759
|
+
(((x)&XS1_SS_DEVICE_ID0_REVISION_MASK) >> XS1_SS_DEVICE_ID0_REVISION_SHIFT)
|
1760
|
+
#define XS1_SS_DEVICE_ID0_REVISION_SET(x, v) \
|
1761
|
+
(((x) & ~XS1_SS_DEVICE_ID0_REVISION_MASK) | \
|
1762
|
+
(((v) << XS1_SS_DEVICE_ID0_REVISION_SHIFT) & \
|
1763
|
+
XS1_SS_DEVICE_ID0_REVISION_MASK))
|
1764
|
+
#define XS1_SS_DEVICE_ID0_BOOT_CTRL_SHIFT 0x10
|
1765
|
+
#define XS1_SS_DEVICE_ID0_BOOT_CTRL_SIZE 0x8
|
1766
|
+
#define XS1_SS_DEVICE_ID0_BOOT_CTRL_MASK \
|
1767
|
+
(((1 << XS1_SS_DEVICE_ID0_BOOT_CTRL_SIZE) - 1) \
|
1768
|
+
<< XS1_SS_DEVICE_ID0_BOOT_CTRL_SHIFT)
|
1769
|
+
#define XS1_SS_DEVICE_ID0_BOOT_CTRL(x) \
|
1770
|
+
(((x)&XS1_SS_DEVICE_ID0_BOOT_CTRL_MASK) >> XS1_SS_DEVICE_ID0_BOOT_CTRL_SHIFT)
|
1771
|
+
#define XS1_SS_DEVICE_ID0_BOOT_CTRL_SET(x, v) \
|
1772
|
+
(((x) & ~XS1_SS_DEVICE_ID0_BOOT_CTRL_MASK) | \
|
1773
|
+
(((v) << XS1_SS_DEVICE_ID0_BOOT_CTRL_SHIFT) & \
|
1774
|
+
XS1_SS_DEVICE_ID0_BOOT_CTRL_MASK))
|
1775
|
+
#define XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_SHIFT 0x0
|
1776
|
+
#define XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_SIZE 0x8
|
1777
|
+
#define XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_MASK \
|
1778
|
+
(((1 << XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_SIZE) - 1) \
|
1779
|
+
<< XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_SHIFT)
|
1780
|
+
#define XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC(x) \
|
1781
|
+
(((x)&XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_MASK) >> \
|
1782
|
+
XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_SHIFT)
|
1783
|
+
#define XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_SET(x, v) \
|
1784
|
+
(((x) & ~XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_MASK) | \
|
1785
|
+
(((v) << XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_SHIFT) & \
|
1786
|
+
XS1_SS_DEVICE_ID1_NUM_PLINKS_PER_PROC_MASK))
|
1787
|
+
#define XS1_SS_DEVICE_ID1_NUM_PROCESSORS_SHIFT 0x8
|
1788
|
+
#define XS1_SS_DEVICE_ID1_NUM_PROCESSORS_SIZE 0x8
|
1789
|
+
#define XS1_SS_DEVICE_ID1_NUM_PROCESSORS_MASK \
|
1790
|
+
(((1 << XS1_SS_DEVICE_ID1_NUM_PROCESSORS_SIZE) - 1) \
|
1791
|
+
<< XS1_SS_DEVICE_ID1_NUM_PROCESSORS_SHIFT)
|
1792
|
+
#define XS1_SS_DEVICE_ID1_NUM_PROCESSORS(x) \
|
1793
|
+
(((x)&XS1_SS_DEVICE_ID1_NUM_PROCESSORS_MASK) >> \
|
1794
|
+
XS1_SS_DEVICE_ID1_NUM_PROCESSORS_SHIFT)
|
1795
|
+
#define XS1_SS_DEVICE_ID1_NUM_PROCESSORS_SET(x, v) \
|
1796
|
+
(((x) & ~XS1_SS_DEVICE_ID1_NUM_PROCESSORS_MASK) | \
|
1797
|
+
(((v) << XS1_SS_DEVICE_ID1_NUM_PROCESSORS_SHIFT) & \
|
1798
|
+
XS1_SS_DEVICE_ID1_NUM_PROCESSORS_MASK))
|
1799
|
+
#define XS1_SS_DEVICE_ID1_NUM_SLINKS_SHIFT 0x10
|
1800
|
+
#define XS1_SS_DEVICE_ID1_NUM_SLINKS_SIZE 0x8
|
1801
|
+
#define XS1_SS_DEVICE_ID1_NUM_SLINKS_MASK \
|
1802
|
+
(((1 << XS1_SS_DEVICE_ID1_NUM_SLINKS_SIZE) - 1) \
|
1803
|
+
<< XS1_SS_DEVICE_ID1_NUM_SLINKS_SHIFT)
|
1804
|
+
#define XS1_SS_DEVICE_ID1_NUM_SLINKS(x) \
|
1805
|
+
(((x)&XS1_SS_DEVICE_ID1_NUM_SLINKS_MASK) >> \
|
1806
|
+
XS1_SS_DEVICE_ID1_NUM_SLINKS_SHIFT)
|
1807
|
+
#define XS1_SS_DEVICE_ID1_NUM_SLINKS_SET(x, v) \
|
1808
|
+
(((x) & ~XS1_SS_DEVICE_ID1_NUM_SLINKS_MASK) | \
|
1809
|
+
(((v) << XS1_SS_DEVICE_ID1_NUM_SLINKS_SHIFT) & \
|
1810
|
+
XS1_SS_DEVICE_ID1_NUM_SLINKS_MASK))
|
1811
|
+
#define XS1_SS_NODE_CONFIG_HEADERS_SHIFT 0x0
|
1812
|
+
#define XS1_SS_NODE_CONFIG_HEADERS_SIZE 0x1
|
1813
|
+
#define XS1_SS_NODE_CONFIG_HEADERS_MASK \
|
1814
|
+
(((1 << XS1_SS_NODE_CONFIG_HEADERS_SIZE) - 1) \
|
1815
|
+
<< XS1_SS_NODE_CONFIG_HEADERS_SHIFT)
|
1816
|
+
#define XS1_SS_NODE_CONFIG_HEADERS(x) \
|
1817
|
+
(((x)&XS1_SS_NODE_CONFIG_HEADERS_MASK) >> XS1_SS_NODE_CONFIG_HEADERS_SHIFT)
|
1818
|
+
#define XS1_SS_NODE_CONFIG_HEADERS_SET(x, v) \
|
1819
|
+
(((x) & ~XS1_SS_NODE_CONFIG_HEADERS_MASK) | \
|
1820
|
+
(((v) << XS1_SS_NODE_CONFIG_HEADERS_SHIFT) & \
|
1821
|
+
XS1_SS_NODE_CONFIG_HEADERS_MASK))
|
1822
|
+
#define XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_SHIFT 0x8
|
1823
|
+
#define XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_SIZE 0x1
|
1824
|
+
#define XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_MASK \
|
1825
|
+
(((1 << XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_SIZE) - 1) \
|
1826
|
+
<< XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_SHIFT)
|
1827
|
+
#define XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG(x) \
|
1828
|
+
(((x)&XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_MASK) >> \
|
1829
|
+
XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_SHIFT)
|
1830
|
+
#define XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_SET(x, v) \
|
1831
|
+
(((x) & ~XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_MASK) | \
|
1832
|
+
(((v) << XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_SHIFT) & \
|
1833
|
+
XS1_SS_NODE_CONFIG_DISABLE_PLL_CTL_REG_MASK))
|
1834
|
+
#define XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_SHIFT 0x1f
|
1835
|
+
#define XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_SIZE 0x1
|
1836
|
+
#define XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_MASK \
|
1837
|
+
(((1 << XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_SIZE) - 1) \
|
1838
|
+
<< XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_SHIFT)
|
1839
|
+
#define XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE(x) \
|
1840
|
+
(((x)&XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_MASK) >> \
|
1841
|
+
XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_SHIFT)
|
1842
|
+
#define XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_SET(x, v) \
|
1843
|
+
(((x) & ~XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_MASK) | \
|
1844
|
+
(((v) << XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_SHIFT) & \
|
1845
|
+
XS1_SS_NODE_CONFIG_DISABLE_SSCTL_UPDATE_MASK))
|
1846
|
+
#define XS1_SS_NODE_ID_ID_SHIFT 0x0
|
1847
|
+
#define XS1_SS_NODE_ID_ID_SIZE 0x10
|
1848
|
+
#define XS1_SS_NODE_ID_ID_MASK \
|
1849
|
+
(((1 << XS1_SS_NODE_ID_ID_SIZE) - 1) << XS1_SS_NODE_ID_ID_SHIFT)
|
1850
|
+
#define XS1_SS_NODE_ID_ID(x) \
|
1851
|
+
(((x)&XS1_SS_NODE_ID_ID_MASK) >> XS1_SS_NODE_ID_ID_SHIFT)
|
1852
|
+
#define XS1_SS_NODE_ID_ID_SET(x, v) \
|
1853
|
+
(((x) & ~XS1_SS_NODE_ID_ID_MASK) | \
|
1854
|
+
(((v) << XS1_SS_NODE_ID_ID_SHIFT) & XS1_SS_NODE_ID_ID_MASK))
|
1855
|
+
#define XS1_SS_PLL_CTL_INPUT_DIVISOR_SHIFT 0x0
|
1856
|
+
#define XS1_SS_PLL_CTL_INPUT_DIVISOR_SIZE 0x7
|
1857
|
+
#define XS1_SS_PLL_CTL_INPUT_DIVISOR_MASK \
|
1858
|
+
(((1 << XS1_SS_PLL_CTL_INPUT_DIVISOR_SIZE) - 1) \
|
1859
|
+
<< XS1_SS_PLL_CTL_INPUT_DIVISOR_SHIFT)
|
1860
|
+
#define XS1_SS_PLL_CTL_INPUT_DIVISOR(x) \
|
1861
|
+
(((x)&XS1_SS_PLL_CTL_INPUT_DIVISOR_MASK) >> \
|
1862
|
+
XS1_SS_PLL_CTL_INPUT_DIVISOR_SHIFT)
|
1863
|
+
#define XS1_SS_PLL_CTL_INPUT_DIVISOR_SET(x, v) \
|
1864
|
+
(((x) & ~XS1_SS_PLL_CTL_INPUT_DIVISOR_MASK) | \
|
1865
|
+
(((v) << XS1_SS_PLL_CTL_INPUT_DIVISOR_SHIFT) & \
|
1866
|
+
XS1_SS_PLL_CTL_INPUT_DIVISOR_MASK))
|
1867
|
+
#define XS1_SS_PLL_CTL_FEEDBACK_MUL_SHIFT 0x8
|
1868
|
+
#define XS1_SS_PLL_CTL_FEEDBACK_MUL_SIZE 0xd
|
1869
|
+
#define XS1_SS_PLL_CTL_FEEDBACK_MUL_MASK \
|
1870
|
+
(((1 << XS1_SS_PLL_CTL_FEEDBACK_MUL_SIZE) - 1) \
|
1871
|
+
<< XS1_SS_PLL_CTL_FEEDBACK_MUL_SHIFT)
|
1872
|
+
#define XS1_SS_PLL_CTL_FEEDBACK_MUL(x) \
|
1873
|
+
(((x)&XS1_SS_PLL_CTL_FEEDBACK_MUL_MASK) >> XS1_SS_PLL_CTL_FEEDBACK_MUL_SHIFT)
|
1874
|
+
#define XS1_SS_PLL_CTL_FEEDBACK_MUL_SET(x, v) \
|
1875
|
+
(((x) & ~XS1_SS_PLL_CTL_FEEDBACK_MUL_MASK) | \
|
1876
|
+
(((v) << XS1_SS_PLL_CTL_FEEDBACK_MUL_SHIFT) & \
|
1877
|
+
XS1_SS_PLL_CTL_FEEDBACK_MUL_MASK))
|
1878
|
+
#define XS1_SS_PLL_CTL_POST_DIVISOR_SHIFT 0x17
|
1879
|
+
#define XS1_SS_PLL_CTL_POST_DIVISOR_SIZE 0x3
|
1880
|
+
#define XS1_SS_PLL_CTL_POST_DIVISOR_MASK \
|
1881
|
+
(((1 << XS1_SS_PLL_CTL_POST_DIVISOR_SIZE) - 1) \
|
1882
|
+
<< XS1_SS_PLL_CTL_POST_DIVISOR_SHIFT)
|
1883
|
+
#define XS1_SS_PLL_CTL_POST_DIVISOR(x) \
|
1884
|
+
(((x)&XS1_SS_PLL_CTL_POST_DIVISOR_MASK) >> XS1_SS_PLL_CTL_POST_DIVISOR_SHIFT)
|
1885
|
+
#define XS1_SS_PLL_CTL_POST_DIVISOR_SET(x, v) \
|
1886
|
+
(((x) & ~XS1_SS_PLL_CTL_POST_DIVISOR_MASK) | \
|
1887
|
+
(((v) << XS1_SS_PLL_CTL_POST_DIVISOR_SHIFT) & \
|
1888
|
+
XS1_SS_PLL_CTL_POST_DIVISOR_MASK))
|
1889
|
+
#define XS1_SS_APP_PLL_ENABLE_SHIFT 0x1b
|
1890
|
+
#define XS1_SS_APP_PLL_ENABLE_SIZE 0x1
|
1891
|
+
#define XS1_SS_APP_PLL_ENABLE_MASK \
|
1892
|
+
(((1 << XS1_SS_APP_PLL_ENABLE_SIZE) - 1) << XS1_SS_APP_PLL_ENABLE_SHIFT)
|
1893
|
+
#define XS1_SS_APP_PLL_ENABLE(x) \
|
1894
|
+
(((x)&XS1_SS_APP_PLL_ENABLE_MASK) >> XS1_SS_APP_PLL_ENABLE_SHIFT)
|
1895
|
+
#define XS1_SS_APP_PLL_ENABLE_SET(x, v) \
|
1896
|
+
(((x) & ~XS1_SS_APP_PLL_ENABLE_MASK) | \
|
1897
|
+
(((v) << XS1_SS_APP_PLL_ENABLE_SHIFT) & XS1_SS_APP_PLL_ENABLE_MASK))
|
1898
|
+
#define XS1_SS_FRAC_N_PERIOD_CYC_CNT_SHIFT 0x0
|
1899
|
+
#define XS1_SS_FRAC_N_PERIOD_CYC_CNT_SIZE 0x8
|
1900
|
+
#define XS1_SS_FRAC_N_PERIOD_CYC_CNT_MASK \
|
1901
|
+
(((1 << XS1_SS_FRAC_N_PERIOD_CYC_CNT_SIZE) - 1) \
|
1902
|
+
<< XS1_SS_FRAC_N_PERIOD_CYC_CNT_SHIFT)
|
1903
|
+
#define XS1_SS_FRAC_N_PERIOD_CYC_CNT(x) \
|
1904
|
+
(((x)&XS1_SS_FRAC_N_PERIOD_CYC_CNT_MASK) >> \
|
1905
|
+
XS1_SS_FRAC_N_PERIOD_CYC_CNT_SHIFT)
|
1906
|
+
#define XS1_SS_FRAC_N_PERIOD_CYC_CNT_SET(x, v) \
|
1907
|
+
(((x) & ~XS1_SS_FRAC_N_PERIOD_CYC_CNT_MASK) | \
|
1908
|
+
(((v) << XS1_SS_FRAC_N_PERIOD_CYC_CNT_SHIFT) & \
|
1909
|
+
XS1_SS_FRAC_N_PERIOD_CYC_CNT_MASK))
|
1910
|
+
#define XS1_SS_FRAC_N_F_HIGH_CYC_CNT_SHIFT 0x8
|
1911
|
+
#define XS1_SS_FRAC_N_F_HIGH_CYC_CNT_SIZE 0x8
|
1912
|
+
#define XS1_SS_FRAC_N_F_HIGH_CYC_CNT_MASK \
|
1913
|
+
(((1 << XS1_SS_FRAC_N_F_HIGH_CYC_CNT_SIZE) - 1) \
|
1914
|
+
<< XS1_SS_FRAC_N_F_HIGH_CYC_CNT_SHIFT)
|
1915
|
+
#define XS1_SS_FRAC_N_F_HIGH_CYC_CNT(x) \
|
1916
|
+
(((x)&XS1_SS_FRAC_N_F_HIGH_CYC_CNT_MASK) >> \
|
1917
|
+
XS1_SS_FRAC_N_F_HIGH_CYC_CNT_SHIFT)
|
1918
|
+
#define XS1_SS_FRAC_N_F_HIGH_CYC_CNT_SET(x, v) \
|
1919
|
+
(((x) & ~XS1_SS_FRAC_N_F_HIGH_CYC_CNT_MASK) | \
|
1920
|
+
(((v) << XS1_SS_FRAC_N_F_HIGH_CYC_CNT_SHIFT) & \
|
1921
|
+
XS1_SS_FRAC_N_F_HIGH_CYC_CNT_MASK))
|
1922
|
+
#define XS1_SS_FRAC_N_ENABLE_SHIFT 0x1f
|
1923
|
+
#define XS1_SS_FRAC_N_ENABLE_SIZE 0x1
|
1924
|
+
#define XS1_SS_FRAC_N_ENABLE_MASK \
|
1925
|
+
(((1 << XS1_SS_FRAC_N_ENABLE_SIZE) - 1) << XS1_SS_FRAC_N_ENABLE_SHIFT)
|
1926
|
+
#define XS1_SS_FRAC_N_ENABLE(x) \
|
1927
|
+
(((x)&XS1_SS_FRAC_N_ENABLE_MASK) >> XS1_SS_FRAC_N_ENABLE_SHIFT)
|
1928
|
+
#define XS1_SS_FRAC_N_ENABLE_SET(x, v) \
|
1929
|
+
(((x) & ~XS1_SS_FRAC_N_ENABLE_MASK) | \
|
1930
|
+
(((v) << XS1_SS_FRAC_N_ENABLE_SHIFT) & XS1_SS_FRAC_N_ENABLE_MASK))
|
1931
|
+
#define XS1_SS_PLL_CTL_NLOCK_SHIFT 0x1e
|
1932
|
+
#define XS1_SS_PLL_CTL_NRESET_SHIFT 0x1f
|
1933
|
+
#define XS1_SS_CLK_DIVIDER_CLK_DIV_SHIFT 0x0
|
1934
|
+
#define XS1_SS_CLK_DIVIDER_CLK_DIV_SIZE 0x10
|
1935
|
+
#define XS1_SS_CLK_DIVIDER_CLK_DIV_MASK \
|
1936
|
+
(((1 << XS1_SS_CLK_DIVIDER_CLK_DIV_SIZE) - 1) \
|
1937
|
+
<< XS1_SS_CLK_DIVIDER_CLK_DIV_SHIFT)
|
1938
|
+
#define XS1_SS_CLK_DIVIDER_CLK_DIV(x) \
|
1939
|
+
(((x)&XS1_SS_CLK_DIVIDER_CLK_DIV_MASK) >> XS1_SS_CLK_DIVIDER_CLK_DIV_SHIFT)
|
1940
|
+
#define XS1_SS_CLK_DIVIDER_CLK_DIV_SET(x, v) \
|
1941
|
+
(((x) & ~XS1_SS_CLK_DIVIDER_CLK_DIV_MASK) | \
|
1942
|
+
(((v) << XS1_SS_CLK_DIVIDER_CLK_DIV_SHIFT) & \
|
1943
|
+
XS1_SS_CLK_DIVIDER_CLK_DIV_MASK))
|
1944
|
+
#define XS1_SS_SSWITCH_REF_CLK_DIV_SHIFT 0x0
|
1945
|
+
#define XS1_SS_SSWITCH_REF_CLK_DIV_SIZE 0x10
|
1946
|
+
#define XS1_SS_SSWITCH_REF_CLK_DIV_MASK \
|
1947
|
+
(((1 << XS1_SS_SSWITCH_REF_CLK_DIV_SIZE) - 1) \
|
1948
|
+
<< XS1_SS_SSWITCH_REF_CLK_DIV_SHIFT)
|
1949
|
+
#define XS1_SS_SSWITCH_REF_CLK_DIV(x) \
|
1950
|
+
(((x)&XS1_SS_SSWITCH_REF_CLK_DIV_MASK) >> XS1_SS_SSWITCH_REF_CLK_DIV_SHIFT)
|
1951
|
+
#define XS1_SS_SSWITCH_REF_CLK_DIV_SET(x, v) \
|
1952
|
+
(((x) & ~XS1_SS_SSWITCH_REF_CLK_DIV_MASK) | \
|
1953
|
+
(((v) << XS1_SS_SSWITCH_REF_CLK_DIV_SHIFT) & \
|
1954
|
+
XS1_SS_SSWITCH_REF_CLK_DIV_MASK))
|
1955
|
+
#define XS1_DIM0_DIR_SHIFT 0x0
|
1956
|
+
#define XS1_DIM0_DIR_SIZE 0x4
|
1957
|
+
#define XS1_DIM0_DIR_MASK (((1 << XS1_DIM0_DIR_SIZE) - 1) << XS1_DIM0_DIR_SHIFT)
|
1958
|
+
#define XS1_DIM0_DIR(x) (((x)&XS1_DIM0_DIR_MASK) >> XS1_DIM0_DIR_SHIFT)
|
1959
|
+
#define XS1_DIM0_DIR_SET(x, v) \
|
1960
|
+
(((x) & ~XS1_DIM0_DIR_MASK) | \
|
1961
|
+
(((v) << XS1_DIM0_DIR_SHIFT) & XS1_DIM0_DIR_MASK))
|
1962
|
+
#define XS1_DIM1_DIR_SHIFT 0x4
|
1963
|
+
#define XS1_DIM1_DIR_SIZE 0x4
|
1964
|
+
#define XS1_DIM1_DIR_MASK (((1 << XS1_DIM1_DIR_SIZE) - 1) << XS1_DIM1_DIR_SHIFT)
|
1965
|
+
#define XS1_DIM1_DIR(x) (((x)&XS1_DIM1_DIR_MASK) >> XS1_DIM1_DIR_SHIFT)
|
1966
|
+
#define XS1_DIM1_DIR_SET(x, v) \
|
1967
|
+
(((x) & ~XS1_DIM1_DIR_MASK) | \
|
1968
|
+
(((v) << XS1_DIM1_DIR_SHIFT) & XS1_DIM1_DIR_MASK))
|
1969
|
+
#define XS1_DIM2_DIR_SHIFT 0x8
|
1970
|
+
#define XS1_DIM2_DIR_SIZE 0x4
|
1971
|
+
#define XS1_DIM2_DIR_MASK (((1 << XS1_DIM2_DIR_SIZE) - 1) << XS1_DIM2_DIR_SHIFT)
|
1972
|
+
#define XS1_DIM2_DIR(x) (((x)&XS1_DIM2_DIR_MASK) >> XS1_DIM2_DIR_SHIFT)
|
1973
|
+
#define XS1_DIM2_DIR_SET(x, v) \
|
1974
|
+
(((x) & ~XS1_DIM2_DIR_MASK) | \
|
1975
|
+
(((v) << XS1_DIM2_DIR_SHIFT) & XS1_DIM2_DIR_MASK))
|
1976
|
+
#define XS1_DIM3_DIR_SHIFT 0xc
|
1977
|
+
#define XS1_DIM3_DIR_SIZE 0x4
|
1978
|
+
#define XS1_DIM3_DIR_MASK (((1 << XS1_DIM3_DIR_SIZE) - 1) << XS1_DIM3_DIR_SHIFT)
|
1979
|
+
#define XS1_DIM3_DIR(x) (((x)&XS1_DIM3_DIR_MASK) >> XS1_DIM3_DIR_SHIFT)
|
1980
|
+
#define XS1_DIM3_DIR_SET(x, v) \
|
1981
|
+
(((x) & ~XS1_DIM3_DIR_MASK) | \
|
1982
|
+
(((v) << XS1_DIM3_DIR_SHIFT) & XS1_DIM3_DIR_MASK))
|
1983
|
+
#define XS1_DIM4_DIR_SHIFT 0x10
|
1984
|
+
#define XS1_DIM4_DIR_SIZE 0x4
|
1985
|
+
#define XS1_DIM4_DIR_MASK (((1 << XS1_DIM4_DIR_SIZE) - 1) << XS1_DIM4_DIR_SHIFT)
|
1986
|
+
#define XS1_DIM4_DIR(x) (((x)&XS1_DIM4_DIR_MASK) >> XS1_DIM4_DIR_SHIFT)
|
1987
|
+
#define XS1_DIM4_DIR_SET(x, v) \
|
1988
|
+
(((x) & ~XS1_DIM4_DIR_MASK) | \
|
1989
|
+
(((v) << XS1_DIM4_DIR_SHIFT) & XS1_DIM4_DIR_MASK))
|
1990
|
+
#define XS1_DIM5_DIR_SHIFT 0x14
|
1991
|
+
#define XS1_DIM5_DIR_SIZE 0x4
|
1992
|
+
#define XS1_DIM5_DIR_MASK (((1 << XS1_DIM5_DIR_SIZE) - 1) << XS1_DIM5_DIR_SHIFT)
|
1993
|
+
#define XS1_DIM5_DIR(x) (((x)&XS1_DIM5_DIR_MASK) >> XS1_DIM5_DIR_SHIFT)
|
1994
|
+
#define XS1_DIM5_DIR_SET(x, v) \
|
1995
|
+
(((x) & ~XS1_DIM5_DIR_MASK) | \
|
1996
|
+
(((v) << XS1_DIM5_DIR_SHIFT) & XS1_DIM5_DIR_MASK))
|
1997
|
+
#define XS1_DIM6_DIR_SHIFT 0x18
|
1998
|
+
#define XS1_DIM6_DIR_SIZE 0x4
|
1999
|
+
#define XS1_DIM6_DIR_MASK (((1 << XS1_DIM6_DIR_SIZE) - 1) << XS1_DIM6_DIR_SHIFT)
|
2000
|
+
#define XS1_DIM6_DIR(x) (((x)&XS1_DIM6_DIR_MASK) >> XS1_DIM6_DIR_SHIFT)
|
2001
|
+
#define XS1_DIM6_DIR_SET(x, v) \
|
2002
|
+
(((x) & ~XS1_DIM6_DIR_MASK) | \
|
2003
|
+
(((v) << XS1_DIM6_DIR_SHIFT) & XS1_DIM6_DIR_MASK))
|
2004
|
+
#define XS1_DIM7_DIR_SHIFT 0x1c
|
2005
|
+
#define XS1_DIM7_DIR_SIZE 0x4
|
2006
|
+
#define XS1_DIM7_DIR_MASK (((1 << XS1_DIM7_DIR_SIZE) - 1) << XS1_DIM7_DIR_SHIFT)
|
2007
|
+
#define XS1_DIM7_DIR(x) (((x)&XS1_DIM7_DIR_MASK) >> XS1_DIM7_DIR_SHIFT)
|
2008
|
+
#define XS1_DIM7_DIR_SET(x, v) \
|
2009
|
+
(((x) & ~XS1_DIM7_DIR_MASK) | \
|
2010
|
+
(((v) << XS1_DIM7_DIR_SHIFT) & XS1_DIM7_DIR_MASK))
|
2011
|
+
#define XS1_DIM8_DIR_SHIFT 0x0
|
2012
|
+
#define XS1_DIM8_DIR_SIZE 0x4
|
2013
|
+
#define XS1_DIM8_DIR_MASK (((1 << XS1_DIM8_DIR_SIZE) - 1) << XS1_DIM8_DIR_SHIFT)
|
2014
|
+
#define XS1_DIM8_DIR(x) (((x)&XS1_DIM8_DIR_MASK) >> XS1_DIM8_DIR_SHIFT)
|
2015
|
+
#define XS1_DIM8_DIR_SET(x, v) \
|
2016
|
+
(((x) & ~XS1_DIM8_DIR_MASK) | \
|
2017
|
+
(((v) << XS1_DIM8_DIR_SHIFT) & XS1_DIM8_DIR_MASK))
|
2018
|
+
#define XS1_DIM9_DIR_SHIFT 0x4
|
2019
|
+
#define XS1_DIM9_DIR_SIZE 0x4
|
2020
|
+
#define XS1_DIM9_DIR_MASK (((1 << XS1_DIM9_DIR_SIZE) - 1) << XS1_DIM9_DIR_SHIFT)
|
2021
|
+
#define XS1_DIM9_DIR(x) (((x)&XS1_DIM9_DIR_MASK) >> XS1_DIM9_DIR_SHIFT)
|
2022
|
+
#define XS1_DIM9_DIR_SET(x, v) \
|
2023
|
+
(((x) & ~XS1_DIM9_DIR_MASK) | \
|
2024
|
+
(((v) << XS1_DIM9_DIR_SHIFT) & XS1_DIM9_DIR_MASK))
|
2025
|
+
#define XS1_DIMA_DIR_SHIFT 0x8
|
2026
|
+
#define XS1_DIMA_DIR_SIZE 0x4
|
2027
|
+
#define XS1_DIMA_DIR_MASK (((1 << XS1_DIMA_DIR_SIZE) - 1) << XS1_DIMA_DIR_SHIFT)
|
2028
|
+
#define XS1_DIMA_DIR(x) (((x)&XS1_DIMA_DIR_MASK) >> XS1_DIMA_DIR_SHIFT)
|
2029
|
+
#define XS1_DIMA_DIR_SET(x, v) \
|
2030
|
+
(((x) & ~XS1_DIMA_DIR_MASK) | \
|
2031
|
+
(((v) << XS1_DIMA_DIR_SHIFT) & XS1_DIMA_DIR_MASK))
|
2032
|
+
#define XS1_DIMB_DIR_SHIFT 0xc
|
2033
|
+
#define XS1_DIMB_DIR_SIZE 0x4
|
2034
|
+
#define XS1_DIMB_DIR_MASK (((1 << XS1_DIMB_DIR_SIZE) - 1) << XS1_DIMB_DIR_SHIFT)
|
2035
|
+
#define XS1_DIMB_DIR(x) (((x)&XS1_DIMB_DIR_MASK) >> XS1_DIMB_DIR_SHIFT)
|
2036
|
+
#define XS1_DIMB_DIR_SET(x, v) \
|
2037
|
+
(((x) & ~XS1_DIMB_DIR_MASK) | \
|
2038
|
+
(((v) << XS1_DIMB_DIR_SHIFT) & XS1_DIMB_DIR_MASK))
|
2039
|
+
#define XS1_DIMC_DIR_SHIFT 0x10
|
2040
|
+
#define XS1_DIMC_DIR_SIZE 0x4
|
2041
|
+
#define XS1_DIMC_DIR_MASK (((1 << XS1_DIMC_DIR_SIZE) - 1) << XS1_DIMC_DIR_SHIFT)
|
2042
|
+
#define XS1_DIMC_DIR(x) (((x)&XS1_DIMC_DIR_MASK) >> XS1_DIMC_DIR_SHIFT)
|
2043
|
+
#define XS1_DIMC_DIR_SET(x, v) \
|
2044
|
+
(((x) & ~XS1_DIMC_DIR_MASK) | \
|
2045
|
+
(((v) << XS1_DIMC_DIR_SHIFT) & XS1_DIMC_DIR_MASK))
|
2046
|
+
#define XS1_DIMD_DIR_SHIFT 0x14
|
2047
|
+
#define XS1_DIMD_DIR_SIZE 0x4
|
2048
|
+
#define XS1_DIMD_DIR_MASK (((1 << XS1_DIMD_DIR_SIZE) - 1) << XS1_DIMD_DIR_SHIFT)
|
2049
|
+
#define XS1_DIMD_DIR(x) (((x)&XS1_DIMD_DIR_MASK) >> XS1_DIMD_DIR_SHIFT)
|
2050
|
+
#define XS1_DIMD_DIR_SET(x, v) \
|
2051
|
+
(((x) & ~XS1_DIMD_DIR_MASK) | \
|
2052
|
+
(((v) << XS1_DIMD_DIR_SHIFT) & XS1_DIMD_DIR_MASK))
|
2053
|
+
#define XS1_DIME_DIR_SHIFT 0x18
|
2054
|
+
#define XS1_DIME_DIR_SIZE 0x4
|
2055
|
+
#define XS1_DIME_DIR_MASK (((1 << XS1_DIME_DIR_SIZE) - 1) << XS1_DIME_DIR_SHIFT)
|
2056
|
+
#define XS1_DIME_DIR(x) (((x)&XS1_DIME_DIR_MASK) >> XS1_DIME_DIR_SHIFT)
|
2057
|
+
#define XS1_DIME_DIR_SET(x, v) \
|
2058
|
+
(((x) & ~XS1_DIME_DIR_MASK) | \
|
2059
|
+
(((v) << XS1_DIME_DIR_SHIFT) & XS1_DIME_DIR_MASK))
|
2060
|
+
#define XS1_DIMF_DIR_SHIFT 0x1c
|
2061
|
+
#define XS1_DIMF_DIR_SIZE 0x4
|
2062
|
+
#define XS1_DIMF_DIR_MASK (((1 << XS1_DIMF_DIR_SIZE) - 1) << XS1_DIMF_DIR_SHIFT)
|
2063
|
+
#define XS1_DIMF_DIR(x) (((x)&XS1_DIMF_DIR_MASK) >> XS1_DIMF_DIR_SHIFT)
|
2064
|
+
#define XS1_DIMF_DIR_SET(x, v) \
|
2065
|
+
(((x) & ~XS1_DIMF_DIR_MASK) | \
|
2066
|
+
(((v) << XS1_DIMF_DIR_SHIFT) & XS1_DIMF_DIR_MASK))
|
2067
|
+
#define XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_SHIFT 0x0
|
2068
|
+
#define XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_SIZE 0x1
|
2069
|
+
#define XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_MASK \
|
2070
|
+
(((1 << XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_SIZE) - 1) \
|
2071
|
+
<< XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_SHIFT)
|
2072
|
+
#define XS1_GLOBAL_DEBUG_ENABLE_INDEBUG(x) \
|
2073
|
+
(((x)&XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_MASK) >> \
|
2074
|
+
XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_SHIFT)
|
2075
|
+
#define XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_SET(x, v) \
|
2076
|
+
(((x) & ~XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_MASK) | \
|
2077
|
+
(((v) << XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_SHIFT) & \
|
2078
|
+
XS1_GLOBAL_DEBUG_ENABLE_INDEBUG_MASK))
|
2079
|
+
#define XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_SHIFT 0x1
|
2080
|
+
#define XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_SIZE 0x1
|
2081
|
+
#define XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_MASK \
|
2082
|
+
(((1 << XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_SIZE) - 1) \
|
2083
|
+
<< XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_SHIFT)
|
2084
|
+
#define XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ(x) \
|
2085
|
+
(((x)&XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_MASK) >> \
|
2086
|
+
XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_SHIFT)
|
2087
|
+
#define XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_SET(x, v) \
|
2088
|
+
(((x) & ~XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_MASK) | \
|
2089
|
+
(((v) << XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_SHIFT) & \
|
2090
|
+
XS1_GLOBAL_DEBUG_ENABLE_GLOBAL_DEBUG_REQ_MASK))
|
2091
|
+
#define XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_SHIFT 0x0
|
2092
|
+
#define XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_SIZE 0x1
|
2093
|
+
#define XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_MASK \
|
2094
|
+
(((1 << XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_SIZE) - 1) \
|
2095
|
+
<< XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_SHIFT)
|
2096
|
+
#define XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG(x) \
|
2097
|
+
(((x)&XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_MASK) >> \
|
2098
|
+
XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_SHIFT)
|
2099
|
+
#define XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_SET(x, v) \
|
2100
|
+
(((x) & ~XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_MASK) | \
|
2101
|
+
(((v) << XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_SHIFT) & \
|
2102
|
+
XS1_GLOBAL_DEBUG_SOURCE_XCORE0_INDEBUG_MASK))
|
2103
|
+
#define XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_SHIFT 0x1
|
2104
|
+
#define XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_SIZE 0x1
|
2105
|
+
#define XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_MASK \
|
2106
|
+
(((1 << XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_SIZE) - 1) \
|
2107
|
+
<< XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_SHIFT)
|
2108
|
+
#define XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG(x) \
|
2109
|
+
(((x)&XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_MASK) >> \
|
2110
|
+
XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_SHIFT)
|
2111
|
+
#define XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_SET(x, v) \
|
2112
|
+
(((x) & ~XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_MASK) | \
|
2113
|
+
(((v) << XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_SHIFT) & \
|
2114
|
+
XS1_GLOBAL_DEBUG_SOURCE_XCORE1_INDEBUG_MASK))
|
2115
|
+
#define XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_SHIFT 0x4
|
2116
|
+
#define XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_SIZE 0x1
|
2117
|
+
#define XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_MASK \
|
2118
|
+
(((1 << XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_SIZE) - 1) \
|
2119
|
+
<< XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_SHIFT)
|
2120
|
+
#define XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG(x) \
|
2121
|
+
(((x)&XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_MASK) >> \
|
2122
|
+
XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_SHIFT)
|
2123
|
+
#define XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_SET(x, v) \
|
2124
|
+
(((x) & ~XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_MASK) | \
|
2125
|
+
(((v) << XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_SHIFT) & \
|
2126
|
+
XS1_GLOBAL_DEBUG_SOURCE_EXTERNAL_PAD_INDEBUG_MASK))
|
2127
|
+
#define XS1_LINK_SRC_INUSE_SHIFT 0x0
|
2128
|
+
#define XS1_LINK_SRC_INUSE_SIZE 0x1
|
2129
|
+
#define XS1_LINK_SRC_INUSE_MASK \
|
2130
|
+
(((1 << XS1_LINK_SRC_INUSE_SIZE) - 1) << XS1_LINK_SRC_INUSE_SHIFT)
|
2131
|
+
#define XS1_LINK_SRC_INUSE(x) \
|
2132
|
+
(((x)&XS1_LINK_SRC_INUSE_MASK) >> XS1_LINK_SRC_INUSE_SHIFT)
|
2133
|
+
#define XS1_LINK_SRC_INUSE_SET(x, v) \
|
2134
|
+
(((x) & ~XS1_LINK_SRC_INUSE_MASK) | \
|
2135
|
+
(((v) << XS1_LINK_SRC_INUSE_SHIFT) & XS1_LINK_SRC_INUSE_MASK))
|
2136
|
+
#define XS1_LINK_DST_INUSE_SHIFT 0x1
|
2137
|
+
#define XS1_LINK_DST_INUSE_SIZE 0x1
|
2138
|
+
#define XS1_LINK_DST_INUSE_MASK \
|
2139
|
+
(((1 << XS1_LINK_DST_INUSE_SIZE) - 1) << XS1_LINK_DST_INUSE_SHIFT)
|
2140
|
+
#define XS1_LINK_DST_INUSE(x) \
|
2141
|
+
(((x)&XS1_LINK_DST_INUSE_MASK) >> XS1_LINK_DST_INUSE_SHIFT)
|
2142
|
+
#define XS1_LINK_DST_INUSE_SET(x, v) \
|
2143
|
+
(((x) & ~XS1_LINK_DST_INUSE_MASK) | \
|
2144
|
+
(((v) << XS1_LINK_DST_INUSE_SHIFT) & XS1_LINK_DST_INUSE_MASK))
|
2145
|
+
#define XS1_LINK_JUNK_SHIFT 0x2
|
2146
|
+
#define XS1_LINK_JUNK_SIZE 0x1
|
2147
|
+
#define XS1_LINK_JUNK_MASK \
|
2148
|
+
(((1 << XS1_LINK_JUNK_SIZE) - 1) << XS1_LINK_JUNK_SHIFT)
|
2149
|
+
#define XS1_LINK_JUNK(x) (((x)&XS1_LINK_JUNK_MASK) >> XS1_LINK_JUNK_SHIFT)
|
2150
|
+
#define XS1_LINK_JUNK_SET(x, v) \
|
2151
|
+
(((x) & ~XS1_LINK_JUNK_MASK) | \
|
2152
|
+
(((v) << XS1_LINK_JUNK_SHIFT) & XS1_LINK_JUNK_MASK))
|
2153
|
+
#define XS1_LINK_NETWORK_SHIFT 0x4
|
2154
|
+
#define XS1_LINK_NETWORK_SIZE 0x2
|
2155
|
+
#define XS1_LINK_NETWORK_MASK \
|
2156
|
+
(((1 << XS1_LINK_NETWORK_SIZE) - 1) << XS1_LINK_NETWORK_SHIFT)
|
2157
|
+
#define XS1_LINK_NETWORK(x) \
|
2158
|
+
(((x)&XS1_LINK_NETWORK_MASK) >> XS1_LINK_NETWORK_SHIFT)
|
2159
|
+
#define XS1_LINK_NETWORK_SET(x, v) \
|
2160
|
+
(((x) & ~XS1_LINK_NETWORK_MASK) | \
|
2161
|
+
(((v) << XS1_LINK_NETWORK_SHIFT) & XS1_LINK_NETWORK_MASK))
|
2162
|
+
#define XS1_LINK_DIRECTION_SHIFT 0x8
|
2163
|
+
#define XS1_LINK_DIRECTION_SIZE 0x4
|
2164
|
+
#define XS1_LINK_DIRECTION_MASK \
|
2165
|
+
(((1 << XS1_LINK_DIRECTION_SIZE) - 1) << XS1_LINK_DIRECTION_SHIFT)
|
2166
|
+
#define XS1_LINK_DIRECTION(x) \
|
2167
|
+
(((x)&XS1_LINK_DIRECTION_MASK) >> XS1_LINK_DIRECTION_SHIFT)
|
2168
|
+
#define XS1_LINK_DIRECTION_SET(x, v) \
|
2169
|
+
(((x) & ~XS1_LINK_DIRECTION_MASK) | \
|
2170
|
+
(((v) << XS1_LINK_DIRECTION_SHIFT) & XS1_LINK_DIRECTION_MASK))
|
2171
|
+
#define XS1_XLINK_INTER_TOKEN_DELAY_SHIFT 0x0
|
2172
|
+
#define XS1_XLINK_INTER_TOKEN_DELAY_SIZE 0xb
|
2173
|
+
#define XS1_XLINK_INTER_TOKEN_DELAY_MASK \
|
2174
|
+
(((1 << XS1_XLINK_INTER_TOKEN_DELAY_SIZE) - 1) \
|
2175
|
+
<< XS1_XLINK_INTER_TOKEN_DELAY_SHIFT)
|
2176
|
+
#define XS1_XLINK_INTER_TOKEN_DELAY(x) \
|
2177
|
+
(((x)&XS1_XLINK_INTER_TOKEN_DELAY_MASK) >> XS1_XLINK_INTER_TOKEN_DELAY_SHIFT)
|
2178
|
+
#define XS1_XLINK_INTER_TOKEN_DELAY_SET(x, v) \
|
2179
|
+
(((x) & ~XS1_XLINK_INTER_TOKEN_DELAY_MASK) | \
|
2180
|
+
(((v) << XS1_XLINK_INTER_TOKEN_DELAY_SHIFT) & \
|
2181
|
+
XS1_XLINK_INTER_TOKEN_DELAY_MASK))
|
2182
|
+
#define XS1_XLINK_INTRA_TOKEN_DELAY_SHIFT 0xb
|
2183
|
+
#define XS1_XLINK_INTRA_TOKEN_DELAY_SIZE 0xb
|
2184
|
+
#define XS1_XLINK_INTRA_TOKEN_DELAY_MASK \
|
2185
|
+
(((1 << XS1_XLINK_INTRA_TOKEN_DELAY_SIZE) - 1) \
|
2186
|
+
<< XS1_XLINK_INTRA_TOKEN_DELAY_SHIFT)
|
2187
|
+
#define XS1_XLINK_INTRA_TOKEN_DELAY(x) \
|
2188
|
+
(((x)&XS1_XLINK_INTRA_TOKEN_DELAY_MASK) >> XS1_XLINK_INTRA_TOKEN_DELAY_SHIFT)
|
2189
|
+
#define XS1_XLINK_INTRA_TOKEN_DELAY_SET(x, v) \
|
2190
|
+
(((x) & ~XS1_XLINK_INTRA_TOKEN_DELAY_MASK) | \
|
2191
|
+
(((v) << XS1_XLINK_INTRA_TOKEN_DELAY_SHIFT) & \
|
2192
|
+
XS1_XLINK_INTRA_TOKEN_DELAY_MASK))
|
2193
|
+
#define XS1_XLINK_RX_RESET_SHIFT 0x17
|
2194
|
+
#define XS1_XLINK_RX_RESET_SIZE 0x1
|
2195
|
+
#define XS1_XLINK_RX_RESET_MASK \
|
2196
|
+
(((1 << XS1_XLINK_RX_RESET_SIZE) - 1) << XS1_XLINK_RX_RESET_SHIFT)
|
2197
|
+
#define XS1_XLINK_RX_RESET(x) \
|
2198
|
+
(((x)&XS1_XLINK_RX_RESET_MASK) >> XS1_XLINK_RX_RESET_SHIFT)
|
2199
|
+
#define XS1_XLINK_RX_RESET_SET(x, v) \
|
2200
|
+
(((x) & ~XS1_XLINK_RX_RESET_MASK) | \
|
2201
|
+
(((v) << XS1_XLINK_RX_RESET_SHIFT) & XS1_XLINK_RX_RESET_MASK))
|
2202
|
+
#define XS1_XLINK_HELLO_SHIFT 0x18
|
2203
|
+
#define XS1_XLINK_HELLO_SIZE 0x1
|
2204
|
+
#define XS1_XLINK_HELLO_MASK \
|
2205
|
+
(((1 << XS1_XLINK_HELLO_SIZE) - 1) << XS1_XLINK_HELLO_SHIFT)
|
2206
|
+
#define XS1_XLINK_HELLO(x) (((x)&XS1_XLINK_HELLO_MASK) >> XS1_XLINK_HELLO_SHIFT)
|
2207
|
+
#define XS1_XLINK_HELLO_SET(x, v) \
|
2208
|
+
(((x) & ~XS1_XLINK_HELLO_MASK) | \
|
2209
|
+
(((v) << XS1_XLINK_HELLO_SHIFT) & XS1_XLINK_HELLO_MASK))
|
2210
|
+
#define XS1_TX_CREDIT_SHIFT 0x19
|
2211
|
+
#define XS1_TX_CREDIT_SIZE 0x1
|
2212
|
+
#define XS1_TX_CREDIT_MASK \
|
2213
|
+
(((1 << XS1_TX_CREDIT_SIZE) - 1) << XS1_TX_CREDIT_SHIFT)
|
2214
|
+
#define XS1_TX_CREDIT(x) (((x)&XS1_TX_CREDIT_MASK) >> XS1_TX_CREDIT_SHIFT)
|
2215
|
+
#define XS1_TX_CREDIT_SET(x, v) \
|
2216
|
+
(((x) & ~XS1_TX_CREDIT_MASK) | \
|
2217
|
+
(((v) << XS1_TX_CREDIT_SHIFT) & XS1_TX_CREDIT_MASK))
|
2218
|
+
#define XS1_RX_CREDIT_SHIFT 0x1a
|
2219
|
+
#define XS1_RX_CREDIT_SIZE 0x1
|
2220
|
+
#define XS1_RX_CREDIT_MASK \
|
2221
|
+
(((1 << XS1_RX_CREDIT_SIZE) - 1) << XS1_RX_CREDIT_SHIFT)
|
2222
|
+
#define XS1_RX_CREDIT(x) (((x)&XS1_RX_CREDIT_MASK) >> XS1_RX_CREDIT_SHIFT)
|
2223
|
+
#define XS1_RX_CREDIT_SET(x, v) \
|
2224
|
+
(((x) & ~XS1_RX_CREDIT_MASK) | \
|
2225
|
+
(((v) << XS1_RX_CREDIT_SHIFT) & XS1_RX_CREDIT_MASK))
|
2226
|
+
#define XS1_XLINK_RX_ERROR_SHIFT 0x1b
|
2227
|
+
#define XS1_XLINK_RX_ERROR_SIZE 0x1
|
2228
|
+
#define XS1_XLINK_RX_ERROR_MASK \
|
2229
|
+
(((1 << XS1_XLINK_RX_ERROR_SIZE) - 1) << XS1_XLINK_RX_ERROR_SHIFT)
|
2230
|
+
#define XS1_XLINK_RX_ERROR(x) \
|
2231
|
+
(((x)&XS1_XLINK_RX_ERROR_MASK) >> XS1_XLINK_RX_ERROR_SHIFT)
|
2232
|
+
#define XS1_XLINK_RX_ERROR_SET(x, v) \
|
2233
|
+
(((x) & ~XS1_XLINK_RX_ERROR_MASK) | \
|
2234
|
+
(((v) << XS1_XLINK_RX_ERROR_SHIFT) & XS1_XLINK_RX_ERROR_MASK))
|
2235
|
+
#define XS1_XLINK_WIDE_SHIFT 0x1e
|
2236
|
+
#define XS1_XLINK_WIDE_SIZE 0x1
|
2237
|
+
#define XS1_XLINK_WIDE_MASK \
|
2238
|
+
(((1 << XS1_XLINK_WIDE_SIZE) - 1) << XS1_XLINK_WIDE_SHIFT)
|
2239
|
+
#define XS1_XLINK_WIDE(x) (((x)&XS1_XLINK_WIDE_MASK) >> XS1_XLINK_WIDE_SHIFT)
|
2240
|
+
#define XS1_XLINK_WIDE_SET(x, v) \
|
2241
|
+
(((x) & ~XS1_XLINK_WIDE_MASK) | \
|
2242
|
+
(((v) << XS1_XLINK_WIDE_SHIFT) & XS1_XLINK_WIDE_MASK))
|
2243
|
+
#define XS1_XLINK_ENABLE_SHIFT 0x1f
|
2244
|
+
#define XS1_XLINK_ENABLE_SIZE 0x1
|
2245
|
+
#define XS1_XLINK_ENABLE_MASK \
|
2246
|
+
(((1 << XS1_XLINK_ENABLE_SIZE) - 1) << XS1_XLINK_ENABLE_SHIFT)
|
2247
|
+
#define XS1_XLINK_ENABLE(x) \
|
2248
|
+
(((x)&XS1_XLINK_ENABLE_MASK) >> XS1_XLINK_ENABLE_SHIFT)
|
2249
|
+
#define XS1_XLINK_ENABLE_SET(x, v) \
|
2250
|
+
(((x) & ~XS1_XLINK_ENABLE_MASK) | \
|
2251
|
+
(((v) << XS1_XLINK_ENABLE_SHIFT) & XS1_XLINK_ENABLE_MASK))
|
2252
|
+
#define XS1_XSTATIC_DEST_CHAN_END_SHIFT 0x0
|
2253
|
+
#define XS1_XSTATIC_DEST_CHAN_END_SIZE 0x5
|
2254
|
+
#define XS1_XSTATIC_DEST_CHAN_END_MASK \
|
2255
|
+
(((1 << XS1_XSTATIC_DEST_CHAN_END_SIZE) - 1) \
|
2256
|
+
<< XS1_XSTATIC_DEST_CHAN_END_SHIFT)
|
2257
|
+
#define XS1_XSTATIC_DEST_CHAN_END(x) \
|
2258
|
+
(((x)&XS1_XSTATIC_DEST_CHAN_END_MASK) >> XS1_XSTATIC_DEST_CHAN_END_SHIFT)
|
2259
|
+
#define XS1_XSTATIC_DEST_CHAN_END_SET(x, v) \
|
2260
|
+
(((x) & ~XS1_XSTATIC_DEST_CHAN_END_MASK) | \
|
2261
|
+
(((v) << XS1_XSTATIC_DEST_CHAN_END_SHIFT) & \
|
2262
|
+
XS1_XSTATIC_DEST_CHAN_END_MASK))
|
2263
|
+
#define XS1_XSTATIC_ENABLE_SHIFT 0x1f
|
2264
|
+
#define XS1_XSTATIC_ENABLE_SIZE 0x1
|
2265
|
+
#define XS1_XSTATIC_ENABLE_MASK \
|
2266
|
+
(((1 << XS1_XSTATIC_ENABLE_SIZE) - 1) << XS1_XSTATIC_ENABLE_SHIFT)
|
2267
|
+
#define XS1_XSTATIC_ENABLE(x) \
|
2268
|
+
(((x)&XS1_XSTATIC_ENABLE_MASK) >> XS1_XSTATIC_ENABLE_SHIFT)
|
2269
|
+
#define XS1_XSTATIC_ENABLE_SET(x, v) \
|
2270
|
+
(((x) & ~XS1_XSTATIC_ENABLE_MASK) | \
|
2271
|
+
(((v) << XS1_XSTATIC_ENABLE_SHIFT) & XS1_XSTATIC_ENABLE_MASK))
|
2272
|
+
#define XS1_SSCTRL_PSCTRL_CORE_NUM_SHIFT 0x8
|
2273
|
+
#define XS1_SSCTRL_PSCTRL_CORE_NUM_SIZE 0x8
|
2274
|
+
#define XS1_SSCTRL_PSCTRL_CORE_NUM_MASK \
|
2275
|
+
(((1 << XS1_SSCTRL_PSCTRL_CORE_NUM_SIZE) - 1) \
|
2276
|
+
<< XS1_SSCTRL_PSCTRL_CORE_NUM_SHIFT)
|
2277
|
+
#define XS1_SSCTRL_PSCTRL_CORE_NUM(x) \
|
2278
|
+
(((x)&XS1_SSCTRL_PSCTRL_CORE_NUM_MASK) >> XS1_SSCTRL_PSCTRL_CORE_NUM_SHIFT)
|
2279
|
+
#define XS1_SSCTRL_PSCTRL_CORE_NUM_SET(x, v) \
|
2280
|
+
(((x) & ~XS1_SSCTRL_PSCTRL_CORE_NUM_MASK) | \
|
2281
|
+
(((v) << XS1_SSCTRL_PSCTRL_CORE_NUM_SHIFT) & \
|
2282
|
+
XS1_SSCTRL_PSCTRL_CORE_NUM_MASK))
|
2283
|
+
#define XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_SHIFT 0x0
|
2284
|
+
#define XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_SIZE 0x2
|
2285
|
+
#define XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_MASK \
|
2286
|
+
(((1 << XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_SIZE) - 1) \
|
2287
|
+
<< XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_SHIFT)
|
2288
|
+
#define XS1_USB_PHY_CFG0_UTMI_XCVRSELECT(x) \
|
2289
|
+
(((x)&XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_MASK) >> \
|
2290
|
+
XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_SHIFT)
|
2291
|
+
#define XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_SET(x, v) \
|
2292
|
+
(((x) & ~XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_MASK) | \
|
2293
|
+
(((v) << XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_SHIFT) & \
|
2294
|
+
XS1_USB_PHY_CFG0_UTMI_XCVRSELECT_MASK))
|
2295
|
+
#define XS1_USB_PHY_CFG0_UTMI_TERMSELECT_SHIFT 0x2
|
2296
|
+
#define XS1_USB_PHY_CFG0_UTMI_TERMSELECT_SIZE 0x1
|
2297
|
+
#define XS1_USB_PHY_CFG0_UTMI_TERMSELECT_MASK \
|
2298
|
+
(((1 << XS1_USB_PHY_CFG0_UTMI_TERMSELECT_SIZE) - 1) \
|
2299
|
+
<< XS1_USB_PHY_CFG0_UTMI_TERMSELECT_SHIFT)
|
2300
|
+
#define XS1_USB_PHY_CFG0_UTMI_TERMSELECT(x) \
|
2301
|
+
(((x)&XS1_USB_PHY_CFG0_UTMI_TERMSELECT_MASK) >> \
|
2302
|
+
XS1_USB_PHY_CFG0_UTMI_TERMSELECT_SHIFT)
|
2303
|
+
#define XS1_USB_PHY_CFG0_UTMI_TERMSELECT_SET(x, v) \
|
2304
|
+
(((x) & ~XS1_USB_PHY_CFG0_UTMI_TERMSELECT_MASK) | \
|
2305
|
+
(((v) << XS1_USB_PHY_CFG0_UTMI_TERMSELECT_SHIFT) & \
|
2306
|
+
XS1_USB_PHY_CFG0_UTMI_TERMSELECT_MASK))
|
2307
|
+
#define XS1_USB_PHY_CFG0_UTMI_OPMODE_SHIFT 0x3
|
2308
|
+
#define XS1_USB_PHY_CFG0_UTMI_OPMODE_SIZE 0x2
|
2309
|
+
#define XS1_USB_PHY_CFG0_UTMI_OPMODE_MASK \
|
2310
|
+
(((1 << XS1_USB_PHY_CFG0_UTMI_OPMODE_SIZE) - 1) \
|
2311
|
+
<< XS1_USB_PHY_CFG0_UTMI_OPMODE_SHIFT)
|
2312
|
+
#define XS1_USB_PHY_CFG0_UTMI_OPMODE(x) \
|
2313
|
+
(((x)&XS1_USB_PHY_CFG0_UTMI_OPMODE_MASK) >> \
|
2314
|
+
XS1_USB_PHY_CFG0_UTMI_OPMODE_SHIFT)
|
2315
|
+
#define XS1_USB_PHY_CFG0_UTMI_OPMODE_SET(x, v) \
|
2316
|
+
(((x) & ~XS1_USB_PHY_CFG0_UTMI_OPMODE_MASK) | \
|
2317
|
+
(((v) << XS1_USB_PHY_CFG0_UTMI_OPMODE_SHIFT) & \
|
2318
|
+
XS1_USB_PHY_CFG0_UTMI_OPMODE_MASK))
|
2319
|
+
#define XS1_USB_PHY_CFG0_UTMI_SUSPENDM_SHIFT 0x5
|
2320
|
+
#define XS1_USB_PHY_CFG0_UTMI_SUSPENDM_SIZE 0x1
|
2321
|
+
#define XS1_USB_PHY_CFG0_UTMI_SUSPENDM_MASK \
|
2322
|
+
(((1 << XS1_USB_PHY_CFG0_UTMI_SUSPENDM_SIZE) - 1) \
|
2323
|
+
<< XS1_USB_PHY_CFG0_UTMI_SUSPENDM_SHIFT)
|
2324
|
+
#define XS1_USB_PHY_CFG0_UTMI_SUSPENDM(x) \
|
2325
|
+
(((x)&XS1_USB_PHY_CFG0_UTMI_SUSPENDM_MASK) >> \
|
2326
|
+
XS1_USB_PHY_CFG0_UTMI_SUSPENDM_SHIFT)
|
2327
|
+
#define XS1_USB_PHY_CFG0_UTMI_SUSPENDM_SET(x, v) \
|
2328
|
+
(((x) & ~XS1_USB_PHY_CFG0_UTMI_SUSPENDM_MASK) | \
|
2329
|
+
(((v) << XS1_USB_PHY_CFG0_UTMI_SUSPENDM_SHIFT) & \
|
2330
|
+
XS1_USB_PHY_CFG0_UTMI_SUSPENDM_MASK))
|
2331
|
+
#define XS1_USB_PHY_CFG0_DPPULLDOWN_SHIFT 0x6
|
2332
|
+
#define XS1_USB_PHY_CFG0_DPPULLDOWN_SIZE 0x1
|
2333
|
+
#define XS1_USB_PHY_CFG0_DPPULLDOWN_MASK \
|
2334
|
+
(((1 << XS1_USB_PHY_CFG0_DPPULLDOWN_SIZE) - 1) \
|
2335
|
+
<< XS1_USB_PHY_CFG0_DPPULLDOWN_SHIFT)
|
2336
|
+
#define XS1_USB_PHY_CFG0_DPPULLDOWN(x) \
|
2337
|
+
(((x)&XS1_USB_PHY_CFG0_DPPULLDOWN_MASK) >> XS1_USB_PHY_CFG0_DPPULLDOWN_SHIFT)
|
2338
|
+
#define XS1_USB_PHY_CFG0_DPPULLDOWN_SET(x, v) \
|
2339
|
+
(((x) & ~XS1_USB_PHY_CFG0_DPPULLDOWN_MASK) | \
|
2340
|
+
(((v) << XS1_USB_PHY_CFG0_DPPULLDOWN_SHIFT) & \
|
2341
|
+
XS1_USB_PHY_CFG0_DPPULLDOWN_MASK))
|
2342
|
+
#define XS1_USB_PHY_CFG0_DMPULLDOWN_SHIFT 0x7
|
2343
|
+
#define XS1_USB_PHY_CFG0_DMPULLDOWN_SIZE 0x1
|
2344
|
+
#define XS1_USB_PHY_CFG0_DMPULLDOWN_MASK \
|
2345
|
+
(((1 << XS1_USB_PHY_CFG0_DMPULLDOWN_SIZE) - 1) \
|
2346
|
+
<< XS1_USB_PHY_CFG0_DMPULLDOWN_SHIFT)
|
2347
|
+
#define XS1_USB_PHY_CFG0_DMPULLDOWN(x) \
|
2348
|
+
(((x)&XS1_USB_PHY_CFG0_DMPULLDOWN_MASK) >> XS1_USB_PHY_CFG0_DMPULLDOWN_SHIFT)
|
2349
|
+
#define XS1_USB_PHY_CFG0_DMPULLDOWN_SET(x, v) \
|
2350
|
+
(((x) & ~XS1_USB_PHY_CFG0_DMPULLDOWN_MASK) | \
|
2351
|
+
(((v) << XS1_USB_PHY_CFG0_DMPULLDOWN_SHIFT) & \
|
2352
|
+
XS1_USB_PHY_CFG0_DMPULLDOWN_MASK))
|
2353
|
+
#define XS1_USB_PHY_CFG0_TXBITSTUFF_EN_SHIFT 0x8
|
2354
|
+
#define XS1_USB_PHY_CFG0_TXBITSTUFF_EN_SIZE 0x1
|
2355
|
+
#define XS1_USB_PHY_CFG0_TXBITSTUFF_EN_MASK \
|
2356
|
+
(((1 << XS1_USB_PHY_CFG0_TXBITSTUFF_EN_SIZE) - 1) \
|
2357
|
+
<< XS1_USB_PHY_CFG0_TXBITSTUFF_EN_SHIFT)
|
2358
|
+
#define XS1_USB_PHY_CFG0_TXBITSTUFF_EN(x) \
|
2359
|
+
(((x)&XS1_USB_PHY_CFG0_TXBITSTUFF_EN_MASK) >> \
|
2360
|
+
XS1_USB_PHY_CFG0_TXBITSTUFF_EN_SHIFT)
|
2361
|
+
#define XS1_USB_PHY_CFG0_TXBITSTUFF_EN_SET(x, v) \
|
2362
|
+
(((x) & ~XS1_USB_PHY_CFG0_TXBITSTUFF_EN_MASK) | \
|
2363
|
+
(((v) << XS1_USB_PHY_CFG0_TXBITSTUFF_EN_SHIFT) & \
|
2364
|
+
XS1_USB_PHY_CFG0_TXBITSTUFF_EN_MASK))
|
2365
|
+
#define XS1_USB_PHY_CFG0_PLL_EN_SHIFT 0x9
|
2366
|
+
#define XS1_USB_PHY_CFG0_PLL_EN_SIZE 0x1
|
2367
|
+
#define XS1_USB_PHY_CFG0_PLL_EN_MASK \
|
2368
|
+
(((1 << XS1_USB_PHY_CFG0_PLL_EN_SIZE) - 1) << XS1_USB_PHY_CFG0_PLL_EN_SHIFT)
|
2369
|
+
#define XS1_USB_PHY_CFG0_PLL_EN(x) \
|
2370
|
+
(((x)&XS1_USB_PHY_CFG0_PLL_EN_MASK) >> XS1_USB_PHY_CFG0_PLL_EN_SHIFT)
|
2371
|
+
#define XS1_USB_PHY_CFG0_PLL_EN_SET(x, v) \
|
2372
|
+
(((x) & ~XS1_USB_PHY_CFG0_PLL_EN_MASK) | \
|
2373
|
+
(((v) << XS1_USB_PHY_CFG0_PLL_EN_SHIFT) & XS1_USB_PHY_CFG0_PLL_EN_MASK))
|
2374
|
+
#define XS1_USB_PHY_CFG0_LPM_ALIVE_SHIFT 0xa
|
2375
|
+
#define XS1_USB_PHY_CFG0_LPM_ALIVE_SIZE 0x1
|
2376
|
+
#define XS1_USB_PHY_CFG0_LPM_ALIVE_MASK \
|
2377
|
+
(((1 << XS1_USB_PHY_CFG0_LPM_ALIVE_SIZE) - 1) \
|
2378
|
+
<< XS1_USB_PHY_CFG0_LPM_ALIVE_SHIFT)
|
2379
|
+
#define XS1_USB_PHY_CFG0_LPM_ALIVE(x) \
|
2380
|
+
(((x)&XS1_USB_PHY_CFG0_LPM_ALIVE_MASK) >> XS1_USB_PHY_CFG0_LPM_ALIVE_SHIFT)
|
2381
|
+
#define XS1_USB_PHY_CFG0_LPM_ALIVE_SET(x, v) \
|
2382
|
+
(((x) & ~XS1_USB_PHY_CFG0_LPM_ALIVE_MASK) | \
|
2383
|
+
(((v) << XS1_USB_PHY_CFG0_LPM_ALIVE_SHIFT) & \
|
2384
|
+
XS1_USB_PHY_CFG0_LPM_ALIVE_MASK))
|
2385
|
+
#define XS1_USB_PHY_CFG0_IDPAD_EN_SHIFT 0xb
|
2386
|
+
#define XS1_USB_PHY_CFG0_IDPAD_EN_SIZE 0x1
|
2387
|
+
#define XS1_USB_PHY_CFG0_IDPAD_EN_MASK \
|
2388
|
+
(((1 << XS1_USB_PHY_CFG0_IDPAD_EN_SIZE) - 1) \
|
2389
|
+
<< XS1_USB_PHY_CFG0_IDPAD_EN_SHIFT)
|
2390
|
+
#define XS1_USB_PHY_CFG0_IDPAD_EN(x) \
|
2391
|
+
(((x)&XS1_USB_PHY_CFG0_IDPAD_EN_MASK) >> XS1_USB_PHY_CFG0_IDPAD_EN_SHIFT)
|
2392
|
+
#define XS1_USB_PHY_CFG0_IDPAD_EN_SET(x, v) \
|
2393
|
+
(((x) & ~XS1_USB_PHY_CFG0_IDPAD_EN_MASK) | \
|
2394
|
+
(((v) << XS1_USB_PHY_CFG0_IDPAD_EN_SHIFT) & \
|
2395
|
+
XS1_USB_PHY_CFG0_IDPAD_EN_MASK))
|
2396
|
+
#define XS1_USB_PHY_CFG0_XTLSEL_SHIFT 0xc
|
2397
|
+
#define XS1_USB_PHY_CFG0_XTLSEL_SIZE 0x3
|
2398
|
+
#define XS1_USB_PHY_CFG0_XTLSEL_MASK \
|
2399
|
+
(((1 << XS1_USB_PHY_CFG0_XTLSEL_SIZE) - 1) << XS1_USB_PHY_CFG0_XTLSEL_SHIFT)
|
2400
|
+
#define XS1_USB_PHY_CFG0_XTLSEL(x) \
|
2401
|
+
(((x)&XS1_USB_PHY_CFG0_XTLSEL_MASK) >> XS1_USB_PHY_CFG0_XTLSEL_SHIFT)
|
2402
|
+
#define XS1_USB_PHY_CFG0_XTLSEL_SET(x, v) \
|
2403
|
+
(((x) & ~XS1_USB_PHY_CFG0_XTLSEL_MASK) | \
|
2404
|
+
(((v) << XS1_USB_PHY_CFG0_XTLSEL_SHIFT) & XS1_USB_PHY_CFG0_XTLSEL_MASK))
|
2405
|
+
#define XS1_USB_PHY_CFG2_PONRST_SHIFT 0x0
|
2406
|
+
#define XS1_USB_PHY_CFG2_PONRST_SIZE 0x1
|
2407
|
+
#define XS1_USB_PHY_CFG2_PONRST_MASK \
|
2408
|
+
(((1 << XS1_USB_PHY_CFG2_PONRST_SIZE) - 1) << XS1_USB_PHY_CFG2_PONRST_SHIFT)
|
2409
|
+
#define XS1_USB_PHY_CFG2_PONRST(x) \
|
2410
|
+
(((x)&XS1_USB_PHY_CFG2_PONRST_MASK) >> XS1_USB_PHY_CFG2_PONRST_SHIFT)
|
2411
|
+
#define XS1_USB_PHY_CFG2_PONRST_SET(x, v) \
|
2412
|
+
(((x) & ~XS1_USB_PHY_CFG2_PONRST_MASK) | \
|
2413
|
+
(((v) << XS1_USB_PHY_CFG2_PONRST_SHIFT) & XS1_USB_PHY_CFG2_PONRST_MASK))
|
2414
|
+
#define XS1_USB_PHY_CFG2_UTMI_RESET_SHIFT 0x1
|
2415
|
+
#define XS1_USB_PHY_CFG2_UTMI_RESET_SIZE 0x1
|
2416
|
+
#define XS1_USB_PHY_CFG2_UTMI_RESET_MASK \
|
2417
|
+
(((1 << XS1_USB_PHY_CFG2_UTMI_RESET_SIZE) - 1) \
|
2418
|
+
<< XS1_USB_PHY_CFG2_UTMI_RESET_SHIFT)
|
2419
|
+
#define XS1_USB_PHY_CFG2_UTMI_RESET(x) \
|
2420
|
+
(((x)&XS1_USB_PHY_CFG2_UTMI_RESET_MASK) >> XS1_USB_PHY_CFG2_UTMI_RESET_SHIFT)
|
2421
|
+
#define XS1_USB_PHY_CFG2_UTMI_RESET_SET(x, v) \
|
2422
|
+
(((x) & ~XS1_USB_PHY_CFG2_UTMI_RESET_MASK) | \
|
2423
|
+
(((v) << XS1_USB_PHY_CFG2_UTMI_RESET_SHIFT) & \
|
2424
|
+
XS1_USB_PHY_CFG2_UTMI_RESET_MASK))
|
2425
|
+
#define XS1_USB_PHY_CFG3_VCONTROL_SHIFT 0x0
|
2426
|
+
#define XS1_USB_PHY_CFG3_VCONTROL_SIZE 0x4
|
2427
|
+
#define XS1_USB_PHY_CFG3_VCONTROL_MASK \
|
2428
|
+
(((1 << XS1_USB_PHY_CFG3_VCONTROL_SIZE) - 1) \
|
2429
|
+
<< XS1_USB_PHY_CFG3_VCONTROL_SHIFT)
|
2430
|
+
#define XS1_USB_PHY_CFG3_VCONTROL(x) \
|
2431
|
+
(((x)&XS1_USB_PHY_CFG3_VCONTROL_MASK) >> XS1_USB_PHY_CFG3_VCONTROL_SHIFT)
|
2432
|
+
#define XS1_USB_PHY_CFG3_VCONTROL_SET(x, v) \
|
2433
|
+
(((x) & ~XS1_USB_PHY_CFG3_VCONTROL_MASK) | \
|
2434
|
+
(((v) << XS1_USB_PHY_CFG3_VCONTROL_SHIFT) & \
|
2435
|
+
XS1_USB_PHY_CFG3_VCONTROL_MASK))
|
2436
|
+
#define XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_SHIFT 0x4
|
2437
|
+
#define XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_SIZE 0x1
|
2438
|
+
#define XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_MASK \
|
2439
|
+
(((1 << XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_SIZE) - 1) \
|
2440
|
+
<< XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_SHIFT)
|
2441
|
+
#define XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE(x) \
|
2442
|
+
(((x)&XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_MASK) >> \
|
2443
|
+
XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_SHIFT)
|
2444
|
+
#define XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_SET(x, v) \
|
2445
|
+
(((x) & ~XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_MASK) | \
|
2446
|
+
(((v) << XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_SHIFT) & \
|
2447
|
+
XS1_USB_PHY_CFG3_EXTERNAL_TEST_MODE_MASK))
|
2448
|
+
#define XS1_USB_PHY_CFG3_LS_EN_SHIFT 0x5
|
2449
|
+
#define XS1_USB_PHY_CFG3_LS_EN_SIZE 0x1
|
2450
|
+
#define XS1_USB_PHY_CFG3_LS_EN_MASK \
|
2451
|
+
(((1 << XS1_USB_PHY_CFG3_LS_EN_SIZE) - 1) << XS1_USB_PHY_CFG3_LS_EN_SHIFT)
|
2452
|
+
#define XS1_USB_PHY_CFG3_LS_EN(x) \
|
2453
|
+
(((x)&XS1_USB_PHY_CFG3_LS_EN_MASK) >> XS1_USB_PHY_CFG3_LS_EN_SHIFT)
|
2454
|
+
#define XS1_USB_PHY_CFG3_LS_EN_SET(x, v) \
|
2455
|
+
(((x) & ~XS1_USB_PHY_CFG3_LS_EN_MASK) | \
|
2456
|
+
(((v) << XS1_USB_PHY_CFG3_LS_EN_SHIFT) & XS1_USB_PHY_CFG3_LS_EN_MASK))
|
2457
|
+
#define XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_SHIFT 0x6
|
2458
|
+
#define XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_SIZE 0x1
|
2459
|
+
#define XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_MASK \
|
2460
|
+
(((1 << XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_SIZE) - 1) \
|
2461
|
+
<< XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_SHIFT)
|
2462
|
+
#define XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM(x) \
|
2463
|
+
(((x)&XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_MASK) >> \
|
2464
|
+
XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_SHIFT)
|
2465
|
+
#define XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_SET(x, v) \
|
2466
|
+
(((x) & ~XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_MASK) | \
|
2467
|
+
(((v) << XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_SHIFT) & \
|
2468
|
+
XS1_USB_PHY_CFG3_UTMI_VCONTROLLOADM_MASK))
|
2469
|
+
#define XS1_USB_PHY_CFG3_HS_BIST_MODE_SHIFT 0x7
|
2470
|
+
#define XS1_USB_PHY_CFG3_HS_BIST_MODE_SIZE 0x1
|
2471
|
+
#define XS1_USB_PHY_CFG3_HS_BIST_MODE_MASK \
|
2472
|
+
(((1 << XS1_USB_PHY_CFG3_HS_BIST_MODE_SIZE) - 1) \
|
2473
|
+
<< XS1_USB_PHY_CFG3_HS_BIST_MODE_SHIFT)
|
2474
|
+
#define XS1_USB_PHY_CFG3_HS_BIST_MODE(x) \
|
2475
|
+
(((x)&XS1_USB_PHY_CFG3_HS_BIST_MODE_MASK) >> \
|
2476
|
+
XS1_USB_PHY_CFG3_HS_BIST_MODE_SHIFT)
|
2477
|
+
#define XS1_USB_PHY_CFG3_HS_BIST_MODE_SET(x, v) \
|
2478
|
+
(((x) & ~XS1_USB_PHY_CFG3_HS_BIST_MODE_MASK) | \
|
2479
|
+
(((v) << XS1_USB_PHY_CFG3_HS_BIST_MODE_SHIFT) & \
|
2480
|
+
XS1_USB_PHY_CFG3_HS_BIST_MODE_MASK))
|
2481
|
+
#define XS1_USB_SHIM_CFG_AND_RXV_RXA_SHIFT 0x0
|
2482
|
+
#define XS1_USB_SHIM_CFG_AND_RXV_RXA_SIZE 0x1
|
2483
|
+
#define XS1_USB_SHIM_CFG_AND_RXV_RXA_MASK \
|
2484
|
+
(((1 << XS1_USB_SHIM_CFG_AND_RXV_RXA_SIZE) - 1) \
|
2485
|
+
<< XS1_USB_SHIM_CFG_AND_RXV_RXA_SHIFT)
|
2486
|
+
#define XS1_USB_SHIM_CFG_AND_RXV_RXA(x) \
|
2487
|
+
(((x)&XS1_USB_SHIM_CFG_AND_RXV_RXA_MASK) >> \
|
2488
|
+
XS1_USB_SHIM_CFG_AND_RXV_RXA_SHIFT)
|
2489
|
+
#define XS1_USB_SHIM_CFG_AND_RXV_RXA_SET(x, v) \
|
2490
|
+
(((x) & ~XS1_USB_SHIM_CFG_AND_RXV_RXA_MASK) | \
|
2491
|
+
(((v) << XS1_USB_SHIM_CFG_AND_RXV_RXA_SHIFT) & \
|
2492
|
+
XS1_USB_SHIM_CFG_AND_RXV_RXA_MASK))
|
2493
|
+
#define XS1_USB_SHIM_CFG_FLAG_MODE_SHIFT 0x1
|
2494
|
+
#define XS1_USB_SHIM_CFG_FLAG_MODE_SIZE 0x1
|
2495
|
+
#define XS1_USB_SHIM_CFG_FLAG_MODE_MASK \
|
2496
|
+
(((1 << XS1_USB_SHIM_CFG_FLAG_MODE_SIZE) - 1) \
|
2497
|
+
<< XS1_USB_SHIM_CFG_FLAG_MODE_SHIFT)
|
2498
|
+
#define XS1_USB_SHIM_CFG_FLAG_MODE(x) \
|
2499
|
+
(((x)&XS1_USB_SHIM_CFG_FLAG_MODE_MASK) >> XS1_USB_SHIM_CFG_FLAG_MODE_SHIFT)
|
2500
|
+
#define XS1_USB_SHIM_CFG_FLAG_MODE_SET(x, v) \
|
2501
|
+
(((x) & ~XS1_USB_SHIM_CFG_FLAG_MODE_MASK) | \
|
2502
|
+
(((v) << XS1_USB_SHIM_CFG_FLAG_MODE_SHIFT) & \
|
2503
|
+
XS1_USB_SHIM_CFG_FLAG_MODE_MASK))
|
2504
|
+
#define XS1_WATCHDOG_COUNT_ENABLE_SHIFT 0x0
|
2505
|
+
#define XS1_WATCHDOG_COUNT_ENABLE_SIZE 0x1
|
2506
|
+
#define XS1_WATCHDOG_COUNT_ENABLE_MASK \
|
2507
|
+
(((1 << XS1_WATCHDOG_COUNT_ENABLE_SIZE) - 1) \
|
2508
|
+
<< XS1_WATCHDOG_COUNT_ENABLE_SHIFT)
|
2509
|
+
#define XS1_WATCHDOG_COUNT_ENABLE(x) \
|
2510
|
+
(((x)&XS1_WATCHDOG_COUNT_ENABLE_MASK) >> XS1_WATCHDOG_COUNT_ENABLE_SHIFT)
|
2511
|
+
#define XS1_WATCHDOG_COUNT_ENABLE_SET(x, v) \
|
2512
|
+
(((x) & ~XS1_WATCHDOG_COUNT_ENABLE_MASK) | \
|
2513
|
+
(((v) << XS1_WATCHDOG_COUNT_ENABLE_SHIFT) & \
|
2514
|
+
XS1_WATCHDOG_COUNT_ENABLE_MASK))
|
2515
|
+
#define XS1_WATCHDOG_TRIGGER_ENABLE_SHIFT 0x1
|
2516
|
+
#define XS1_WATCHDOG_TRIGGER_ENABLE_SIZE 0x1
|
2517
|
+
#define XS1_WATCHDOG_TRIGGER_ENABLE_MASK \
|
2518
|
+
(((1 << XS1_WATCHDOG_TRIGGER_ENABLE_SIZE) - 1) \
|
2519
|
+
<< XS1_WATCHDOG_TRIGGER_ENABLE_SHIFT)
|
2520
|
+
#define XS1_WATCHDOG_TRIGGER_ENABLE(x) \
|
2521
|
+
(((x)&XS1_WATCHDOG_TRIGGER_ENABLE_MASK) >> XS1_WATCHDOG_TRIGGER_ENABLE_SHIFT)
|
2522
|
+
#define XS1_WATCHDOG_TRIGGER_ENABLE_SET(x, v) \
|
2523
|
+
(((x) & ~XS1_WATCHDOG_TRIGGER_ENABLE_MASK) | \
|
2524
|
+
(((v) << XS1_WATCHDOG_TRIGGER_ENABLE_SHIFT) & \
|
2525
|
+
XS1_WATCHDOG_TRIGGER_ENABLE_MASK))
|
2526
|
+
#define XS1_WATCHDOG_PRESCALER_VALUE_SHIFT 0x0
|
2527
|
+
#define XS1_WATCHDOG_PRESCALER_VALUE_SIZE 0x10
|
2528
|
+
#define XS1_WATCHDOG_PRESCALER_VALUE_MASK \
|
2529
|
+
(((1 << XS1_WATCHDOG_PRESCALER_VALUE_SIZE) - 1) \
|
2530
|
+
<< XS1_WATCHDOG_PRESCALER_VALUE_SHIFT)
|
2531
|
+
#define XS1_WATCHDOG_PRESCALER_VALUE(x) \
|
2532
|
+
(((x)&XS1_WATCHDOG_PRESCALER_VALUE_MASK) >> \
|
2533
|
+
XS1_WATCHDOG_PRESCALER_VALUE_SHIFT)
|
2534
|
+
#define XS1_WATCHDOG_PRESCALER_VALUE_SET(x, v) \
|
2535
|
+
(((x) & ~XS1_WATCHDOG_PRESCALER_VALUE_MASK) | \
|
2536
|
+
(((v) << XS1_WATCHDOG_PRESCALER_VALUE_SHIFT) & \
|
2537
|
+
XS1_WATCHDOG_PRESCALER_VALUE_MASK))
|
2538
|
+
#define XS1_WATCHDOG_PRESCALER_WRAP_VALUE_SHIFT 0x0
|
2539
|
+
#define XS1_WATCHDOG_PRESCALER_WRAP_VALUE_SIZE 0x10
|
2540
|
+
#define XS1_WATCHDOG_PRESCALER_WRAP_VALUE_MASK \
|
2541
|
+
(((1 << XS1_WATCHDOG_PRESCALER_WRAP_VALUE_SIZE) - 1) \
|
2542
|
+
<< XS1_WATCHDOG_PRESCALER_WRAP_VALUE_SHIFT)
|
2543
|
+
#define XS1_WATCHDOG_PRESCALER_WRAP_VALUE(x) \
|
2544
|
+
(((x)&XS1_WATCHDOG_PRESCALER_WRAP_VALUE_MASK) >> \
|
2545
|
+
XS1_WATCHDOG_PRESCALER_WRAP_VALUE_SHIFT)
|
2546
|
+
#define XS1_WATCHDOG_PRESCALER_WRAP_VALUE_SET(x, v) \
|
2547
|
+
(((x) & ~XS1_WATCHDOG_PRESCALER_WRAP_VALUE_MASK) | \
|
2548
|
+
(((v) << XS1_WATCHDOG_PRESCALER_WRAP_VALUE_SHIFT) & \
|
2549
|
+
XS1_WATCHDOG_PRESCALER_WRAP_VALUE_MASK))
|
2550
|
+
#define XS1_WATCHDOG_COUNT_VALUE_SHIFT 0x0
|
2551
|
+
#define XS1_WATCHDOG_COUNT_VALUE_SIZE 0xc
|
2552
|
+
#define XS1_WATCHDOG_COUNT_VALUE_MASK \
|
2553
|
+
(((1 << XS1_WATCHDOG_COUNT_VALUE_SIZE) - 1) << XS1_WATCHDOG_COUNT_VALUE_SHIFT)
|
2554
|
+
#define XS1_WATCHDOG_COUNT_VALUE(x) \
|
2555
|
+
(((x)&XS1_WATCHDOG_COUNT_VALUE_MASK) >> XS1_WATCHDOG_COUNT_VALUE_SHIFT)
|
2556
|
+
#define XS1_WATCHDOG_COUNT_VALUE_SET(x, v) \
|
2557
|
+
(((x) & ~XS1_WATCHDOG_COUNT_VALUE_MASK) | \
|
2558
|
+
(((v) << XS1_WATCHDOG_COUNT_VALUE_SHIFT) & XS1_WATCHDOG_COUNT_VALUE_MASK))
|
2559
|
+
#define XS1_WATCHDOG_HAS_TRIGGERED_SHIFT 0x0
|
2560
|
+
#define XS1_WATCHDOG_HAS_TRIGGERED_SIZE 0x1
|
2561
|
+
#define XS1_WATCHDOG_HAS_TRIGGERED_MASK \
|
2562
|
+
(((1 << XS1_WATCHDOG_HAS_TRIGGERED_SIZE) - 1) \
|
2563
|
+
<< XS1_WATCHDOG_HAS_TRIGGERED_SHIFT)
|
2564
|
+
#define XS1_WATCHDOG_HAS_TRIGGERED(x) \
|
2565
|
+
(((x)&XS1_WATCHDOG_HAS_TRIGGERED_MASK) >> XS1_WATCHDOG_HAS_TRIGGERED_SHIFT)
|
2566
|
+
#define XS1_WATCHDOG_HAS_TRIGGERED_SET(x, v) \
|
2567
|
+
(((x) & ~XS1_WATCHDOG_HAS_TRIGGERED_MASK) | \
|
2568
|
+
(((v) << XS1_WATCHDOG_HAS_TRIGGERED_SHIFT) & \
|
2569
|
+
XS1_WATCHDOG_HAS_TRIGGERED_MASK))
|
2570
|
+
#define XS1_MIPI_STATUS0_OSC_CLK_ACT_SHIFT 0x0
|
2571
|
+
#define XS1_MIPI_STATUS0_OSC_CLK_ACT_SIZE 0x1
|
2572
|
+
#define XS1_MIPI_STATUS0_OSC_CLK_ACT_MASK \
|
2573
|
+
(((1 << XS1_MIPI_STATUS0_OSC_CLK_ACT_SIZE) - 1) \
|
2574
|
+
<< XS1_MIPI_STATUS0_OSC_CLK_ACT_SHIFT)
|
2575
|
+
#define XS1_MIPI_STATUS0_OSC_CLK_ACT(x) \
|
2576
|
+
(((x)&XS1_MIPI_STATUS0_OSC_CLK_ACT_MASK) >> \
|
2577
|
+
XS1_MIPI_STATUS0_OSC_CLK_ACT_SHIFT)
|
2578
|
+
#define XS1_MIPI_STATUS0_OSC_CLK_ACT_SET(x, v) \
|
2579
|
+
(((x) & ~XS1_MIPI_STATUS0_OSC_CLK_ACT_MASK) | \
|
2580
|
+
(((v) << XS1_MIPI_STATUS0_OSC_CLK_ACT_SHIFT) & \
|
2581
|
+
XS1_MIPI_STATUS0_OSC_CLK_ACT_MASK))
|
2582
|
+
#define XS1_MIPI_STATUS0_OSC_CLK_READY_SHIFT 0x1
|
2583
|
+
#define XS1_MIPI_STATUS0_OSC_CLK_READY_SIZE 0x1
|
2584
|
+
#define XS1_MIPI_STATUS0_OSC_CLK_READY_MASK \
|
2585
|
+
(((1 << XS1_MIPI_STATUS0_OSC_CLK_READY_SIZE) - 1) \
|
2586
|
+
<< XS1_MIPI_STATUS0_OSC_CLK_READY_SHIFT)
|
2587
|
+
#define XS1_MIPI_STATUS0_OSC_CLK_READY(x) \
|
2588
|
+
(((x)&XS1_MIPI_STATUS0_OSC_CLK_READY_MASK) >> \
|
2589
|
+
XS1_MIPI_STATUS0_OSC_CLK_READY_SHIFT)
|
2590
|
+
#define XS1_MIPI_STATUS0_OSC_CLK_READY_SET(x, v) \
|
2591
|
+
(((x) & ~XS1_MIPI_STATUS0_OSC_CLK_READY_MASK) | \
|
2592
|
+
(((v) << XS1_MIPI_STATUS0_OSC_CLK_READY_SHIFT) & \
|
2593
|
+
XS1_MIPI_STATUS0_OSC_CLK_READY_MASK))
|
2594
|
+
#define XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_SHIFT 0x2
|
2595
|
+
#define XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_SIZE 0x1
|
2596
|
+
#define XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_MASK \
|
2597
|
+
(((1 << XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_SIZE) - 1) \
|
2598
|
+
<< XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_SHIFT)
|
2599
|
+
#define XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G(x) \
|
2600
|
+
(((x)&XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_MASK) >> \
|
2601
|
+
XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_SHIFT)
|
2602
|
+
#define XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_SET(x, v) \
|
2603
|
+
(((x) & ~XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_MASK) | \
|
2604
|
+
(((v) << XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_SHIFT) & \
|
2605
|
+
XS1_MIPI_STATUS0_BIT_CLK_GREATER_THAN_2400G_MASK))
|
2606
|
+
#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_SHIFT 0x3
|
2607
|
+
#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_SIZE 0x1
|
2608
|
+
#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_MASK \
|
2609
|
+
(((1 << XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_SIZE) - 1) \
|
2610
|
+
<< XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_SHIFT)
|
2611
|
+
#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN0(x) \
|
2612
|
+
(((x)&XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_MASK) >> \
|
2613
|
+
XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_SHIFT)
|
2614
|
+
#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_SET(x, v) \
|
2615
|
+
(((x) & ~XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_MASK) | \
|
2616
|
+
(((v) << XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_SHIFT) & \
|
2617
|
+
XS1_MIPI_STATUS0_DATA_CORRECT_LAN0_MASK))
|
2618
|
+
#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_SHIFT 0x4
|
2619
|
+
#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_SIZE 0x1
|
2620
|
+
#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_MASK \
|
2621
|
+
(((1 << XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_SIZE) - 1) \
|
2622
|
+
<< XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_SHIFT)
|
2623
|
+
#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN1(x) \
|
2624
|
+
(((x)&XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_MASK) >> \
|
2625
|
+
XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_SHIFT)
|
2626
|
+
#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_SET(x, v) \
|
2627
|
+
(((x) & ~XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_MASK) | \
|
2628
|
+
(((v) << XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_SHIFT) & \
|
2629
|
+
XS1_MIPI_STATUS0_DATA_CORRECT_LAN1_MASK))
|
2630
|
+
#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_SHIFT 0x5
|
2631
|
+
#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_SIZE 0x1
|
2632
|
+
#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_MASK \
|
2633
|
+
(((1 << XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_SIZE) - 1) \
|
2634
|
+
<< XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_SHIFT)
|
2635
|
+
#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN2(x) \
|
2636
|
+
(((x)&XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_MASK) >> \
|
2637
|
+
XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_SHIFT)
|
2638
|
+
#define XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_SET(x, v) \
|
2639
|
+
(((x) & ~XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_MASK) | \
|
2640
|
+
(((v) << XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_SHIFT) & \
|
2641
|
+
XS1_MIPI_STATUS0_DATA_CORRECT_LAN2_MASK))
|
2642
|
+
#define XS1_MIPI_STATUS0_STOPSTATE_CLK_SHIFT 0xc
|
2643
|
+
#define XS1_MIPI_STATUS0_STOPSTATE_CLK_SIZE 0x1
|
2644
|
+
#define XS1_MIPI_STATUS0_STOPSTATE_CLK_MASK \
|
2645
|
+
(((1 << XS1_MIPI_STATUS0_STOPSTATE_CLK_SIZE) - 1) \
|
2646
|
+
<< XS1_MIPI_STATUS0_STOPSTATE_CLK_SHIFT)
|
2647
|
+
#define XS1_MIPI_STATUS0_STOPSTATE_CLK(x) \
|
2648
|
+
(((x)&XS1_MIPI_STATUS0_STOPSTATE_CLK_MASK) >> \
|
2649
|
+
XS1_MIPI_STATUS0_STOPSTATE_CLK_SHIFT)
|
2650
|
+
#define XS1_MIPI_STATUS0_STOPSTATE_CLK_SET(x, v) \
|
2651
|
+
(((x) & ~XS1_MIPI_STATUS0_STOPSTATE_CLK_MASK) | \
|
2652
|
+
(((v) << XS1_MIPI_STATUS0_STOPSTATE_CLK_SHIFT) & \
|
2653
|
+
XS1_MIPI_STATUS0_STOPSTATE_CLK_MASK))
|
2654
|
+
#define XS1_MIPI_STATUS0_STOPSTATE_LAN0_SHIFT 0xd
|
2655
|
+
#define XS1_MIPI_STATUS0_STOPSTATE_LAN0_SIZE 0x1
|
2656
|
+
#define XS1_MIPI_STATUS0_STOPSTATE_LAN0_MASK \
|
2657
|
+
(((1 << XS1_MIPI_STATUS0_STOPSTATE_LAN0_SIZE) - 1) \
|
2658
|
+
<< XS1_MIPI_STATUS0_STOPSTATE_LAN0_SHIFT)
|
2659
|
+
#define XS1_MIPI_STATUS0_STOPSTATE_LAN0(x) \
|
2660
|
+
(((x)&XS1_MIPI_STATUS0_STOPSTATE_LAN0_MASK) >> \
|
2661
|
+
XS1_MIPI_STATUS0_STOPSTATE_LAN0_SHIFT)
|
2662
|
+
#define XS1_MIPI_STATUS0_STOPSTATE_LAN0_SET(x, v) \
|
2663
|
+
(((x) & ~XS1_MIPI_STATUS0_STOPSTATE_LAN0_MASK) | \
|
2664
|
+
(((v) << XS1_MIPI_STATUS0_STOPSTATE_LAN0_SHIFT) & \
|
2665
|
+
XS1_MIPI_STATUS0_STOPSTATE_LAN0_MASK))
|
2666
|
+
#define XS1_MIPI_STATUS0_STOPSTATE_LAN1_SHIFT 0xe
|
2667
|
+
#define XS1_MIPI_STATUS0_STOPSTATE_LAN1_SIZE 0x1
|
2668
|
+
#define XS1_MIPI_STATUS0_STOPSTATE_LAN1_MASK \
|
2669
|
+
(((1 << XS1_MIPI_STATUS0_STOPSTATE_LAN1_SIZE) - 1) \
|
2670
|
+
<< XS1_MIPI_STATUS0_STOPSTATE_LAN1_SHIFT)
|
2671
|
+
#define XS1_MIPI_STATUS0_STOPSTATE_LAN1(x) \
|
2672
|
+
(((x)&XS1_MIPI_STATUS0_STOPSTATE_LAN1_MASK) >> \
|
2673
|
+
XS1_MIPI_STATUS0_STOPSTATE_LAN1_SHIFT)
|
2674
|
+
#define XS1_MIPI_STATUS0_STOPSTATE_LAN1_SET(x, v) \
|
2675
|
+
(((x) & ~XS1_MIPI_STATUS0_STOPSTATE_LAN1_MASK) | \
|
2676
|
+
(((v) << XS1_MIPI_STATUS0_STOPSTATE_LAN1_SHIFT) & \
|
2677
|
+
XS1_MIPI_STATUS0_STOPSTATE_LAN1_MASK))
|
2678
|
+
#define XS1_MIPI_SHIM_STATUS_REG_SHIFT 0x0
|
2679
|
+
#define XS1_MIPI_SHIM_STATUS_REG_SIZE 0x1
|
2680
|
+
#define XS1_MIPI_SHIM_STATUS_REG_MASK \
|
2681
|
+
(((1 << XS1_MIPI_SHIM_STATUS_REG_SIZE) - 1) << XS1_MIPI_SHIM_STATUS_REG_SHIFT)
|
2682
|
+
#define XS1_MIPI_SHIM_STATUS_REG(x) \
|
2683
|
+
(((x)&XS1_MIPI_SHIM_STATUS_REG_MASK) >> XS1_MIPI_SHIM_STATUS_REG_SHIFT)
|
2684
|
+
#define XS1_MIPI_SHIM_STATUS_REG_SET(x, v) \
|
2685
|
+
(((x) & ~XS1_MIPI_SHIM_STATUS_REG_MASK) | \
|
2686
|
+
(((v) << XS1_MIPI_SHIM_STATUS_REG_SHIFT) & XS1_MIPI_SHIM_STATUS_REG_MASK))
|
2687
|
+
#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_SHIFT 0x0
|
2688
|
+
#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_SIZE 0x1
|
2689
|
+
#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_MASK \
|
2690
|
+
(((1 << XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_SIZE) - 1) \
|
2691
|
+
<< XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_SHIFT)
|
2692
|
+
#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN(x) \
|
2693
|
+
(((x)&XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_MASK) >> \
|
2694
|
+
XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_SHIFT)
|
2695
|
+
#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_SET(x, v) \
|
2696
|
+
(((x) & ~XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_MASK) | \
|
2697
|
+
(((v) << XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_SHIFT) & \
|
2698
|
+
XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_EN_MASK))
|
2699
|
+
#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_SHIFT 0x8
|
2700
|
+
#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_SIZE 0x8
|
2701
|
+
#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_MASK \
|
2702
|
+
(((1 << XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_SIZE) - 1) \
|
2703
|
+
<< XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_SHIFT)
|
2704
|
+
#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE(x) \
|
2705
|
+
(((x)&XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_MASK) >> \
|
2706
|
+
XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_SHIFT)
|
2707
|
+
#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_SET(x, v) \
|
2708
|
+
(((x) & ~XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_MASK) | \
|
2709
|
+
(((v) << XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_SHIFT) & \
|
2710
|
+
XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_DATATYPE_MASK))
|
2711
|
+
#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_SHIFT 0x10
|
2712
|
+
#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_SIZE 0x6
|
2713
|
+
#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_MASK \
|
2714
|
+
(((1 << XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_SIZE) - 1) \
|
2715
|
+
<< XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_SHIFT)
|
2716
|
+
#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE(x) \
|
2717
|
+
(((x)&XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_MASK) >> \
|
2718
|
+
XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_SHIFT)
|
2719
|
+
#define XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_SET(x, v) \
|
2720
|
+
(((x) & ~XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_MASK) | \
|
2721
|
+
(((v) << XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_SHIFT) & \
|
2722
|
+
XS1_MIPI_SHIM_CFG0_PIXEL_DEMUX_MODE_MASK))
|
2723
|
+
#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_SHIFT 0x19
|
2724
|
+
#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_SIZE 0x1
|
2725
|
+
#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_MASK \
|
2726
|
+
(((1 << XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_SIZE) - 1) \
|
2727
|
+
<< XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_SHIFT)
|
2728
|
+
#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT(x) \
|
2729
|
+
(((x)&XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_MASK) >> \
|
2730
|
+
XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_SHIFT)
|
2731
|
+
#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_SET(x, v) \
|
2732
|
+
(((x) & ~XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_MASK) | \
|
2733
|
+
(((v) << XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_SHIFT) & \
|
2734
|
+
XS1_MIPI_SHIM_CFG0_SEL_DEBUG_OUT_MASK))
|
2735
|
+
#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG_SHIFT 0x1a
|
2736
|
+
#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG_SIZE 0x1
|
2737
|
+
#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG_MASK \
|
2738
|
+
(((1 << XS1_MIPI_SHIM_CFG0_SEL_DEBUG_SIZE) - 1) \
|
2739
|
+
<< XS1_MIPI_SHIM_CFG0_SEL_DEBUG_SHIFT)
|
2740
|
+
#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG(x) \
|
2741
|
+
(((x)&XS1_MIPI_SHIM_CFG0_SEL_DEBUG_MASK) >> \
|
2742
|
+
XS1_MIPI_SHIM_CFG0_SEL_DEBUG_SHIFT)
|
2743
|
+
#define XS1_MIPI_SHIM_CFG0_SEL_DEBUG_SET(x, v) \
|
2744
|
+
(((x) & ~XS1_MIPI_SHIM_CFG0_SEL_DEBUG_MASK) | \
|
2745
|
+
(((v) << XS1_MIPI_SHIM_CFG0_SEL_DEBUG_SHIFT) & \
|
2746
|
+
XS1_MIPI_SHIM_CFG0_SEL_DEBUG_MASK))
|
2747
|
+
#define XS1_LPDDR_PE_TREFI_CNT_SHIFT 0x0
|
2748
|
+
#define XS1_LPDDR_PE_TREFI_CNT_SIZE 0xb
|
2749
|
+
#define XS1_LPDDR_PE_TREFI_CNT_MASK \
|
2750
|
+
(((1 << XS1_LPDDR_PE_TREFI_CNT_SIZE) - 1) << XS1_LPDDR_PE_TREFI_CNT_SHIFT)
|
2751
|
+
#define XS1_LPDDR_PE_TREFI_CNT(x) \
|
2752
|
+
(((x)&XS1_LPDDR_PE_TREFI_CNT_MASK) >> XS1_LPDDR_PE_TREFI_CNT_SHIFT)
|
2753
|
+
#define XS1_LPDDR_PE_TREFI_CNT_SET(x, v) \
|
2754
|
+
(((x) & ~XS1_LPDDR_PE_TREFI_CNT_MASK) | \
|
2755
|
+
(((v) << XS1_LPDDR_PE_TREFI_CNT_SHIFT) & XS1_LPDDR_PE_TREFI_CNT_MASK))
|
2756
|
+
#define XS1_LPDDR_PE_TRAS_CNT_SHIFT 0xb
|
2757
|
+
#define XS1_LPDDR_PE_TRAS_CNT_SIZE 0x4
|
2758
|
+
#define XS1_LPDDR_PE_TRAS_CNT_MASK \
|
2759
|
+
(((1 << XS1_LPDDR_PE_TRAS_CNT_SIZE) - 1) << XS1_LPDDR_PE_TRAS_CNT_SHIFT)
|
2760
|
+
#define XS1_LPDDR_PE_TRAS_CNT(x) \
|
2761
|
+
(((x)&XS1_LPDDR_PE_TRAS_CNT_MASK) >> XS1_LPDDR_PE_TRAS_CNT_SHIFT)
|
2762
|
+
#define XS1_LPDDR_PE_TRAS_CNT_SET(x, v) \
|
2763
|
+
(((x) & ~XS1_LPDDR_PE_TRAS_CNT_MASK) | \
|
2764
|
+
(((v) << XS1_LPDDR_PE_TRAS_CNT_SHIFT) & XS1_LPDDR_PE_TRAS_CNT_MASK))
|
2765
|
+
#define XS1_LPDDR_PE_TXSR_CNT_SHIFT 0xf
|
2766
|
+
#define XS1_LPDDR_PE_TXSR_CNT_SIZE 0x6
|
2767
|
+
#define XS1_LPDDR_PE_TXSR_CNT_MASK \
|
2768
|
+
(((1 << XS1_LPDDR_PE_TXSR_CNT_SIZE) - 1) << XS1_LPDDR_PE_TXSR_CNT_SHIFT)
|
2769
|
+
#define XS1_LPDDR_PE_TXSR_CNT(x) \
|
2770
|
+
(((x)&XS1_LPDDR_PE_TXSR_CNT_MASK) >> XS1_LPDDR_PE_TXSR_CNT_SHIFT)
|
2771
|
+
#define XS1_LPDDR_PE_TXSR_CNT_SET(x, v) \
|
2772
|
+
(((x) & ~XS1_LPDDR_PE_TXSR_CNT_MASK) | \
|
2773
|
+
(((v) << XS1_LPDDR_PE_TXSR_CNT_SHIFT) & XS1_LPDDR_PE_TXSR_CNT_MASK))
|
2774
|
+
#define XS1_LPDDR_PE_TWR_CNT_SHIFT 0x15
|
2775
|
+
#define XS1_LPDDR_PE_TWR_CNT_SIZE 0x3
|
2776
|
+
#define XS1_LPDDR_PE_TWR_CNT_MASK \
|
2777
|
+
(((1 << XS1_LPDDR_PE_TWR_CNT_SIZE) - 1) << XS1_LPDDR_PE_TWR_CNT_SHIFT)
|
2778
|
+
#define XS1_LPDDR_PE_TWR_CNT(x) \
|
2779
|
+
(((x)&XS1_LPDDR_PE_TWR_CNT_MASK) >> XS1_LPDDR_PE_TWR_CNT_SHIFT)
|
2780
|
+
#define XS1_LPDDR_PE_TWR_CNT_SET(x, v) \
|
2781
|
+
(((x) & ~XS1_LPDDR_PE_TWR_CNT_MASK) | \
|
2782
|
+
(((v) << XS1_LPDDR_PE_TWR_CNT_SHIFT) & XS1_LPDDR_PE_TWR_CNT_MASK))
|
2783
|
+
#define XS1_LPDDR_PE_TRC_CNT_SHIFT 0x0
|
2784
|
+
#define XS1_LPDDR_PE_TRC_CNT_SIZE 0x4
|
2785
|
+
#define XS1_LPDDR_PE_TRC_CNT_MASK \
|
2786
|
+
(((1 << XS1_LPDDR_PE_TRC_CNT_SIZE) - 1) << XS1_LPDDR_PE_TRC_CNT_SHIFT)
|
2787
|
+
#define XS1_LPDDR_PE_TRC_CNT(x) \
|
2788
|
+
(((x)&XS1_LPDDR_PE_TRC_CNT_MASK) >> XS1_LPDDR_PE_TRC_CNT_SHIFT)
|
2789
|
+
#define XS1_LPDDR_PE_TRC_CNT_SET(x, v) \
|
2790
|
+
(((x) & ~XS1_LPDDR_PE_TRC_CNT_MASK) | \
|
2791
|
+
(((v) << XS1_LPDDR_PE_TRC_CNT_SHIFT) & XS1_LPDDR_PE_TRC_CNT_MASK))
|
2792
|
+
#define XS1_LPDDR_PE_TRCD_CNT_SHIFT 0x4
|
2793
|
+
#define XS1_LPDDR_PE_TRCD_CNT_SIZE 0x3
|
2794
|
+
#define XS1_LPDDR_PE_TRCD_CNT_MASK \
|
2795
|
+
(((1 << XS1_LPDDR_PE_TRCD_CNT_SIZE) - 1) << XS1_LPDDR_PE_TRCD_CNT_SHIFT)
|
2796
|
+
#define XS1_LPDDR_PE_TRCD_CNT(x) \
|
2797
|
+
(((x)&XS1_LPDDR_PE_TRCD_CNT_MASK) >> XS1_LPDDR_PE_TRCD_CNT_SHIFT)
|
2798
|
+
#define XS1_LPDDR_PE_TRCD_CNT_SET(x, v) \
|
2799
|
+
(((x) & ~XS1_LPDDR_PE_TRCD_CNT_MASK) | \
|
2800
|
+
(((v) << XS1_LPDDR_PE_TRCD_CNT_SHIFT) & XS1_LPDDR_PE_TRCD_CNT_MASK))
|
2801
|
+
#define XS1_LPDDR_PE_TRP_CNT_SHIFT 0x7
|
2802
|
+
#define XS1_LPDDR_PE_TRP_CNT_SIZE 0x3
|
2803
|
+
#define XS1_LPDDR_PE_TRP_CNT_MASK \
|
2804
|
+
(((1 << XS1_LPDDR_PE_TRP_CNT_SIZE) - 1) << XS1_LPDDR_PE_TRP_CNT_SHIFT)
|
2805
|
+
#define XS1_LPDDR_PE_TRP_CNT(x) \
|
2806
|
+
(((x)&XS1_LPDDR_PE_TRP_CNT_MASK) >> XS1_LPDDR_PE_TRP_CNT_SHIFT)
|
2807
|
+
#define XS1_LPDDR_PE_TRP_CNT_SET(x, v) \
|
2808
|
+
(((x) & ~XS1_LPDDR_PE_TRP_CNT_MASK) | \
|
2809
|
+
(((v) << XS1_LPDDR_PE_TRP_CNT_SHIFT) & XS1_LPDDR_PE_TRP_CNT_MASK))
|
2810
|
+
#define XS1_LPDDR_PE_TRFC_CNT_SHIFT 0xa
|
2811
|
+
#define XS1_LPDDR_PE_TRFC_CNT_SIZE 0x5
|
2812
|
+
#define XS1_LPDDR_PE_TRFC_CNT_MASK \
|
2813
|
+
(((1 << XS1_LPDDR_PE_TRFC_CNT_SIZE) - 1) << XS1_LPDDR_PE_TRFC_CNT_SHIFT)
|
2814
|
+
#define XS1_LPDDR_PE_TRFC_CNT(x) \
|
2815
|
+
(((x)&XS1_LPDDR_PE_TRFC_CNT_MASK) >> XS1_LPDDR_PE_TRFC_CNT_SHIFT)
|
2816
|
+
#define XS1_LPDDR_PE_TRFC_CNT_SET(x, v) \
|
2817
|
+
(((x) & ~XS1_LPDDR_PE_TRFC_CNT_MASK) | \
|
2818
|
+
(((v) << XS1_LPDDR_PE_TRFC_CNT_SHIFT) & XS1_LPDDR_PE_TRFC_CNT_MASK))
|
2819
|
+
#define XS1_LPDDR_PE_TRRD_CNT_SHIFT 0xf
|
2820
|
+
#define XS1_LPDDR_PE_TRRD_CNT_SIZE 0x2
|
2821
|
+
#define XS1_LPDDR_PE_TRRD_CNT_MASK \
|
2822
|
+
(((1 << XS1_LPDDR_PE_TRRD_CNT_SIZE) - 1) << XS1_LPDDR_PE_TRRD_CNT_SHIFT)
|
2823
|
+
#define XS1_LPDDR_PE_TRRD_CNT(x) \
|
2824
|
+
(((x)&XS1_LPDDR_PE_TRRD_CNT_MASK) >> XS1_LPDDR_PE_TRRD_CNT_SHIFT)
|
2825
|
+
#define XS1_LPDDR_PE_TRRD_CNT_SET(x, v) \
|
2826
|
+
(((x) & ~XS1_LPDDR_PE_TRRD_CNT_MASK) | \
|
2827
|
+
(((v) << XS1_LPDDR_PE_TRRD_CNT_SHIFT) & XS1_LPDDR_PE_TRRD_CNT_MASK))
|
2828
|
+
#define XS1_LPDDR_PE_EN_256M_DEV_SIZE_SHIFT 0x11
|
2829
|
+
#define XS1_LPDDR_PE_EN_256M_DEV_SIZE_SIZE 0x1
|
2830
|
+
#define XS1_LPDDR_PE_EN_256M_DEV_SIZE_MASK \
|
2831
|
+
(((1 << XS1_LPDDR_PE_EN_256M_DEV_SIZE_SIZE) - 1) \
|
2832
|
+
<< XS1_LPDDR_PE_EN_256M_DEV_SIZE_SHIFT)
|
2833
|
+
#define XS1_LPDDR_PE_EN_256M_DEV_SIZE(x) \
|
2834
|
+
(((x)&XS1_LPDDR_PE_EN_256M_DEV_SIZE_MASK) >> \
|
2835
|
+
XS1_LPDDR_PE_EN_256M_DEV_SIZE_SHIFT)
|
2836
|
+
#define XS1_LPDDR_PE_EN_256M_DEV_SIZE_SET(x, v) \
|
2837
|
+
(((x) & ~XS1_LPDDR_PE_EN_256M_DEV_SIZE_MASK) | \
|
2838
|
+
(((v) << XS1_LPDDR_PE_EN_256M_DEV_SIZE_SHIFT) & \
|
2839
|
+
XS1_LPDDR_PE_EN_256M_DEV_SIZE_MASK))
|
2840
|
+
#define XS1_DEVICE_ID0_VERSION_VALUE 0x0
|
2841
|
+
#define XS1_DEVICE_ID0_REVISION_VALUE 0x4
|
2842
|
+
#define XS1_PS_DBG_HANDLER XS1_PS_DBG_SCRATCH_0
|
2843
|
+
#define XS1_PS_DBG_COMMAND XS1_PS_DBG_SCRATCH_1
|
2844
|
+
#define XS1_PS_DBG_ARG0_REG XS1_PS_DBG_SCRATCH_2
|
2845
|
+
#define XS1_PS_DBG_ARG1_REG XS1_PS_DBG_SCRATCH_3
|
2846
|
+
#define XS1_PS_DBG_ARG2_REG XS1_PS_DBG_SCRATCH_4
|
2847
|
+
#define XS1_PS_DBG_ARG3_REG XS1_PS_DBG_SCRATCH_5
|
2848
|
+
#define XS1_PS_DBG_ARG4_REG XS1_PS_DBG_SCRATCH_6
|
2849
|
+
#define XS1_PS_DBG_ARG5_REG XS1_PS_DBG_SCRATCH_7
|
2850
|
+
#define XS1_PSWITCH_DBG_HANDLER_NUM XS1_PSWITCH_DBG_SCRATCH_0_NUM
|
2851
|
+
#define XS1_PSWITCH_DBG_COMMAND_NUM XS1_PSWITCH_DBG_SCRATCH_1_NUM
|
2852
|
+
#define XS1_PSWITCH_DBG_ARG0_NUM XS1_PSWITCH_DBG_SCRATCH_2_NUM
|
2853
|
+
#define XS1_PSWITCH_DBG_ARG1_NUM XS1_PSWITCH_DBG_SCRATCH_3_NUM
|
2854
|
+
#define XS1_PSWITCH_DBG_ARG2_NUM XS1_PSWITCH_DBG_SCRATCH_4_NUM
|
2855
|
+
#define XS1_PSWITCH_DBG_ARG3_NUM XS1_PSWITCH_DBG_SCRATCH_5_NUM
|
2856
|
+
#define XS1_PSWITCH_DBG_ARG4_NUM XS1_PSWITCH_DBG_SCRATCH_6_NUM
|
2857
|
+
#define XS1_PSWITCH_DBG_ARG5_NUM XS1_PSWITCH_DBG_SCRATCH_7_NUM
|
2858
|
+
#define XS1_XMOS_PHY_CONF_WIDTH 0x3
|
2859
|
+
#define XS1_USB_PHY_VCONTROL_SETUP_LENGTH 0x6
|
2860
|
+
#define XS1_USB_PHY_ENTER_BIST_LENGTH 0x40
|
2861
|
+
#define XS1_USB_PHY_CLKCNT_WIDTH 0x4
|
2862
|
+
#define XS1_USB_BISTGO_CTR_WIDTH 0x4
|
2863
|
+
#define XS1_USB_TESTGO_CTR_WIDTH 0x4
|
2864
|
+
#define XS1_USB_TESTGO_PULSE_LENGTH 0x8
|
2865
|
+
#define XS1_USB_BISTGO_PULSE_LENGTH 0x8
|
2866
|
+
#define XS1_CRC5_RESULT_WIDTH 0x5
|
2867
|
+
#define XS1_MS_NIBBLE "7:4"
|
2868
|
+
#define XS1_LS_NIBBLE "3:0"
|
2869
|
+
#endif /* _xs3a_registers_h_ */
|