tdl-xoa-driver 1.4.0__py3-none-any.whl → 1.5.0__py3-none-any.whl

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (50) hide show
  1. {tdl_xoa_driver-1.4.0.dist-info → tdl_xoa_driver-1.5.0.dist-info}/METADATA +8 -8
  2. {tdl_xoa_driver-1.4.0.dist-info → tdl_xoa_driver-1.5.0.dist-info}/RECORD +49 -36
  3. xoa_driver/__init__.py +2 -2
  4. xoa_driver/enums.py +2 -0
  5. xoa_driver/exceptions.py +2 -0
  6. xoa_driver/functions/anlt.py +2 -0
  7. xoa_driver/functions/anlt_ll_debug.py +2 -0
  8. xoa_driver/functions/cli/__init__.py +21 -0
  9. xoa_driver/functions/cli/_cli_manager.py +541 -0
  10. xoa_driver/functions/cli/_config_block.py +334 -0
  11. xoa_driver/functions/cli/_socket_driver.py +111 -0
  12. xoa_driver/functions/cli/port_config.py +116 -0
  13. xoa_driver/functions/cli/testbed_config.py +179 -0
  14. xoa_driver/functions/cmis/__init__.py +8 -0
  15. xoa_driver/functions/cmis/_constants.py +25 -0
  16. xoa_driver/functions/cmis/_replies.py +600 -0
  17. xoa_driver/functions/cmis/_utils.py +49 -0
  18. xoa_driver/functions/cmis/cdb.py +1266 -0
  19. xoa_driver/functions/exceptions.py +2 -0
  20. xoa_driver/functions/headers.py +2 -0
  21. xoa_driver/functions/mgmt.py +42 -19
  22. xoa_driver/functions/tools.py +9 -3
  23. xoa_driver/hlfuncs.py +6 -2
  24. xoa_driver/internals/commands/c_commands.py +6 -10
  25. xoa_driver/internals/commands/enums.py +25 -1
  26. xoa_driver/internals/commands/p_commands.py +38 -2
  27. xoa_driver/internals/commands/pl1_commands.py +130 -73
  28. xoa_driver/internals/commands/pp_commands.py +44 -55
  29. xoa_driver/internals/commands/pr_commands.py +17 -16
  30. xoa_driver/internals/commands/px_commands.py +54 -54
  31. xoa_driver/internals/core/transporter/logger/__state_on_user.py +1 -1
  32. xoa_driver/internals/exceptions/modules.py +4 -3
  33. xoa_driver/internals/hli/modules/modules_l23/family_edun.py +82 -0
  34. xoa_driver/internals/hli/modules/modules_l23/family_g.py +1 -1
  35. xoa_driver/internals/hli/modules/modules_l23/family_l1.py +19 -0
  36. xoa_driver/internals/hli/ports/port_l23/edun_l1.py +181 -0
  37. xoa_driver/internals/hli/ports/port_l23/family_edun.py +82 -0
  38. xoa_driver/internals/hli/ports/port_l23/family_l1.py +14 -8
  39. xoa_driver/internals/state_storage/modules_state.py +20 -0
  40. xoa_driver/internals/state_storage/testers_state.py +10 -0
  41. xoa_driver/lli.py +1 -0
  42. xoa_driver/misc.py +1 -0
  43. xoa_driver/modules.py +22 -0
  44. xoa_driver/ports.py +22 -0
  45. xoa_driver/testers.py +2 -0
  46. xoa_driver/utils.py +2 -0
  47. xoa_driver/functions/cli.py +0 -581
  48. {tdl_xoa_driver-1.4.0.dist-info → tdl_xoa_driver-1.5.0.dist-info}/WHEEL +0 -0
  49. {tdl_xoa_driver-1.4.0.dist-info → tdl_xoa_driver-1.5.0.dist-info}/licenses/LICENSE +0 -0
  50. {tdl_xoa_driver-1.4.0.dist-info → tdl_xoa_driver-1.5.0.dist-info}/top_level.txt +0 -0
@@ -1,3 +1,5 @@
1
+ """The exception high-level function module."""
2
+
1
3
  from __future__ import annotations
2
4
 
3
5
  from xoa_driver.ports import GenericAnyPort
@@ -1,3 +1,5 @@
1
+ """The packet headers high-level function module."""
2
+
1
3
  from ipaddress import IPv4Address, IPv6Address
2
4
  from binascii import hexlify
3
5
  from xoa_driver.misc import Hex
@@ -1,13 +1,23 @@
1
+ """
2
+ The resource management high-level function module,
3
+ including testers, modules, ports, and streams.
4
+ """
5
+
1
6
  from __future__ import annotations
2
7
  import asyncio
3
- import typing as t
8
+ from typing import (
9
+ TYPE_CHECKING,
10
+ Any,
11
+ Union,
12
+ )
4
13
  from xoa_driver import enums, testers
5
14
  from xoa_driver.utils import apply
6
- from xoa_driver.internals.hli.ports.port_l23.family_l import FamilyL
7
- from xoa_driver.internals.hli.ports.port_l23.family_l1 import FamilyFreya
8
- from xoa_driver.ports import GenericAnyPort, GenericL23Port
9
- from xoa_driver.modules import GenericAnyModule, GenericL23Module, ModuleChimera, Z800FreyaModule
10
- from xoa_driver.testers import GenericAnyTester, L23Tester
15
+ if TYPE_CHECKING:
16
+ from xoa_driver.internals.hli.ports.port_l23.family_l import FamilyL
17
+ from xoa_driver.internals.hli.ports.port_l23.family_l1 import FamilyFreya
18
+ from xoa_driver.ports import GenericAnyPort, GenericL23Port
19
+ from xoa_driver.modules import GenericAnyModule, GenericL23Module, ModuleChimera, Z800FreyaModule, Z1600EdunModule
20
+ from xoa_driver.testers import GenericAnyTester, L23Tester
11
21
  from .exceptions import (
12
22
  NotSupportMedia,
13
23
  NotSupportPortSpeed,
@@ -18,10 +28,6 @@ from itertools import chain # type: ignore[Pylance false warning]
18
28
  from datetime import datetime
19
29
  import json
20
30
 
21
- PcsPmaSupported = (FamilyL, FamilyFreya)
22
- AutoNegSupported = (FamilyL, FamilyFreya)
23
- LinkTrainingSupported = FamilyL
24
-
25
31
 
26
32
  # region Testers
27
33
  async def reserve_tester(tester: GenericAnyTester, force: bool = True) -> None:
@@ -150,14 +156,14 @@ async def release_module(
150
156
 
151
157
  def get_module_supported_media(
152
158
  module: GenericL23Module | ModuleChimera,
153
- ) -> list[dict[str, t.Any]]:
159
+ ) -> list[dict[str, Any]]:
154
160
  """
155
161
  Get a list of supported media, port speed and count of the module.
156
162
 
157
163
  :param module: The module object
158
164
  :type module: GenericAnyModule
159
165
  :return: List of supported media, port speed and count
160
- :rtype: list[dict[str, t.Any]]
166
+ :rtype: list[dict[str, Any]]
161
167
  """
162
168
  supported_media_list = []
163
169
  item = {}
@@ -174,7 +180,7 @@ def get_module_supported_media(
174
180
 
175
181
 
176
182
  async def set_module_media_config(
177
- module: t.Union[GenericL23Module, ModuleChimera],
183
+ module: Union[GenericL23Module, ModuleChimera],
178
184
  media: enums.MediaConfigurationType,
179
185
  force: bool = True,
180
186
  ) -> None:
@@ -210,7 +216,7 @@ async def set_module_media_config(
210
216
 
211
217
 
212
218
  async def set_module_port_config(
213
- module: t.Union[GenericL23Module, ModuleChimera],
219
+ module: Union[GenericL23Module, ModuleChimera],
214
220
  port_count: int,
215
221
  port_speed: int,
216
222
  force: bool = True,
@@ -219,7 +225,7 @@ async def set_module_port_config(
219
225
  Set module's port-speed configuration
220
226
 
221
227
  :param module: The module object
222
- :type module: t.Union[GenericL23Module, ModuleChimera]
228
+ :type module: Union[GenericL23Module, ModuleChimera]
223
229
  :param port_count: The port count
224
230
  :type port_count: int
225
231
  :param port_speed: The port speed in Mbps, e.g. 40000 for 40G
@@ -258,7 +264,7 @@ async def set_module_port_config(
258
264
 
259
265
 
260
266
  async def set_module_config(
261
- module: t.Union[GenericL23Module, ModuleChimera],
267
+ module: Union[GenericL23Module, ModuleChimera],
262
268
  media: enums.MediaConfigurationType,
263
269
  port_count: int,
264
270
  port_speed: int,
@@ -267,7 +273,7 @@ async def set_module_config(
267
273
  """Change the module configuration to the target media, port count and port speed.
268
274
 
269
275
  :param module: the module object
270
- :type module: t.Union[GenericL23Module, ModuleChimera]
276
+ :type module: Union[GenericL23Module, ModuleChimera]
271
277
  :param media: the target media for the module
272
278
  :type media: enums.MediaConfigurationType
273
279
  :param port_count: the target port count
@@ -332,12 +338,13 @@ async def get_module_eol_days(module: GenericAnyModule) -> int:
332
338
  return timedelta.days
333
339
 
334
340
 
335
- async def get_module_cage_insertion_count(module: Z800FreyaModule, cage_index: int) -> int:
341
+ from xoa_driver.modules import GenericAnyModule, GenericL23Module, ModuleChimera, Z800FreyaModule, Z1600EdunModule
342
+ async def get_module_cage_insertion_count(module: Union[Z800FreyaModule, Z1600EdunModule], cage_index: int) -> int:
336
343
  """
337
344
  Get module cage insertion count
338
345
 
339
346
  :param module: The Z800 Freya module object
340
- :type module: Z800FreyaModule
347
+ :type module: Union[Z800FreyaModule, Z1600EdunModule]
341
348
  :param cage_index: The cage index
342
349
  :type module: int
343
350
  :return: Insertion count of the cage
@@ -355,6 +362,22 @@ async def get_module_cage_insertion_count(module: Z800FreyaModule, cage_index: i
355
362
  return result
356
363
 
357
364
 
365
+ async def get_module_cage_count(module: Union[Z800FreyaModule, Z1600EdunModule]) -> int:
366
+ """
367
+ Get module cage count
368
+
369
+ :param module: The Z800 Freya module object
370
+ :type module: Union[Z800FreyaModule, Z1600EdunModule]
371
+ :return: The number of cages in the module
372
+ :rtype: int
373
+ """
374
+ resp = await module.health.cage_insertion.get()
375
+ info_js = resp.info
376
+ info_dict = json.loads(info_js)
377
+ result = len(info_dict['1']['data'])
378
+ return result
379
+
380
+
358
381
  # endregion
359
382
 
360
383
 
@@ -1,14 +1,20 @@
1
1
  from __future__ import annotations
2
- from typing import Any
2
+ from typing import (
3
+ TYPE_CHECKING,
4
+ Any,
5
+ )
6
+
7
+ if TYPE_CHECKING:
8
+ from xoa_driver.ports import GenericAnyPort
3
9
 
4
- from xoa_driver.ports import GenericAnyPort
5
10
  from xoa_driver.internals.core import interfaces as itf
6
11
  from xoa_driver.lli import commands
7
12
  from xoa_driver import enums
8
13
 
9
14
 
10
15
  def get_ctx(port: GenericAnyPort) -> tuple["itf.IConnection", int, int]:
11
- return (port._conn, *port.kind)
16
+ module_id, port_id = port.kind # Explicitly unpack to two ints
17
+ return (port._conn, module_id, port_id)
12
18
 
13
19
 
14
20
  def dictionize_autoneg_status(
xoa_driver/hlfuncs.py CHANGED
@@ -1,11 +1,14 @@
1
1
  #: High-level functions
2
+ """High-level functions."""
3
+
2
4
  from xoa_driver.functions import (
3
5
  anlt,
4
- cli,
6
+ cli as config_io,
5
7
  mgmt,
6
8
  anlt_ll_debug,
7
9
  exceptions,
8
10
  headers,
11
+ cmis,
9
12
  )
10
13
 
11
14
  __all__ = (
@@ -13,6 +16,7 @@ __all__ = (
13
16
  "mgmt",
14
17
  "anlt_ll_debug",
15
18
  "exceptions",
16
- "cli",
19
+ "config_io",
17
20
  "headers",
21
+ "cmis",
18
22
  )
@@ -23,7 +23,8 @@ from xoa_driver.internals.core.transporter.protocol.payload import (
23
23
  XmpMacAddress,
24
24
  XmpSequence,
25
25
  XmpStr,
26
- Hex
26
+ Hex,
27
+ XmpJson,
27
28
  )
28
29
  from .enums import (
29
30
  ReservedStatus,
@@ -1239,7 +1240,7 @@ class C_WATCHDOG:
1239
1240
  @dataclass
1240
1241
  class C_DEBUGCMD:
1241
1242
  """
1242
- Chassis debug command
1243
+ Chassis debug command for internal use only.
1243
1244
  """
1244
1245
 
1245
1246
  code: typing.ClassVar[int] = 37
@@ -1249,16 +1250,11 @@ class C_DEBUGCMD:
1249
1250
  _cmd_xindex: int
1250
1251
 
1251
1252
  class GetDataAttr(ResponseBodyStruct):
1252
- data: typing.List[int] = field(XmpSequence(types_chunk=[XmpInt()]))
1253
-
1254
- class SetDataAttr(RequestBodyStruct):
1255
- data: typing.List[int] = field(XmpSequence(types_chunk=[XmpInt()]))
1253
+ data: dict = field(XmpJson(min_len=2))
1256
1254
 
1257
1255
  def get(self) -> Token[GetDataAttr]:
1258
1256
  return Token(self._connection, build_get_request(self, indices=[self._cmd_xindex]))
1259
1257
 
1260
- def set(self, data: typing.List[int]) -> Token[None]:
1261
- return Token(self._connection, build_set_request(self, indices=[self._cmd_xindex], data=data))
1262
1258
 
1263
1259
 
1264
1260
  @register_command
@@ -2028,8 +2024,8 @@ class C_MODEL_NUMBER:
2028
2024
  _connection: 'interfaces.IConnection'
2029
2025
 
2030
2026
  class GetDataAttr(ResponseBodyStruct):
2031
- number: ChassisModelNumber = field(XmpInt())
2032
- """ChassisModelNumber, the model of the Xena tester"""
2027
+ number: str = field(XmpStr())
2028
+ """str, the model of the Xena tester"""
2033
2029
 
2034
2030
  def get(self) -> Token[GetDataAttr]:
2035
2031
  """Get the Xena chassis model number.
@@ -1069,6 +1069,18 @@ class MediaConfigurationType(IntEnum):
1069
1069
  QSFP28_NRZ_ANLT = 123
1070
1070
  """QSFP28, 25G serdes, L1/ANLT"""
1071
1071
 
1072
+ SMPX_112 = 124
1073
+ """SMPX 112Gbps serdes"""
1074
+
1075
+ SMPX_224 = 125
1076
+ """SMPX 224Gbps serdes"""
1077
+
1078
+ OSFP_1600 = 126
1079
+ """OSFP 1.6T"""
1080
+
1081
+ OSFP_1600_ANLT = 127
1082
+ """OSFP 1.6T, L1/ANLT"""
1083
+
1072
1084
  UNKNOWN = 255
1073
1085
 
1074
1086
 
@@ -3165,7 +3177,13 @@ class ChassisModelName(IntEnum):
3165
3177
  Z_800_Q_A_C_FREYA = 16
3166
3178
  Z_800_O_A_C_FREYA = 17
3167
3179
  E_100_Q_C_CHIMERA = 18
3168
-
3180
+ Z_100_Q_X_C_LOKI = 19
3181
+ Z_400_Q_X_C_THOR = 20
3182
+ Z_800_Q_X_C_FREYA = 21
3183
+ Z_1604_S_C_EDUN = 22
3184
+ Z_1608_O_C_EDUN = 23
3185
+ B_6400 = 24
3186
+
3169
3187
  class ModuleModelName(IntEnum):
3170
3188
  NA = 0
3171
3189
  Z_01_T_ODIN = 1
@@ -3180,6 +3198,12 @@ class ModuleModelName(IntEnum):
3180
3198
  Z_800_Q_FREYA = 10
3181
3199
  Z_800_O_FREYA = 11
3182
3200
  E_100_Q_CHIMERA = 12
3201
+ Z_100_Q_X_LOKI = 13
3202
+ Z_400_Q_X_THOR = 14
3203
+ Z_800_Q_X_FREYA = 15
3204
+ Z_1604_S_EDUN = 16
3205
+ Z_1608_O_EDUN = 17
3206
+ Z_1616_O_EDUN = 18
3183
3207
 
3184
3208
  class ModuleConfigStatus(IntEnum):
3185
3209
  UNKNOWN = 0
@@ -601,7 +601,44 @@ class P_CAPABILITIES:
601
601
  * Bit 0: Normal modifier (16/24-bit) supports little-endian
602
602
  * Bit 1: Extended modifier (32-bit) supports little-endian
603
603
  """
604
-
604
+ capture_bitmask: int = field(XmpInt(), min_version=470)
605
+ """integer, bitmask indicating capture capabilities.
606
+
607
+ If all bits are 0: CAPTURE_NOT_SUPPORTED
608
+
609
+ Bits [0:11] are for Start triggers:
610
+
611
+ * Bit 0: CAPTURE_START_ON
612
+ * Bit 1: CAPTURE_START_FCSERROR
613
+ * Bit 2: CAPTURE_START_FILTER
614
+ * Bit 3: CAPTURE_START_PLDERROR
615
+ * Bit 4-11: Reserved
616
+
617
+ Bits [12:23] are for Stop triggers:
618
+
619
+ * Bit 12: CAPTURE_STOP_FULL
620
+ * Bit 13: CAPTURE_STOP_FCSERROR
621
+ * Bit 14: CAPTURE_STOP_FILTER
622
+ * Bit 15: CAPTURE_STOP_PLDERROR
623
+ * Bit 16: CAPTURE_STOP_USERSTOP
624
+ * Bit 17-23: Reserved
625
+
626
+ Bits [24:31] are for Keep modes:
627
+
628
+ * Bit 24: CAPTURE_KEEP_ALL
629
+ * Bit 25: CAPTURE_KEEP_FCSERR
630
+ * Bit 26: CAPTURE_KEEP_NOTPLD
631
+ * Bit 27: CAPTURE_KEEP_TPLD
632
+ * Bit 28: CAPTURE_KEEP_FILTER
633
+ * Bit 29: CAPTURE_KEEP_PLDERR
634
+ * Bit 30-31: Reserved
635
+ """
636
+ num_txeq_pre: int = field(XmpInt(), min_version=470)
637
+ """The number of postcursors = num_txeq - num_txeq_pre - 1."""
638
+ txeq_max_seq: typing.List[int] = field(XmpSequence(types_chunk=[XmpInt()], length=10), min_version=470)
639
+ """max value of individual TXEQ taps, SEQuential: <pre-n> <pre-(n-q)> ... <prr1> <main> <post1> <post2> ...."""
640
+ txeq_min_seq: typing.List[int] = field(XmpSequence(types_chunk=[XmpInt()], length=10), min_version=470)
641
+ """min-value of individual TXEQ taps, SEQuential: <pre-n> <pre-(n-q)> ... <prr1> <main> <post1> <post2> ...."""
605
642
 
606
643
 
607
644
  def get(self) -> Token[GetDataAttr]:
@@ -1512,7 +1549,6 @@ class P_XMITONE:
1512
1549
  A valid Frame Check Sum is written into the final four bytes.
1513
1550
 
1514
1551
  :param hex_data: raw bytes of the packet in hex to transmit
1515
- :rtype: typing.List[str]
1516
1552
  """
1517
1553
 
1518
1554
  return Token(self._connection, build_set_request(self, module=self._module, port=self._port, hex_data=hex_data))
@@ -832,7 +832,16 @@ class PL1_PRESET_CONFIG_COEFF:
832
832
  @dataclass
833
833
  class PL1_PHYTXEQ_LEVEL:
834
834
  """
835
- Control and monitor the equalizer settings of the on-board PHY in the transmission direction (towards the transceiver cage).
835
+ Control and monitor the equalizer settings (mV/dB values) of the on-board PHY in the transmission direction (towards the transceiver cage).
836
+
837
+ This command returns a variable number of tap values with module-dependent ordering:
838
+
839
+ - **Regular Freya**: Original fixed format [pre3, pre2, pre, main, post]
840
+ - **Loki-4P and H-Freya/Edun**: Variable number in N*pre, main, M*post layout
841
+ [pre_n, pre_n-1, ..., pre_1, main, post_1, post_2, ..., post_m]
842
+
843
+ Use P_CAPABILITIES to query ``numtxeqtaps`` and ``numtxeqpretaps`` to determine
844
+ the number of taps and layout.
836
845
 
837
846
  .. note::
838
847
 
@@ -849,44 +858,63 @@ class PL1_PHYTXEQ_LEVEL:
849
858
  _serdes_xindex: int
850
859
 
851
860
  class GetDataAttr(ResponseBodyStruct):
852
- pre3: int = field(XmpInt())
853
- """integer, pre3 tap value in dB/10, ranges from 0 to 71. Default = 0 (neutral)"""
854
- pre2: int = field(XmpInt())
855
- """integer, pre2 tap value in dB/10, ranges from 0 to 71. Default = 0 (neutral)"""
856
- pre: int = field(XmpInt())
857
- """integer, pre tap value in dB/10, ranges from 0 to 187. Default = 0 (neutral)"""
858
- main: int = field(XmpInt())
859
- """integer, main tap value in mV, ranges from 507 to 998."""
860
- post: int = field(XmpInt())
861
- """integer, post tap value in dB/10, ranges from 0 to 187 Default = 0 (neutral)"""
862
-
861
+ tap_values: typing.List[int] = field(XmpSequence(types_chunk=[XmpInt()]))
862
+ """list of integers, TX EQ tap values in mV/dB. The number and layout depend on the platform:
863
+
864
+ - Regular Freya: [pre3, pre2, pre, main, post] where pre3/pre2 in dB/10 (0-71), pre/post in dB/10 (0-187), main in mV (507-998)
865
+ - Loki-4P and H-Freya/Edun: [pre_n, ..., pre_1, main, post_1, post_2, ..., post_m]
866
+ where N = numtxeqpretaps and M = numtxeqtaps - numtxeqpretaps - 1
867
+ """
868
+
863
869
  class SetDataAttr(RequestBodyStruct):
864
- pre3: int = field(XmpInt())
865
- """integer, pre3 tap value in dB/10, ranges from 0 to 71. Default = 0 (neutral)"""
866
- pre2: int = field(XmpInt())
867
- """integer, pre2 tap value in dB/10, ranges from 0 to 71. Default = 0 (neutral)"""
868
- pre: int = field(XmpInt())
869
- """integer, pre tap value in dB/10, ranges from 0 to 187. Default = 0 (neutral)"""
870
- main: int = field(XmpInt())
871
- """integer, main tap value in mV, ranges from 507 to 998."""
872
- post: int = field(XmpInt())
873
- """integer, post tap value in dB/10, ranges from 0 to 187 Default = 0 (neutral)"""
870
+ tap_values: typing.List[int] = field(XmpSequence(types_chunk=[XmpInt()]))
871
+ """list of integers, TX EQ tap values in mV/dB. The number and layout depend on the platform:
872
+
873
+ - Regular Freya: [pre3, pre2, pre, main, post] where pre3/pre2 in dB/10 (0-71), pre/post in dB/10 (0-187), main in mV (507-998)
874
+ - Loki-4P and H-Freya/Edun: [pre_n, ..., pre_1, main, post_1, post_2, ..., post_m]
875
+ where N = numtxeqpretaps and M = numtxeqtaps - numtxeqpretaps - 1
876
+ """
874
877
 
875
878
  def get(self) -> Token[GetDataAttr]:
879
+ """Get the TX equalizer settings (mV/dB values) of the on-board PHY.
880
+
881
+ The returned tap values layout depends on the platform. Query P_CAPABILITIES
882
+ for ``numtxeqtaps`` and ``numtxeqpretaps`` to determine the format.
883
+
884
+ :return: list of TX EQ tap values in mV/dB
885
+ :rtype: PL1_PHYTXEQ_LEVEL.GetDataAttr
886
+ """
876
887
 
877
888
  return Token(self._connection, build_get_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex]))
878
889
 
879
- def set(self, pre3:int, pre2: int, pre: int, main: int, post: int) -> Token[None]:
890
+ def set(self, tap_values: typing.List[int]) -> Token[None]:
891
+ """Set the TX equalizer settings (mV/dB values) of the on-board PHY.
892
+
893
+ The tap values layout depends on the platform. Query P_CAPABILITIES
894
+ for ``numtxeqtaps`` and ``numtxeqpretaps`` to determine the required format.
895
+
896
+ :param tap_values: list of TX EQ tap values in mV/dB in platform-specific order
897
+ :type tap_values: typing.List[int]
898
+ """
880
899
 
881
900
  return Token(
882
901
  self._connection,
883
- build_set_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex], pre3=pre3, pre2=pre2, pre=pre, main=main, post=post))
884
-
902
+ build_set_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex], tap_values=tap_values))
903
+
885
904
  @register_command
886
905
  @dataclass
887
906
  class PL1_PHYTXEQ_COEFF:
888
907
  """
889
- Control and monitor the equalizer settings of the on-board PHY in the transmission direction (towards the transceiver cage).
908
+ Control and monitor the equalizer settings (IEEE coefficient values) of the on-board PHY in the transmission direction (towards the transceiver cage).
909
+
910
+ This command returns a variable number of tap values with module-dependent ordering:
911
+
912
+ - **Regular Freya**: Original fixed format [pre3, pre2, pre, main, post]
913
+ - **Loki-4P and H-Freya/Edun**: Variable number in N*pre, main, M*post layout
914
+ [pre_n, pre_n-1, ..., pre_1, main, post_1, post_2, ..., post_m]
915
+
916
+ Use P_CAPABILITIES to query ``numtxeqtaps`` and ``numtxeqpretaps`` to determine
917
+ the number of taps and layout.
890
918
 
891
919
  .. note::
892
920
 
@@ -913,38 +941,48 @@ class PL1_PHYTXEQ_COEFF:
913
941
  _serdes_xindex: int
914
942
 
915
943
  class GetDataAttr(ResponseBodyStruct):
916
- pre3: int = field(XmpInt())
917
- """integer, pre3 tap value, negative, scaled by 1E3. Default = 0 (neutral)"""
918
- pre2: int = field(XmpInt())
919
- """integer, pre2 tap value, positive, scaled by 1E3. Default = 0 (neutral)"""
920
- pre: int = field(XmpInt())
921
- """integer, pre tap value, negative, scaled by 1E3. Default = 0 (neutral)"""
922
- main: int = field(XmpInt())
923
- """integer, main tap value, positive, scaled by 1E3. Default = 1000"""
924
- post: int = field(XmpInt())
925
- """integer, post tap value, negative, scaled by 1E3. Default = 0 (neutral)"""
926
-
944
+ tap_values: typing.List[int] = field(XmpSequence(types_chunk=[XmpInt()]))
945
+ """list of integers, TX EQ tap values as IEEE coefficients scaled by 1E3. The number and layout depend on the platform:
946
+
947
+ - Regular Freya: [pre3, pre2, pre, main, post] where pre3/pre/post are negative, pre2/main are positive
948
+ - Loki-4P and H-Freya/Edun: [pre_n, ..., pre_1, main, post_1, ..., post_m]
949
+ where N = numtxeqpretaps and M = numtxeqtaps - numtxeqpretaps - 1
950
+ """
951
+
927
952
  class SetDataAttr(RequestBodyStruct):
928
- pre3: int = field(XmpInt())
929
- """integer, pre3 tap value, negative, scaled by 1E3. Default = 0 (neutral)"""
930
- pre2: int = field(XmpInt())
931
- """integer, pre2 tap value, positive, scaled by 1E3. Default = 0 (neutral)"""
932
- pre: int = field(XmpInt())
933
- """integer, pre tap value, negative, scaled by 1E3. Default = 0 (neutral)"""
934
- main: int = field(XmpInt())
935
- """integer, main tap value, positive, scaled by 1E3. Default = 1000"""
936
- post: int = field(XmpInt())
937
- """integer, post tap value, negative, scaled by 1E3. Default = 0 (neutral)"""
953
+ tap_values: typing.List[int] = field(XmpSequence(types_chunk=[XmpInt()]))
954
+ """list of integers, TX EQ tap values as IEEE coefficients scaled by 1E3. The number and layout depend on the platform:
955
+
956
+ - Regular Freya: [pre3, pre2, pre, main, post] where pre3/pre/post are negative, pre2/main are positive
957
+ - Loki-4P and H-Freya/Edun: [pre_n, ..., pre_1, main, post_1, ..., post_m]
958
+ where N = numtxeqpretaps and M = numtxeqtaps - numtxeqpretaps - 1
959
+ """
938
960
 
939
961
  def get(self) -> Token[GetDataAttr]:
962
+ """Get the TX equalizer settings (IEEE coefficient values) of the on-board PHY.
963
+
964
+ The returned tap values layout depends on the platform. Query P_CAPABILITIES
965
+ for ``numtxeqtaps`` and ``numtxeqpretaps`` to determine the format.
966
+
967
+ :return: list of TX EQ tap values as IEEE coefficients scaled by 1E3
968
+ :rtype: PL1_PHYTXEQ_COEFF.GetDataAttr
969
+ """
940
970
 
941
971
  return Token(self._connection, build_get_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex]))
942
972
 
943
- def set(self, pre3:int, pre2: int, pre: int, main: int, post: int) -> Token[None]:
973
+ def set(self, tap_values: typing.List[int]) -> Token[None]:
974
+ """Set the TX equalizer settings (IEEE coefficient values) of the on-board PHY.
975
+
976
+ The tap values layout depends on the platform. Query P_CAPABILITIES
977
+ for ``numtxeqtaps`` and ``numtxeqpretaps`` to determine the required format.
978
+
979
+ :param tap_values: list of TX EQ tap values as IEEE coefficients scaled by 1E3 in platform-specific order
980
+ :type tap_values: typing.List[int]
981
+ """
944
982
 
945
983
  return Token(
946
984
  self._connection,
947
- build_set_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex], pre3=pre3, pre2=pre2, pre=pre, main=main, post=post))
985
+ build_set_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex], tap_values=tap_values))
948
986
 
949
987
  @register_command
950
988
  @dataclass
@@ -1345,7 +1383,16 @@ class PL1_ANLT:
1345
1383
  @dataclass
1346
1384
  class PL1_PHYTXEQ:
1347
1385
  """
1348
- Control and monitor the equalizer settings of the on-board PHY in the transmission direction (towards the transceiver cage).
1386
+ Control and monitor the equalizer settings (native values) of the on-board PHY in the transmission direction (towards the transceiver cage).
1387
+
1388
+ This command returns a variable number of tap values with module-dependent ordering:
1389
+
1390
+ - **Regular Freya**: Original fixed format [pre3, pre2, pre, main, post]
1391
+ - **Loki-4P and H-Freya/Edun**: Variable number in N*pre, main, M*post layout
1392
+ [pre_n, pre_n-1, ..., pre_1, main, post_1, post_2, ..., post_m]
1393
+
1394
+ Use P_CAPABILITIES to query ``numtxeqtaps`` and ``numtxeqpretaps`` to determine
1395
+ the number of taps and layout.
1349
1396
 
1350
1397
  .. note::
1351
1398
 
@@ -1362,38 +1409,48 @@ class PL1_PHYTXEQ:
1362
1409
  _serdes_xindex: int
1363
1410
 
1364
1411
  class GetDataAttr(ResponseBodyStruct):
1365
- pre3: int = field(XmpInt())
1366
- """integer, pre3 tap value. Default = 0 (neutral)"""
1367
- pre2: int = field(XmpInt())
1368
- """integer, pre2 tap value. Default = 0 (neutral)"""
1369
- pre: int = field(XmpInt())
1370
- """integer, pre tap value. Default = 0 (neutral)"""
1371
- main: int = field(XmpInt())
1372
- """integer, main tap value."""
1373
- post: int = field(XmpInt())
1374
- """integer, post tap value. Default = 0 (neutral)"""
1375
-
1412
+ tap_values: typing.List[int] = field(XmpSequence(types_chunk=[XmpInt()]))
1413
+ """list of integers, TX EQ tap values (native values). The number and layout depend on the platform:
1414
+
1415
+ - Regular Freya: [pre3, pre2, pre, main, post]
1416
+ - Loki-4P and H-Freya/Edun: [pre_n, ..., pre_1, main, post_1, ..., post_m]
1417
+ where N = numtxeqpretaps and M = numtxeqtaps - numtxeqpretaps - 1
1418
+ """
1419
+
1376
1420
  class SetDataAttr(RequestBodyStruct):
1377
- pre3: int = field(XmpInt())
1378
- """integer, pre3 tap value. Default = 0 (neutral)"""
1379
- pre2: int = field(XmpInt())
1380
- """integer, pre2 tap value. Default = 0 (neutral)"""
1381
- pre: int = field(XmpInt())
1382
- """integer, pre tap value. Default = 0 (neutral)"""
1383
- main: int = field(XmpInt())
1384
- """integer, main tap value."""
1385
- post: int = field(XmpInt())
1386
- """integer, post tap value. Default = 0 (neutral)"""
1421
+ tap_values: typing.List[int] = field(XmpSequence(types_chunk=[XmpInt()]))
1422
+ """list of integers, TX EQ tap values (native values). The number and layout depend on the platform:
1423
+
1424
+ - Regular Freya: [pre3, pre2, pre, main, post]
1425
+ - Loki-4P and H-Freya/Edun: [pre_n, ..., pre_1, main, post_1, ..., post_m]
1426
+ where N = numtxeqpretaps and M = numtxeqtaps - numtxeqpretaps - 1
1427
+ """
1387
1428
 
1388
1429
  def get(self) -> Token[GetDataAttr]:
1430
+ """Get the TX equalizer settings (native values) of the on-board PHY.
1431
+
1432
+ The returned tap values layout depends on the platform. Query P_CAPABILITIES
1433
+ for ``numtxeqtaps`` and ``numtxeqpretaps`` to determine the format.
1434
+
1435
+ :return: list of TX EQ tap values (native values)
1436
+ :rtype: PL1_PHYTXEQ.GetDataAttr
1437
+ """
1389
1438
 
1390
1439
  return Token(self._connection, build_get_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex]))
1391
1440
 
1392
- def set(self, pre3:int, pre2: int, pre: int, main: int, post: int) -> Token[None]:
1441
+ def set(self, tap_values: typing.List[int]) -> Token[None]:
1442
+ """Set the TX equalizer settings (native values) of the on-board PHY.
1443
+
1444
+ The tap values layout depends on the platform. Query P_CAPABILITIES
1445
+ for ``numtxeqtaps`` and ``numtxeqpretaps`` to determine the required format.
1446
+
1447
+ :param tap_values: list of TX EQ tap values (native values) in platform-specific order
1448
+ :type tap_values: typing.List[int]
1449
+ """
1393
1450
 
1394
1451
  return Token(
1395
1452
  self._connection,
1396
- build_set_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex], pre3=pre3, pre2=pre2, pre=pre, main=main, post=post))
1453
+ build_set_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex], tap_values=tap_values))
1397
1454
 
1398
1455
  @register_command
1399
1456
  @dataclass