siliconcompiler 0.36.0__py3-none-any.whl → 0.36.1__py3-none-any.whl

siliconcompiler/tools/yosys/lec_asic.py

@@ -1,4 +1,5 @@
 import re
+from typing import Optional
 
 from siliconcompiler import sc_open
 
@@ -15,6 +16,18 @@ class ASICLECTask(_ASICTask):
         self.add_parameter("induction_steps", "int",
                            "Number of induction steps for yosys equivalence checking", defvalue=10)
 
+    def set_yosys_inductionsteps(self, steps: int,
+                                 step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the number of induction steps for yosys equivalence checking.
+
+        Args:
+            steps (int): The number of steps.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "induction_steps", steps, step=step, index=index)
+
     def task(self):
         return "lec_asic"
 

siliconcompiler/tools/yosys/syn_asic.py

@@ -2,7 +2,7 @@ import json
 
 import os.path
 
-from typing import Optional
+from typing import Optional, Union, List
 
 from siliconcompiler.tools.yosys.prepareLib import process_liberty_file
 from siliconcompiler import sc_open
@@ -56,14 +56,14 @@ class _ASICTask(ASICTask, YosysTask):
             if not scenario.get_libcorner():
                 continue
             if "setup" in scenario.get_check():
-                self.add_synthesis_corner(scenario.get_libcorner())
+                self.add_yosys_synthesiscorner(scenario.get_libcorner())
                 return
 
         if scenarios:
             # try getting it from first constraint with a valid libcorner
             for scenario in scenarios.get_scenario().values():
                 if scenario.get_libcorner():
-                    self.add_synthesis_corner(scenario.get_libcorner())
+                    self.add_yosys_synthesiscorner(scenario.get_libcorner())
                     return
 
     def pre_process(self):
@@ -132,6 +132,28 @@ class _ASICTask(ASICTask, YosysTask):
                 self.add("var", 'synthesis_libraries', output_file)
 
     def add_synthesis_corner(self, corner, step=None, index=None, clobber=True):
+        """Deprecated"""
+        import warnings
+        warnings.warn(
+            "add_synthesis_corner is deprecated. "
+            "Please use add_yosys_synthesiscorner instead.",
+            DeprecationWarning,
+            stacklevel=2
+        )
+        self.add_yosys_synthesiscorner(corner, step=step, index=index, clobber=clobber)
+
+    def add_yosys_synthesiscorner(self, corner: str,
+                                  step: Optional[str] = None, index: Optional[str] = None,
+                                  clobber: bool = False):
+        """
+        Adds a timing corner to use for synthesis.
+
+        Args:
+            corner (str): The name of the corner.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+            clobber (bool, optional): If True, overwrites the existing list. Defaults to False.
+        """
         if clobber:
             self.set("var", "synthesis_corner", corner, step=step, index=index)
         else:
@@ -316,24 +338,331 @@ class ASICSynthesis(_ASICTask, YosysTask):
 
     def set_yosys_useslang(self, enable: bool,
                            step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables using the slang frontend.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
         self.set("var", "use_slang", enable, step=step, index=index)
 
+    def set_yosys_autoname(self, enable: bool,
+                           step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables renaming wires based on registers.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "autoname", enable, step=step, index=index)
+
     def set_yosys_tieundefined(self, tie: str,
                                step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets how to handle undefined signals in the netlist.
+
+        Args:
+            tie (str): The tie strategy ('high', 'low', 'none').
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
         self.set("var", "tie_undef", tie, step=step, index=index)
 
     def set_yosys_addtiecells(self, enable: bool,
                               step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables adding tie high and tie low cells.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
         self.set("var", "add_tieoffs", enable, step=step, index=index)
 
     def set_yosys_addbuffers(self, enable: bool,
                              step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables adding buffers.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
         self.set("var", "add_buffers", enable, step=step, index=index)
 
     def set_yosys_optundriven(self, enable: bool,
                               step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables marking undriven nets during optimization.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
         self.set("var", "opt_undriven", enable, step=step, index=index)
 
+    def set_yosys_mapadders(self, enable: bool,
+                            step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables techmapping adders in Yosys.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "map_adders", enable, step=step, index=index)
+
+    def set_yosys_memorylibmap(self, file: str,
+                               step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the file used to map memories with Yosys.
+
+        Args:
+            file (str): The path to the library map file.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "memory_libmap", file, step=step, index=index)
+
+    def set_yosys_memorytechmap(self, file: str,
+                                step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the file used to techmap memories with Yosys.
+
+        Args:
+            file (str): The path to the technology map file.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "memory_techmap", file, step=step, index=index)
+
+    def add_yosys_synthextramap(self, map: Union[str, List[str]],
+                                step: Optional[str] = None, index: Optional[str] = None,
+                                clobber: bool = False):
+        """
+        Adds files used in synthesis to perform additional techmapping.
+
+        Args:
+            map (Union[str, List[str]]): The map file(s) to add.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+            clobber (bool, optional): If True, overwrites the existing list. Defaults to False.
+        """
+        if clobber:
+            self.set("var", "synth_extra_map", map, step=step, index=index)
+        else:
+            self.add("var", "synth_extra_map", map, step=step, index=index)
+
+    def add_yosys_preservemodules(self, modules: Union[str, List[str]],
+                                  step: Optional[str] = None, index: Optional[str] = None,
+                                  clobber: bool = False):
+        """
+        Adds modules to prevent flattening.
+
+        Args:
+            modules (Union[str, List[str]]): The module name(s) to preserve.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+            clobber (bool, optional): If True, overwrites the existing list. Defaults to False.
+        """
+        if clobber:
+            self.set("var", "preserve_modules", modules, step=step, index=index)
+        else:
+            self.add("var", "preserve_modules", modules, step=step, index=index)
+
+    def add_yosys_blackboxmodules(self, modules: Union[str, List[str]],
+                                  step: Optional[str] = None, index: Optional[str] = None,
+                                  clobber: bool = False):
+        """
+        Adds modules to exclude from synthesis by replacing them with empty blackboxes.
+
+        Args:
+            modules (Union[str, List[str]]): The module name(s) to blackbox.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+            clobber (bool, optional): If True, overwrites the existing list. Defaults to False.
+        """
+        if clobber:
+            self.set("var", "blackbox_modules", modules, step=step, index=index)
+        else:
+            self.add("var", "blackbox_modules", modules, step=step, index=index)
+
+    def set_yosys_flatten(self, enable: bool,
+                          step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables invoking synth with the -flatten option.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "flatten", enable, step=step, index=index)
+
+    def set_yosys_autoflatten(self, enable: bool,
+                              step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables attempting to determine how to flatten the design.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "auto_flatten", enable, step=step, index=index)
+
+    def set_yosys_hierthreshold(self, threshold: int,
+                                step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the instance limit for the number of cells in a module to preserve.
+
+        Args:
+            threshold (int): The instance limit.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "hier_threshold", threshold, step=step, index=index)
+
+    def set_yosys_hierarchyseparator(self, separator: str,
+                                     step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the hierarchy separator used during design flattening.
+
+        Args:
+            separator (str): The separator character.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "hierarchy_separator", separator, step=step, index=index)
+
+    def set_yosys_strategy(self, strategy: str,
+                           step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the ABC synthesis strategy.
+
+        Args:
+            strategy (str): The strategy name (e.g., 'DELAY1', 'AREA2').
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "strategy", strategy, step=step, index=index)
+
+    def set_yosys_abcconstraintdriver(self, driver: str,
+                                      step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the buffer that drives the ABC techmapping.
+
+        Args:
+            driver (str): The driver cell name.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "abc_constraint_driver", driver, step=step, index=index)
+
+    def set_yosys_abcclockperiod(self, period: float,
+                                 step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the clock period to use for synthesis.
+
+        Args:
+            period (float): The clock period in ps.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "abc_clock_period", period, step=step, index=index)
+
+    def set_yosys_abcconstraintload(self, load: float,
+                                    step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the capacitive load for the ABC techmapping.
+
+        Args:
+            load (float): The load in fF.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "abc_constraint_load", load, step=step, index=index)
+
+    def set_yosys_abcclockderating(self, derating: float,
+                                   step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the derating to apply to the clock period for ABC synthesis.
+
+        Args:
+            derating (float): The derating factor.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "abc_clock_derating", derating, step=step, index=index)
+
+    def set_yosys_mapclockgates(self, enable: bool,
+                                step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables mapping clockgates during synthesis.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "map_clockgates", enable, step=step, index=index)
+
+    def set_yosys_minclockgatefanout(self, fanout: int,
+                                     step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the minimum clockgate fanout.
+
+        Args:
+            fanout (int): The minimum fanout.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "min_clockgate_fanout", fanout, step=step, index=index)
+
+    def set_yosys_lockdesign(self, enable: bool,
+                             step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables attempting to lock the design with moosic.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "lock_design", enable, step=step, index=index)
+
+    def set_yosys_lockdesignkey(self, key: str,
+                                step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the lock locking key.
+
+        Args:
+            key (str): The key.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "lock_design_key", key, step=step, index=index)
+
+    def set_yosys_lockdesignport(self, port: str,
+                                 step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the lock locking port name.
+
+        Args:
+            port (str): The port name.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "lock_design_port", port, step=step, index=index)
+
     def task(self):
         return "syn_asic"
 

siliconcompiler/tools/yosys/syn_fpga.py

@@ -30,8 +30,40 @@ class FPGASynthesis(YosysTask):
 
     def set_yosys_useslang(self, enable: bool,
                            step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables using the slang frontend.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
         self.set("var", "use_slang", enable, step=step, index=index)
 
+    def set_yosys_synthoptmode(self, mode: str,
+                               step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the optimization mode for synthesis.
+
+        Args:
+            mode (str): The optimization mode ('none', 'delay', 'area').
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "synth_opt_mode", mode, step=step, index=index)
+
+    def set_yosys_synthinsertbuffers(self, enable: bool,
+                                     step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Enables or disables buffer insertion during synthesis.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "synth_insert_buffers", enable, step=step, index=index)
+
     def task(self):
         return "syn_fpga"
 

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "52d1fc05168f094b574222330fc7968589eabfb4",
+    "git-commit": "0004adbadb9b28cbc00b87c0b2a089164e439441",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -17,7 +17,7 @@
   },
   "opensta": {
     "git-url": "https://github.com/parallaxsw/OpenSTA.git",
-    "git-commit": "4afa443892bcba34f7c6a54b8e58ae2920dec9b5",
+    "git-commit": "128ea3cf283ba2ac0af699543c8e037cc9bfc0a5",
     "auto-update": true
   },
   "netgen": {
@@ -168,7 +168,7 @@
   },
   "keplerformal": {
     "git-url": "https://github.com/keplertech/kepler-formal.git",
-    "git-commit": "ea6b0ce62f6f8fd2327e79913a07c74a3210551d",
+    "git-commit": "c1edd4a196536385255f4c882e4001d534d4638b",
     "auto-update": false
   }
 }

{siliconcompiler-0.36.0.dist-info → siliconcompiler-0.36.1.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: siliconcompiler
-Version: 0.36.0
+Version: 0.36.1
 Summary: A compiler framework that automates translation from source code to silicon.
 Author: Zero ASIC
 License: Apache License 2.0
@@ -31,7 +31,7 @@ Requires-Dist: docker<8.0.0,>=7.1.0
 Requires-Dist: fastjsonschema<2.22.0,>=2.20.0
 Requires-Dist: graphviz<0.22,>=0.20
 Requires-Dist: orjson<4,>=3.11.0
-Requires-Dist: packaging<25,>=21.3
+Requires-Dist: packaging<26,>=21.3
 Requires-Dist: requests<2.33.0,>=2.32.0
 Requires-Dist: Pillow<11.4.0,>=11.3.0
 Requires-Dist: PyYAML<7.0.0,>=6.0.0