siliconcompiler 0.36.0__py3-none-any.whl → 0.36.1__py3-none-any.whl
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- siliconcompiler/_metadata.py +1 -1
- siliconcompiler/tools/chisel/convert.py +44 -0
- siliconcompiler/tools/ghdl/convert.py +37 -2
- siliconcompiler/tools/icarus/compile.py +14 -0
- siliconcompiler/tools/klayout/drc.py +14 -0
- siliconcompiler/tools/klayout/export.py +40 -0
- siliconcompiler/tools/klayout/operations.py +40 -0
- siliconcompiler/tools/openroad/__init__.py +11 -0
- siliconcompiler/tools/openroad/_apr.py +754 -1
- siliconcompiler/tools/openroad/antenna_repair.py +26 -0
- siliconcompiler/tools/openroad/fillmetal_insertion.py +14 -0
- siliconcompiler/tools/openroad/global_placement.py +67 -0
- siliconcompiler/tools/openroad/global_route.py +15 -0
- siliconcompiler/tools/openroad/init_floorplan.py +14 -0
- siliconcompiler/tools/openroad/macro_placement.py +252 -0
- siliconcompiler/tools/openroad/power_grid.py +43 -0
- siliconcompiler/tools/openroad/rcx_bench.py +28 -0
- siliconcompiler/tools/openroad/rcx_extract.py +14 -0
- siliconcompiler/tools/openroad/rdlroute.py +14 -0
- siliconcompiler/tools/openroad/repair_design.py +41 -0
- siliconcompiler/tools/openroad/repair_timing.py +54 -0
- siliconcompiler/tools/openroad/screenshot.py +31 -1
- siliconcompiler/tools/openroad/scripts/apr/preamble.tcl +8 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_init_floorplan.tcl +5 -1
- siliconcompiler/tools/openroad/write_data.py +76 -0
- siliconcompiler/tools/opensta/timing.py +37 -2
- siliconcompiler/tools/slang/elaborate.py +16 -1
- siliconcompiler/tools/surelog/parse.py +54 -0
- siliconcompiler/tools/verilator/compile.py +120 -0
- siliconcompiler/tools/vivado/syn_fpga.py +27 -0
- siliconcompiler/tools/vpr/route.py +40 -0
- siliconcompiler/tools/xdm/convert.py +14 -0
- siliconcompiler/tools/xyce/simulate.py +26 -0
- siliconcompiler/tools/yosys/lec_asic.py +13 -0
- siliconcompiler/tools/yosys/syn_asic.py +332 -3
- siliconcompiler/tools/yosys/syn_fpga.py +32 -0
- siliconcompiler/toolscripts/_tools.json +3 -3
- {siliconcompiler-0.36.0.dist-info → siliconcompiler-0.36.1.dist-info}/METADATA +2 -2
- {siliconcompiler-0.36.0.dist-info → siliconcompiler-0.36.1.dist-info}/RECORD +43 -43
- {siliconcompiler-0.36.0.dist-info → siliconcompiler-0.36.1.dist-info}/WHEEL +0 -0
- {siliconcompiler-0.36.0.dist-info → siliconcompiler-0.36.1.dist-info}/entry_points.txt +0 -0
- {siliconcompiler-0.36.0.dist-info → siliconcompiler-0.36.1.dist-info}/licenses/LICENSE +0 -0
- {siliconcompiler-0.36.0.dist-info → siliconcompiler-0.36.1.dist-info}/top_level.txt +0 -0
siliconcompiler/_metadata.py
CHANGED
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@@ -4,6 +4,8 @@ import glob
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import os.path
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from typing import Optional, List, Union
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from siliconcompiler import sc_open
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from siliconcompiler import Task
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self.add_parameter("targetdir", "str", "Output target directory name",
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defvalue="chisel-output")
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def set_chisel_application(self, application: str,
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step: Optional[str] = None, index: Optional[str] = None) -> None:
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"""
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Sets the application name of the chisel program.
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Args:
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application (str): The application name.
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step (str, optional): The specific step to apply this configuration to.
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index (str, optional): The specific index to apply this configuration to.
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"""
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self.set("var", "application", application, step=step, index=index)
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def add_chisel_argument(self, argument: Union[str, List[str]],
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step: Optional[str] = None, index: Optional[str] = None,
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clobber: bool = False) -> None:
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"""
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Adds arguments for the chisel build.
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Args:
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argument (Union[str, List[str]]): The argument(s) to add.
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step (str, optional): The specific step to apply this configuration to.
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index (str, optional): The specific index to apply this configuration to.
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clobber (bool, optional): If True, overwrites the existing list. Defaults to False.
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"""
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if clobber:
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self.set("var", "argument", argument, step=step, index=index)
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else:
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self.add("var", "argument", argument, step=step, index=index)
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def set_chisel_targetdir(self, targetdir: str,
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step: Optional[str] = None,
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index: Optional[str] = None) -> None:
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"""
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Sets the output target directory name.
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Args:
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targetdir (str): The target directory name.
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step (str, optional): The specific step to apply this configuration to.
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index (str, optional): The specific index to apply this configuration to.
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"""
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self.set("var", "targetdir", targetdir, step=step, index=index)
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def tool(self):
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return "chisel"
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from typing import Optional
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from siliconcompiler import Task
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self.add_parameter("use_latches", "bool", "add the --latches flag", defvalue=False)
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def set_usefsynopsys(self, value: bool):
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-
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"""Deprecated: use set_ghdl_usefsynopsys instead."""
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import warnings
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warnings.warn("set_usefsynopsys is deprecated, use set_ghdl_usefsynopsys instead.",
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DeprecationWarning, stacklevel=2)
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self.set_ghdl_usefsynopsys(value)
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def set_ghdl_usefsynopsys(self, value: bool,
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step: Optional[str] = None,
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index: Optional[str] = None):
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"""
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Adds the -fsynopsys flag to the GHDL command.
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Args:
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value (bool): Whether to add the flag.
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step (str, optional): The step to associate with this setting.
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index (str, optional): The index to associate with this setting.
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"""
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self.set("var", "use_fsynopsys", value, step=step, index=index)
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def set_uselatches(self, value: bool):
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"""Deprecated: use set_ghdl_uselatches instead."""
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import warnings
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warnings.warn("set_uselatches is deprecated, use set_ghdl_uselatches instead.",
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DeprecationWarning, stacklevel=2)
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self.set_ghdl_uselatches(value)
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def set_ghdl_uselatches(self, value: bool,
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step: Optional[str] = None,
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index: Optional[str] = None):
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"""
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Adds the --latches flag to the GHDL command.
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Args:
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value (bool): Whether to add the flag.
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step (str, optional): The step to associate with this setting.
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index (str, optional): The index to associate with this setting.
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"""
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self.set("var", "use_latches", value, step=step, index=index)
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def tool(self):
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return "ghdl"
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from typing import Optional
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from siliconcompiler import Task
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@@ -14,6 +15,19 @@ class CompileTask(Task):
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'See the corresponding "-g" flags in the Icarus manual for more "'
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'"information.')
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def set_icarus_veriloggeneration(self, gen: str,
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step: Optional[str] = None,
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index: Optional[str] = None):
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"""
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Sets the Verilog language generation for Icarus.
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Args:
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gen (str): The Verilog generation to use.
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step (str, optional): The specific step to apply this configuration to.
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index (str, optional): The specific index to apply this configuration to.
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"""
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self.set("var", "verilog_generation", gen, step=step, index=index)
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def tool(self):
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return "icarus"
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from typing import Optional
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from xml.etree import ElementTree
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from siliconcompiler.tools.klayout import KLayoutTask
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self.add_parameter("drc_name", "str", "name of the DRC deck to run")
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def set_klayout_drcname(self, name: str,
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"""
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Sets the name of the DRC deck to run.
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Args:
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name (str): The name of the DRC deck.
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step (str, optional): The specific step to apply this configuration to.
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index (str, optional): The specific index to apply this configuration to.
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"""
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self.set("var", "drc_name", name, step=step, index=index)
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from typing import Optional
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def set_klayout_stream(self, stream: str,
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index: Optional[str] = None):
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"""
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Sets the stream format for generation.
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stream (str): The stream format to use.
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step (str, optional): The specific step to apply this configuration to.
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index (str, optional): The specific index to apply this configuration to.
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"""
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def set_klayout_timestamps(self, enable: bool,
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"""
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Enables or disables exporting GDSII with timestamps.
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Args:
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enable (bool): Whether to enable timestamps.
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step (str, optional): The specific step to apply this configuration to.
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index (str, optional): The specific index to apply this configuration to.
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"""
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self.set("var", "timestamps", enable, step=step, index=index)
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def set_klayout_screenshot(self, enable: bool,
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"""
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Enables or disables generating a screenshot of the layout.
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enable (bool): Whether to generate a screenshot.
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step (str, optional): The specific step to apply this configuration to.
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index (str, optional): The specific index to apply this configuration to.
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"""
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self.set("var", "screenshot", enable, step=step, index=index)
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def task(self):
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def set_klayout_operations(self, operations: List[Tuple[str, str]],
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"""
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Sets the list of operations to perform.
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operations (List[Tuple[str, str]]): The list of operations.
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step (str, optional): The specific step to apply this configuration to.
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index (str, optional): The specific index to apply this configuration to.
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"""
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self.set("var", "operations", operations, step=step, index=index)
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def set_klayout_stream(self, stream: str,
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Sets the stream format for generation.
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stream (str): The stream format to use.
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step (str, optional): The specific step to apply this configuration to.
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index (str, optional): The specific index to apply this configuration to.
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"""
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self.set("var", "stream", stream, step=step, index=index)
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def set_klayout_timestamps(self, enable: bool,
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step: Optional[str] = None,
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index: Optional[str] = None):
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"""
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Args:
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enable (bool): Whether to enable timestamps.
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step (str, optional): The specific step to apply this configuration to.
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index (str, optional): The specific index to apply this configuration to.
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"""
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"router and only uses the specified tech vias")
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self.define_tool_parameter("openroad", "drt_repair_pdn_vias", "str",
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"Via layer to repair after detailed routing")
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self.define_tool_parameter("openroad", "drt_via_in_pin_layers", "(str,str)",
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"Tuple of layers for vias in pin layers")
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def set_openroad_rclayers(self, signal: str = None, clock: str = None):
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"""
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self.set("tool", "openroad", "drt_repair_pdn_vias", layer)
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def set_openroad_detailedrouteviainpinlayers(self, layer1: str, layer2: str):
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"""Sets the via layers used in pin layers during detailed routing.
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Args:
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layer1 (str): The first layer for vias in pin layers.
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layer2 (str): The second layer for vias in pin layers.
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"""
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self.set("tool", "openroad", "drt_via_in_pin_layers", (layer1, layer2))
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|
168
|
+
|
|
158
169
|
|
|
159
170
|
class OpenROADStdCellLibrary(StdCellLibrary):
|
|
160
171
|
"""
|