siliconcompiler 0.35.4__py3-none-any.whl → 0.36.1__py3-none-any.whl

siliconcompiler/tools/opensta/scripts/sc_report_libraries.tcl

@@ -22,7 +22,7 @@ set sc_design [sc_top]
 # APR Parameters
 set sc_targetlibs [sc_get_asic_libraries logic]
 set sc_delaymodel [sc_cfg_get asic delaymodel]
-set sc_scenarios [dict keys [sc_cfg_get constraint timing]]
+set sc_scenarios [dict keys [sc_cfg_get constraint timing scenario]]
 
 ###############################
 # Optional
@@ -41,7 +41,7 @@ define_corners {*}$sc_scenarios
 foreach lib "$sc_targetlibs $sc_macrolibs" {
     #Liberty
     foreach corner $sc_scenarios {
-        foreach libcorner [sc_cfg_get constraint timing $corner libcorner] {
+        foreach libcorner [sc_cfg_get constraint timing scenario $corner libcorner] {
             if { [sc_cfg_exists library $lib output $libcorner $sc_delaymodel] } {
                 foreach lib_file [sc_cfg_get library $lib output $libcorner $sc_delaymodel] {
                     puts "Reading liberty file for ${corner} ($libcorner): ${lib_file}"

siliconcompiler/tools/opensta/scripts/sc_timing.tcl

@@ -23,10 +23,10 @@ if { $opensta_timing_mode == "asic" } {
     set sc_logiclibs [sc_cfg_get asic asiclib]
     set sc_delaymodel [sc_cfg_get asic delaymodel]
 
-    foreach corner [dict keys [sc_cfg_get constraint timing]] {
+    foreach corner [dict keys [sc_cfg_get constraint timing scenario]] {
         if {
             $sc_timing_mode == {} ||
-            [sc_cfg_get constraint timing $corner mode] == $sc_timing_mode
+            [sc_cfg_get constraint timing scenario $corner mode] == $sc_timing_mode
         } {
             lappend sc_scenarios $corner
         }
@@ -56,7 +56,7 @@ if { $opensta_timing_mode == "asic" } {
     foreach corner $sc_scenarios {
         foreach lib $sc_logiclibs {
             set lib_filesets []
-            foreach libcorner [sc_cfg_get constraint timing $corner libcorner] {
+            foreach libcorner [sc_cfg_get constraint timing scenario $corner libcorner] {
                 if {
                     [sc_cfg_exists library $lib asic \
                         libcornerfileset $libcorner $sc_delaymodel]
@@ -115,15 +115,13 @@ if { [file exists "inputs/${sc_topmodule}.sdc"] } {
     }
 
     if { $sc_timing_mode != {} } {
-        foreach corner $sc_scenarios {
-            set sdcfileset [sc_cfg_get constraint timing $corner sdcfileset]
-            foreach sdc [sc_cfg_get_fileset $sc_topmodulelib $sdcfileset sdc] {
-                if { [lsearch -exact $sdc_files $sdc] == -1 } {
-                    # read step constraint if exists
-                    puts "Reading mode (${sc_timing_mode}) SDC: ${sdc}"
-                    lappend sdc_files $sdc
-                    read_sdc $sdc
-                }
+        set sdcfileset [sc_cfg_get constraint timing mode $sc_timing_mode sdcfileset]
+        foreach sdc [sc_cfg_get_fileset $sc_topmodulelib $sdcfileset sdc] {
+            if { [lsearch -exact $sdc_files $sdc] == -1 } {
+                # read step constraint if exists
+                puts "Reading mode (${sc_timing_mode}) SDC: ${sdc}"
+                lappend sdc_files $sdc
+                read_sdc $sdc
             }
         }
     }
@@ -168,7 +166,7 @@ puts "Timing path groups: [sta::path_group_names]"
 
 if { $opensta_timing_mode == "asic" } {
     foreach corner $sc_scenarios {
-        set pex_corner [sc_cfg_get constraint timing $corner pexcorner]
+        set pex_corner [sc_cfg_get constraint timing scenario $corner pexcorner]
 
         set spef_file "inputs/${sc_topmodule}.${pex_corner}.spef"
         if { [file exists $spef_file] } {
@@ -178,7 +176,7 @@ if { $opensta_timing_mode == "asic" } {
     }
 
     foreach corner $sc_scenarios {
-        set pex_corner [sc_cfg_get constraint timing $corner pexcorner]
+        set pex_corner [sc_cfg_get constraint timing scenario $corner pexcorner]
 
         set input_sdf_file "inputs/${sc_topmodule}.${pex_corner}.sdf"
         if { [file exists $input_sdf_file] } {

siliconcompiler/tools/opensta/timing.py

@@ -2,6 +2,8 @@ import re
 
 import os.path
 
+from typing import Optional
+
 from siliconcompiler import sc_open
 
 from siliconcompiler.tools.opensta import OpenSTATask
@@ -27,8 +29,43 @@ class TimingTaskBase(OpenSTATask):
                            defvalue="tools/_common/sdc/sc_constraints.sdc",
                            dataroot="siliconcompiler")
 
-    def set_timing_mode(self, mode: str, step: str = None, index: str = None):
-        return self.set("var", "timing_mode", mode, step=step, index=index)
+    def set_opensta_topnpaths(self, n: int,
+                              step: Optional[str] = None,
+                              index: Optional[str] = None):
+        """
+        Sets the number of paths to report timing for.
+
+        Args:
+            n (int): The number of paths.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "top_n_paths", n, step=step, index=index)
+
+    def set_opensta_uniquepathgroupsperclock(self, enable: bool,
+                                             step: Optional[str] = None,
+                                             index: Optional[str] = None):
+        """
+        Enables or disables generating separate path groups per clock.
+
+        Args:
+            enable (bool): Whether to enable unique path groups per clock.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "unique_path_groups_per_clock", enable, step=step, index=index)
+
+    def set_opensta_timingmode(self, mode: str,
+                               step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the timing mode to use.
+
+        Args:
+            mode (str): The timing mode to use.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "timing_mode", mode, step=step, index=index)
 
     def setup(self):
         super().setup()
@@ -40,6 +77,8 @@ class TimingTaskBase(OpenSTATask):
 
         if self.get("var", "timing_mode"):
             self.add_required_key("var", "timing_mode")
+            if self.get("var", "timing_mode") not in self.project.constraint.timing.get_modes():
+                raise LookupError(f'{self.get("var", "timing_mode")} is not a defined mode')
         self.add_required_key("var", "top_n_paths")
         self.add_required_key("var", "unique_path_groups_per_clock")
         self.add_required_key("var", "opensta_generic_sdc")
@@ -149,7 +188,7 @@ class TimingTaskBase(OpenSTATask):
             self.record_metric("drvs", drv_count, source_file=[drv_report])
 
     def __report_map(self, metric):
-        corners = self.project.getkeys('constraint', 'timing')
+        corners = self.project.getkeys('constraint', 'timing', 'scenario')
         mapping = {
             "power": [f"reports/power.{corner}.rpt" for corner in corners],
             "unconstrained": ["reports/unconstrained.rpt", "reports/unconstrained.topN.rpt"],

siliconcompiler/tools/slang/elaborate.py

@@ -1,6 +1,8 @@
+from typing import Optional, Union
+
 import os.path
-from siliconcompiler.tools.slang import pyslang
 
+from siliconcompiler.tools.slang import pyslang
 
 from siliconcompiler.tools.slang import SlangTask
 
@@ -18,6 +20,19 @@ class Elaborate(SlangTask):
             "true/false, if true add the source file path information",
             True)
 
+    def set_slang_includesourcepaths(self, enable: bool,
+                                     step: Optional[str] = None,
+                                     index: Optional[Union[int, str]] = None):
+        """
+        Enables or disables adding source file path information to the output.
+
+        Args:
+            enable (bool): True to include source paths, False to exclude.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "include_source_paths", enable, step=step, index=index)
+
     def task(self):
         return "elaborate"
 

siliconcompiler/tools/surelog/parse.py

@@ -3,6 +3,8 @@ import sys
 
 import os.path
 
+from typing import Optional
+
 from siliconcompiler import sc_open
 from siliconcompiler import utils
 
@@ -23,6 +25,58 @@ class ElaborateTask(Task):
         self.add_parameter("disable_note", "bool",
                            "true/false, when true instructs Surelog to not log notes.")
 
+    def set_surelog_enablelowmem(self, enable: bool,
+                                 step: Optional[str] = None,
+                                 index: Optional[str] = None):
+        """
+        Enables or disables low memory mode.
+
+        Args:
+            enable (bool): Whether to enable low memory mode.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "enable_lowmem", enable, step=step, index=index)
+
+    def set_surelog_disablewritecache(self, disable: bool,
+                                      step: Optional[str] = None,
+                                      index: Optional[str] = None):
+        """
+        Disables or enables writing to the cache.
+
+        Args:
+            disable (bool): Whether to disable writing to the cache.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "disable_write_cache", disable, step=step, index=index)
+
+    def set_surelog_disableinfo(self, disable: bool,
+                                step: Optional[str] = None,
+                                index: Optional[str] = None):
+        """
+        Disables or enables logging info messages.
+
+        Args:
+            disable (bool): Whether to disable logging info messages.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "disable_info", disable, step=step, index=index)
+
+    def set_surelog_disablenote(self, disable: bool,
+                                step: Optional[str] = None,
+                                index: Optional[str] = None):
+        """
+        Disables or enables logging note messages.
+
+        Args:
+            disable (bool): Whether to disable logging note messages.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "disable_note", disable, step=step, index=index)
+
     def tool(self):
         return "surelog"
 

siliconcompiler/tools/verilator/compile.py

@@ -1,4 +1,5 @@
 import shlex
+from typing import Optional, List, Union
 
 from siliconcompiler.tools.verilator import VerilatorTask
 
@@ -35,6 +36,125 @@ class CompileTask(VerilatorTask):
         self.add_parameter("initialize_random", "bool",
                            "true/false, when true registers will reset with a random value")
 
+    def set_verilator_mode(self, mode: str,
+                           step: Optional[str] = None,
+                           index: Optional[str] = None):
+        """
+        Sets the compilation mode for Verilator.
+
+        Args:
+            mode (str): The compilation mode.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "mode", mode, step=step, index=index)
+
+    def set_verilator_trace(self, enable: bool,
+                            step: Optional[str] = None,
+                            index: Optional[str] = None):
+        """
+        Enables or disables trace generation.
+
+        Args:
+            enable (bool): Whether to enable trace generation.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "trace", enable, step=step, index=index)
+
+    def set_verilator_tracetype(self, trace_type: str,
+                                step: Optional[str] = None,
+                                index: Optional[str] = None):
+        """
+        Sets the type of wave file to create when trace is enabled.
+
+        Args:
+            trace_type (str): The trace type.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "trace_type", trace_type, step=step, index=index)
+
+    def add_verilator_cincludes(self, include: Union[str, List[str]],
+                                step: Optional[str] = None,
+                                index: Optional[str] = None,
+                                clobber: bool = False):
+        """
+        Adds include directories for the C++ compiler.
+
+        Args:
+            include (Union[str, List[str]]): The include directory/directories to add.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+            clobber (bool, optional): If True, overwrites the existing list. Defaults to False.
+        """
+        if clobber:
+            self.set("var", "cincludes", include, step=step, index=index)
+        else:
+            self.add("var", "cincludes", include, step=step, index=index)
+
+    def add_verilator_cflags(self, flag: Union[str, List[str]],
+                             step: Optional[str] = None,
+                             index: Optional[str] = None,
+                             clobber: bool = False):
+        """
+        Adds flags for the C++ compiler.
+
+        Args:
+            flag (Union[str, List[str]]): The flag(s) to add.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+            clobber (bool, optional): If True, overwrites the existing list. Defaults to False.
+        """
+        if clobber:
+            self.set("var", "cflags", flag, step=step, index=index)
+        else:
+            self.add("var", "cflags", flag, step=step, index=index)
+
+    def add_verilator_ldflags(self, flag: Union[str, List[str]],
+                              step: Optional[str] = None,
+                              index: Optional[str] = None,
+                              clobber: bool = False):
+        """
+        Adds flags for the linker.
+
+        Args:
+            flag (Union[str, List[str]]): The flag(s) to add.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+            clobber (bool, optional): If True, overwrites the existing list. Defaults to False.
+        """
+        if clobber:
+            self.set("var", "ldflags", flag, step=step, index=index)
+        else:
+            self.add("var", "ldflags", flag, step=step, index=index)
+
+    def set_verilator_pinsbv(self, width: int,
+                             step: Optional[str] = None,
+                             index: Optional[str] = None):
+        """
+        Sets the datatype width for SystemC inputs/outputs.
+
+        Args:
+            width (int): The bit width.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "pins_bv", width, step=step, index=index)
+
+    def set_verilator_initializerandom(self, enable: bool,
+                                       step: Optional[str] = None,
+                                       index: Optional[str] = None):
+        """
+        Enables or disables random initialization of registers.
+
+        Args:
+            enable (bool): Whether to enable random initialization.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "initialize_random", enable, step=step, index=index)
+
     def task(self):
         return "compile"
 

siliconcompiler/tools/vivado/syn_fpga.py

@@ -1,3 +1,4 @@
+from typing import Optional
 from siliconcompiler.tools.vivado import VivadoTask
 
 
@@ -9,6 +10,32 @@ class SynthesisTask(VivadoTask):
         self.add_parameter("synth_directive", "str", "synthesis directive", defvalue="Default")
         self.add_parameter("synth_mode", "str", "synthesis mode", defvalue="none")
 
+    def set_vivado_synthdirective(self, directive: str,
+                                  step: Optional[str] = None,
+                                  index: Optional[str] = None):
+        """
+        Sets the synthesis directive.
+
+        Args:
+            directive (str): The synthesis directive.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "synth_directive", directive, step=step, index=index)
+
+    def set_vivado_synthmode(self, mode: str,
+                             step: Optional[str] = None,
+                             index: Optional[str] = None):
+        """
+        Sets the synthesis mode.
+
+        Args:
+            mode (str): The synthesis mode.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "synth_mode", mode, step=step, index=index)
+
     def task(self):
         return "syn_fpga"
 

siliconcompiler/tools/vpr/route.py

@@ -1,4 +1,5 @@
 import shutil
+from typing import Optional
 
 from siliconcompiler.tools.vpr import VPRTask
 
@@ -19,6 +20,45 @@ class RouteTask(VPRTask):
                            "set the timing corner for files generated by the post-implementation "
                            "netlist", defvalue="typical")
 
+    def set_vpr_maxrouteriterations(self, iterations: int,
+                                    step: Optional[str] = None,
+                                    index: Optional[str] = None):
+        """
+        Sets the maximum number of routing iterations.
+
+        Args:
+            iterations (int): The maximum number of iterations.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "max_router_iterations", iterations, step=step, index=index)
+
+    def set_vpr_genpostimplementationnetlist(self, enable: bool,
+                                             step: Optional[str] = None,
+                                             index: Optional[str] = None):
+        """
+        Enables or disables generating a post-implementation netlist.
+
+        Args:
+            enable (bool): Whether to generate the netlist.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "gen_post_implementation_netlist", enable, step=step, index=index)
+
+    def set_vpr_timingcorner(self, corner: str,
+                             step: Optional[str] = None,
+                             index: Optional[str] = None):
+        """
+        Sets the timing corner for files generated by the post-implementation netlist.
+
+        Args:
+            corner (str): The timing corner.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "timing_corner", corner, step=step, index=index)
+
     def task(self):
         return "route"
 

siliconcompiler/tools/xdm/convert.py

@@ -2,6 +2,7 @@ import shutil
 
 import os.path
 
+from typing import Optional
 from siliconcompiler import Task
 
 
@@ -14,6 +15,19 @@ class ConvertTask(Task):
                            "the naming scheme for siliconcompiler",
                            defvalue=True)
 
+    def set_xdm_rename(self, enable: bool,
+                       step: Optional[str] = None,
+                       index: Optional[str] = None):
+        """
+        Enables or disables renaming the output file.
+
+        Args:
+            enable (bool): Whether to rename the output file.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "rename", enable, step=step, index=index)
+
     def tool(self):
         return "xdm"
 

siliconcompiler/tools/xyce/simulate.py

@@ -1,5 +1,7 @@
 import os.path
 
+from typing import Union, Optional
+
 from siliconcompiler import Task
 
 
@@ -11,6 +13,30 @@ class SimulateTask(Task):
         self.add_parameter("trace_format", "<ASCII,binary>", "Format to use for traces.",
                            defvalue="ASCII")
 
+    def set_xyce_trace(self, enable: bool,
+                       step: Optional[str] = None, index: Optional[Union[int, str]] = None):
+        """
+        Enables or disables dumping all signals.
+
+        Args:
+            enable (bool): True to enable, False to disable.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set('var', 'trace', enable, step=step, index=index)
+
+    def set_xyce_traceformat(self, trace_format: str,
+                             step: Optional[str] = None, index: Optional[Union[int, str]] = None):
+        """
+        Sets the format to use for traces.
+
+        Args:
+            trace_format (str): The format to use for traces.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set('var', 'trace_format', trace_format, step=step, index=index)
+
     def tool(self):
         return "xyce"
 

siliconcompiler/tools/yosys/lec_asic.py

@@ -1,4 +1,5 @@
 import re
+from typing import Optional
 
 from siliconcompiler import sc_open
 
@@ -15,6 +16,18 @@ class ASICLECTask(_ASICTask):
         self.add_parameter("induction_steps", "int",
                            "Number of induction steps for yosys equivalence checking", defvalue=10)
 
+    def set_yosys_inductionsteps(self, steps: int,
+                                 step: Optional[str] = None, index: Optional[str] = None):
+        """
+        Sets the number of induction steps for yosys equivalence checking.
+
+        Args:
+            steps (int): The number of steps.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "induction_steps", steps, step=step, index=index)
+
     def task(self):
         return "lec_asic"