siliconcompiler 0.35.4__py3-none-any.whl → 0.36.0__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/apr/sc_write_data.tcl

@@ -60,7 +60,7 @@ if { [sc_cfg_tool_task_get var write_spef] } {
     if { [sc_cfg_tool_task_get var use_spef] } {
         set lib_pex [dict create]
         foreach scenario $sc_scenarios {
-            set pexcorner [sc_cfg_get constraint timing $scenario pexcorner]
+            set pexcorner [sc_cfg_get constraint timing scenario $scenario pexcorner]
 
             dict set lib_pex $scenario $pexcorner
         }
@@ -107,11 +107,11 @@ foreach corner $sc_scenarios {
 ###############################
 
 foreach corner $sc_scenarios {
-    if { [sc_cfg_exists constraint timing $corner voltage] } {
-        foreach net [dict keys [sc_cfg_get constraint timing $corner voltage]] {
+    if { [sc_cfg_exists constraint timing scenario $corner voltage] } {
+        foreach net [dict keys [sc_cfg_get constraint timing scenario $corner voltage]] {
             set_pdnsim_net_voltage -corner $corner \
                 -net $net \
-                -voltage [sc_cfg_get constraint timing $corner voltage $net]
+                -voltage [sc_cfg_get constraint timing scenario $corner voltage $net]
         }
     }
 }

siliconcompiler/tools/openroad/scripts/common/procs.tcl

@@ -238,10 +238,10 @@ proc sc_design_has_unplaced_macros { } {
 # Print macros placement
 ###########################
 
-proc sc_print_macro_information { } {
+proc sc_print_macro_information { { insts [] } } {
     set print_header "true"
     foreach inst [[ord::get_db_block] getInsts] {
-        if { [$inst isBlock] } {
+        if { [$inst isBlock] || [lsearch -exact $insts [$inst getName]] != -1 } {
             set master [$inst getMaster]
             set status [$inst getPlacementStatus]
 
@@ -388,17 +388,22 @@ proc sc_psm_check_nets { } {
 # Save an image
 ###########################
 
-proc sc_save_image { title path { gif false } { pixels 1000 } } {
+proc sc_save_image { title path { gif -1 } { pixels 1000 } } {
     utl::info FLW 1 "Saving \"$title\" to $path"
 
     save_image -resolution [sc_image_resolution $pixels] \
         -area [sc_image_area] \
         $path
 
-    if { $gif } {
+    if { $gif >= 0 } {
+        set gif_args []
+        if { [sc_check_version 26866] } {
+            lappend gif_args -key $gif
+        }
         save_animated_gif -add \
             -resolution [sc_image_resolution $pixels] \
-            -area [sc_image_area]
+            -area [sc_image_area] \
+            {*}$gif_args
     }
 }
 
@@ -458,6 +463,10 @@ proc sc_image_setup_default { } {
     gui::set_display_controls "Nets/*" visible true
     gui::set_display_controls "Instances/*" visible true
     gui::set_display_controls "Shape Types/*" visible true
+    if { [llength [[ord::get_db_block] getBTerms]] > 10000 } {
+        # Avoid performance issues with too many IOs
+        gui::set_display_controls "Shape Types/Pins" visible false
+    }
     gui::set_display_controls "Misc/Instances/*" visible true
     gui::set_display_controls "Misc/Instances/Pin Names" visible false
     gui::set_display_controls "Misc/Scale bar" visible true

siliconcompiler/tools/openroad/scripts/common/read_liberty.tcl

@@ -1,4 +1,4 @@
-set sc_scenarios [dict keys [sc_cfg_get constraint timing]]
+set sc_scenarios [dict keys [sc_cfg_get constraint timing scenario]]
 set sc_delaymodel [sc_cfg_get asic delaymodel]
 
 # Read Liberty
@@ -7,7 +7,7 @@ define_corners {*}$sc_scenarios
 foreach corner $sc_scenarios {
     foreach lib $sc_logiclibs {
         set lib_filesets []
-        foreach libcorner [sc_cfg_get constraint timing $corner libcorner] {
+        foreach libcorner [sc_cfg_get constraint timing scenario $corner libcorner] {
             if { [sc_cfg_exists library $lib asic libcornerfileset $libcorner $sc_delaymodel] } {
                 lappend lib_filesets \
                     {*}[sc_cfg_get library $lib asic libcornerfileset $libcorner $sc_delaymodel]

siliconcompiler/tools/openroad/scripts/common/reports.tcl

@@ -84,13 +84,16 @@ if { [sc_cfg_tool_task_check_in_list drv_violations var reports] } {
 }
 
 puts "$PREFIX floating nets"
-tee -file reports/floating_nets.rpt \
+puts "Reporting floating nets: reports/floating_nets.rpt"
+tee -quiet -file reports/floating_nets.rpt \
     "report_floating_nets -verbose"
 if { [sc_check_version 19048] } {
     puts "$PREFIX overdriven nets"
-    tee -file reports/overdriven_nets.rpt \
+    puts "Reporting overdriven nets: reports/overdriven_nets.rpt"
+    tee -quiet -file reports/overdriven_nets.rpt \
         "report_overdriven_nets -verbose"
-    tee -file reports/overdriven_nets_with_parallel.rpt \
+    puts "Reporting overdriven nets: reports/overdriven_nets_with_parallel.rpt"
+    tee -quiet -file reports/overdriven_nets_with_parallel.rpt \
         "report_overdriven_nets -include_parallel_driven -verbose"
 }
 

siliconcompiler/tools/openroad/scripts/common/screenshot.tcl

@@ -5,7 +5,7 @@ sc_image_setup_default
 sc_save_image \
     "screenshot" \
     "outputs/${sc_topmodule}.png" \
-    false \
+    -1 \
     [sc_cfg_tool_task_get var show_vertical_resolution]
 
 gui::restore_display_controls

siliconcompiler/tools/openroad/scripts/common/write_data_physical.tcl

@@ -1,3 +1,11 @@
 write_db "outputs/${sc_topmodule}.odb"
 write_def "outputs/${sc_topmodule}.def"
 write_verilog -include_pwr_gnd "outputs/${sc_topmodule}.vg"
+
+set remove_cells []
+foreach lib [sc_cfg_get asic asiclib] {
+    foreach celltype "decap tie filler tap endcap antenna physicalonly" {
+        lappend remove_cells {*}[sc_cfg_get library $lib asic cells $celltype]
+    }
+}
+write_verilog -remove_cells $remove_cells "outputs/${sc_topmodule}.lec.vg"

siliconcompiler/tools/openroad/scripts/common/write_images.tcl

@@ -1,6 +1,6 @@
 # Adopted from https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/3f9740e6b3643835e918d78ae1d377d65af0f0fb/flow/scripts/save_images.tcl
 
-proc sc_image_heatmap { name ident image_name title { gif false } { allow_bin_adjust 1 } } {
+proc sc_image_heatmap { name ident image_name title { gif -1 } { allow_bin_adjust 1 } } {
     lassign [sc_cfg_tool_task_get var ord_heatmap_bins] ord_heatmap_bins_x ord_heatmap_bins_y
 
     file mkdir reports/images/heatmap
@@ -124,12 +124,12 @@ proc sc_image_irdrop { net corner } {
         return
     }
 
-    set gif false
+    set gif -1
     if { [sc_check_version 21574] } {
-        set gif true
-    }
-    if { $gif } {
-        save_animated_gif -start "reports/images/heatmap/irdrop/${net}.${corner}.gif"
+        set gif [save_animated_gif -start "reports/images/heatmap/irdrop/${net}.${corner}.gif"]
+        if { $gif == "" } {
+            set gif 0
+        }
     }
     foreach layer [[ord::get_db_tech] getLayers] {
         if { [$layer getRoutingLevel] == 0 } {
@@ -160,8 +160,12 @@ proc sc_image_irdrop { net corner } {
             gui::delete_label $label
         }
     }
-    if { $gif } {
-        save_animated_gif -end
+    if { $gif >= 0 } {
+        if { [sc_check_version 26866] } {
+            save_animated_gif -end -key $gif
+        } else {
+            save_animated_gif -end
+        }
     }
 }
 
@@ -176,7 +180,7 @@ proc sc_image_routing_congestion { } {
         "Routing" \
         "routing_congestion.png" \
         "routing congestion" \
-        0 \
+        -1 \
         0
 }
 
@@ -194,7 +198,7 @@ proc sc_image_estimated_routing_congestion { } {
             "RUDY" \
             "estimated_routing_congestion.png" \
             "estimated routing congestion" \
-            0 \
+            -1 \
             0
     } err
     unsuppress_message GRT 10
@@ -342,7 +346,7 @@ proc sc_image_timing_histograms { } {
 
     if { [sc_cfg_tool_task_check_in_list setup var reports] } {
         set path reports/images/timing/setup.histogram.png
-        utl::info FLW 1 "Saving setup timing histogram to $path"
+        utl::info FLW 1 "Saving \"setup timing histogram\" to $path"
         save_histogram_image $path \
             -mode setup \
             -width 500 \
@@ -350,7 +354,7 @@ proc sc_image_timing_histograms { } {
     }
     if { [sc_cfg_tool_task_check_in_list hold var reports] } {
         set path reports/images/timing/hold.histogram.png
-        utl::info FLW 1 "Saving hold timing histogram to $path"
+        utl::info FLW 1 "Saving \"hold timing histogram\" to $path"
         save_histogram_image $path \
             -mode hold \
             -width 500 \

siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl

@@ -149,5 +149,7 @@ utl::pop_metrics_stage
 ###############################
 
 utl::push_metrics_stage "sc__write__{}"
-source "$sc_refdir/common/write_data_physical.tcl"
+write_db "outputs/${sc_topmodule}.odb"
+write_def "outputs/${sc_topmodule}.def"
+write_verilog -include_pwr_gnd "outputs/${sc_topmodule}.vg"
 utl::pop_metrics_stage

siliconcompiler/tools/openroad/write_data.py

@@ -74,10 +74,10 @@ class WriteViewsTask(APRTask, OpenROADSTAParameter, OpenROADPSMParameter):
             for corner in self.get("var", "pex_corners"):
                 self.add_output_file(ext=f"{corner}.spef")
         if self.get("var", "write_liberty"):
-            for corner in self.project.getkeys("constraint", "timing"):
+            for corner in self.project.getkeys("constraint", "timing", "scenario"):
                 self.add_output_file(ext=f"{corner}.lib")
         if self.get("var", "write_sdf"):
-            for corner in self.project.getkeys("constraint", "timing"):
+            for corner in self.project.getkeys("constraint", "timing", "scenario"):
                 self.add_output_file(ext=f"{corner}.sdf")
 
         self.add_required_key("var", "ord_abstract_lef_bloat_layers")

siliconcompiler/tools/opensta/scripts/sc_check_library.tcl

@@ -22,7 +22,7 @@ set sc_design [sc_top]
 # APR Parameters
 set sc_targetlibs [sc_get_asic_libraries logic]
 set sc_delaymodel [sc_cfg_get asic delaymodel]
-set sc_scenarios [dict keys [sc_cfg_get constraint timing]]
+set sc_scenarios [dict keys [sc_cfg_get constraint timing scenario]]
 
 ###############################
 # Optional
@@ -41,7 +41,7 @@ define_corners {*}$sc_scenarios
 foreach lib "$sc_targetlibs $sc_macrolibs" {
     #Liberty
     foreach corner $sc_scenarios {
-        foreach libcorner [sc_cfg_get constraint timing $corner libcorner] {
+        foreach libcorner [sc_cfg_get constraint timing scenario $corner libcorner] {
             if { [sc_cfg_exists library $lib output $libcorner $sc_delaymodel] } {
                 foreach lib_file [sc_cfg_get library $lib output $libcorner $sc_delaymodel] {
                     puts "Reading liberty file for ${corner} ($libcorner): ${lib_file}"

siliconcompiler/tools/opensta/scripts/sc_report_libraries.tcl

@@ -22,7 +22,7 @@ set sc_design [sc_top]
 # APR Parameters
 set sc_targetlibs [sc_get_asic_libraries logic]
 set sc_delaymodel [sc_cfg_get asic delaymodel]
-set sc_scenarios [dict keys [sc_cfg_get constraint timing]]
+set sc_scenarios [dict keys [sc_cfg_get constraint timing scenario]]
 
 ###############################
 # Optional
@@ -41,7 +41,7 @@ define_corners {*}$sc_scenarios
 foreach lib "$sc_targetlibs $sc_macrolibs" {
     #Liberty
     foreach corner $sc_scenarios {
-        foreach libcorner [sc_cfg_get constraint timing $corner libcorner] {
+        foreach libcorner [sc_cfg_get constraint timing scenario $corner libcorner] {
             if { [sc_cfg_exists library $lib output $libcorner $sc_delaymodel] } {
                 foreach lib_file [sc_cfg_get library $lib output $libcorner $sc_delaymodel] {
                     puts "Reading liberty file for ${corner} ($libcorner): ${lib_file}"

siliconcompiler/tools/opensta/scripts/sc_timing.tcl

@@ -23,10 +23,10 @@ if { $opensta_timing_mode == "asic" } {
     set sc_logiclibs [sc_cfg_get asic asiclib]
     set sc_delaymodel [sc_cfg_get asic delaymodel]
 
-    foreach corner [dict keys [sc_cfg_get constraint timing]] {
+    foreach corner [dict keys [sc_cfg_get constraint timing scenario]] {
         if {
             $sc_timing_mode == {} ||
-            [sc_cfg_get constraint timing $corner mode] == $sc_timing_mode
+            [sc_cfg_get constraint timing scenario $corner mode] == $sc_timing_mode
         } {
             lappend sc_scenarios $corner
         }
@@ -56,7 +56,7 @@ if { $opensta_timing_mode == "asic" } {
     foreach corner $sc_scenarios {
         foreach lib $sc_logiclibs {
             set lib_filesets []
-            foreach libcorner [sc_cfg_get constraint timing $corner libcorner] {
+            foreach libcorner [sc_cfg_get constraint timing scenario $corner libcorner] {
                 if {
                     [sc_cfg_exists library $lib asic \
                         libcornerfileset $libcorner $sc_delaymodel]
@@ -115,15 +115,13 @@ if { [file exists "inputs/${sc_topmodule}.sdc"] } {
     }
 
     if { $sc_timing_mode != {} } {
-        foreach corner $sc_scenarios {
-            set sdcfileset [sc_cfg_get constraint timing $corner sdcfileset]
-            foreach sdc [sc_cfg_get_fileset $sc_topmodulelib $sdcfileset sdc] {
-                if { [lsearch -exact $sdc_files $sdc] == -1 } {
-                    # read step constraint if exists
-                    puts "Reading mode (${sc_timing_mode}) SDC: ${sdc}"
-                    lappend sdc_files $sdc
-                    read_sdc $sdc
-                }
+        set sdcfileset [sc_cfg_get constraint timing mode $sc_timing_mode sdcfileset]
+        foreach sdc [sc_cfg_get_fileset $sc_topmodulelib $sdcfileset sdc] {
+            if { [lsearch -exact $sdc_files $sdc] == -1 } {
+                # read step constraint if exists
+                puts "Reading mode (${sc_timing_mode}) SDC: ${sdc}"
+                lappend sdc_files $sdc
+                read_sdc $sdc
             }
         }
     }
@@ -168,7 +166,7 @@ puts "Timing path groups: [sta::path_group_names]"
 
 if { $opensta_timing_mode == "asic" } {
     foreach corner $sc_scenarios {
-        set pex_corner [sc_cfg_get constraint timing $corner pexcorner]
+        set pex_corner [sc_cfg_get constraint timing scenario $corner pexcorner]
 
         set spef_file "inputs/${sc_topmodule}.${pex_corner}.spef"
         if { [file exists $spef_file] } {
@@ -178,7 +176,7 @@ if { $opensta_timing_mode == "asic" } {
     }
 
     foreach corner $sc_scenarios {
-        set pex_corner [sc_cfg_get constraint timing $corner pexcorner]
+        set pex_corner [sc_cfg_get constraint timing scenario $corner pexcorner]
 
         set input_sdf_file "inputs/${sc_topmodule}.${pex_corner}.sdf"
         if { [file exists $input_sdf_file] } {

siliconcompiler/tools/opensta/timing.py

@@ -2,6 +2,8 @@ import re
 
 import os.path
 
+from typing import Optional
+
 from siliconcompiler import sc_open
 
 from siliconcompiler.tools.opensta import OpenSTATask
@@ -27,7 +29,7 @@ class TimingTaskBase(OpenSTATask):
                            defvalue="tools/_common/sdc/sc_constraints.sdc",
                            dataroot="siliconcompiler")
 
-    def set_timing_mode(self, mode: str, step: str = None, index: str = None):
+    def set_timing_mode(self, mode: str, step: Optional[str] = None, index: Optional[str] = None):
         return self.set("var", "timing_mode", mode, step=step, index=index)
 
     def setup(self):
@@ -40,6 +42,8 @@ class TimingTaskBase(OpenSTATask):
 
         if self.get("var", "timing_mode"):
             self.add_required_key("var", "timing_mode")
+            if self.get("var", "timing_mode") not in self.project.constraint.timing.get_modes():
+                raise LookupError(f'{self.get("var", "timing_mode")} is not a defined mode')
         self.add_required_key("var", "top_n_paths")
         self.add_required_key("var", "unique_path_groups_per_clock")
         self.add_required_key("var", "opensta_generic_sdc")
@@ -149,7 +153,7 @@ class TimingTaskBase(OpenSTATask):
             self.record_metric("drvs", drv_count, source_file=[drv_report])
 
     def __report_map(self, metric):
-        corners = self.project.getkeys('constraint', 'timing')
+        corners = self.project.getkeys('constraint', 'timing', 'scenario')
         mapping = {
             "power": [f"reports/power.{corner}.rpt" for corner in corners],
             "unconstrained": ["reports/unconstrained.rpt", "reports/unconstrained.topN.rpt"],

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "dd56d50c413ecd215117898437c57bec68b59a87",
+    "git-commit": "52d1fc05168f094b574222330fc7968589eabfb4",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -17,7 +17,7 @@
   },
   "opensta": {
     "git-url": "https://github.com/parallaxsw/OpenSTA.git",
-    "git-commit": "bd3efdc322c0677eb8e3d76f22ab297f7a6048b9",
+    "git-commit": "4afa443892bcba34f7c6a54b8e58ae2920dec9b5",
     "auto-update": true
   },
   "netgen": {
@@ -145,7 +145,7 @@
   },
   "yosys-slang": {
     "git-url": "https://github.com/povik/yosys-slang.git",
-    "git-commit": "875539b8cae5a2ac7c86fee43b1e38a743ee8659",
+    "git-commit": "64b44616a3798f07453b14ea03e4ac8a16b77313",
     "docker-depends": "yosys",
     "auto-update": true
   },
@@ -163,7 +163,12 @@
   },
   "surfer": {
     "git-url": "https://gitlab.com/surfer-project/surfer.git",
-    "git-commit": "v0.3.0",
+    "git-commit": "v0.5.0",
+    "auto-update": true
+  },
+  "keplerformal": {
+    "git-url": "https://github.com/keplertech/kepler-formal.git",
+    "git-commit": "ea6b0ce62f6f8fd2327e79913a07c74a3210551d",
     "auto-update": false
   }
 }

siliconcompiler/toolscripts/ubuntu22/install-keplerformal.sh

@@ -0,0 +1,72 @@
+#!/bin/bash
+
+set -ex
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL=sudo
+else
+    SUDO_INSTALL=""
+fi
+
+sudo apt-get update
+
+sudo apt-get install -y build-essential libfl-dev
+
+# From: https://github.com/keplertech/kepler-formal/blob/ea6b0ce62f6f8fd2327e79913a07c74a3210551d/README.md
+sudo apt-get install -y g++ libboost-dev python3-dev capnproto libcapnp-dev libtbb-dev \
+    pkg-config bison flex doxygen libspdlog-dev libfmt-dev libboost-iostreams-dev zlib1g-dev
+
+sudo apt-get install -y git
+
+mkdir -p deps
+cd deps
+
+python3 -m venv .keplerformal --clear
+. .keplerformal/bin/activate
+python3 -m pip install cmake==3.31.6
+
+git clone $(python3 ${src_path}/_tools.py --tool keplerformal --field git-url) keplerformal
+cd keplerformal
+git checkout $(python3 ${src_path}/_tools.py --tool keplerformal --field git-commit)
+git submodule update --init --recursive
+
+git apply - <<EOF
+diff --git a/CMakeLists.txt b/CMakeLists.txt
+index 65d0d04..a67d38f 100644
+--- a/CMakeLists.txt
++++ b/CMakeLists.txt
+@@ -26,9 +26,9 @@ add_subdirectory(thirdparty)
+ 
+ # option(ENABLE_UNIT_TESTS ON)
+ # if(ENABLE_UNIT_TESTS)
+-include(CTest)
+-enable_testing()
+-add_subdirectory(test)
++# include(CTest)
++# enable_testing()
++# add_subdirectory(test)
+ # endif()
+ 
+ option(CODE_COVERAGE "Enable coverage reporting" OFF)
+EOF
+
+cmake_args=""
+if [ ! -z ${PREFIX} ]; then
+    cmake_args="-DCMAKE_INSTALL_PREFIX=$PREFIX"
+fi
+
+mkdir -p build
+cd build
+cmake .. -DCMAKE_BUILD_TYPE=Release \
+    -DCMAKE_CXX_FLAGS_RELEASE="-Ofast -march=native -ffast-math -flto" \
+    -DCMAKE_EXE_LINKER_FLAGS="-flto" \
+	-DCMAKE_INSTALL_RPATH_USE_LINK_PATH=TRUE \
+    $cmake_args
+make -j$(nproc)
+$SUDO_INSTALL make install
+
+cd -

siliconcompiler/toolscripts/ubuntu24/install-keplerformal.sh

@@ -0,0 +1,72 @@
+#!/bin/bash
+
+set -ex
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL=sudo
+else
+    SUDO_INSTALL=""
+fi
+
+sudo apt-get update
+
+sudo apt-get install -y build-essential libfl-dev
+
+# From: https://github.com/keplertech/kepler-formal/blob/ea6b0ce62f6f8fd2327e79913a07c74a3210551d/README.md
+sudo apt-get install -y g++ libboost-dev python3-dev capnproto libcapnp-dev libtbb-dev \
+    pkg-config bison flex doxygen libspdlog-dev libfmt-dev libboost-iostreams-dev zlib1g-dev
+
+sudo apt-get install -y git
+
+mkdir -p deps
+cd deps
+
+python3 -m venv .keplerformal --clear
+. .keplerformal/bin/activate
+python3 -m pip install cmake==3.31.6
+
+git clone $(python3 ${src_path}/_tools.py --tool keplerformal --field git-url) keplerformal
+cd keplerformal
+git checkout $(python3 ${src_path}/_tools.py --tool keplerformal --field git-commit)
+git submodule update --init --recursive
+
+git apply - <<EOF
+diff --git a/CMakeLists.txt b/CMakeLists.txt
+index 65d0d04..a67d38f 100644
+--- a/CMakeLists.txt
++++ b/CMakeLists.txt
+@@ -26,9 +26,9 @@ add_subdirectory(thirdparty)
+ 
+ # option(ENABLE_UNIT_TESTS ON)
+ # if(ENABLE_UNIT_TESTS)
+-include(CTest)
+-enable_testing()
+-add_subdirectory(test)
++# include(CTest)
++# enable_testing()
++# add_subdirectory(test)
+ # endif()
+ 
+ option(CODE_COVERAGE "Enable coverage reporting" OFF)
+EOF
+
+cmake_args=""
+if [ ! -z ${PREFIX} ]; then
+    cmake_args="-DCMAKE_INSTALL_PREFIX=$PREFIX"
+fi
+
+mkdir -p build
+cd build
+cmake .. -DCMAKE_BUILD_TYPE=Release \
+    -DCMAKE_CXX_FLAGS_RELEASE="-Ofast -march=native -ffast-math -flto" \
+    -DCMAKE_EXE_LINKER_FLAGS="-flto" \
+	-DCMAKE_INSTALL_RPATH_USE_LINK_PATH=TRUE \
+    $cmake_args
+make -j$(nproc)
+$SUDO_INSTALL make install
+
+cd -

siliconcompiler/utils/multiprocessing.py

@@ -145,6 +145,7 @@ class MPManager(metaclass=_ManagerSingleton):
 
         # Settings
         self.__settings = SettingsManager(default_sc_path("settings.json"), self.__logger)
+        self.__transient_settings = SettingsManager(None, self.__logger)
 
         # Register cleanup function to run at exit
         atexit.register(MPManager.stop)
@@ -272,6 +273,16 @@ class MPManager(metaclass=_ManagerSingleton):
         """
         return MPManager().__settings
 
+    @staticmethod
+    def get_transient_settings() -> SettingsManager:
+        """
+        Provides access to the shared transient SettingsManager instance.
+
+        Returns:
+            SettingsManager: The singleton transient settings instance.
+        """
+        return MPManager().__transient_settings
+
     @staticmethod
     def get_dashboard() -> Board:
         """